EMC EM78P343N

EM78P341/2/3N
8-Bit Microprocessor
with OTP ROM
Product
Specification
DOC. VERSION 1.0
ELAN MICROELECTRONICS CORP.
December 2006
Contents
Trademark Acknowledgments:
IBM is a registered trademark and PS/2 is a trademark of IBM.
Windows is a trademark of Microsoft Corporation.
ELAN and ELAN logo
are trademarks of ELAN Microelectronics Corporation.
Copyright © 2005 by ELAN Microelectronics Corporation
All Rights Reserved
Printed in Taiwan
The contents of this specification are subject to change without further notice. ELAN Microelectronics assumes no
responsibility concerning the accuracy, adequacy, or completeness of this specification. ELAN Microelectronics
makes no commitment to update, or to keep current the information and material contained in this specification.
Such information and material may change to conform to each confirmed order.
In no event shall ELAN Microelectronics be made responsible for any claims attributed to errors, omissions, or
other inaccuracies in the information or material contained in this specification. ELAN Microelectronics shall not
be liable for direct, indirect, special incidental, or consequential damages arising from the use of such information
or material.
The software (if any) described in this specification is furnished under a license or nondisclosure agreement, and
may be used or copied only in accordance with the terms of such agreement.
ELAN Microelectronics products are not intended for use in life support appliances, devices, or systems. Use of
ELAN Microelectronics product in such applications is not supported and is prohibited.
NO PART OF THIS SPECIFICATION MAY BE REPRODUCED OR TRANSMITTED IN ANY FORM OR BY
ANY MEANS WITHOUT THE EXPRESSED WRITTEN PERMISSION OF ELAN MICROELECTRONICS.
ELAN MICROELECTRONICS CORPORATION
Headquarters:
Hong Kong:
USA:
No. 12, Innovation Road 1
Hsinchu Science Park
Hsinchu, TAIWAN 30077
Tel: +886 3 563-9977
Fax: +886 3 563-9966
http://www.emc.com.tw
Elan (HK) Microelectronics
Corporation, Ltd.
Flat A, 19F., World Tech Centre
95 How Ming Street, Kwun Tong
Kowloon, HONG KONG
Tel: +852 2723-3376
Fax: +852 2723-7780
[email protected]
Elan Information
Technology Group (U.S.A.)
Europe:
Shenzhen:
Shanghai:
Elan Microelectronics Corp.
(Europe)
Elan Microelectronics
Shenzhen, Ltd.
Elan Microelectronics
Shanghai, Ltd.
Siewerdtstrasse 105
8050 Zurich, SWITZERLAND
Tel: +41 43 299-4060
Fax: +41 43 299-4079
http://www.elan-europe.com
SSMEC Bldg., 3F, Gaoxin S. Ave.
Shenzhen Hi-Tech Industrial Park
Shenzhen, Guandong, CHINA
Tel: +86 755 2601-0565
Fax: +86 755 2601-0500
23/Bldg. #115 Lane 572, Bibo Road
Zhangjiang Hi-Tech Park
Shanghai, CHINA
Tel: +86 21 5080-3866
Fax: +86 21 5080-4600
1821 Saratoga Ave., Suite 250
Saratoga, CA 95070
U.S.A.
Tel: +1 408 366-8225
Fax: +1 408 366-8220
Contents
Contents
1
2
3
4
5
6
General Description ................................................................................................ 3
Features ................................................................................................................... 3
Pin Assignment ....................................................................................................... 4
Functional Block Diagram ...................................................................................... 5
Pin Description........................................................................................................ 6
5.1
EM78P341NP/M............................................................................................... 6
5.2
EM78P342NP/M............................................................................................... 7
5.3 EM78P343NP/M/KM......................................................................................... 8
Function Description .............................................................................................. 9
6.1
Operational Registers ....................................................................................... 9
6.1.1
6.1.2
6.1.3
6.1.4
6.1.5
6.1.6
6.1.7
6.1.8
6.1.9
6.1.10
6.1.11
6.1.12
6.1.13
6.1.14
6.1.15
6.1.16
6.2
R0 (Indirect Address Register) .......................................................................... 9
R1 (Time Clock /Counter) ................................................................................... 9
R2 (Program Counter) and Stack ....................................................................... 9
6.1.3.1 Data Memory Configuration................................................................11
R3 (Status Register) ......................................................................................... 12
R4 (RAM Select Register) ................................................................................ 12
R5 ~ R6 (Port 5 ~ Port 6).................................................................................. 13
R7 (Port 7) ........................................................................................................ 13
R8 (AISR: ADC Input Select Register) ............................................................. 14
R9 (ADCON: ADC Control Register) ................................................................ 15
RA (ADOC: ADC Offset Calibration Register) .................................................. 17
RB (ADDATA: Converted Value of ADC) .......................................................... 17
RC (ADDATA1H: Converted Value of ADC) ..................................................... 17
RD (ADDATA1L: Converted Value of ADC) ...................................................... 18
RE (Interrupt Status 2 & Wake-up Control Register) ........................................ 18
RF (Interrupt Status 2 Register)........................................................................ 19
R10 ~ R3F ........................................................................................................ 19
Special Purpose Registers.............................................................................. 20
6.2.1
6.2.2
6.2.3
6.2.4
6.2.5
6.2.6
6.2.7
6.2.8
6.2.9
A (Accumulator) ................................................................................................ 20
CONT (Control Register) .................................................................................. 20
IOC50 ~ IOC70 (I/O Port Control Register)...................................................... 21
IOC80 (Comparator and TCCA Control Register) ............................................ 21
IOC90 (TCCB and TCCC Control Register) ..................................................... 22
IOCA0 (IR and TCCC Scale Control Register)................................................. 23
IOCB0 (Pull-Down Control Register) ................................................................ 24
IOCC0 (Open-Drain Control Register) ............................................................. 24
IOCD0 (Pull-high Control Register) .................................................................. 25
Product Specification (V1.0) 12.01.2006
•iii
Contents
6.2.10
6.2.11
6.2.12
6.2.13
6.2.14
6.2.15
6.2.16
6.2.17
6.2.18
6.2.19
6.2.20
6.2.21
6.2.21
6.3
6.4
TCC/WDT and Prescaler ................................................................................ 33
I/O Ports ......................................................................................................... 35
6.4.1
6.5
6.5.2
6.7.3
6.7.4
6.7.5
6.7.6
Overview........................................................................................................... 62
Function Description ......................................................................................... 63
Programming the Related Registers ............................................................... 65
Timer/Counter................................................................................................. 66
6.9.1
6.9.2
6.9.3
iv •
ADC Control Register (AISR/R8, ADCON/R9, ADOC/RA)............................... 55
6.7.1.1 R8 (AISR: ADC Input Select Register) .............................................. 55
6.7.1.2 R9 (ADCON: AD Control Register).................................................... 56
6.7.1.3 RA (ADOC: AD Offset Calibration Register) ...................................... 57
ADC Sampling Time ......................................................................................... 58
AD Conversion Time......................................................................................... 58
ADC Operation during Sleep Mode .................................................................. 59
Programming Process/Considerations ............................................................. 59
6.7.6.1 Programming Process ....................................................................... 59
6.7.6.2 Sample Demo Programs ................................................................... 60
Infrared Remote Control Application/PWM Waveform Generation .................. 62
6.8.1
6.8.2
6.8.3
6.9
Reset and Wake-up Operation ......................................................................... 37
6.5.1.1 Wake-up and Interrupt Modes Operation Summary.......................... 40
6.5.1.2 Register Initial Values after Reset ..................................................... 46
6.5.1.3 Controller Reset Block Diagram ........................................................ 51
The T and P Status under Status (R3) Register ............................................... 51
Interrupt .......................................................................................................... 52
Analog-To-Digital Converter (ADC) ................................................................. 55
6.7.1
6.8
Usage of Port 5 Input Change Wake-up/Interrupt Function ............................. 37
Reset and Wake-up ........................................................................................ 37
6.5.1
6.6
6.7
IOCE0 (WDT Control & Interrupt Mask Registers 2) ........................................ 25
IOCF0 (Interrupt Mask Register) ...................................................................... 26
IOC51 (TCCA Counter) .................................................................................... 27
IOC61 (TCCB Counter) .................................................................................... 28
IOC71 (TCCBH/MSB Counter)......................................................................... 28
IOC81 (TCCC Counter) .................................................................................... 28
IOC91 (Low-Time Register).............................................................................. 29
IOCA1 (High Time Register)............................................................................. 29
IOCB1 High/Low Time Scale Control Register)................................................ 29
IOCC1 (TCC Prescaler Counter)...................................................................... 30
IOCD1 (LVD Control Register) ......................................................................... 31
IOCE1 (Output Sink Select Control Register) .................................................. 32
IOCF1 (Pull-high Control Register)................................................................... 33
Overview........................................................................................................... 66
Function Description ......................................................................................... 66
Programming the Related Registers ................................................................ 68
Product Specification (V1.0) 12.01.2006
Contents
6.10 Comparator..................................................................................................... 68
6.10.1
6.10.2
6.10.3
6.10.4
6.10.5
External Reference Signal................................................................................ 69
Comparator Outputs ......................................................................................... 69
Using a Comparator as an Operation Amplifier ................................................ 70
Comparator Interrupt ........................................................................................ 70
Wake-up from Sleep Mode ............................................................................... 70
6.11 Oscillator ........................................................................................................ 71
6.11.1
6.11.2
6.11.3
6.11.4
Oscillator Modes ............................................................................................... 71
Crystal Oscillator/Ceramic Resonators (Crystal) .............................................. 71
External RC Oscillator Mode ............................................................................ 73
Internal RC Oscillator Mode ............................................................................. 74
6.12 Power-on Considerations................................................................................ 75
6.12.1 Programmable WDT Time-out Period .............................................................. 75
6.12.2 External Power-on Reset Circuit ...................................................................... 75
6.12.3 Residual Voltage Protection ............................................................................. 76
6.13 Code Option ................................................................................................... 77
6.13.1 Code Option Register (Word 0) ........................................................................ 77
6.13.2 Code Option Register (Word 1) ........................................................................ 78
6.13.3 Customer ID Register (Word 2) ........................................................................ 79
6.14 Low Voltage Detector...................................................................................... 80
6.14.1 Low Voltage Reset............................................................................................ 80
6.14.2 Low Voltage Detector........................................................................................ 80
6.14.2.1 IOCD1 (LVD Control Register) .......................................................... 80
6.14.2.2 RE (Interrupt Status 2 & Wake-up Control Register) ......................... 81
6.14.3 Programming Process ...................................................................................... 82
6.15 Instruction Set................................................................................................. 83
7
Absolute Maximum Ratings.................................................................................. 85
8
DC Electrical Characteristics................................................................................ 85
8.1
8.2
AD Converter Characteristics ......................................................................... 86
Comparator (OP) Characteristics.................................................................... 87
8.3
Device Characteristics .................................................................................... 88
9
AC Electrical Characteristic.................................................................................. 89
10
Timing Diagrams ................................................................................................... 90
Product Specification (V1.0) 12.01.2006
•v
Contents
APPENDIX
A.
B
Package Type ........................................................................................................ 91
Packaging Configuration ...................................................................................... 91
B.1 14-Lead Plastic Dual in line (PDIP) — 300 mil ................................................ 91
B.2 14-Lead Plastic Small Outline (SOP) — 150 mil ............................................. 92
B.3 18-Lead Plastic Dual in line (PDIP) — 300 mil ................................................ 91
B.4 18-Lead Plastic Small Outline (SOP) — 300 mil ............................................. 92
B.5 20-Lead Plastic Shrink Small Outline (SSOP) — 209 mil................................ 93
B.6 20-Lead Plastic Dual-in-line (PDIP) — 300 mil................................................ 94
C
B.7 20-Lead Plastic Small Outline (SOPP) — 300 mil........................................... 95
Quality Assurance and Reliability ........................................................................ 96
C.1 Address Trap Detect ....................................................................................... 96
Specification Revision History
Specification Revision History
Doc. Version
1.0
vi •
Revision Description
Initial released version
Date
2006/12/01
Product Specification (V1.0) 12.01.2006
EM78P341N/342N/343N
8-Bit Microprocessor with OTP ROM
1
General Description
The EM78P341N, EM78P342N and EM78P343N are 8-bit microprocessors designed and developed with low-power and
high-speed CMOS technology. The series have an on-chip 2K×13-bit Electrical One Time Programmable Read Only
Memory (OTP-ROM). It provides a protection bit to prevent intrusion of user’s OTP memory code. Three Code option bits
are also available to meet user’s requirements.
With enhanced OTP-ROM features, the EM78P341N, EM78P342N and EM78P343N provide a convenient way of
developing and verifying user’s programs. Moreover, this OTP device offers the advantages of easy and effective
program updates, using development and programming tools. User can avail of the ELAN Writer to easily program his
development code.
2
„
Features
•
•
•
•
•
•
•
•
„
•
8 level stacks for subroutine nesting
„
4 programmable Level Voltage Reset (LVR) : 4.0V,
3.5V, 2.7V, 1.8V (POR)
•
Less than 1.5 mA at 5V/4MHz
Typically 15 µA, at 3V/32kHz
•
Typically 1 µA, during sleep mode
Three bidirectional I/O ports : P5, P6, P7
•
„
18 I/O pins
8 Programmable pull-down I/O pins
•
•
•
•
•
16 programmable pull-high I/O pins
8 Programmable open-drain I/O pins
External interrupt : P60
Commercial version:
Operating voltage range: 1.9V~5.5V
„
•
•
•
•
Commercial version:
Operating voltage range: 0°C ~ 70°C
Industrial version:
Operating voltage range: -40°C ~ 85°C
Operating frequency range:
Main clock
•
•
Crystal mode:
DC ~ 20MHz/2clks @ 4V; DC ~16 MHz/2clks @ 3V
DC ~ 4MHz/2clks @ 1.9V
ERC mode:
DC ~ 4MHz/2clks @ 5V; DC ~ 4MHz/2clks @ 3V
DC ~ 8MHz/2clks @ 3V; DC ~ 250ns inst. cycle @
3V
Product Specification (V1.0) 12.01.2006
(This specification is subject to change without further notice)
„
8-bit real time clock/counter (TCC) with selective signal
sources, trigger edges, and overflow interrupt
8-bit real time clock/counter (TCCA, TCCC) and 16-bit
real time clock/counter (TCCB) with selective signal
sources, trigger edges, and overflow interrupt
8-bit channels Analog-to-Digital Converter with 12-bit
resolution
One pair of comparators or OP
TCC, TCCA, TCCB, TCCC overflow interrupt
Input-port status changed interrupt (wake-up from
sleep mode)
External interrupt
ADC completion interrupt
IR/PWM interrupt
Comparator status change interrupt
Low voltage detect (LVD) interrupt
Special features
•
Industrial version:
Operating voltage range: 2.1V~5.5V
Easily implemented IR (or infrared remote control)
Seven available interrupts:
•
•
Wake-up port : P5
IRC mode:
Oscillation mode : 4MHz, 16MHz, 1MHz, 455kHz
Process deviation : Typ±3%, Max±5%
Temperature deviation : ±10% (-40°C~85°C )
Peripheral configuration
•
•
4 programmable Level Voltage Detector (LVD) :
4.5V, 4.0V, 3.3V, 2.2V
Operating temperature range: -40~85°C
•
„
80×8 bits on chip registers (SRAM)
Operating voltage range:
•
„
2K×13 bits on chip ROM
I/O port configuration
•
•
•
•
•
•
•
„
•
CPU configuration
Programmable free running watchdog timer
(4.5ms:18ms)
Power saving Sleep mode
Selectable Oscillation mode
Power-on voltage detector available (1.7 V± 0.1V)
Package type:
•
•
•
•
•
•
•
14-pin DIP 300mil
:
EM78P341NP
14-pin SOP 150mil
:
EM78P341NM
18-pin DIP 300mil
:
EM78P342NP
18-pin SOP 300mil
:
EM78P342NM
20-pin DIP 300mil
:
EM78P343NP
20-pin SOP 300mil
:
20-pin SSOP 209mil
EM78P343NM
:
EM78P343NKM
•1
EM78P341N/342N/343N
8-Bit Microprocessor with OTP ROM
3 Pin Assignment
(1)
14-Pin DIP/SOP
(2)
18
2
17
P54/TCC/VREF
3
16
P55/OSCI/ADC6
15
P70/OSCO/ADC5
P51/ADC1
13
P50/ADC0
/RESET
4
12
P55/OSCI/ADC6
Vss
5
11
P70/OSCO/ADC5
P60//INT
6
10
VDD
P53/ADC3
2
3
/RESET
4
EM78P341NP
EM78P341NM
14
EM78P342NP
EM78P342NM
1
1
P54/TCC/VREF
P51/ADC1
P52/ADC2
P53/ADC3
P52/ADC2
14
13
P50/ADC0
VDD
P67/IR OUT/ADC4
Vss
5
P61/TCCA
7
P60//INT
6
9
P67/IR OUT/ADC4
P62/TCCB
8
11
P65/CIN+
P61/TCCA
7
8
P66/CIN-
P63/TCCC
9
10
P64/CO
Fig. 3-1 14-pin EM78P341NP/NM
(3)
18-Pin DIP/SOP
12
P66/CIN-
Fig. 3-2 18-pin EM78P342NP/NM
20-Pin DIP/SOP/SSOP
1
20
P57/ADC7
2
19
P51/ADC1
P53/ADC3
3
18
P50/ADC0
P54/TCC/VREF
4
17
P55/OSCI/ADC6
16
P70/OSCO/ADC5
EM78P343N
P56
P52/ADC2
/RESET
5
Vss
6
P60//INT
7
P61/TCCA
8
13
P62/TCCB
9
12
P65/CIN+
P63/TCCC
10
11
P64/CO
15
VDD
14
P67/IR OUT/ADC4
P66/CIN-
Fig. 3-3 20-pin EM78P343NP/NM/NKM
2•
Product Specification (V1.0) 12.01.2006
(This specification is subject to change without further notice)
EM78P341N/342N/343N
8-Bit Microprocessor with OTP ROM
4 Functional Block Diagram
PC
ROM
Ext.
OSC.
Int.
RC
Start-up
timer
Ext.
RC
WDT
Instruction
Register
P70
P71
8-level stack
(13 bit)
TCCB
TCCB
Instruction
Decoder
TCCC
TCCC
Reset
Infrared
remote
control
circuit
P6
P60
P61
P62
P63
P64
P65
P66
P67
TCCA
TCCA
Oscillation
Generation
IR out
TCC
TCC
Mux
ALU
R4
LVD
RAM
P5
ACC
R3 (Status
Reg.)
P50
P51
P52
P53
P54
P55
P56
P57
Interrupt
control
register
LVR
Interrupt
circuit
ADC
Comparator
(CO) or OP
Ext INT
Ain0~3
Cin+ Cin- CO
Fig. 4-1 EM78P341N/342N/343N Functional Block Diagram
Product Specification (V1.0) 12.01.2006
(This specification is subject to change without further notice)
•3
EM78P341N/342N/343N
8-Bit Microprocessor with OTP ROM
5
Pin Description
5.1 EM78P341NP/M
Symbol
Type
Function
P50~P55
1~3, 12~14
I/O
6-bit General purpose input/output pins
Pull-high/pull-down
Wake up from sleep mode when the pin status changes
Default value at power-on reset
P60, P61
66, 67
6~9
I/O
4-bit General purpose input/output pins
Open drain
Default value at power-on reset
P70~P71
11, 4
I/O
2-bit General purpose input/output pins
Default value at power-on reset
6
I
External interrupt pin triggered by a falling or a rising edge.
Defined by CONT <7>
1, 2, 9
11~14
I
7-bit Analog-to-Digital Converter
Defined by ADCON (R9)<1:0>
3
I
External reference voltage for ADC
Defined by ADCON (R9) <7>.
4
I
General-purpose Input only
If it remains at logic low, the device will be reset
Wake-up from sleep mode when pin status changes
Voltage on /RESET must not exceed Vdd during normal mode
TCC, TCCA
3, 7
I
External Counter input
TCC defined by CONT<5>
TCCA defined by IOC80 <1>
OSCI
12
I
Crystal type: Crystal input terminal or external clock input pin
RC type: RC oscillator input pin
O
Crystal type: Output terminal for crystal oscillator or external
clock input pin.
RC type: Clock output with a duration of one instruction cycle
time. The prescaler is determined by the
CONT register.
External clock signal input.
/INT
ADC0~ADC6
VREF
/RESET
OSCO
4•
Pin No.
11
IR OUT
13
O
IR mode output pin.
Driving current = 10mA when the output voltage drops to
Vdd-0.5V at Vdd = 5V
Sinking current = 15mA when the output voltage drops to
GND+0.5V at Vdd = 5V
VDD
10
–
Power supply
VSS
5
–
Ground
Product Specification (V1.0) 12.01.2006
(This specification is subject to change without further notice)
EM78P341N/342N/343N
8-Bit Microprocessor with OTP ROM
5.2 EM78P342NP/M
Symbol
Pin No.
Type
Function
I/O
6-bit General purpose input/output pins
Pull-high/pull-down
Wake up from sleep mode when the pin status changes
Default value at power-on reset
P60~67
6~13
I/O
8-bit General purpose input/output pins
Open drain
Default value at power-on reset
P70~P71
15, 4
I/O
2-bit General purpose input/output pins
Default value at power-on reset
6
I
External interrupt pin triggered by a falling or a rising edge.
Defined by CONT <7>
1, 2, 13
15~18
I
7-bit Analog-to-Digital Converter
Defined by ADCON (R9)<1:0>
VREF
3
I
CINCIN+
CO
12
11
10
I
I
O
P50~P55
/INT
ADC0~ADC6
/RESET
1~3, 16~18
4
External reference voltage for ADC
Defined by ADCON (R9) <7>.
“-“ : the input pin of Vin- of the comparator
“+” : the input pin of Vin+ of the comparator
Pin CO is the comparator output
Defined by IOC80 <4:3>
I
General-purpose Input only
If it remains at logic low, the device will be reset
Wake-up from sleep mode when pin status changes
Voltage on /RESET must not exceed Vdd during normal mode
TCC, TCCA
TCCB, TCCC
3, 7
8~9
I
External Counter input
TCC defined by CONT<5>
TCCA defined by IOC80 <1>
TCCB defined by IOC90 <5>
TCCC defined by IOC90 <1>
OSCI
16
I
Crystal type: Crystal input terminal or external clock input pin
RC type: RC oscillator input pin
O
Crystal type: Output terminal for crystal oscillator or external
clock input pin.
RC type: Clock output with a duration of one instruction cycle
time. The prescaler is determined by the
CONT register.
External clock signal input.
OSCO
15
IR OUT
13
O
IR mode output pin.
Capable of driving and sinking current = 20mA when the output
voltage drops to 0.7Vdd at rise to 0.3Vdd at
Vdd = 5V
VDD
14
–
Power supply
VSS
5
–
Ground
Product Specification (V1.0) 12.01.2006
(This specification is subject to change without further notice)
•5
EM78P341N/342N/343N
8-Bit Microprocessor with OTP ROM
5.3 EM78P343NP/M/KM
Symbol
Type
Function
1~4, 17~20
I/O
8-bit General purpose input/output pins
Pull-high/pull-down
Wake up from sleep mode when the pin status changes
Default value at power-on reset
P60~67
7~14
I/O
8-bit General purpose input/output pins
Open drain
Default value at power-on reset
P70~P71
16, 5
I/O
2-bit General purpose input/output pins
Default value at power-on reset
7
I
External interrupt pin triggered by a falling or a rising edge.
Defined by CONT <7>
2, 3, 14
16~20
I
8-bit Analog-to-Digital Converter
Defined by ADCON (R9) <2:0>
VREF
4
I
CINCIN+
CO
13
12
11
I
I
O
P50~P57
/INT
ADC0~ADC7
/RESET
TCC, TCCA
TCCB, TCCC
OSCI
OSCO
6•
Pin No.
External reference voltage for ADC
Defined by ADCON (R9) <7>.
“-“ : the input pin of Vin- of the comparator
“+” : the input pin of Vin+ of the comparator
Pin CO is the comparator output
Defined by IOC80 <4:3>
I
General-purpose Input only
If it remains at logic low, the device will be reset
Wake-up from sleep mode when pin status changes
Voltage on /RESET must not exceed Vdd during normal mode
4, 8
9~10
I
External Counter input
TCC defined by CONT<5>
TCCA defined by IOC80 <1>
TCCB defined by IOC90 <5>
TCCC defined by IOC90 <1>
17
I
Crystal type: Crystal input terminal or external clock input pin
RC type: RC oscillator input pin
O
Crystal type: Output terminal for crystal oscillator or external
clock input pin.
RC type: Clock output with a duration of one instruction cycle
time. The prescaler is determined by the
CONT register.
External clock signal input.
5
16
IR OUT
14
O
IR mode output pin.
Capable of driving and sinking current = 20mA when the output
voltage drops to 0.7Vdd at rise to 0.3Vdd at
Vdd = 5V
VDD
15
–
Power supply
VSS
6
–
Ground
Product Specification (V1.0) 12.01.2006
(This specification is subject to change without further notice)
EM78P341N/342N/343N
8-Bit Microprocessor with OTP ROM
6
Function Description
6.1 Operational Registers
6.1.1 R0 (Indirect Address Register)
R0 is not a physically implemented register. Its major function is to perform as an
indirect address pointer. Any instruction using R0 as a pointer, actually accesses the
data pointed by the RAM Select Register (R4).
6.1.2 R1 (Time Clock /Counter)
„
Incremented by an external signal edge which is defined by the TE bit (CONT-4)
through the TCC pin, or by the instruction cycle clock.
„
Writable and readable as any other registers
„
The TCC prescaler counter (IOCC1) is assigned to TCC
„
The contents of the IOCC1 register is cleared whenever –
• a value is written to the TCC register.
• a value is written to the TCC prescaler bits (Bits 3, 2, 1, 0 of the CONT register)
• there is power-on reset, /RESET, or WDT time out reset.
6.1.3 R2 (Program Counter) and Stack
R3
A10
A9 A8
A7
~
A0
Hardware Interrupt Vector
01 PAGE1 0400~07FF
000H
003H
~
021H
Stack Level 1
Stack Level 2
Stack Level 3
Stack Level 4
Stack Level 5
Stack Level 6
Stack Level 7
Stack Level 8
On-chip Program
3FEH
Memory
User Memory Space
CALL
RET
RETL
RETI
00 PAGE0 0000~03FF
Reset Vector
7FFH
Fig. 6-1 Program Counter Organization
„
R2 and hardware stacks are 11-bit wide. The structure is depicted in the table
under Section 6.1.3.1, Data Memory Configuration (next page).
„
Generates 2K×13 bits on-chip ROM addresses to the relative programming
instruction codes. One program page is 1024 words long.
„
The contents of R2 are all set to "0"s when a RESET condition occurs.
Product Specification (V1.0) 12.01.2006
(This specification is subject to change without further notice)
•7
EM78P341N/342N/343N
8-Bit Microprocessor with OTP ROM
„
"JMP" instruction allows direct loading of the lower 10 program counter bits. Thus,
"JMP" allows PC to jump to any location within a page.
„
"CALL" instruction loads the lower 10 bits of the PC, and then PC+1 is pushed into
the stack. Thus, the subroutine entry address can be located anywhere within a
page.
„
"RET" ("RETL k", "RETI") instruction loads the program counter with the contents
of the top of stack.
„
"ADD R2, A" allows a relative address to be added to the current PC, and the ninth
and above bits of the PC will increase progressively.
„
"MOV R2, A" allows loading of an address from the "A" register to the lower 8 bits of
the PC, and the ninth and tenth bits (A8 ~ A9) of the PC will remain unchanged.
„
Any instruction (except “ADD R2,A”) that is written to R2 (e.g., "MOV R2, A", "BC
R2, 6",⋅⋅⋅⋅⋅) will cause the ninth bit and the tenth bit (A8 ~ A9) of the PC to remain
unchanged.
„
In the case of EM78P341N/342N/343N, the most significant bit (A10) will be loaded
with the content of PS0 in the status register (R3) upon execution of a "JMP",
"CALL", or any other instructions set which write to R2.
„
All instructions are single instruction cycle (fclk/2 or fclk/4) except for the
instructions that are written to R2. Note that these instructions need one or two
instructions cycle as determined by Code Option Register CYES bit.
8•
Product Specification (V1.0) 12.01.2006
(This specification is subject to change without further notice)
EM78P341N/342N/343N
8-Bit Microprocessor with OTP ROM
6.1.3.1 Data Memory Configuration
Address
R Page Registers
00
R0 (Indirect Addressing Register)
Reserve
Reserve
01
R1 (Timer Clock Counter)
Reserve
Reserve
02
R2 (Program Counter)
Reserve
Reserve
03
R3 (Status Register)
Reserve
Reserve
04
R4 (RAM Select Register)
Reserve
Reserve
05
R5 (Port 5)
IOC50 (I/O Port Control Register)
IOC51 (TCCA Counter)
06
R6 (Port 6)
IOC60 (I/O Port Control Register)
IOC61 (TCCB LSB Counter)
07
R7 (Port 7)
IOC70 (I/O Port Control Register)
IOC71 (TCCB HSB Counter)
08
R8 (ADC Input Select Register
IOC80
09
R9 (ADC Control Register)
IOC90
0A
0B
0C
0D
0E
0F
10
︰
1F
20
：
3F
RA (ADC Offset Calibration
Register)
(Converted
value
RB
AD11~AD4 of ADC)
RC (Converted value
AD11~AD8 of ADC)
(Converted value
RD
AD7~AD0 of ADC)
RE (Interrupt Status 2 and
Wake-up Control Register
RF (Interrupt Status Register 1)
IOCX0 Page Registers
IOCA0
IOCB0
IOCC0
(Comparator and TCCA
Control Register)
(TCCB and TCCC
Control Register)
(IR and TCCC Scale
Control Register)
(Pull-down Control
Register)
(Open-drain Control
Register)
IOCX1 Page Registers
IOC81 (TCCC Counter)
IOC91 (Low-Time Register)
IOCA1 (High-Time Register)
IOCB1
(High-Time and Low-Time
Scale Control Register)
IOCC1 (TCC Prescaler Control)
IOCD0 (Pull-high Control Register) IOCD1 (LVD Control Register)
IOCE0 (WDT Control Register and
Interrupt Mask Register 2)
IOCE1 (High Output Sink Current)
IOCF0 (Interrupt Mask Register 1)
IOCF1 (Pull-high Control Register)
General Registers
Bank 0
Bank 1
Product Specification (V1.0) 12.01.2006
(This specification is subject to change without further notice)
•9
EM78P341N/342N/343N
8-Bit Microprocessor with OTP ROM
6.1.4 R3 (Status Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RST
IOCS
-
T
P
Z
DC
C
Bit 7 (RST): Bit of reset type
Set to “1” if wake-up from sleep on pin change, comparator status
change, or AD conversion completed. Set to “0” if wake-up from other
reset types.
Bit 6 (IOCS): Select the Segment of IO control register
0 = Segment 0 (IOC50 ~ IOCF0) selected
1 = Segment 1 (IOC51 ~ IOCC1) selected
Bit 5:
Not used (reserved)
Bit 4 (T):
Time-out bit. Set to “1” by the "SLEP" and "WDTC" commands or during
power on, and reset to “0” by WDT time-out (see Section 6.5.2, The T
and P Status under Status Register for more details).
Bit 3 (P):
Power-down bit. Set to “1” during power-on or by a "WDTC" command
and reset to “0” by a "SLEP" command (see Section 6.5.2, The T and P
Status under Status Register for more details).
Bit 2 (Z):
Zero flag. Set to "1" if the result of an arithmetic or logic operation is
zero.
Bit 1 (DC):
Auxiliary carry flag
Bit 0 (C):
Carry flag
6.1.5 R4 (RAM Select Register)
Bit 7:
Set to “0” all the time
Bit 6:
Used to select Bank 0 or Bank 1 of register
Bits 5~0:
Used to select a register (address: 00~0F, 10~3F) in the indirect
addressing mode
See the table under Section 6.1.3.1, Data Memory Configuration.
10 •
Product Specification (V1.0) 12.01.2006
(This specification is subject to change without further notice)
EM78P341N/342N/343N
8-Bit Microprocessor with OTP ROM
6.1.6 R5 ~ R6 (Port 5 ~ Port 6)
R5 & R6 are I/O registers
The upper two bits of R5 are fixed to “0” (if EM78P342N is selected).
Only the lower six bits of R5 are available (this applies to EM78P342N only
since EM78P343N can use all the bits)
6.1.7 R7 (Port 7)
Bit
7
6
5
4
3
2
1
0
EM78P342N/343N
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
I/O
I/O
ICE342N
C3
C2
C1
C0
RCM1
RCM0
I/O
I/O
NOTE
„
R7 is an I/O register
„
For EM78P342N/343N, only the lower 2 bit of R7 is available.
Bit 7 ~ Bit 2:
[With EM78P342N/343N]: Unimplemented, read as ‘0’.
[With Simulator (C3~C0, RCM1, & RCM0)]: IRC calibration bits in IRC oscillator
mode. In IRC oscillator mode of ICE342N simulator, these
are the IRC mode selection bits and IRC calibration bits.
Bit 7 ~ Bit 4 (C3 ~ C0): Calibrator of internal RC mode
C3
C2
C1
C0
Frequency (MHz)
0
0
0
0
(1-36%) x F
0
0
0
1
(1-31.5%) x F
0
0
1
0
(1-27%) x F
0
0
1
1
(1-22.5%) x F
0
0
1
1
0
0
0
1
(1-18%) x F
(1-13.5%) x F
0
1
1
0
(1-9%) x F
0
1
1
1
(1-4.5%) x F
1
1
1
1
F (default)
1
1
1
0
(1+4.5%) x F
1
1
0
1
(1+9%) x F
1
1
0
0
(1+135%) x F
1
0
1
1
(1+18%) x F
1
0
1
0
(1+22.5%) x F
1
0
0
1
(1+27%) x F
1
0
0
0
(1+31.5%) x F
Note: 1. Frequency values shown are theoretical and taken from an instance of a high frequency mode.
Hence, they are shown for reference only. Definite values depend on the actual process.
2. Similar way of calculation is also applicable for low frequency mode.
Product Specification (V1.0) 12.01.2006
(This specification is subject to change without further notice)
• 11
EM78P341N/342N/343N
8-Bit Microprocessor with OTP ROM
Bit 3 & Bit 2 (RCM1, RCM0):
IRC mode selection bits
RCM 1
RCM 0
Frequency (MHz)
1
1
4 (default)
1
0
16
0
1
1
0
0
455kHz
6.1.8 R8 (AISR: ADC Input Select Register)
The AISR register defines the I/O Port as analog inputs or as digital I/O, individually.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ADE7
ADE6
ADE5
ADE4
ADE3
ADE2
ADE1
ADE0
Bit 7 (ADE7): AD converter enable bit of P57 pin
0 = Disable ADC7, P57 functions as I/O pin
1 = Enable ADC7 to function as analog input pin
Bit 6 (ADE6): AD converter enable bit of P55 pin
0 = Disable ADC6, P55 functions as I/O pin
1 = Enable ADC6 to function as analog input pin
Bit 5 (ADE5): AD converter enable bit of P70 pin
0 = Disable ADC5, P70 functions as I/O pin
1 = Enable ADC5 to function as analog input pin
Bit 4 (ADE4): AD converter enable bit of P67 pin
0 = Disable ADC4, P67 functions as I/O pin
1 = Enable ADC4 to function as analog input pin
Bit 3 (ADE3): AD converter enable bit of P53 pin
0 = Disable ADC3, P53 functions as I/O pin
1 = Enable ADC3 to function as analog input pin
Bit 2 (ADE2): AD converter enable bit of P52 pin
0 = Disable ADC2, P52 functions as I/O pin
1 = Enable ADC2 to function as analog input pin
Bit 1 (ADE1): AD converter enable bit of P51 pin
0 = Disable ADC1, P51 functions as I/O pin
1 = Enable ADC1 to function as analog input pin
Bit 0 (ADE0): AD converter enable bit of P50 pin.
0 = Disable ADC0, P50 function as I/O pin
1 = Enable ADC0 to function as analog input pin
12 •
Product Specification (V1.0) 12.01.2006
(This specification is subject to change without further notice)
EM78P341N/342N/343N
8-Bit Microprocessor with OTP ROM
NOTE
The P55/OSCI/ADC6 pin cannot be applied to OSCI and ADC6 at the same time.
If P55/OSCI/ADC6 functions as OSCI oscillator input pin, then ADE6 bit for R8 must
be ”0” and ADIS2~0 do not select “ 110”. The P55/OSCI/ADC6 pin priority is as follows:
P55/OSCI/ADC6 Pin Priority
High
Medium
Low
OSCI
ADC6
P55
The P70/OSCO/ADC5 pin cannot be applied to OSCO and ADC5 at the same time.
If P70/OSCO/ADC5 acts as OSCO oscillator input pin, then ADE5 bit for R8 must be ”0”
and ADIS2~0 do not select “101”. The P70/OSCO/ADC5 pin priority is as follows:
P70/OSCO/ADC5 Pin Priority
High
Medium
Low
OSCO
ADC5
P70
The P66/IR OUT/ADC4 pin cannot be applied to IR OUT and ADC4 at the same time.
If P67/IR OUT/ADC4 functions as ADC4 analog input pin, then IROUTE bit for IOCA0
must be “0”..
If P67/IR OUT/ADC4 functions as IR OUT analog input pin, then ADE4 bit for R8 must
be ”0” and ADIS2~0 do not select “100”.
The P67/IR OUT/ADC4 pin priority is as follows:
P67/IR OUT/ADC4 Pin Priority
6.1.9
High
Medium
Low
ADC7
IR OUT
P67
R9 (ADCON: ADC Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
VREFS
CKR1
CKR0
ADRUN
ADPD
ADIS2
ADIS1
ADIS0
Bit 7 (VREFS): The input source of the Vref of the ADC
0 = The Vref of the ADC is connected to Vdd (default value), and the
VREF/TCC/P54 pin carries out the function of P54
1 = The Vref of the ADC is connected to VREF/TCC/P54
Product Specification (V1.0) 12.01.2006
(This specification is subject to change without further notice)
• 13
EM78P341N/342N/343N
8-Bit Microprocessor with OTP ROM
NOTE
„
The P54/TCC/VREF pin cannot be applied to TCC and VREF at the same time.
If P53/TCC/VREF functions as VREF analog input pin, then CONT Bit 5 “TS”
must be “0.”
„
The VREF/TCC/P54 Pin Priority is as follows:
P53/TCC/VREF Pin Priority
High
Medium
Low
VREF
TCC
P54
Bit 6 & Bit 5 (CKR1 & CKR0): The prescaler of ADC oscillator clock rate
00 = 1: 16 (default value)
01 = 1: 4
10 = 1: 64
11 = 1: 8
CPUS
1
1
1
1
0
CKR1:CKR0
00
01
10
11
XX
Operation Mode
Max. Operation Frequency
Fosc/16
Fosc/4
Fosc/64
Fosc/8
Internal RC
4MHz
1MHz
16MHz
2MHz
-
Bit 4 (ADRUN): ADC starts to RUN.
1 = an AD conversion is started. This bit can be set by software
0 = Reset upon completion of the conversion. This bit cannot be
reset through software
Bit 3 (ADPD):
ADC Power-down mode
1 = ADC is operating
0 = Switch off the resistor reference to save power even while the
CPU is operating
Bit 2 ~ Bit 0 (ADIS2 ~ADIS0): Analog Input Select
000 = ADIN0/P50
001 = ADIN1/P51
010 = ADIN2/P52
011 = ADIN3/P53
100 = ADIN0/P67
101 = ADIN1/P70
110 = ADIN2/P55
111 = ADIN3/P57
These bits can only be changed when the ADIF bit (see Section 6.1.14, RE (Interrupt
Status 2 & Wake-up Control Register)) and the ADRUN bit are both LOW.
14 •
Product Specification (V1.0) 12.01.2006
(This specification is subject to change without further notice)
EM78P341N/342N/343N
8-Bit Microprocessor with OTP ROM
6.1.10 RA (ADOC: ADC Offset Calibration Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
CALI
SIGN
VOF[2]
VOF[1]
VOF[0]
“0”
“0”
“0”
Bit 7 (CALI):
Calibration enable bit for ADC offset
0 = Calibration disable
1 = Calibration enable
Bit 6 (SIGN):
Polarity bit of offset voltage
0 = Negative voltage
1 = Positive voltage
Bit 5 ~ Bit 3 (VOF[2] ~ VOF[0]): Offset voltage bits
Bit 2 ~ Bit 0:
VOF[2]
VOF[1]
VOF[0]
EM78P342N/343N
ICE342N
0
0
0
0LSB
0LSB
0
0
1
2LSB
2LSB
0
1
0
4LSB
4LSB
0
1
1
6LSB
6LSB
1
0
0
8LSB
8LSB
1
1
0
1
1
0
10LSB
12LSB
10LSB
12LSB
1
1
1
14LSB
14LSB
Unimplemented, read as ‘0’
6.1.11 RB (ADDATA: Converted Value of ADC)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
AD11
AD10
AD9
AD8
AD7
AD6
AD5
AD4
When the AD conversion is completed, the result is loaded into the ADDATA. The
ADRUN bit is cleared, and the ADIF (see Section 6.1.14, RE (Interrupt Status 2 &
Wake-up Control Register)) is set.
RB is read only.
6.1.12 RC (ADDATA1H: Converted Value of ADC)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
1
0
“0”
“0”
“0”
“0”
AD11
AD10
AD9
AD8
When the AD conversion is completed, the result is loaded into the ADDATA1H. The
ADRUN bit is cleared, and the ADIF (see Section 6.1.14, RE (Interrupt Status 2 &
Wake-Up Control Register)) is set.
RC is read only
Product Specification (V1.0) 12.01.2006
(This specification is subject to change without further notice)
• 15
EM78P341N/342N/343N
8-Bit Microprocessor with OTP ROM
6.1.13 RD (ADDATA1L: Converted Value of ADC)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
When the AD conversion is completed, the result is loaded into the ADDATA1L. The
ADRUN bit is cleared, and the ADIF (see Section 6.1.14, RE (Interrupt Status 2 &
Wake-up Control Register)) is set.
RD is read only
6.1.14 RE (Interrupt Status 2 & Wake-up Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
/LVD
LVDIF
ADIF
CMPIF
ADWE
CMPWE
ICWE
LVDWE
NOTE
■ RE <5,4> can be cleared by instruction but cannot be set.
■ IOCE0 is the interrupt mask register.
■ Reading RE will result to "logic AND" of RE and IOCE0.
Bit 7 (/LVD):
Low voltage Detector state. This is a read only bit. When the VDD
pin voltage is lower than LVD voltage interrupt level (selected by
LVD1 and LVD0), this bit will be cleared.
0 = low voltage is detected
1 = low voltage is not detected or LVD function is disabled
Bit 6 (LVDIF):
Bit 5 (ADIF):
Low Voltage Detector interrupt flag
LVDIF is reset to “0” by software.
Interrupt flag for analog to digital conversion. Set when AD
conversion is completed. Reset by software.
0 = no interrupt occurs
1 = interrupt request
Bit 4 (CMPIF):
Comparator interrupt flag. Set when a change occurs in the
Comparator output. Reset by software.
0 = no interrupt occurs
1 = interrupt request
Bit 3 (ADWE):
ADC wake-up enable bit
0 = Disable ADC wake-up
1 = Enable ADC wake-up
When AD Conversion enters sleep mode, this bit must be set to
“Enable“.
16 •
Product Specification (V1.0) 12.01.2006
(This specification is subject to change without further notice)
EM78P341N/342N/343N
8-Bit Microprocessor with OTP ROM
Bit 2 (CMPWE): Comparator wake-up enable bit
0 = Disable Comparator wake-up
1 = Enable Comparator wake-up
When Comparator enters sleep mode, this bit must be set to “Enable“.
Bit 1 (ICWE):
Port 5 input change to wake-up status enable bit
0 = Disable Port 5 input change to wake-up status
1 = Enable Port 5 input change to wake-up status
When Port 5 change enters sleep mode, this bit must be set to “Enable“.
Bit 0 (LVDWE): Low Voltage Detect wake-up enable bit
0 = Disable Low Voltage Detect wake-up
1 = Enable Low Voltage Detect wake-up
When the Low Voltage Detect is used to enter an interrupt vector or to
wake-up the IC from sleep with Low Voltage Detect running, the
LVDWE bit must be set to “Enable“.
6.1.15 RF (Interrupt Status 2 Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
LPWTIF
HPWTIF
TCCCIF
TCCBIF
TCCAIF
EXIF
ICIF
TCIF
NOTE
■ “1” means there is interrupt request; “0” means no interrupt occurs
■ RF can be cleared by instruction but cannot be set.
■ IOCF0 is the relative interrupt mask register.
■ Reading RF will result to "logic AND" of RF and IOCF0.
Bit 7 (LPWTIF): Internal low-pulse width timer underflow interrupt flag for IR/PWM
function. Reset by software.
Bit 6 (HPWTIF): Internal high-pulse width timer underflow interrupt flag for IR/PWM
function. Reset by software.
Bit 5 (TCCCIF): TCCC overflow interrupt flag. Set when TCCC overflows. Reset by
software.
Bit 4 (TCCBIF): TCCB overflow interrupt flag. Set when TCCC overflows. Reset by
software.
Bit 3 (TCCAIF):
TCCA overflow interrupt flag. Set when TCCC overflows. Reset by
software.
Bit 2 (EXIF):
External interrupt flag. Set by falling edge on /INT pin. Reset by
software.
Bit 1 (ICIF):
Port 5 input status change interrupt flag. Set when Port 5 input
changes. Reset by software.
Bit 0 (TCIF):
TCC overflow interrupt flag. Set when TCC overflows. Reset by
software.
6.1.16 R10 ~ R3F
All of these are 8-bit general-purpose registers.
Product Specification (V1.0) 12.01.2006
(This specification is subject to change without further notice)
• 17
EM78P341N/342N/343N
8-Bit Microprocessor with OTP ROM
6.2 Special Purpose Registers
6.2.1 A (Accumulator)
Internal data transfer operation, or instruction operand holding usually involves the
temporary storage function of the Accumulator. The Accumulator is not an
addressable register.
6.2.2 CONT (Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTE
INT
TS
TE
PSTE
PST2
PST1
PST0
NOTE
■ The CONT register is both readable and writable.
■ Bit 6 is read only.
Bit 7 (INTE): INT signal edge
0 = interrupt occurs at a rising edge on the INT pin
1 = interrupt occurs at a falling edge on the INT pin
Bit 6 (INT):
Interrupt enable flag
0 = masked by DISI or hardware interrupt
1 = enabled by the ENI/RETI instructions
This bit is readable only.
Bit 5 (TS):
TCC signal source
0 = internal instruction cycle clock. P54 is bi-directional I/O pin.
1 = transition on the TCC pin
Bit 4 (TE):
TCC signal edge
0 = increment if the transition from low to high takes place on the TCC
pin
1 = increment if the transition from high to low takes place on the TCC
pin.
Bit 3 (PSTE): Prescaler enable bit for TCC
0 = prescaler disable bit. TCC rate is 1:1.
1 = prescaler enable bit. TCC rate is set as Bit 2 ~ Bit 0.
Bit 2 ~ Bit 0 (PST2 ~ PST0): TCC prescaler bits
PST2
PST1
PST0
TCC Rate
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1:2
1:4
1:8
1:16
1:32
1:64
1:128
1:256
Note: Tcc time-out period [1/Fosc x prescaler x 256 (Tcc cnt) x 1 (CLK=2)]
Tcc time-out period [1/Fosc x prescaler x 256 (Tcc cnt) x 2 (CLK=4)]
18 •
Product Specification (V1.0) 12.01.2006
(This specification is subject to change without further notice)
EM78P341N/342N/343N
8-Bit Microprocessor with OTP ROM
6.2.3 IOC50 ~ IOC70 (I/O Port Control Register)
„
"1" sets the relative I/O pin into high impedance, while "0" defines the relative I/O
pin as output.
„
Only the lower six bits of IOC50 can be defined (this applies to EM78P341N/342N
only since all bits of EM78P343N can be used).
„
Only Bit 0, Bit 1, Bit 6, Bit 7 of IOC60 can be defined (this applies to EM78P341N
only since all bits of EM78P343N can be used)
„
Only the lower two bits of IOC70 can be defined, the others bits are not available.
„
IOC50, IOC60, and IOC70 registers are all readable and writable
6.2.4 IOC80 (Comparator and TCCA Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
–
–
CMPOUT
COS1
COS0
TCCAEN
TCCATS
TCCATE
NOTE
■ Bits 4 ~ 0 of the IOC80 register are both readable and writable
■ EM78P341N cannot use the OP/comparator function
■ Bit 5 of the IOC80 register is readable only.
Bit 7 & Bit 6: Not used
Bit 5 (CMPOUT): Result of the comparator output. This bit is readable only.
Bit 4 & Bit 3 (COS1 & COS0): Comparator/OP Select bits
COS1
COS0
0
0
0
1
Function Description
Comparator and OP are not used. P64, P65, and P66 function as
normal I/O pin
Used as Comparator and P64 functions as normal I/O pin
1
0
Used as Comparator and P64 functions as Comparator output pin (CO)
1
1
Used as OP and P64 functions as OP output pin (CO)
Bit 2 (TCCAEN):
TCCA enable bit
0 = disable TCCA
1 = enable TCCA as a counter
Bit 1 (TCCATS):
TCCA signal source
0 =: internal instruction cycle clock. P61 is a bidirectional I/O pin.
1 = transit through the TCCA pin
Bit 0 (TCCATE):
TCCA signal edge
0 = increment if transition from low to high takes place on the
TCCA pin
1 = increment if transition from high to low takes place on the
TCCA pin
Product Specification (V1.0) 12.01.2006
(This specification is subject to change without further notice)
• 19
EM78P341N/342N/343N
8-Bit Microprocessor with OTP ROM
6.2.5 IOC90 (TCCB and TCCC Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TCCBHE
TCCBEN
TCCBTS
TCCBTE
–
TCCCEN
TCCCTS
TCCCTE
NOTE
The EM78P341N cannot define Bit 5, Bit 4, Bit 1, and Bit 0 of the IOC90.
Bit 7 (TCCBHE): Control bit is used to enable the most significant byte of the counter
1 = Enable the most significant byte of TCCBH
TCCB is a 16-bit counter.
0 = Disable the most significant byte of TCCBH (default value)
TCCB is an 8-bit counter.
Bit 6 (TCCBEN): TCCB enable bit
0 = disable TCCB
1 = enable TCCB as a counter
Bit 5 (TCCBTS) TCCB signal source
0 = internal instruction cycle clock. P62 is a bi-directional I/O pin.
1 = transit through the TCCB/P62 pin
Bit 4 (TCCBTE): TCCB signal edge
0 = increment if the transition from low to high takes place on the
TCCB pin
1 = increment if the transition from high to low takes place on the
TCCB pin
Bit 3:
Not used.
Bit 2 (TCCCEN): TCCC enable bit
0 = disable TCCC
1 = enable TCCC as a counter
Bit 1 (TCCCTS) TCCC signal source
0 = internal instruction cycle clock. P63 is a bidirectional I/O pin.
1 = transit through the TCCC/P63 pin
Bit 0 (TCCCTE): TCCC signal edge
0 = increment if the transition from low to high takes place on the
TCCC pin
1 = increment if the transition from high to low takes place on the
TCCC pin
20 •
Product Specification (V1.0) 12.01.2006
(This specification is subject to change without further notice)
EM78P341N/342N/343N
8-Bit Microprocessor with OTP ROM
6.2.6 IOCA0 (IR and TCCC Scale Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TCCCSE
TCCCS2
TCCCS1
TCCCS0
IRE
HF
LGP
IROUTE
Bit 7 (TCCCSE): Scale enable bit for TCCC
An 8-bit counter is provided as scale for TCCC and IR-Mode. When
in IR-Mode, TCCC counter scale uses the low-time segments of the
pulse generated by Fcarrier frequency modulation (see Fig. 6-11 in
Section 6.8.2, Function Description).
0 = scale disable bit, TCCC rate is 1:1
1 = scale enable bit, TCCC rate is set as Bit 6 ~ Bit 4
Bit 6 ~ Bit 4 (TCCCS2 ~ TCCCS0): TCCC scale bits
The TCCCS2 ~ TCCCS0 bits of the IOCA0 register are used to
determine the scale ratio of TCCC as shown below:
Bit 3 (IRE):
TCCCS2
TCCCS1
TCCCS0
TCCC Rate
0
0
0
1:2
0
0
1
1:4
0
1
0
1:8
0
1
1
1:16
1
0
0
1:32
1
0
1
1:64
1
1
0
1:128
1
1
1
1:256
Infrared Remote Enable bit
0 = Disable IRE, i.e., disable H/W Modulator Function. The IROUT
pin is fixed at a high level and the TCCC is an Up Counter.
1 = Enable IRE, i.e., enable H/W Modulator Function. Pin 67 is
defined as IROUT. If HP=1, the TCCC counter scale uses the
low-time segments of the pulse generated by the Fcarrier
frequency modulation (see Fig. 6-11 in Section 6.8.2, Function
Description). When HP=0, the TCCC is an Up Counter.
Bit 2 (HF):
High Frequency bit
0 = PWM application. IROUT waveform is achieved base on the
high-pulse width timer and low-pulse width timer which
determine the high time width and low time width respectively.
1 = IR application mode. The low-time segments of the pulse
generated by the Fcarrier frequency modulation (see Fig. 6-11 in
Section 6.8.2, Function Description)
Bit 1 (LGP):
Long Pulse.
0 = The high-time and low-time registers are valid
1 = The high-time register is ignored. A single pulse is generated.
Product Specification (V1.0) 12.01.2006
(This specification is subject to change without further notice)
• 21
EM78P341N/342N/343N
8-Bit Microprocessor with OTP ROM
Bit 0 (IROUTE): Control bit used to define the P67 (IROUT) pin function
0 = P67 defined as bi-directional I/O pin
1 = P67 defined as IROUT. Under this condition, the I/O control bit
of P67 (Bit 7 of IOC60) must be set to “0”
6.2.7 IOCB0 (Pull-Down Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
/PD57
/PD56
/PD55
/PD54
/PD53
/PD52
/PD51
/PD50
NOTE
IOCB0 register is both readable and writable
Bit 7 (/PD57): Control bit used to enable the pull-down function of the P57 pin
(applicable to EM78P343N only)
0 = Enable internal pull-down
1 = Disable internal pull-down
Bit 6 (/PD56): Control bit is used to enable the pull-down function of the P56 pin
(applicable to EM78P343N only)
Bit 5 (/PD55): Control bit used to enable the pull-down function of the P55 pin
Bit 4 (/PD54): Control bit used to enable the pull-down function of the P54 pin
Bit 3 (/PD53): Control bit used to enable the pull-down function of the P53 pin
Bit 2 (/PD52): Control bit used to enable the pull-down function of the P52 pin
Bit 1 (/PD51): Control bit used to enable the pull-down function of the P51 pin
Bit 0 (/PD50): Control bit used to enable the pull-down function of the P50 pin.
6.2.8 IOCC0 (Open-Drain Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
/OD67
/OD66
/OD65
/OD64
/OD63
/OD62
/OD61
/OD60
NOTE
The IOCC0 register is both readable and writable.
Bit 7 (/OD67): Control bit is used to enable the open-drain output of the P67 pin
0 = Enable open-drain output
1 = Disable open-drain output
Bit 6 (/OD66): Control bit used to enable the open-drain output of the P66 pin
Bit 5 (/OD65): Control bit used to enable the open-drain output of the P65 pin
(Not applicable to EM78P341N)
22 •
Product Specification (V1.0) 12.01.2006
(This specification is subject to change without further notice)
EM78P341N/342N/343N
8-Bit Microprocessor with OTP ROM
Bit 4 (/OD64): Control bit used to enable the open-drain of the P64 pin
(Not applicable to EM78P341N)
Bit 3 (/OD63): Control bit used to enable the open-drain of the P63 pin
(Not applicable to EM78P341N)
Bit 2 (/OD62): Control bit used to enable the open-drain of the P62 pin
(Not applicable to EM78P341N)
Bit 1 (/OD61): Control bit used to enable the open-drain of the P61 pin
Bit 0 (/OD60): Control bit used to enable the open-drain of the P60 pin
6.2.9 IOCD0 (Pull-high Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
/PH57
/PH56
/PH55
/PH54
/PH53
/PH52
/PH51
/PH50
NOTE
The IOCD0 register is both readable and writable.
Bit 7 (/PH57): Control bit is used to enable the pull-high of the P57 pin (applicable to
EM78P343N only).
0 = Enable internal pull-high
1 = Disable internal pull-high
Bit 6 (/PH56): Control bit used to enable the pull-high function of the P56 pin
(applicable to EM78P343N only).
Bit 5 (/PH55): Control bit used to enable the pull-high function of the P55 pin.
Bit 4 (/PH54): Control bit used to enable the pull-high function of the P54 pin.
Bit 3 (/PH53): Control bit used to enable the pull-high function of the P53 pin.
Bit 2 (/PH52): Control bit used to enable the pull-high function of the P52 pin.
Bit 1 (/PH51): Control bit used to enable the pull-high function of the P51 pin.
Bit 0 (/PH50): Control bit used to enable the pull-high function of the P50 pin.
6.2.10 IOCE0 (WDT Control & Interrupt Mask Registers 2)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
WDTE
EIS
ADIE
CMPIE
PSWE
PSW2
PSW1
PSW0
Bit 7 (WDTE): Control bit used to enable Watchdog Timer
0 = Disable WDT
1 = Enable WDT
WDTE is both readable and writable.
Product Specification (V1.0) 12.01.2006
(This specification is subject to change without further notice)
• 23
EM78P341N/342N/343N
8-Bit Microprocessor with OTP ROM
Bit 6 (EIS):
Control bit used to define the function of the P60 (/INT) pin
0 = P60, bidirectional I/O pin
1 = /INT, external interrupt pin. In this case, the I/O control bit of P60
(Bit 0 of IOC60) must be set to "1".
NOTE
■ When EIS is "0", the path of /INT is masked. When EIS is "1", the status of /INT pin
can also be read by way of reading Port 6 (R6). Refer to Fig. 6-3 (I/O Port and I/O
Control Register Circuit for P60 (/INT)) under Section 6.4 (I/O Ports).
■ EIS is both readable and writable.
Bit 5 (ADIE):
ADIF interrupt enable bit
0 = disable ADIF interrupt
1 = enable ADIF interrupt
Bit 4 (CMPIE): CMPIF interrupt enable bit.
0 = disable CMPIF interrupt
1 = enable CMPIF interrupt
Bit 3 (PSWE): Prescaler enable bit for WDT
0 = prescaler disable bit, WDT rate is 1:1
1 = prescaler enable bit, WDT rate is set as Bit 2 ~ Bit 0
Bit 2 ~ Bit 0 (PSW2 ~ PSW0): WDT prescaler bits
PSW2
PSW1
PSW0
WDT Rate
0
0
0
1:2
0
0
1
1:4
0
1
0
1:8
0
1
1
1:16
1
0
0
1:32
1
0
1
1:64
1
1
0
1:128
1
1
1
1:256
6.2.11 IOCF0 (Interrupt Mask Register)
24 •
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
LPWTIE
HPWTIE
TCCCIE
TCCBIE
TCCAIE
EXIE
ICIE
TCIE
Product Specification (V1.0) 12.01.2006
(This specification is subject to change without further notice)
EM78P341N/342N/343N
8-Bit Microprocessor with OTP ROM
NOTE
■ The IOCF0 register is both readable and writable.
■ Individual interrupt is enabled by setting its associated control bit in the IOCF0 and in
IOCE0 Bit 4 & 5 to "1".
■ Global interrupt is enabled by the ENI instruction and is disabled by the DISI
instruction. Refer to Fig. 6-7 (Interrupt Input Circuit) under Section 6.6 (Interrupt).
Bit 7 (LPWTIE): LPWTIF interrupt enable bit
0 = Disable LPWTIF interrupt
1 = Enable LPWTIF interrupt
Bit 6 (HPWTIE): HPWTIF interrupt enable bit
0 = Disable HPWTIF interrupt
1 = Enable HPWTIF interrupt
Bit 5 (TCCCIE): TCCCIF interrupt enable bit
0 = Disable TCCCIF interrupt
1 = Enable TCCCIF interrupt
Bit 4 (TCCBIE): TCCBIF interrupt enable bit
0 = Disable TCCBIF interrupt
1 = Enable TCCBIF interrupt
Bit 3 (TCCAIE): TCCAIF interrupt enable bit
0 = Disable TCCAIF interrupt
1 = Enable TCCAIF interrupt
Bit 2 (EXIE):
EXIF interrupt enable bit
0 = Disable EXIF interrupt
1 = Enable EXIF interrupt
Bit 1 (ICIE):
ICIF interrupt enable bit
0 = Disable ICIF interrupt
1 = Enable ICIF interrupt
Bit 0 (TCIE):
TCIF interrupt enable bit.
0 = Disable TCIF interrupt
1 = Enable TCIF interrupt
6.2.12 IOC51 (TCCA Counter)
IOC51 (TCCA) is an 8-bit clock counter. It can be read, written, and cleared on any
reset condition and is an Up Counter.
NOTE
■ TCCA timeout period [1/Fosc x (256-TCCA cnt) x 1(CLK=2)]
■ TCCA timeout period [1/Fosc x (256-TCCA cnt) x 2 (CLK=4)]
Product Specification (V1.0) 12.01.2006
(This specification is subject to change without further notice)
• 25
EM78P341N/342N/343N
8-Bit Microprocessor with OTP ROM
6.2.13 IOC61 (TCCB Counter)
IOC61 (TCCB) is an 8-bit clock counter for the least significant byte of TCCBX (TCCB).
It can be read, written, and cleared on any reset condition and it is an Up Counter.
6.2.14 IOC71 (TCCBH/MSB Counter)
IOC71 (TCCBH/MSB) is an 8-bit clock counter for the most significant byte of TCCBX
(TCCBH). It can be read, written, and cleared on any reset condition.
When TCCBHE (IOC90) is “0,” then TCCBH is disabled. When TCCBHE is”1,” then
TCCB is a 16-bit counter.
NOTE
When TCCBH is Disabled:
■ TCCB timeout period [1/Fosc x ( 256 - TCCB cnt ) x 1 (CLK=2)]
■ TCCB timeout period [1/Fosc x ( 256 - TCCB cnt ) x 2 (CLK=4)]
When TCCBH is Enabled:
■ TCCB timeout period {1/Fosc x [ 65536 - (TCCBH * 256 + TCCB cnt)] x 1 (CLK=2)}
■ TCCB timeout period {1/Fosc x [ 65536 - (TCCBH * 256 + TCCB cnt)] x 2 (CLK=4)}
6.2.15 IOC81 (TCCC Counter)
IOC81 (TCCC) is an 8-bit clock counter that can be extended to 16-bit counter. It can
be read, written, and cleared on any reset condition.
If HF (Bit 2 of IOCA0) = 1 and IRE (Bit 3 of IOCA0) = 1, TCCC counter scale uses the
low-time segments of the pulse generated by the Fcarrier frequency modulation (see
Fig. 6-11 in Section 6.8.2, Function Description). Then TCCC value will be TCCC
predicted value.
When HP = 0 or IRE = 0, the TCCC is an UP Counter.
NOTE
In TCCC Up Counter mode:
■ TCCC timeout period [1/Fosc x scaler (IOCA0) x (256-TCCC cnt) x 1 (CLK=2)]
■ TCCC timeout period [1/Fosc x scaler (IOCA0) x (256-TCCC cnt) x 2 (CLK=4)]
When HP = 1 and IRE = 1, TCCC counter scale uses the low-time segments of the
pulse generated by the Fcarrier frequency modulation.
NOTE
In IR mode:
■ Fcarrier = FT/ 2 { [1+decimal TCCC Counter value (IOC81)] * TCCC Scale (IOCA0) }
■ FT is system clock: FT = Fosc/1 (CLK=2)
FT = Fosc/2 (CLK=4)
26 •
Product Specification (V1.0) 12.01.2006
(This specification is subject to change without further notice)
EM78P341N/342N/343N
8-Bit Microprocessor with OTP ROM
6.2.16 IOC91 (Low-Time Register)
The 8-bit Low-time register controls the active or Low segment of the pulse.
The decimal value of its contents determines the number of oscillator cycles and
verifies that the IR OUT pin is active. The active period of IR OUT can be calculated as
follows:
NOTE
■ Low time width = { [1+decimal low-time value (IOC91)] * Low time Scale (IOCB1) } / FT
■ FT is system clock: FT = Fosc/1 (CLK=2)
FT = Fosc/2 (CLK=4)
When an interrupt is generated by the Low time down counter underflow (if enabled),
the next instruction will be fetched from address 015H (Low time).
6.2.17 IOCA1 (High Time Register)
The 8-bit High-time register controls the inactive or High period of the pulse.
The decimal value of its contents determines the number of oscillator cycles and
verifies that the IR OUT pin is inactive. The inactive period of IR OUT can be calculated
as follows:
NOTE
■ High time width = {[1+decimal high-time value (IOCA1)] * High time Scale (IOCB1) } / FT
■ FT is system clock: FT=Fosc/1(CLK=2)
FT=Fosc/2(CLK=4)
When an interrupt is generated by the High time down counter underflow (when
enabled), the next instruction will be fetched from Address 012H (High time).
6.2.18 IOCB1 High/Low Time Scale Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
HTSE
HTS2
HTS1
HTS0
LTSE
LTS2
LTS1
LTS0
Bit 7 (HTSE): High-time scale enable bit
0 = scale disable bit, High-time rate is 1:1
1 = scale enable bit, High-time rate is set as Bit 6~Bit 4.
Product Specification (V1.0) 12.01.2006
(This specification is subject to change without further notice)
• 27
EM78P341N/342N/343N
8-Bit Microprocessor with OTP ROM
Bit 6 ~ Bit 4 (HTS2 ~ HTS0): High-time scale bits:
HTS2
HTS1
HTS0
High-time rate
0
0
0
1:2
0
0
1
1:4
0
1
0
1:8
0
1
1
1:16
1
0
0
1:32
1
0
1
1:64
1
1
1
1
0
1
1:128
1:256
Bit 3 (LTSE): Low-time scale enable bit.
0 = scale disable bit, Low-time rate is 1:1
1 = scale enable bit, Low-time rate is set as Bit 2~Bit 0.
Bit 2 ~ Bit 0 (LTS2 ~ LTS0): Low-time scale bits:
LTS2
LTS1
LTS0
Low-time Rate
0
0
0
1:2
0
0
1
1:4
0
1
0
1:8
0
1
1
1:16
1
0
0
1:32
1
0
1
1:64
1
1
0
1:128
1
1
1
1:256
6.2.19 IOCC1 (TCC Prescaler Counter)
TCC prescaler counter can be read and written to:
PST2 PST1 PST0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TCC
Rate
-
-
V
1:2
1:4
0
0
0
-
-
-
-
-
0
0
1
-
-
-
-
-
-
V
V
0
1
0
-
-
-
-
-
V
V
V
1:8
0
1
1
-
-
-
-
V
V
V
V
1:16
1
0
0
-
-
-
V
V
V
V
V
1:32
1
1
0
1
1
0
-
V
V
V
V
V
V
V
V
V
V
V
V
V
1:64
1:128
1
1
1
V
V
V
V
V
V
V
V
1:256
V = valid value
The TCC prescaler counter is assigned to TCC (R1).
The contents of the IOCC1 register are cleared when one of the following occurs:
28 •
„
a value is written to TCC register
„
a value is written to TCC prescaler bits (Bits 3, 2, 1, 0 of CONT)
„
power-on reset, /RESET
„
WDT time out reset
Product Specification (V1.0) 12.01.2006
(This specification is subject to change without further notice)
EM78P341N/342N/343N
8-Bit Microprocessor with OTP ROM
6.2.20 IOCD1 (LVD Control Register)
Bit
EM78P342N/343N
ICE342N
7
6
-
-
5
TYPE1 TYPE0
4
3
2
1
0
-
-
LVDIE
LVDEN
LVD1
LVD0
LVR1
LVR0
LVDIE
LVDEN
LVD1
LVD0
Bits 7~6 (Type 1 ~ Type 0): Type selection for EM78P343N or EM78P342N or
EM78P341N or 108C.
Type 1, Type 0
VDD Reset Level
11
10
01
00
EM78P343N (Default) (20PIN)
EM78P342N (18PIN)
EM78P341N (14PIN)
108C (8PIN)
Bits 5~4 (LVR1 ~ LVR0): Low Voltage Reset enable bits.
LVR1, LVR0
VDD Reset Level
11
10
01
00
2.7V
3.5V
4.0V
VDD Release Level
NA (Power-on Reset)
2.9V
3.7V
4.2V
NOTE
■ IOCD1<3> register is both readable and writable
■ Individual interrupt is enabled by setting its associated control bit in the IOCD1 <4> to "1"
■ Global interrupt is enabled by the ENI instruction and is disabled by the DISI
instruction. Refer to Fig. 6-8 (Interrupt Input Circuit) under Section 6.6 (Interrupt).
Bit 3 (LVDIE): Low voltage Detector interrupt enable bit.
0 = Disable Low voltage Detector interrupt.
1 = Enable Low voltage Detector interrupt.
When the detect low level voltage is used to enter an interrupt vector or
enter next instruction, the LVDIE bit must be set to “Enable“.
Bit 2 (LVDEN):
Low Voltage Detector enable bit
0 = Low voltage detector disable
1 = Low voltage detector enable
Bit 1~0 (LVD1:0): Low Voltage Detector level bits.
LVDEN
1
LVD1,LVD0
11
1
10
1
01
1
00
0
XX
Product Specification (V1.0) 12.01.2006
(This specification is subject to change without further notice)
LVD voltage Interrupt level
/LVD
Vdd ≤ 2.3V
0
Vdd > 2.3V
1
Vdd ≤ 3.3V
Vdd > 3.3V
0
1
Vdd ≤ 4.0V
0
Vdd > 4.0V
1
Vdd ≤ 4.5V
0
Vdd > 4.5V
1
NA
0
• 29
EM78P341N/342N/343N
8-Bit Microprocessor with OTP ROM
6.2.21 IOCE1 (Output Sink Select Control Register)
Bit
7
4
3
2
1
0
TIMERSC CPUS
IDLE
HS3
HS2
HS1
HS0
WDTPS TIMERSC CPUS
IDLE
HS3
HS2
HS1
HS0
EM78P342N/343N
ICE342N
Bit 7 (WDTPS):
-
6
5
WDT time-out period selection bit.
0 : 4.5ms
1 : 18ms
Bit 6 (TIMERSC): TCC, TCCA, TCCB, TCCC clock sources select 0/1 → Fs/Fm*
Fs: sub frequency for WDT internal RC time base
Fm: main-oscillator clock
Bit 5 (CPUS):
CPU Oscillator Source Select, 0/1 → sub-oscillator (fs) / main
oscillator (fosc)
When CPUS=0, the CPU oscillator select sub-oscillator and the
main oscillator is stopped.
Bit 4 (IDLE):
Idle Mode Enable Bit. This bit will decide SLEP instruction which
mode to go.
0 : Idle=”0”+SLEP instruction → sleep mode
1 : Idle=”1”+SLEP instruction → idle mode
CPU Operation Mode
Code
option
HLFS=1
RESET
Normal Mode
fosc:oscillation
fs: oscillation
external
interrupt
CPU: using fosc
wake up
external
interrupt
SLEEP Mode
CPUS="0"
CPUS="1"
IDLE="0"
+SLEP
fosc:stop
fs: stop
IDLE="1
"+SLEP
IDLE="1
"+SLEP
Green Mode
fosc:stop
fs: oscillation
IDLE="0"
SLEP
CPU: stop
IDLE Mode
fosc:stop
fs: oscillation
CPU: using fs
wake up
CPU: stop
Fig. 6-2 CPU Operation Mode
30 •
Bit 3 (HS3):
Output Sink current Select for P63
(Not applicable for EM78P341N)
Bit 2 (HS2):
Output Sink current Select for P62.
(Not applicable for EM78P341N)
Bit 1 (HS1):
Output Sink current Select for P61.
Bit 0 (HS0):
Output Sink current Select for P60.
HSx
VDD = 5V, Sink Current
0
20mA (in 0.3VDD)
1
90mA (in 0.3VDD)
Product Specification (V1.0) 12.01.2006
(This specification is subject to change without further notice)
EM78P341N/342N/343N
8-Bit Microprocessor with OTP ROM
6.2.21 IOCF1 (Pull-high Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
/PH67
/PH66
/PH65
/PH64
/PH63
/PH62
/PH61
/PH60
NOTE
The IOCD0 register is both readable and writable.
Bit 7 (/PH67): Control bit is used to enable the pull-high of the P67 pin.
0 = Enable internal pull-high
1 = Disable internal pull-high
Bit 6 (/PH66): Control bit used to enable the pull-high function of the P66 pin.
Bit 5 (/PH65): Control bit used to enable the pull-high function of the P65 pin.
(Not applicable for EM78P341N)
Bit 4 (/PH64): Control bit used to enable the pull-high function of the P64 pin.
(Not applicable for EM78P341N)
Bit 3 (/PH63): Control bit used to enable the pull-high function of the P63 pin.
(Not applicable for EM78P341N)
Bit 2 (/PH62): Control bit used to enable the pull-high function of the P62 pin.
(Not applicable for EM78P341N)
Bit 1 (/PH61): Control bit used to enable the pull-high function of the P61 pin.
Bit 0 (/PH60): Control bit used to enable the pull-high function of the P60 pin.
6.3 TCC/WDT and Prescaler
There are two 8-bit counters available as prescalers that can be extended to 16-bit
counter for the TCC and WDT respectively. The PST2 ~ PST0 bits of the CONT
register are used to determine the ratio of the TCC prescaler, and the PWR2 ~ PWR0
bits of the IOCE0 register are used to determine the WDT prescaler. The prescaler
counter is cleared by the instructions each time such instructions are written into TCC.
The WDT and prescaler will be cleared by the “WDTC” and “SLEP” instructions. Fig.
6-1 (next page) depicts the block diagram of TCC/WDT.
TCC (R1) is an 8-bit timer/counter. The TCC clock source can be internal clock or
external signal input (edge selectable from the TCC pin). If TCC signal source is from
an internal clock, TCC will be incremented by 1 at every instruction cycle (without
prescaler). Referring to Fig. 6-1, CLK=Fosc/2 or CLK=Fosc/4 is dependent to the Code
Option bit <CLKS>. CLK=Fosc/2 if the CLKS bit is "0," and CLK=Fosc/4 if the CLKS bit
is "1." If the TCC signal source is from an external clock input, TCC will be incremented
by 1 at every falling edge or rising edge of the TCC pin. The TCC pin input time length
(kept at High or Low level) must be greater than 1CLK.
Product Specification (V1.0) 12.01.2006
(This specification is subject to change without further notice)
• 31
EM78P341N/342N/343N
8-Bit Microprocessor with OTP ROM
NOTE
The internal TCC will stop running when in sleep mode. However, during AD
conversion, when TCC is set to “SLEP” instruction, if the ADWE bit of the RE register is
enabled, TCC will keep on running.
The watchdog timer is a free running on-chip RC oscillator. The WDT will keep on
running even when the oscillator driver has been turned off (i.e., in sleep mode).
During normal operation or in sleep mode, a WDT time-out (if enabled) will cause the
device to reset. The WDT can be enabled or disabled any time during normal mode
through software programming. Refer to WDTE bit of IOCE0 register (Section 6.2.10
IOCE0 (WDT Control & Interrupt Mask Registers 2). With no prescaler, the WDT
1
2
time-out period is approximately 18ms or 4.5ms .
CLK (Fosc/2 or Fosc/4)
Data Bus
0
TCC Pin
1
8-Bit Counter (IOCC1)
MUX
8 to 1 MUX
TE (CONT)
Prescaler
TS (CONT)
WDT
SYNC
2 cycles
TCC (R1)
TCC overflow
interrupt
PSR2~0
(CONT)
8-Bit Counter
8 to 1 MUX
Prescaler
WDTE
(IOCE0)
PSW2~0
(IOCE0)
WDT Time out
Fig. 6-3 TCC and WDT Block Diagram
1
2
32 •
VDD=5V, WDT time-out period = 16.5ms ± 30%
VDD=3V, WDT time-out period = 18ms ± 30%
VDD=5V, WDT time-out period = 4.2ms ± 30%
VDD=3V, WDT time-out period = 4.5ms ± 30%
Product Specification (V1.0) 12.01.2006
(This specification is subject to change without further notice)
EM78P341N/342N/343N
8-Bit Microprocessor with OTP ROM
6.4 I/O Ports
The I/O registers (Port 5, Port 6, and Port 7) are bidirectional tri-state I/O ports. Port 5
is pulled-high and pulled-down internally by software. Likewise, P6 has its open-drain
output set through software. Port 5 features an input status changed interrupt (or
wake-up) function. Each I/O pin can be defined as "input" or "output" pin by the I/O
control register (IOC5 ~ IOC7). The I/O registers and I/O control registers are both
readable and writable. The I/O interface circuits for Port 5, Port 6, and Port 7 are
illustrated in Figures 6-4, 6-5, 6-6, & 6-7 (see next page).
PCRD
PORT
Q
P
R
_
Q
C
L
P
R
Q
_
Q
C
L
D
CLK
PCWR
IOD
D
CLK
PDWR
PDRD
0
1
M
U
X
Note: Open-drain is not shown in the figure.
Fig. 6-4 I/O Port and I/O Control Register Circuit for Port 6 and Port 7
PCRD
Q P
R D
_ CLK
Q C
L
Q P
R D
_ CLK
Q C
L
PORT
Bit 6 of IOCE
P
D R Q
CLK _
C Q
L
0
1
PCWR
IOD
PDWR
M
U
X
PDRD
INT
Note: Open-drain is not shown in the figure.
Fig. 6-5 I/O Port and I/O Control Register Circuit for P60 (/INT)
Product Specification (V1.0) 12.01.2006
(This specification is subject to change without further notice)
• 33
EM78P341N/342N/343N
8-Bit Microprocessor with OTP ROM
PCRD
Q
P
R
_
CLK
Q
D
PCWR
C
L
P50 ~ P57
PORT
Q
P
R
_
CLK
Q
0
1
IOD
D
PDWR
C
L
M
U
X
PDRD
TI n
D
P
R
CLK
C
L
Q
_
Q
Note: Pull-high (down) is not shown in the figure.
Fig. 6-6 I/O Port and I/O Control Register Circuit for Port 50 ~ P57
I O C F.1
R F.1
TI 0
TI 1
….
TI 8
Fig. 6-7 Port 5 Block Diagram with Input Change Interrupt / Wake-up
34 •
Product Specification (V1.0) 12.01.2006
(This specification is subject to change without further notice)
EM78P341N/342N/343N
8-Bit Microprocessor with OTP ROM
6.4.1 Usage of Port 5 Input Change Wake-up/Interrupt Function
(1) Wake-up
(2) Wake-up and Interrupt
(a) Before Sleep
(a) Before Sleep
1. Disable WDT
1. Disable WDT
2. Read I/O Port 5 (MOV R65R5)
2. Read I/O Port 5 (MOV R5,R5)
3. Execute "ENI" or "DISI"
3. Execute "ENI" or "DISI"
4. Enable wake-up bit (Set RE ICWE =1)
4. Enable wake-up bit (Set RE
ICWE =1)
5. Execute "SLEP" instruction
5. Enable interrupt (Set IOCF ICIE =1)
(b) After wake-up
6. Execute "SLEP" instruction
→ Next instruction
(b) After wake-up
1. IF "ENI" → Interrupt vector (008H)
2. IF "DISI" → Next instruction
(3) Interrupt
(a) Before Port 5 pin change
1. Read I/O Port 6 (MOV R5,R5)
2. Execute "ENI" or "DISI"
3. Enable interrupt (Set IOCF ICIE =1)
(b) After Port 5 pin changed (interrupt)
1. IF "ENI" → Interrupt vector (006H)
2. IF "DISI" → Next instruction
6.5 Reset and Wake-up
6.5.1 Reset and Wake-up Operation
A reset is initiated by one of the following events:
1. Power-on reset
2. /RESET pin input "low"
3. WDT time-out (if enabled)
3
The device is kept in reset condition for a period of approximately 18ms (except in LXT
mode) after the reset is detected. When in LXT mode, the reset time is 500ms. Two
3
4
choices (18ms or 4.5ms ) are available for WDT-time out period. Once a reset occurs,
the following functions are performed (the initial address is 000h):
„ The oscillator continues running, or will be started (if in sleep mode)
„ The Program Counter (R2) is set to all "0"
3
4
VDD=5V, WDT Time-out period = 16.5ms ± 30%.
VDD=3V, WDT Time-out period = 18ms ± 30%.
VDD=5V, WDT Time-out period = 4.2ms ± 30%.
VDD=3V, WDT Time-out period = 4.5ms ± 30%.
Product Specification (V1.0) 12.01.2006
(This specification is subject to change without further notice)
• 35
EM78P341N/342N/343N
8-Bit Microprocessor with OTP ROM
„ All I/O port pins are configured as input mode (high-impedance state)
„ The Watchdog Timer and prescaler are cleared
„ When power is switched on, the upper three bits of R3 is cleared
„ The IOCB0 register bits are set to all "1"
„ The IOCC0 register bits are set to all "1"
„ The IOCD0 register bits are set to all "1"
„ Bits 7, 5, and 4 of the IOCE0 register are cleared
„ Bits 5 and 4 of the RE register are cleared
„ RF and IOCF0 registers are cleared
Executing the “SLEP” instruction will assert the sleep (power down) mode. While
entering into sleep mode, the Oscillator, TCC, TCCA, TCCB, and TCCC are stopped.
The WDT (if enabled) is cleared but keeps on running.
During AD conversion, when “SLEP” instruction is set; the Oscillator, TCC, TCCA,
TCCB, and TCCC keep on running. The WDT (if enabled) is cleared but keeps on
running.
The controller can be awakened by:
Case 1
External reset input on /RESET pin
Case 2
WDT time-out (if enabled)
Case 3
Port 5 input status changes (if ICWE is enabled)
Case 4
Comparator output status changes (if CMPWE is enabled)
Case 5
AD conversion completed (if ADWE is enabled)
Case 6
Low Voltage Detector (if LVDWE is enabled)
The first two cases (1 & 2) will cause the EM78P341N/342N/343N to reset. The T and
P flags of R3 can be used to determine the source of the reset (wake-up). Cases 3, 4,
& 5 are considered the continuation of program execution and the global interrupt
("ENI" or "DISI" being executed) determines whether or not the controller branches to
the interrupt vector following wake-up. If ENI is executed before SLEP, the instruction
will begin to execute from Address 0x06 (Case 3), 0x0F (Case 4), and 0x0C (Case 5)
after wake-up. If DISI is executed before SLEP, the execution will restart from the
instruction next to SLEP after wake-up.
Only one of Cases 2 to 5 can be enabled before entering into sleep mode. That is:
Case [a] If WDT is enabled before SLEP, all of the RE bit is disabled. Hence, the
EM78P341N/342N/343N can be awakened only with Case 1 or Case 2.
Refer to the section on Interrupt (Section 6.6) for further details.
Case [b] If Port 5 Input Status Change is used to wake up EM78P341N/342N/343N
and the ICWE bit of the RE register is enabled before SLEP, WDT must be
disabled. Hence, the EM78P341N/342N/343N can be awakened only with
Case 3. Wake-up time is dependent on oscillator mode. In RC mode,
Wake-up time is 32 clocks (for stable oscillators). In High Crystal mode,
Wake-up time is 2ms and 32 clocks (for stable oscillators), and in low Crystal
mode, Wake-up time is 500ms.
36 •
Product Specification (V1.0) 12.01.2006
(This specification is subject to change without further notice)
EM78P341N/342N/343N
8-Bit Microprocessor with OTP ROM
Case [c] If the Comparator output status change is used to wake-up the EM78P342N/
343N and the CMPWE bit of the RE register is enabled before SLEP, WDT
must be disabled by software. Hence, the EM78P342N/343N can be
awakened only with Case 4. Wake-up time is dependent on oscillator mode.
In RC mode the Wake-up time is 32 clocks (for stable oscillators). In High
Crystal mode, Wake-up time is 2ms and 32 clocks (for stable oscillators), and
in low Crystal mode, Wake-up time is 500ms.
Case [d] If AD conversion completed is used to wake-up the EM78P341N/342N/343N
and ADWE bit of RE register is enabled before SLEP, WDT must be disabled
by software. Hence, the EM78P341N342N/343N can be awakened only with
Case 5. The wake-up time is 15 TAD (ADC clock period).
Case[e] If Low voltage detector is used to wake-up the EM78P341N/342N/343N and
the LVDWE bit of Bank 0-RE register is enabled before SLEP, WDT must be
disabled by software.
Hence, the EM78P341N/342N/343N can be
awakened only with Case 6.
Wake-up time is dependent on oscillator mode.
If Port 5 Input Status Change Interrupt is used to wake up the EM78P341N/342N/343N
(as in Case [b] above), the following instructions must be executed before SLEP:
BC
R3, 7
MOV
A, @00xx1110b
IOW
IOCE0
WDTC
MOV
R5, R5
ENI (or DISI)
MOV
A, @xxxxxx1xb
MOV
RE
MOV
A, @xxxxxx1xb
IOW
IOCF0
SLEP
; Select Segment 0
; Select WDT prescaler and Disable WDT
;
;
;
;
Clear WDT and prescaler
Read Port 5
Enable (or disable) global interrupt
Enable Port 5 input change wake-up bit
; Enable Port 5 input change interrupt
; Sleep
Similarly, if the Comparator Interrupt is used to wake up the EM78P341N/342N/343N
(as in Case [c] above), the following instructions must be executed before SLEP:
BC
MOV
R3, 7
A, @xxx10XXXb
IOW
MOV
IOC80
A, @00x11110b
IOW
IOCE0
WDTC
ENI (or DISI)
MOV
A, @xxx0x1xxb
MOV
SLEP
; Select Segment 0
; Select a comparator and P64 functions
as CO pin
; Select WDT prescaler and Disable WDT,
and enable comparator output status
change interrupt
; Clear WDT and prescaler
; Enable (or disable) global interrupt
; Enable comparator output status change
wake-up bit
RE
Product Specification (V1.0) 12.01.2006
(This specification is subject to change without further notice)
; Sleep
• 37
EM78P341N/342N/343N
8-Bit Microprocessor with OTP ROM
6.5.1.1 Wake-up and Interrupt Modes Operation Summary
The controller can be awakened from sleep mode and idle mode. The wake-up signals are listed
as follows.
Wakeup
Signal
Sleep Mode
Idle Mode
Green Mode
Wake-up
+ interrupt
×
(if interrupt is enabled)
+ next instruction
If enable ICWE bit
If enable ICWE bit
Wake-up
Port 5 pin
Wake-up + interrupt
+ interrupt
change
(if interrupt is enabled)
(if interrupt is enabled)
+ next instruction
+ next instruction
Wake-up + interrupt
TCC overflow
x
(if interrupt is enabled)
interrupt
+ next instruction
If enable ADWE bit
If enable ADWE bit
AD
Wake-up + interrupt
Wake-up + interrupt
conversion
(if interrupt is enabled) (if interrupt enable)
complete
+ next instruction
+ next instruction
interrupt
Fs and Fm don’t stop Fs and Fm don’t stop
If enable CMPWE bit
If enable CMPWE bit
Wake-up
Comparator Wake-up + interrupt
+ interrupt
interrupt
(if interrupt enable)
(if interrupt enable)
+ next instruction
+ next instruction
Wake-up
High-pulse
+ interrupt
width timer
x
(if interrupt enable)
underflow
+ next instruction
interrupt
Wake-up
Low-pulse
+ interrupt
width timer
x
(if interrupt enable)
underflow
+ next instruction
interrupt
Wake-up
TCCA
+ interrupt
overflow
x
(if interrupt enable)
interrupt
+ next instruction
Wake-up
TCCB
+ interrupt
overflow
x
(if interrupt enable)
interrupt
+ next instruction
Wake-up
TCCC
+ interrupt
overflow
x
(if interrupt enable)
interrupt
+ next instruction
If Enable LVDWE bit
If Enable LVDWE bit
Low Voltage Wake-up
Wake-up
+ interrupt
+ interrupt
Detector
(if interrupt enable)
(if interrupt enable)
interrupt
+ next instruction
+ next instruction
External
interrupt
Normal Mode
Interrupt
(if interrupt is enabled)
or next instruction
Interrupt
(if interrupt is enabled)
or next instruction
Interrupt
(if interrupt is enabled)
or next instruction
Interrupt
(if interrupt is enabled)
or next instruction
Interrupt
(if interrupt is enabled)
or next instruction
Interrupt
(if interrupt is enabled)
or next instruction
Interrupt
×
(if interrupt is enabled)
Fs and Fm don’t stop
or next instruction
Interrupt
(if interrupt enable)
or next instruction
Interrupt
(if interrupt enable)
or next instruction
Interrupt
(if interrupt enable)
or next instruction
Interrupt
(if interrupt enable)
or next instruction
Interrupt
(if interrupt enable)
or next instruction
Interrupt
(if interrupt enable)
or next instruction
Interrupt
(if interrupt enable)
or next instruction
Interrupt
(if interrupt enable)
or next instruction
Interrupt
(if interrupt enable)
or next instruction
Interrupt
(if interrupt enable)
or next instruction
Interrupt
(if interrupt enable)
or next instruction
Interrupt
(if interrupt enable)
or next instruction
Interrupt
(if interrupt enable)
or next instruction
Interrupt
(if interrupt enable)
or next instruction
WDT Time out
RESET
RESET
RESET
RESET
Low Voltage
Reset
RESET
RESET
RESET
RESET
After wake up:
1. If interrupt is enabled → interrupt+ next instruction
2. If interrupt is disabled → next instruction
38 •
Product Specification (V1.0) 12.01.2006
(This specification is subject to change without further notice)
EM78P341N/342N/343N
8-Bit Microprocessor with OTP ROM
Signal
INT Pin
Sleep Mode
Normal Mode
Green Mode
DISI+IOCF0(EXIE) Bit 2 =1
DISI + IOCF0 (EXIE)
Bit 2=1
DISI + IOCF0 (EXIE)
Bit 2=1
Wake-up + next instruction
Set RF (EXIF)=1
Next Instruction +
Set RF (EXIF)=1
Next Instruction +
Set RF (EXIF)=1
ENI + IOCF0(EXIE) Bit 2 =1
ENI + IOCF0 (EXIE)
Bit 2=1
ENI + IOCF0 (EXIE)
Bit 2=1
Wake-up + Interrupt Vector
(003H) + Set RF (EXIF)=1
Interrupt Vector (003H)
+ Set RF (EXIF)=1
Interrupt Vector (003H)
+ Set RF (EXIF)=1
RE (ICWE) Bit 1=0,
IOCF0 (ICIE) bit 1=0
RE (ICWE) Bit 1=0, IOCF0
(ICIE) Bit 1=0
IOCF0 (ICIE) Bit 1=0
IOCF0 (ICIE) Bit 1=0
Oscillator, TCC, TCCX
and IR/PWM are
stopped.
Port 5 input status
changed wake-up is
invalid.
Oscillator, TCC, TCCX and
IR/PWM keep on running.
Port5 input status changed
wake-up is invalid.
Port 5 input status change Port 5 input status change
interrupted is invalid
interrupted is invalid
RE (ICWE) Bit 1=0,
IOCF0 (ICIE) Bit 1=1
RE (ICWE) Bit 1=0, IOCF0
(ICIE) Bit 1=1
N/A
N/A
Set RF (ICIF)=1,
Oscillator, TCC, TCCX
and IR/PWM are
stopped.
Port 5 input status
changed wake-up is
invalid.
Set RF (ICIF)=1,
Oscillator, TCC, TCCX and
IR/PWM keep on running.
Port5 input status changed
wake-up is invalid.
N/A
N/A
RE (ICWE) Bit 1=1,
IOCF0 (ICIE) Bit 1=0
RE (ICWE) Bit 1=1, IOCF0
(ICIE) Bit1=0
N/A
N/A
Wake-up + Next Instruction
Oscillator, TCC, TCCX and
IR/PWM keep on running.
N/A
N/A
NA
Port 5 Input
Wake-up + Next
Status Change Instruction
Oscillator, TCC, TCCX
and IR/PWM are
stopped.
TCC Over Flow
Idle Mode
RE (ICWE) Bit1=1, DISI
+ IOCF0 (ICIE) Bit 1=1
RE (ICWE) Bit 1=1, DISI +
IOCF0 (ICIE) Bit 1=1
DISI + IOCF0 (ICIE)
Bit 1=1
DISI + IOCF0 (ICIE)
Bit 1=1
Wake-up + Next
Instruction + Set RF
(ICIF)=1
Oscillator, TCC, TCCX
and IR/PWM are
stopped.
Wake-up + Next Instruction
+ Set RF (ICIF)=1
Oscillator, TCC, TCCX and
IR/PWM keep on running.
Next Instruction
+ Set RF (ICIF)=1
Next Instruction
+ Set RF (ICIF)=1
RE (ICWE) Bit 1=1, ENI
+ IOCF0 (ICIE) Bit 1=1
RE (ICWE) Bit 1=1, ENI +
IOCF0 (ICIE) Bit 1=1
ENI + IOCF0 (ICIE)
Bit 1=1
ENI + IOCF0 (ICIE)
Bit 1=1
Wake-up + Interrupt
Vector (006H) + Set RF
(ICIF)=1
Oscillator, TCC, TCCX
and IR/PWM are
stopped.
Wake-up + Interrupt Vector
(006H) + Set RF (ICIF)=1
Oscillator, TCC, TCCX and
IR/PWM keep on running.
Interrupt Vector(006H)
+ Set RF (ICIF)=1
Interrupt Vector(006H)
+ Set RF (ICIF)=1
DISI+IOCF0(TCIE) Bit 0 =1
DISI + IOCF0 (TCIE)
Bit 0=1
DISI + IOCF0 (TCIE)
Bit 0=1
Wake-up + next instruction
Set RF (TCIF)=1
Next Instruction + Set RF
(TCIF)=1
Next Instruction + Set RF
(TCIF)=1
ENI + IOCF0(TCIE)
Bit 0 =1
ENI + IOCF0 (TCIE)
Bit 0=1
ENI + IOCF0 (TCIE)
Bit 0=1
Wake-up + Interrupt Vector
(009H) + Set RF (TCIF)=1
Interrupt Vector (009H) +
Set RF (TCIF)=1
Interrupt Vector (009H) +
Set RF (TCIF)=1
NA
Product Specification (V1.0) 12.01.2006
(This specification is subject to change without further notice)
• 39
EM78P341N/342N/343N
8-Bit Microprocessor with OTP ROM
Signal
Sleep Mode
RE (ADWE) Bit 3=0,
IOCE0 (ADIE) Bit 5=0
Clear R9 (ADRUN)=0,
ADC is stopped,
AD conversion wake-up
is invalid.
Oscillator, TCC, TCCX
and IR/PWM are
stopped.
RE (ADWE) Bit 3=0,
IOCE0 (ADIE) Bit 5=1
Set RF (ADIF)=1, R9
(ADRUN)=0, ADC is
stopped,
AD conversion wake-up
is invalid.
Oscillator, TCC, TCCX
and IR/PWM are
stopped.
Idle Mode
Normal Mode
RE (ADWE) Bit 3=0, IOCE0
(ADIE) Bit 5=0
AD conversion wake-up is
invalid.
RE (ADWE) Bit 3=0, IOCE0
(ADIE) Bit 5=1
AD conversion wake-up is
invalid.
Oscillator, TCC, TCCX
and IR/PWM keep on
running.
Wake-up when ADC
completed.
Oscillator, TCC, TCCX and
IR/PWM keep on running.
Oscillator, TCC, TCCX
and IR/PWM keep on
running.
Wake-up when ADC
completed.
40 •
N/A
N/A
N/A
N/A
N/A
N/A
Wake-up when ADC
completed.
RE (ADWE) Bit 3=1, DISI +
IOCE0 (ADIE) Bit 5=1
DISI + IOCE0 (ADIE)
Bit 5=1
DISI + IOCE0 (ADIE)
Bit 5=1
Next Instruction
Next Instruction
+ RE (ADIF)=1
+ RE (ADIF)=1
ENI + IOCE0 (ADIE)
Bit 5=1
ENI + IOCE0 (ADIE)
Bit 5=1
Interrupt Vector (00CH)
Interrupt Vector (00CH)
+ Set RE (ADIF)=1
+ Set RE (ADIF)=1
Wake-up + Next Instruction
+ RE (ADIF)=1,
Oscillator, TCC, TCCX and
IR/PWM keep on running.
Wake-up when ADC
completed.
RE (ADWE) Bit 3=1, ENI RE (ADWE) Bit 3=1, ENI +
+ IOCE0 (ADIE) Bit 5=1 IOCE0 (ADIE) Bit 5=1
Wake-up + Interrupt
Vector (00CH)+ RE
(ADIF)=1,
N/A
Oscillator, TCC, TCCX and
IR/PWM keep on running.
Wake-up + Next Instruction,
Wake-up + Next
Instruction + RE
(ADIF)=1,
N/A
Set RF (ADIF)=1, R9
(ADRUN)=0, ADC is
stopped,
Wake-up + Next
Instruction,
RE (ADWE) Bit 3=1,
DISI + IOCE0 (ADIE)
Bit 5=1
AD conversion interrupted AD conversion interrupted
is invalid
is invalid
Oscillator, TCC, TCCX and
IR/PWM keep on running.
RE (ADWE) Bit 3=1, IOCE0
(ADIE) Bit 5=0
Wake-up when ADC
completed.
IOCE0 (ADIE) Bit 5=0
Clear R9 (ADRUN)=0, ADC
is stopped,
RE (ADWE) Bit 3=1,
IOCE0 (ADIE) Bit 5=0
Oscillator, TCC, TCCX
AD Conversion and IR/PWM keep on
running.
IOCE0 (ADIE) Bit 5=0
Green Mode
Wake-up + Interrupt Vector
(00CH)+ RE (ADIF)=1,
Oscillator, TCC, TCCX and
IR/PWM keep on running.
Wake-up when ADC
completed.
Product Specification (V1.0) 12.01.2006
(This specification is subject to change without further notice)
EM78P341N/342N/343N
8-Bit Microprocessor with OTP ROM
Signal
Comparator
(Comparator
Output Status
Change)
Sleep Mode
Normal Mode
Green Mode
IOCE0 (CMPIE) Bit 4=0
RE (CMPWE) Bit 2=0,
IOCE0 (CMPIE) Bit 4=0
RE (CMPWE) Bit 2=0,
IOCE0 (CMPIE) Bit 4=0
IOCE0 (CMPIE) Bit 4=0
Comparator output
status changed wake-up
is invalid.
Oscillator, TCC, TCCX
and IR/PWM are
stopped.
Comparator output status
changed wake-up is invalid.
Oscillator, TCC, TCCX and
IR/PWM keep on running.
Comparator output status Comparator output status
change interrupt is invalid. change interrupt is invalid.
RE (CMPWE) Bit 2=0,
IOCE0 (CMPIE) Bit 4=1
RE (CMPWE) Bit 2=0,
IOCE0 (CMPIE) Bit 4=1
N/A
N/A
Set RE (CMPIF)=1,
Comparator output
status changed wake-up
is invalid.
Oscillator, TCC, TCCX
and IR/PWM are
stopped.
Set RE (CMPIF)=1,
Comparator output status
changed wake-up is invalid.
Oscillator, TCC, TCCX and
IR/PWM keep on running.
N/A
N/A
RE (CMPWE) Bit 2=1,
IOCE0 (CMPIE) Bit 4=0
RE (CMPWE) Bit 2=1,
IOCE0 (CMPIE) Bit 4=0
N/A
N/A
Wake-up + Next
Instruction,
Oscillator, TCC, TCCX
and IR/PWM are
stopped.
Wake-up + Next Instruction,
Oscillator, TCC, TCCX and
IR/PWM keep on running.
N/A
N/A
RE (CMPWE) Bit 2=1,
DISI + IOCE0 (CMPIE)
Bit 4=1
RE (CMPWE) Bit 2=1, DISI + DISI + IOCE0 (CMPIE)
IOCE0 (CMPIE) Bit 4=1
Bit 4=1
DISI + IOCE0 (CMPIE)
Bit 4=1
Wake-up + Next
Instruction + Set RE
(CMPIF)=1,
Oscillator, TCC, TCCX
and IR/PWM are
stopped.
Wake-up + Next Instruction
+ Set RE (CMPIF)=1,
Oscillator, TCC, TCCX and
IR/PWM keep on running.
Next Instruction
+ Set RE (CMPIF)=1
RE (CMPWE) Bit 2=1,
ENI + IOCE0 (CMPIE)
Bit 4=1
RE (CMPWE) Bit 2=1, ENI + ENI + IOCE0 (CMPIE)
IOCE0 (CMPIE) Bit 4=1
Bit 4=1
ENI + IOCE0 (CMPIE)
Bit 4=1
Wake-up + Interrupt
Vector (00FH) + Set RE
(CMPIF)=1,Oscillator,
TCC, TCCX and
IR/PWM are stopped.
Wake-up + Interrupt Vector
(00FH) + Set RE
Interrupt Vector (00FH)
(CMPIF)=1,Oscillator, TCC,
+ Set RE (CMPIF)=1
TCCX and IR/PWM keep on
running.
Interrupt Vector (00FH)
+ Set RE (CMPIF)=1
DISI + IOCF0 (HPWTIE)
Bit 6=1
DISI + IOCF0 (HPWTIE)
Bit 6=1
DISI + IOCF0 (HPWTIE)
Bit 6=1
Wake-up +Next Instruction
+ Set RF (HPWTIF)=1
Next Instruction
+ Set RF (HPWTIF)=1
Next Instruction
+ Set RF (HPWTIF)=1
ENI
+ IOCF0 (HPWTIE) Bit 6 =1
ENI
+ IOCF0 (HPWTIE)
Bit 6 =1
ENI
+ IOCF0 (HPWTIE)
Bit 6 =1
Wake-up +Interrupt Vector
(012H)
+ Set RF (HPWTIF)=1
Interrupt Vector (012H)
+ Set RF (HPWTIF)=1
Interrupt Vector (012H)
+ Set RF (HPWTIF)=1
IR/PWM
underflow
interrupt
(High-pulse
width timer
underflow
interrupt)
Idle Mode
N/A
Product Specification (V1.0) 12.01.2006
(This specification is subject to change without further notice)
Next Instruction
+ Set RE (CMPIF)=1
• 41
EM78P341N/342N/343N
8-Bit Microprocessor with OTP ROM
Signal
Sleep Mode
IR/PWM
underflow
interrupt
(Low-pulse
width timer
underflow
interrupt)
N/A
Normal Mode
Green Mode
DISI + IOCF0 (LPWTIE)
Bit 7=1
Idle Mode
DISI + IOCF0 (LPWTIE)
Bit 7=1
DISI + IOCF0 (LPWTIE)
Bit 7=1
Wake-up +Next Instruction
Next Instruction
Next Instruction
+ Set RF (LPWTIF)=1
+ Set RF (LPWTIF)=1
+ Set RF (LPWTIF)=1
ENI + IOCF0 (LPWTIE)
Bit 7 =1
ENI + IOCF0 (LPWTIE)
Bit 7 =1
ENI + IOCF0 (LPWTIE)
Bit 7 =1
Wake-up +Interrupt Vector
(015H)
Interrupt Vector (015H)
Interrupt Vector (015H)
+ Set RF (LPWTIF)=1
+ Set RF (LPWTIF)=1
DISI + IOCF0 (TCCAIE)
Bit 3=1
DISI + IOCF0 (TCCAIE)
Bit 3=1
DISI + IOCF0 (TCCAIE)
Bit 3=1
Wake-up +Next Instruction
Next Instruction
Next Instruction
+ Set RF (TCCAIF)=1
+ Set RF (TCCAIF)=1
+ Set RF (TCCAIF)=1
ENI + IOCF0 (TCCAIE)
Bit 3=1
ENI + IOCF0 (TCCAIE)
Bit 3=1
ENI + IOCF0 (TCCAIE)
Bit 3=1
Wake-up +Interrupt Vector
(018H)
Interrupt Vector (018H)
Interrupt Vector (018H)
+ Set RF (TCCAIF)=1
+ Set RF (TCCAIF)=1
DISI + IOCF0 (TCCBIE)
Bit 4=1
DISI + IOCF0 (TCCBIE)
Bit 4=1
DISI + IOCF0 (TCCBIE)
Bit 4=1
Wake-up +Next Instruction
Next Instruction
Next Instruction
+ Set RF (TCCBIF)=1
+ Set RF (TCCBIF)=1
+ Set RF (TCCBIF)=1
ENI + IOCF0 (TCCBIE)
Bit 4=1
ENI + IOCF0 (TCCBIE)
Bit 4=1
ENI + IOCF0 (TCCBIE)
Bit 4=1
Interrupt Vector (01BH)
Interrupt Vector (01BH)
+ Set RF (TCCBIF)=1
+ Set RF (TCCBIF)=1
DISI + IOCF0 (TCCCIE)
Bit 5=1
DISI + IOCF0 (TCCCIE)
Bit 5=1
DISI + IOCF0 (TCCCIE)
Bit 5=1
Wake-up +Next Instruction
Next Instruction
Next Instruction
+ Set RF (TCCCIF)=1
+ Set RF (TCCCIF)=1
+ Set RF (TCCCIF)=1
ENI + IOCF0 (TCCCIE)
Bit 5=1
ENI + IOCF0 (TCCCIE)
Bit 5=1
ENI + IOCF0 (TCCCIE)
Bit 5=1
Interrupt Vector (01EH)
Interrupt Vector (01EH)
+ Set RF (TCCCIF)=1
+ Set RF (TCCCIF)=1
+ Set RF (LPWTIF)=1
TCCA Over
Flow
N/A
+ Set RF (TCCAIF)=1
TCCB Over
Flow
N/A
Wake-up +Interrupt Vector
(01BH) + Set RF
(TCCBIF)=1
TCCC Over
Flow
N/A
Wake-up +Interrupt Vector
(01EH) + Set RF
(TCCCIF)=1
42 •
Product Specification (V1.0) 12.01.2006
(This specification is subject to change without further notice)
EM78P341N/342N/343N
8-Bit Microprocessor with OTP ROM
Signal
Sleep Mode
IOCD1 (LVDIE) Bit 3=0
Low voltage detector
wake-up is invalid.
Oscillator, TCC, TCCX
and IR/PWM are
stopped.
Low voltage detector
wake-up is invalid.
Oscillator, TCC, TCCX and
IR/PWM keep on running.
Low voltage detector
interrupted is invalid.
RE (LVDWE) Bit 0=0,
IOCD1 (LVDIE) Bit 3=1
RE (LVDWE) Bit 0=0, IOCD1
N/A
(LVDIE) Bit 3=1
N/A
Set RE (LVDIF)=1,
Low voltage detector
wake-up is invalid.
Oscillator, TCC, TCCX and
IR/PWM keep on running.
N/A
RE (LVDWE) Bit 0=1,
IOCD1 (LVDIE) Bit 3=0
RE (LVDWE) Bit 0=1, IOCD1
N/A
(LVDIE) Bit 3=0
N/A
Wake-up + Next
Instruction,
Wake-up + Next Instruction,
Oscillator, TCC, TCCX
and IR/PWM are
stopped.
Wake-up + Next
Instruction + Set RE
(LVDIF)=1,
Oscillator, TCC, TCCX and
IR/PWM keep on running.
N/A
N/A
RE (LVDWE) Bit 0=1, DISI + DISI + IOCD1 (LVDIE)
IOCD1 (LVDIE) Bit 3=1
Bit 3=1
DISI + IOCD1 (LVDIE)
Bit 3=1
Wake-up + Next Instruction
+ Set RE (LVDIF)=1,
Next Instruction
Next Instruction
Oscillator, TCC, TCCX and
IR/PWM keep on running.
+ Set RE (LVDIF)=1
+ Set RE (LVDIF)=1
RE (LVDWE) Bit 2=1,
ENI + IOCD1 (LVDIE)
Bit 3=1
RE (LVDWE) Bit0=1, ENI +
IOCD1 (LVDIE) Bit 3=1
ENI + IOCD1 (LVDIE)
Bit 3=1
ENI + IOCD1 (LVDIE)
Bit 3=1
Wake-up + Interrupt
Vector (021H) + Set RE
(LVDIF)=1,Oscillator,
TCC, TCCX and
IR/PWM are stopped.
Wake-up + Interrupt Vector
(021H) + Set RE
Interrupt Vector (021H)
(LVDIF)=1,Oscillator, TCC,
+ Set RE (LVDIF)=1
TCCX and IR/PWM keep on
running.
Wake-up + Reset
(Address 0x00)
Wake-up + Reset
Wake-up + Reset
(Address 0x00)
Wake-up + Reset
Oscillator, TCC, TCCX
and IR/PWM are
stopped.
Low voltage
reset
Low voltage detector
interrupted is invalid.
N/A
RE (LVDWE) Bit =1,
DISI + IOCD1 (LVDIE)
Bit 3=1
IOCE (WDTE)
Bit 7=1
Green Mode
RE (LVDWE) Bit 0=0, IOCD1
IOCD1 (LVDIE) Bit 3=0
(LVDIE) Bit 3=0
Low voltage detector
wake-up is invalid.
Oscillator, TCC, TCCX
and IR/PWM are
stopped.
WDT Time Out
Normal Mode
RE (LVDWE) Bit 0=0,
IOCD1 (LVDIE) Bit 3=0
Set RE (LVDIF)=1,
Low Voltage
Detector
interrupt
Idle Mode
(Address 0x00)
(Address 0x00)
Product Specification (V1.0) 12.01.2006
(This specification is subject to change without further notice)
Reset (Address 0x00)
Reset (Address 0x00)
Interrupt Vector (021H)
+ Set RE (LVDIF)=1
Reset (Address 0x00)
Reset (Address 0x00)
• 43
EM78P341N/342N/343N
8-Bit Microprocessor with OTP ROM
6.5.1.2 Register Initial Values after Reset
The following summarizes the registers initialized values.
Address
Name
Reset Type
Bit Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
C57
C56
C55
C54
C53
C52
C51
C50
–
–
108C
Type
N/A
IOC50
108C
342N
N/A
IOC70
IOC80
IOC90
N/A
44 •
IOCA0
(IR CR)
IOCB0
(PDCR)
343N
0
1
1
0
1
0
1
0
1
1
1
/RESET and WDT
0
1
0
1
1
0
1
0
1
0
1
1
1
Wake-up from Pin
Change
0
P
0
P
P
0
P
0
P
0
P
P
P
C61
C60
C67
C66
–
341N
342N
C65
C64
C63
C62
343 108C 342N 108C 342N 108C 342N 108C 342N
N
341N 343N 341N 343N 341N 343N 341N 343N
341N
341N
108C 342N 108C 342N
343N
343N
Power-on
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
/RESET and WDT
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Wake-up from Pin
Change
P
0
P
0
P
0
P
0
P
0
P
0
P
0
P
Bit Name
X
X
X
X
X
X
C71
C70
Power-on
0
0
0
0
0
0
1
1
/RESET and WDT
0
0
0
0
0
0
1
1
Wake-up from Pin
Change
P
P
P
P
P
P
P
P
Bit Name
X
X
CMPOUT
COS1
COS0
Power-on
0
0
0
0
0
0
0
0
/RESET and WDT
0
0
0
0
0
0
0
0
Wake-up from Pin
Change
P
P
P
P
P
P
P
P
TCCBHE TCCBEN TCCBTS TCCBTE
X
TCCAEN TCCATS TCCATE
TCCCEN TCCCTS TCCCTE
Power-on
0
0
0
0
0
0
0
0
/RESET and WDT
0
0
0
0
0
0
0
0
Wake-up from Pin
Change
P
P
P
P
P
P
P
P
Bit Name
N/A
343N
1
Bit Name
N/A
343N
342N
108C
N/A
341N
0
Type
IOC60
341N
108C 342N 108C 342N 108C 342N
Power-on
Bit Name
N/A
341N
–
341N 343N 341N 343N
IRE
HF
LGP
IROUTE
Power-on
TCCCSE TCCCS2 TCCCS1 TCCCS0
0
0
0
0
0
0
0
0
/RESET and WDT
0
0
0
0
0
0
0
0
Wake-up from Pin
Change
P
P
P
P
P
P
P
P
Bit Name
/PD57
/PD56
/PD55
/PD54
/PD53
/PD52
/PD51
/PD50
Power-on
1
1
1
1
1
1
1
1
/RESET and WDT
1
1
1
1
1
1
1
1
Wake-up from Pin
Change
P
P
P
P
P
P
P
P
Product Specification (V1.0) 12.01.2006
(This specification is subject to change without further notice)
EM78P341N/342N/343N
8-Bit Microprocessor with OTP ROM
Address
N/A
Name
IOCC0
(ODCR)
Reset Type
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit Name
/OD67
/OD66
/OD65
/OD64
/OD63
/OD62
/OD61
/OD60
Power-on
1
1
1
1
1
1
1
1
/RESET and WDT
1
1
1
1
1
1
1
1
Wake-up from Pin
Change
P
P
P
P
P
P
P
P
/PH57
/PH56
/PH55
/PH54
/PH53
/PH52
/PH51
/PH50
Bit Name
N/A
N/A
IOCD0
(PHCR1)
IOCE0
Power-on
1
1
1
1
1
1
1
1
/RESET and WDT
1
1
1
1
1
1
1
1
Wake-up from Pin
Change
P
P
P
P
P
P
P
P
Bit Name
WDTC
EIS
ADIE
CMPIE
PSWE
PSW2
PSW1
PSW0
Power-on
0
0
0
0
0
0
0
0
/RESET and WDT
0
0
0
0
0
0
0
0
Wake-up from Pin
Change
P
P
P
P
P
P
P
P
EXIE
ICIE
TCIE
Bit Name
N/A
N/A
IOCF0
IOC51
(TCCA)
LPWTIE HPWTIE TCCCIE TCCBIE TCCAIE
Power-on
0
0
0
0
0
0
0
0
/RESET and WDT
0
0
0
0
0
0
0
0
Wake-up from Pin
Change
P
P
P
P
P
P
P
P
Bit Name
TCCA7
TCCA6
TCCA5
TCCA4
TCCA3
TCCA2
TCCA1
TCCA0
Power-on
0
0
0
0
0
0
0
0
/RESET and WDT
0
0
0
0
0
0
0
0
Wake-up from Pin
Change
P
P
P
P
P
P
P
P
TCCB7
TCCB6
TCCB5
TCCB4
TCCB3
TCCB2
TCCB1
TCCB0
Bit Name
N/A
IOC61
(TCCB)
Power-on
0
0
0
0
0
0
0
0
/RESET and WDT
0
0
0
0
0
0
0
0
Wake-up from Pin
Change
P
P
P
P
P
P
P
P
Bit Name
N/A
IOC71
(TCCBH)
N/A
IOC81
(TCCC)
IOC91
(LTR)
TCCBH
0
Power-on
0
0
0
0
0
0
0
0
/RESET and WDT
0
0
0
0
0
0
0
0
Wake-up from Pin
Change
P
P
P
P
P
P
P
P
TCCC7
TCCC6
TCCC5
TCCC4
TCCC3
TCCC2
TCCC1
TCCC0
Bit Name
N/A
TCCBH7 TCCBH6 TCCBH5 TCCBH4 TCCBH3 TCCBH2 TCCBH1
Power-on
0
0
0
0
0
0
0
0
/RESET and WDT
0
0
0
0
0
0
0
0
Wake-up from Pin
Change
P
P
P
P
P
P
P
P
Bit Name
LTR7
LTR6
LTR5
LTR4
LTR3
LTR2
LTR1
LTR0
Power-on
0
0
0
0
0
0
0
0
/RESET and WDT
0
0
0
0
0
0
0
0
Wake-p from Pin
Change
P
P
P
P
P
P
P
P
Product Specification (V1.0) 12.01.2006
(This specification is subject to change without further notice)
• 45
EM78P341N/342N/343N
8-Bit Microprocessor with OTP ROM
Address
Name
Reset Type
Bit Name
N/A
N/A
IOCA1
(HTR)
IOCB1
(HLTS)
IOCC1
(TCCPC)
N/A
0x00
0x01
46 •
R0(IAR)
R1(TCC)
Bit 1
Bit 0
HTR1
HTR0
0
0
0
0
0
0
0
0
0
0
0
0
0
Wake-up from Pin
Change
P
P
P
P
P
P
P
P
Bit Name
HTSE
HTS2
HTS1
HTS0
LTSE
LTS2
LTS1
LTS0
Power-on
0
0
0
0
0
0
0
0
/RESET and WDT
0
0
0
0
0
0
0
0
Wake-up from Pin
Change
P
P
P
P
P
P
P
P
TCCPC7 TCCPC6 TCCPC5 TCCPC4 TCCPC3 TCCPC2 TCCPC1
TCCPC
0
Power-on
0
0
0
0
0
0
0
0
/RESET and WDT
0
0
0
0
0
0
0
0
Wake-up from Pin
Change
P
P
P
P
P
P
P
P
TYPE1
TYPE0
LVR1
LVR0
LVDIE
LVDEN
LVD1
LVD0
IOCE1
Power-on
(HSC)
(ROMLESS) /RESET and WDT
Wake-up from Pin
Change
CONT
Bit 2
HTR2
0
Power-on
IOCD1
(LVD CR)
/RESET and WDT
(ROMLESS)
Wake-up from Pin
Change
IOCF1
(PHCR2)
Bit 3
HTR3
0
Bit Name
N/A
Bit 4
HTR4
0
HS1
N/A
Bit 5
HTR5
/RESET and WDT
Bit Name
N/A
Bit 6
HTR6
Power-on
Bit Name
N/A
Bit 7
HTR7
1
1
1
1
0
0
1
1
P
P
P
P
0
P
1
1
P
P
P
P
P
P
P
P
WDPTS
TIMERS
C
CPUS
IDLE
HS3
HS2
HS1
HS0
1
1
1
1
0
0
0
0
P
1
1
1
0
0
0
0
P
P
P
P
P
P
P
P
/PH67
/PH66
/PH65
/PH64
/PH63
/PH62
/PH61
/PH60
Power-on
1
1
1
1
1
1
1
1
/RESET and WDT
1
1
1
1
1
1
1
1
Wake-up from Pin
Change
P
P
P
P
P
P
P
P
Bit Name
INTE
INT
TS
TE
PSTE
PST2
PST1
PST0
Power-on
1
0
1
1
0
0
0
0
/RESET and WDT
1
0
1
1
0
0
0
0
Wake-up from Pin
Change
P
P
P
P
P
P
P
P
Bit Name
–
–
–
–
–
–
–
–
Power-on
U
U
U
U
U
U
U
U
/RESET and WDT
P
P
P
P
P
P
P
P
Wake-up from Pin
Change
P
P
P
P
P
P
P
P
Bit Name
–
–
–
–
–
–
–
–
Power-on
0
0
0
0
0
0
0
0
/RESET and WDT
0
0
0
0
0
0
00
0
Wake-up from Pin
Change
P
P
P
P
P
P
P
P
Product Specification (V1.0) 12.01.2006
(This specification is subject to change without further notice)
EM78P341N/342N/343N
8-Bit Microprocessor with OTP ROM
Address
0x02
Name
R2 (PC)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit Name
Reset Type
–
–
–
–
–
–
–
–
Power-on
0
0
0
0
0
0
0
0
/RESET and WDT
0
0
0
0
0
0
0
0
Wake-up from Pin
Change
0x03
0x04
R3 (SR)
R4 (RSR)
Jump to address 0x06 or continue to execute next instruction
Bit Name
RST
IOCS
PS0
T
P
Z
DC
C
Power-on
0
0
0
1
1
U
U
U
/RESET and WDT
0
0
0
T
t
P
P
P
Wake-up from Pin
Change
P
P
P
T
t
P
P
P
Bit Name
X
BS
X
X
X
X
X
X
Power-on
0
0
U
U
U
U
U
U
/RESET and WDT
0
0
P
P
P
P
P
P
Wake-up from Pin
Change
0
P
P
P
P
P
P
P
P57
P56
P55
P54
P53
P52
P51
P50
Bit Name
0x05
R5
Power-on
1
1
1
1
1
1
1
1
/RESET and WDT
1
1
1
1
1
1
1
1
Wake-up from Pin
Change
P
P
P
P
P
P
P
P
P67
P66
P65
P64
P63
P62
P61
P60
Bit Name
0x06
0x7
0x8
R6
R7
R8
(AISR)
Power-on
1
1
1
1
1
1
1
1
/RESET and WDT
1
1
1
1
1
1
1
1
Wake-up from Pin
Change
P
P
P
P
P
P
P
P
Bit Name
–
–
–
–
–
–
P71
P70
Power-on
0
0
0
0
0
0
1
1
/RESET and WDT
0
0
0
0
0
0
1
1
Wake-up from Pin
Change
P
P
P
P
P
P
P
P
Bit Name
–
–
–
–
ADE3
ADE2
ADE1
ADE0
Power-on
0
0
0
0
0
0
0
0
/RESET and WDT
0
0
0
0
0
0
0
0
Wake-up from Pin
Change
0
0
0
0
P
P
P
P
VREFS
CKR1
CKR0
ADRUN
ADPD
–
ADIS1
ADIS0
Bit Name
0x9
0xA
R9
(ADCON)
RA
(ADOC)
Power-on
0
0
0
0
0
0
0
0
/RESET and WDT
0
0
0
0
0
0
0
0
Wake-up from Pin
Change
P
P
P
P
P
0
P
P
Bit Name
CALI
SIGN
VOF[2]
VOF[1]
VOF[0]
–
–
–
Power-on
0
0
0
0
0
0
0
0
/RESET and WDT
0
0
0
0
0
0
0
0
Wake-up from Pin
Change
P
P
P
P
P
P
P
P
Product Specification (V1.0) 12.01.2006
(This specification is subject to change without further notice)
• 47
EM78P341N/342N/343N
8-Bit Microprocessor with OTP ROM
Address
0XB
0XC
0XD
0xE
Name
RB
(ADDATA)
Reset Type
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit Name
AD11
AD10
AD9
AD8
AD7
AD6
AD5
AD4
Power-on
U
U
U
U
U
U
U
U
/RESET and WDT
U
U
U
U
U
U
U
U
Wake-up from Pin
Change
P
P
P
P
P
P
P
P
Bit Name
“0”
“0”
“0”
“0”
AD11
AD10
AD9
AD8
0
0
0
0
U
U
U
U
0
0
0
0
U
U
U
U
0
0
0
0
P
P
P
P
Bit Name
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
Power-on
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
P
P
P
P
P
P
P
P
Bit Name
–-
–
ADIF
CMPIF
ADWE
CMPWE
ICWE
–
Power-on
0
0
0
0
0
0
0
0
/RESET and WDT
0
0
0
0
0
0
0
0
Wake-up from Pin
Change
P
P
P
P
P
P
P
P
EXIF
ICIF
TCIF
Power-on
RC
(ADDATA1H) /RESET and WDT
Wake-up from Pin
Change
RD
(ADDATA1L0) /RESET and WDT
Wake-up from Pin
Change
RE
(ISR2)
Bit Name
0xF
0x10~0x3F
RF
(ISR1)
R10~R3F
Power-on
0
0
0
0
0
0
0
0
/RESET and WDT
0
0
0
0
0
0
0
0
Wake-up from Pin
Change
P
P
P
P
P
P
P
P
Bit Name
–
–
–
–
–
–
–
–
Power-on
U
U
U
U
U
U
U
U
/RESET and WDT
P
P
P
P
P
P
P
P
Wake-up from Pin
Change
P
P
P
P
P
P
P
P
Legend: “–” = not used
“u” = unknown or don’t care
48 •
LPWTIF HPWTIF TCCCIF TCCBIF TCCAIF
“P” = previous value before reset
“t” = check “Reset Type” Table in Section 6.5.2
Product Specification (V1.0) 12.01.2006
(This specification is subject to change without further notice)
EM78P341N/342N/343N
8-Bit Microprocessor with OTP ROM
6.5.1.3 Controller Reset Block Diagram
VDD
D
Oscillator
Q
CLK
CLK
CLR
Power-on Reset
Voltage
Detector
ENWDTB
WDT Timeout
Reset
Setup time
WDT
/RESET
Fig. 6-8 Controller Reset Block Diagram
6.5.2 The T and P Status under Status (R3) Register
A reset condition is initiated by one of the following events:
1. Power-on reset
2. /RESET pin input "low"
3. WDT time-out (if enabled)
The values of RST, T, and P as listed in the table below, are used to check how the
processor wakes up.
Reset Type
RST
T
P
Power-on
/RESET during Operating mode
0
0
1
*P
1
*P
/RESET wake-up during SLEEP mode
0
1
0
WDT during Operating mode
0
0
1
WDT wake-up during SLEEP mode
0
0
0
Wake-up on pin change during SLEEP mode
1
1
0
*P: Previous status before reset
The following shows the events that may affect the status of T and P.
Event
RST
T
P
Power-on
0
1
1
WDTC instruction
*P
1
1
WDT time-out
0
0
*P
SLEP instruction
*P
1
0
Wake-up on pin changed during SLEEP mode
1
1
0
*P: Previous value before reset
Product Specification (V1.0) 12.01.2006
(This specification is subject to change without further notice)
• 49
EM78P341N/342N/343N
8-Bit Microprocessor with OTP ROM
6.6 Interrupt
The EM78P341N/342N/343N has six interrupts as listed below:
1. TCC, TCCA, TCCB, TCCC overflow interrupt
2. Port 5 Input Status Change Interrupt
3. External interrupt [(P60, /INT) pin]
4. Analog to Digital conversion completed
5. IR/PWM underflow interrupt
6. When the comparators status changes (not applicable to EM78P341N)
7. Low voltage detector interrupt
Before the Port 5 Input Status Change Interrupt is enabled, reading Port 5 (e.g. "MOV
R5,R5") is necessary. Each Port 5 pin will have this feature if its status changes. The
Port 5 Input Status Change Interrupt will wake up the EM78P341N/342N/343N from
sleep mode if it is enabled prior to going into sleep mode by executing SLEP instruction.
When wake up occurs, the controller will continue to execute program in-line if the global
interrupt is disabled. If enabled, the global interrupt will branch out to the interrupt vector
006H.
External interrupt equipped with digital noise rejection circuit (input pulse less than
system clock time) is eliminated as noise. However, under Low Crystal oscillator (LXT)
mode the noise rejection circuit will be disabled. Edge selection is possible with INTE
of CONT. When an interrupt is generated by the External interrupt (when enabled), the
next instruction will be fetched from address 003H. Refer to the Word 1 Bits 9 & 8
(Section 6.14.2, Code Option Register (Word 1)) for digital noise rejection definition.
RF and RE are the interrupt status register that records the interrupt requests in the
relative flags/bits. IOCF0 and IOCE0 are interrupt mask registers. The global interrupt
is enabled by the ENI instruction and is disabled by the DISI instruction. Once in the
interrupt service routine, the source of an interrupt can be determined by polling the flag
bits in RF. The interrupt flag bit must be cleared by instructions before leaving the
interrupt service routine to avoid recursive interrupts.
The flag (except for the ICIF bit) in the Interrupt Status Register (RF) is set regardless of
the ENI execution. Note that the result of RF will be the logic AND of RF and IOCF0
(refer to figure below). The RETI instruction ends the interrupt routine and enables the
global interrupt (the ENI execution).
When an interrupt is generated by the Timer clock/counter (when enabled), the next
instruction will be fetched from Address 009, 018, 01B, and 01EH (TCC, TCCA, TCCB,
and TCCC respectively).
When an interrupt generated by the AD conversion is completed (when enabled), the
next instruction will be fetched from Address 00CH.
50 •
Product Specification (V1.0) 12.01.2006
(This specification is subject to change without further notice)
EM78P341N/342N/343N
8-Bit Microprocessor with OTP ROM
When an interrupt is generated by the High time / Low time down counter underflow
(when enabled), the next instruction will be fetched from Addresses 012 and 015H
(High time and Low time respectively).
When an interrupt is generated by the Comparators (when enabled), the next
instruction will be fetched from Address 00FH (Comparator interrupt).
When an interrupt is generated by the Low Voltage Detect (when enabled), the next
instruction will be fetched from Address 021 (Low Voltage Detector interrupt).
Before an interrupt subroutine is executed, the contents of ACC and the R3 and R4
registers are saved first by the hardware. If another interrupt occurs, the ACC, R3, and
R4 will be replaced by the new interrupt. After an interrupt service routine is completed,
the ACC, R3, and R4 registers are restored.
VCC
D
/IRQn
P
R
CLK
RF
C
L
Q
IRQn
INT
_
Q
RFRD
IRQm
ENI/DISI
IOCF
Q
P
R
_
Q
C
L
IOD
D
CLK
IOCFWR
/RESET
IOCFRD
RFWR
Fig. 6.9 Interrupt Input Circuit
Interrupt
Interrupt Sources
ACC
occurs
Stack ACC
ENI/DISI
R3
RETI
R4
Sack R3
Stack R4
Fig. 6.10 Interrupt Backup Diagram
Product Specification (V1.0) 12.01.2006
(This specification is subject to change without further notice)
• 51
EM78P341N/342N/343N
8-Bit Microprocessor with OTP ROM
In EM78P341N/342N/343N, each individual interrupt source has its own interrupt
vector as depicted in the table below.
Interrupt Vector
Interrupt Status
Priority*
003H
External interrupt
2
006H
Port 5 pin change
3
009H
TCC overflow interrupt
4
00CH
AD conversion complete interrupt
5
00FH
Comparator interrupt
6
012H
High-pulse width timer underflow interrupt
7
015H
Low-pulse width timer underflow interrupt
8
018H
TCCA overflow interrupt
9
01BH
TCCB overflow interrupt
10
01EH
TCCC overflow interrupt
11
021H
Low Voltage Detector interrupt
1
*Priority: 1 = highest ; 11 = lowest priority
NOTE
■ Comparator interrupt is not applicable to EM78P341N.
52 •
Product Specification (V1.0) 12.01.2006
(This specification is subject to change without further notice)
EM78P341N/342N/343N
8-Bit Microprocessor with OTP ROM
6.7 Analog-To-Digital Converter (ADC)
The analog-to-digital circuitry consist of a 4-bit analog multiplexer; three control
registers (AISR/R8, ADCON/R9, & ADOC/RA), three data registers (ADDATA/RB,
ADDATA1H/RC, & ADDATA1L/RD), and an ADC with 12-bit resolution as shown in the
functional block diagram below. The analog reference voltage (Vref) and the analog
ground are connected via separate input pins.
The ADC module utilizes successive approximation to convert the unknown analog
signal into a digital value. The result is fed to the ADDATA, ADDATA1H, and
ADDATA1L. Input channels are selected by the analog input multiplexer via the
ADCON register Bits ADIS1 and ADIS0.
ADC7
Vref
ADC6
h
c
t
i
w
S
g
o
l
a
n
A
1
8
ADC5
ADC4
ADC3
ADC2
ADC1
ADC0
Power-Down
ADC
( successive approximation )
Start to Convert
Fsco
4-1
MUX
Internal RC
7 ~ 0
AISR
1
ADCON
0
6
3
5
ADCON
RF
11 10
9
8
7
6
ADDATA1H
5
4
3
2
1
0
4
3
ADCON
ADDATA1L
DATA BUS
Fig. 6-11 Analog-to-Digital Conversion Functional Block Diagram
6.7.1 ADC Control Register (AISR/R8, ADCON/R9, ADOC/RA)
6.7.1.1 R8 (AISR: ADC Input Select Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ADE7
ADE6
ADE5
ADE4
ADE3
ADE2
ADE1
ADE0
AISR register defines the P5, P6, P7 pins as analog inputs or as digital I/O, individually.
Bit 7 (ADE7): AD converter enable bit of P57 pin
0 = Disable ADC7, P57 functions as I/O pin
1 = Enable ADC7 to function as analog input pin
Bit 6 (ADE6): AD converter enable bit of P55 pin
0 = Disable ADC6, P55 functions as I/O pin
1 = Enable ADC6 to function as analog input pin
Bit 5 (ADE5): AD converter enable bit of P70 pin
0 = Disable ADC5, P70 functions as I/O pin
1 = Enable ADC5 to function as analog input pin
Product Specification (V1.0) 12.01.2006
(This specification is subject to change without further notice)
• 53
EM78P341N/342N/343N
8-Bit Microprocessor with OTP ROM
Bit 4 (ADE4): AD converter enable bit of P67 pin
0 = Disable ADC4, P67 functions as I/O pin
1 = Enable ADC4 to function as analog input pin
Bit 3 (ADE3):
AD converter enable bit of P53 pin
0 = Disable ADC3, P53 functions as I/O pin
1 = Enable ADC3 to function as analog input pin
Bit 2 (ADE2):
AD converter enable bit of P52 pin
0 = Disable ADC2, P53 functions as I/O pin
1 = Enable ADC2 to function as analog input pin
Bit 1 (ADE1):
AD converter enable bit of P51 pin
0 = Disable ADC1, P51 functions as I/O pin
1 = Enable ADC1 to function as analog input pin
Bit 0 (ADE0):
AD converter enable bit of P50 pin
0 = Disable ADC0, P50 functions as I/O pin
1 = Enable ADC0 to function as analog input pin
6.7.1.2 R9 (ADCON: AD Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
VREFS
CKR1
CKR0
ADRUN
ADPD
ADIS2
ADIS1
ADIS0
The ADCON register controls the operation of the AD conversion and decides which
pin should be currently active.
Bit 7(VREFS): The input source of the ADC Vref
0 = The ADC Vref is connected to Vdd (default value), and the
VREF/TCC/P54 pin carries out the P54 function
1 = The ADC Vref is connected to VREF/TCC/P54
NOTE
The P54/TCC/VREF pin cannot be applied to TCC and VREF at the same time. If
P54/TCC/VREF functions as VREF analog input pin, then CONT Bit 5 (TS) must be “0”.
The P54/TCC/VREF pin priority is as follows:
P54/TCC/VREF Pin Priority
54 •
High
Medium
Low
VREF
TCC
P54
Product Specification (V1.0) 12.01.2006
(This specification is subject to change without further notice)
EM78P341N/342N/343N
8-Bit Microprocessor with OTP ROM
Bit 6 & Bit 5 (CKR1 & CKR0): The prescaler of ADC oscillator clock rate
00 = 1: 16 (default value)
01 = 1: 4
10 = 1: 64
11 = 1: 8
CPUS
CKR1: CKR0
Operation Mode
Max. Operation Frequency
Fosc/16
4MHz
1
00
1
01
Fosc/4
1MHz
1
10
Fosc/64
16MHz
1
11
Fosc/8
2MHz
0
××
Internal RC
−
Bit 4 (ADRUN): ADC starts to RUN
1 = an AD conversion is started. This bit can be set by software.
0 = Reset upon completion of the conversion. This bit cannot be
reset through software
Bit 3 (ADPD):
ADC Power-down mode.
1 = ADC is operating
0 = switch off the resistor reference to save power even
while the CPU is operating.
Bit 2 ~ Bit 0 (ADIS2 ~ ADIS0): Analog Input Select
000 = ADIN0/P50
001 = ADIN1/P51
010 = ADIN2/P52
011 = ADIN3/P53
100 = ADIN0/P67
101 = ADIN1/P70
110 = ADIN2/P55
111 = ADIN3/P57
These bits can only be changed when the ADIF bit and the ADRUN bit
are both LOW.
6.7.1.3 RA (ADOC: AD Offset Calibration Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
CALI
SIGN
VOF[2]
VOF[1]
VOF[0]
–
–
–
Bit 7 (CALI): Calibration enable bit for ADC offset
0 = disable Calibration
1 = enable Calibration
Bit 6 (SIGN): Polarity bit of offset voltage
0 = Negative voltage
1 = Positive voltage
Product Specification (V1.0) 12.01.2006
(This specification is subject to change without further notice)
• 55
EM78P341N/342N/343N
8-Bit Microprocessor with OTP ROM
Bit 5 ~ Bit 3 (VOF[2] ~ VOF[0]): Offset voltage bits
VOF[2]
VOF[1]
VOF[0]
EM78P342N/343N
ICE342N
0
0
0
0
0
1
0LSB
2LSB
0LSB
2LSB
0
1
0
4LSB
4LSB
0
1
1
6LSB
6LSB
1
0
0
8LSB
8LSB
1
0
1
10LSB
10LSB
1
1
0
12LSB
12LSB
1
1
1
14LSB
14LSB
Bit 2 ~ Bit 0: Unimplemented, read as ‘0’.
6.7.2 ADC Data Register (ADDATA/RB, ADDATA1H/RC, ADDATA1L/RD)
When the AD conversion is completed, the result is loaded to the ADDATA, ADDATA1H
and ADDATA1L registers. The ADRUN bit is cleared, and the ADIF is set.
6.7.3 ADC Sampling Time
The accuracy, linearity, and speed of the successive approximation of AD converter are
dependent on the properties of the ADC and the comparator. The source impedance
and the internal sampling impedance directly affect the time required to charge the
sample holding capacitor. The application program controls the length of the sample
time to meet the specified accuracy. Generally speaking, the program should wait for
2µs for each KΩ of the analog source impedance and at least 2µs for the low-impedance
source. The maximum recommended impedance for analog source is 10KΩ at Vdd=5V.
After the analog input channel is selected, this acquisition time must be done before the
conversion is started.
6.7.4 AD Conversion Time
CKR1 and CKR0 select the conversion time (Tct), in terms of instruction cycles. This
allows the MCU to run at a maximum frequency without sacrificing the AD conversion
accuracy. For the EM78P342N/343N, the conversion time per bit is 4µs. The table
below shows the relationship between Tct and the maximum operating frequencies.
CKR1: CKR0 Operation Mode
Max. Operation Max. Conversion
Max. Conversion Rate
Frequency
Rate/Bit
00
01
Fsco/16
Fsco/4
4 MHz
1MHz
250kHz (4µs)
250kHz (4µs)
15×4µs=60µs(16.7kHz)
15×4µs=60µs(16.7kHz)
10
Fsco/64
16MHz
250kHz( 4µs)
15×4µs=60µs(16.7kHz)
11
Fsco/8
2MHz
250kHz (4µs)
15×4µs=1065µs(16.7kHz)
NOTE
■ Pin not used as an analog input pin can be used as a regular input or output pin.
■ During conversion, do not perform output instruction to maintain precision for all of
the pins.
56 •
Product Specification (V1.0) 12.01.2006
(This specification is subject to change without further notice)
EM78P341N/342N/343N
8-Bit Microprocessor with OTP ROM
6.7.5 ADC Operation during Sleep Mode
In order to obtain a more accurate ADC value and reduce power consumption, the AD
conversion remains operational during sleep mode. As the SLEP instruction is
executed, all the MCU operations will stop except for the Oscillator, TCC, TCCA,
TCCB, TCCC and AD conversion.
The AD Conversion is considered completed as determined by:
1. ADRUN bit of R9 register is cleared to “0”.
2. ADIF bit of RE register is set to “1”.
3. ADWE bit of the RE register is set to “1.” Wake-up from ADC conversion (where it
remains in operation during sleep mode).
4. Wake-up and executes the next instruction if ADIE bit of IOCE0 is enabled and the
“DISI” instruction is executed.
5. Wake-up and enters into Interrupt vector (Address 0x00C) if ADIE bit of IOCE0 is
enabled and the “ENI” instruction is executed.
6. Enters into Interrupt vector (Address 0x00C) if ADIE bit of IOCE0 is enabled and the
“ENI” instruction is executed.
The results are fed into the ADDATA, ADDATA1H, and ADDATA1L registers when the
conversion is completed. If the ADIE is enabled, the device will wake up. Otherwise,
the AD conversion will be shut off, no matter what the status of ADPD bit is.
6.7.6 Programming Process/Considerations
6.7.6.1 Programming Process
Follow these steps to obtain data from the ADC:
1. Write to the seven bits (ADE7:ADE0) on the R8 (AISR) register to define the
characteristics of R5 (digital I/O, analog channels, or voltage reference pin)
2. Write to the R9/ADCON register to configure the AD module:
a) Select the ADC input channel (ADIS2: ADIS0)
b) Define the AD conversion clock rate (CKR1: CKR0)
c) Select the VREFS input source of the ADC
d) Set the ADPD bit to 1 to begin sampling
3. Set the ADWE bit, if the wake-up function is employed
4. Set the ADIE bit, if the interrupt function is employed
5. Write “ENI” instruction, if the interrupt function is employed
6. Set the ADRUN bit to 1
7. Write “SLEP” instruction or Polling.
8. Wait for wake-up, ADRUN bit is cleared to “0”, interrupt flag (ADIF) is set “1,” or
ADC interrupt occurs.
Product Specification (V1.0) 12.01.2006
(This specification is subject to change without further notice)
• 57
EM78P341N/342N/343N
8-Bit Microprocessor with OTP ROM
9. Read the ADDATA or ADDATA1H and ADDATA1L conversion data registers. If the
ADC input channel changes at this time, the ADDATA, ADDATA1H, and ADDATA1L
values can be cleared to ‘0’.
10. Clear the interrupt flag bit (ADIF)
11. For the next conversion, go to Step 1 or Step 2 as required. At least two Tct is
required before the next acquisition starts.
NOTE
In order to obtain accurate values, it is necessary to avoid any data transition on the I/O
pins during AD conversion.
6.7.6.2 Sample Demo Programs
A. Define a General Register
R_0 == 0
PSW == 3
PORT5 == 5
PORT6 == 6
R_E== 0XE
; Indirect addressing register
; Status register
; Interrupt status register
B. Define a Control Register
IOC50 == 0X5
IOC60 == 0X6
C_INT== 0XF
; Control Register of Port 5
; Control Register of Port 6
; Interrupt Control Register
C. ADC Control Register
ADDATA == 0xB
AISR == 0x08
ADCON == 0x9
; The contents are the results of ADC
; ADC input select register
; 7
6
5
4
3
2
1
0
; VREFS CKR1 CKR0 ADRUN ADPD ADIS2 ADIS1 ADIS0
D. Define Bits in ADCON
ADRUN == 0x4
ADPD == 0x3
; ADC is executed as the bit is set
; Power Mode of ADC
E. Program Starts
ORG 0
JMP INITIAL
; Initial address
;
ORG 0x0C
; Interrupt vector
JMP CLRRE
;
;
;(User program section)
;
;
58 •
Product Specification (V1.0) 12.01.2006
(This specification is subject to change without further notice)
EM78P341N/342N/343N
8-Bit Microprocessor with OTP ROM
CLRRE:
MOV A,RE
AND A, @0BXX0XXXXX ; To clear the ADIF bit, “X” by application
MOV RE,A
BS ADCON, ADRUN
; To start to execute the next AD conversion
if necessary
RETI
INITIAL:
MOV A,@0B00000001
; To define P50 as an analog input
MOV AISR,A
MOV A,@0B00001000
; To select P50 as an analog input channel, and
AD power on
MOV ADCON,A
; To define P50 as an input pin and set clock
rate at fosc/16
En_ADC:
MOV A, @0BXXXXXXX1 ; To define P50 as an input pin, and the others
IOW PORT5
; are dependent on applications
MOV A, @0BXXXX1XXX ; Enable the ADWE wake-up function of ADC, “X”
by application
MOV RE,A
MOV A, @0BXXXX1XXX ; Enable the ADIE interrupt function of ADC,
“X” by application
IOW C_INT
ENI
; Enable the interrupt function
BS ADCON, ADRUN
; Start to run the ADC
; If the interrupt function is employed, the following three lines
may be ignored
;If Sleep:
SLEP
;
;(User program section)
;
or
;If Polling:
POLLING:
JBC ADCON, ADRUN
JMP POLLING
; To check the ADRUN bit continuously;
; ADRUN bit will be reset as the AD conversion
is completed
;
;(User program section)
;
Product Specification (V1.0) 12.01.2006
(This specification is subject to change without further notice)
• 59
EM78P341N/342N/343N
8-Bit Microprocessor with OTP ROM
6.8 Infrared Remote Control Application/PWM Waveform Generation
6.8.1 Overview
This LSI can easily output infrared carrier or PWM standard waveform. As illustrated
below, the IR and PWM waveform generation function include an 8-bit down count
timer/counter, high-time, low-time, and IR control register. The IROUT pin waveform is
determined by IOCA0 (IR and TCCC scale control register), IOCB1 (high-time rate,
low-time rate control register), IOC81 (TCCC counter), IOCA1 (high-time register), and
IOC91 (low-time register).
FT:CLK(Fosc)
8 Bit counter
8 Bit counter
8 Bit counter
Scale
(IOCA0)
Scale
(IOCB1)
8-to-1 MUX
8-to-1 MUX
8bit binary
down counter
8bit binary
down counter
Scale
(IOCB1)
8-to-1 MUX
Auto-reload buffer
(High-time)(IOCA1)
8
8
Fcarrier
8
Auto-reload buffer
(Low-time)(IOC91)
8
8bit binary
down counter
H/W Modulator
8
Auto-reload buffer
(TCCC)(IOC81)
HF
LG
IR
IROUT
Underflow Interrupt
HPWTIF
LPWTIF
Fig. 6-12 IR/PWM System Block Diagram
NOTE
Details of the Fcarrier high time width and low time width are explained below:
Fcarrier =
FT/ 2 { [1+decimal TCCC Counter value (IOC81)] * TCCC
Scale(IOCA0) }
High time width = { [1+decimal high-time value (IOCA1)] * High time Scale(IOCB1) } /
FT
Low time width = { [1+decimal low-time value (IOC91)] * Low time Scale(IOCB1) } /
FT
Where FT is the system clock FT=Fosc/1(CLK=2)
FT=Fosc/2(CLK=4)
When an interrupt is generated by the High time down counter underflow (when
enabled), the next instruction will be fetched from Address 018 and 01BH (High time
and Low time respectively).
60 •
Product Specification (V1.0) 12.01.2006
(This specification is subject to change without further notice)
EM78P341N/342N/343N
8-Bit Microprocessor with OTP ROM
6.8.2 Function Description
The following figure shows LGP=0 and HF=1. The IROUT waveform modulates the
Fcarrier waveform at low-time segments of the pulse.
Fcarrier
low time width
high time width
low time width
high time width
HF
Start
IRE
IROUT
Fig. 6-13a LGP=0, HF=1, IROUT Pin Output Waveform
The following figure shows LGP=0 and HF=0. The IROUT waveform cannot modulate
the Fcarrier waveform at low-time segments of the pulse. So IROUT waveform is
determined by the high time width and low time width instead. This mode can produce
standard PWM waveform.
Fcarrier
low time width
high time width
low time width
high time width
HF
Start
IRE
IROUT
Fig. 6-13b LGP=0, HF=0, IROUT Pin Output Waveform
Product Specification (V1.0) 12.01.2006
(This specification is subject to change without further notice)
• 61
EM78P341N/342N/343N
8-Bit Microprocessor with OTP ROM
The following figure shows LGP=0 and HF=1. The IROUT waveform modulates the
Fcarrier waveform at low-time segments of the pulse. When IRE goes low from high,
the output waveform of IROUT will keep transmitting until high-time interrupt occurs.
Fcarrier
low time width
high time width
low time width
high time width
HF
Start
IR disable
IRE
IROUT
Always high-level
Fig. 6-13c LGP=0, HF=1, When IRE goes Low from High, IROUT Pin Outputs Waveform
The following figure shows LGP=0 and HF=0. The IROUT waveform cannot modulate
the Fcarrier waveform at low-time segments of the pulse. So IROUT waveform is
determined by high time width and low time width. This mode can produce standard
PWM waveform when IRE goes low from high. The output waveform of IROUT will
keep on transmitting until high-time interrupt occurs.
Fcarrier
low time width
high time width
low time width
high time width
HF
Start
IRE
IROUT
IR disable
Always high-level
Fig. 6-13d LGP=0, HF=0, When IRE goes Low from High, Irout Pin Output Waveform
62 •
Product Specification (V1.0) 12.01.2006
(This specification is subject to change without further notice)
EM78P341N/342N/343N
8-Bit Microprocessor with OTP ROM
The following figure shows LGP=1 and HF=1. When this bit is set to high level, the
high-time segment of the pulse is ignored. So, IROUT waveform output is determined
by low-time width.
Fcarrier
low time width
low time width
low time width
HF
Start
IR disable
IRE
IROUT
Always high-level
Fig. 6-13e LGP=1 and HP=1, IROUT Pin Output Waveform
6.8.3
Programming the Related Registers
When defining IR/PWM, refer to the operation of the related registers as shown in the
tables below.
IR/PWM Related Control Registers
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
0x09
IOC90
0X0A
IR CR
TCCCSE/0 TCCCS2/0 TCCCS1/0 TCCCS0/0
/IOCA0
0x0F
IMR
/IOCF0
0X0B
HLTS
/IOCB1
TCCBHE/0TCCBEN/0 TCCBTS/0 TCCBTE/0
Bit 3
0
IRE/0
HTS2/0
HTS1/0
HTS0/0
Bit 1
Bit 0
TCCCEN/0TCCCTS/0 TCCCTE/0
HF/0
LGP/0
IROUTE/0
EXIE/0
ICIE/0
TCIE/0
LTSE/0
LTS2/0
LTS1/0
LTS0/0
Bit 3
Bit 2
Bit 1
Bit 0
EXIF/0
ICIF/0
TCIF/0
LPWTIE/0 HPWTIE/0 TCCCIE/0 TCCBIE/0 TCCAIE/0
HTSE/0
Bit 2
IR/PWM Related Status/Data Registers
Address
Name
Bit 7
Bit 6
Bit 5
0x0F
ISR/RF
LPWTIF/0 HPWTIF/0 TCCCIF/0 TCCBIF/0 TCCAIF/0
0x06
TCCC
/IOC81
TCCC7/0 TCCC6/0 TCCC5/0 TCCC4/0 TCCC3/0 TCCC2/0 TCCC1/0 TCCC0/0
0X09
LTR
/IOC91
LTR7/0
LTR6/0
LTR5/0
LTR4/0
LTR3/0
LTR2/0
LTR1/0
LTR0/0
0X0A
HTR
/IOCA1
HTR7/0
HTR6/0
HTR5/0
HTR4/0
HTR3/0
HTR2/0
HTR1/0
HTR0/0
Product Specification (V1.0) 12.01.2006
(This specification is subject to change without further notice)
Bit 4
• 63
EM78P341N/342N/343N
8-Bit Microprocessor with OTP ROM
6.9 Timer/Counter
6.9.1 Overview
Timer A (TCCA) is an 8-bit clock counter. Timer B (TCCB) is a 16-bit clock counter.
Timer C (TCCC) is an 8-bit clock counter that can be extended to 16-bit clock counter
with programmable scalers. TCCA, TCCB, and TCCC can be read and written to, and
are cleared at every reset condition.
6.9.2 Function Description
Set predict value
Set predict value
TCCAEN
Set predict value
TCCCEN
TCCBEN
Set TCCCIF
Set TCCBIF
Set TCCAIF
TCCC
TCCB
TCCA
Overflow
Overflow
Overflow
System clock or
External input
System clock or
External input
8-to-1 MUX
TCCCS1 ~ TCCCS0
8 Bit
counter
System clock or
External input
Fig. 6.14 TIMER Block Diagram
Each signal and block of the above Timer block diagram is described as follows:
TCCX: Timer A~C register. TCCX is incremented until it matches with zero, and then
reloads the predicted value. When writing a value to TCCX, the predicted
value and TCCX value become the set value. When reading from TCCX, the
value will be the TCCX direct value. When TCCXEN is enabled, the reloading
of the predicted value to TCCX, TCCXIE is also enabled. TCCXIF will be set at
the same time. It is an up counter.
TCCA Counter (IOC51):
IOC51 (TCCA) is an 8-bit clock counter. It can be read, written to, and cleared
on any reset condition and is an Up Counter.
NOTE
■ TCCA timeout period [1/Fosc x (256-TCCA cnt) x 1 (CLK=2)]
■ TCCA timeout period [1/Fosc x (256-TCCA cnt) x 2 (CLK=4)]
TCCB Counter (IOC61):
IOC61 is an 8-bit clock counter for the least significant byte of TCCBX (TCCB).
It can be read, written, and cleared on any reset condition and is an Up
Counter.
64 •
Product Specification (V1.0) 12.01.2006
(This specification is subject to change without further notice)
EM78P341N/342N/343N
8-Bit Microprocessor with OTP ROM
TCCBH / MSB Counter (IOC71):
IOC71 is an 8-bit clock counter for the most significant byte of TCCBX
(TCCBH). It can be read, written to, and cleared on any reset condition.
When TCCBHE (IOC90) is “0,” then TCCBH is disabled. When TCCBHE is”1,”
then TCCB is a 16-bit length counter.
NOTE
When TCCBH is Disabled:
TCCB timeout period [1/Fosc x ( 256 - TCCB cnt ) x 1 (CLK=2)]
TCCB timeout period [1/Fosc x ( 256 - TCCB cnt ) x 2 (CLK=4)]
When TCCBH is Enabled:
TCCB timeout period {1/Fosc x [ 65536 - (TCCBH * 256 + TCCB cnt)] x 1 (CLK=2)}
TCCB timeout period {1/Fosc x [ 65536 - (TCCBH * 256 + TCCB cnt)] x 2 (CLK=4)}
TCCC Counter (IOC81):
IOC81 (TCCC) is an 8-bit clock counter. It can be read, written to, and cleared
on any reset condition.
If HF (Bit 2 of IOCA0) = 1 and IRE (Bit 3 of IOCA0) = 1, TCCC counter scale
uses the low-time segments of the pulse generated by Fcarrier frequency
modulation (see Fig. 6-11 in Section 6.8.2, Function Description). The TCCC
value will then be the TCCC predicted value.
When HP = 0 or IRE = 0. The TCCC is an Up Counter.
NOTE
In TCCC Up Counter mode:
■ TCCC timeout period [1/Fosc x scaler (IOCA0) x (256-TCCC cnt) x 1(CLK=2)]
■ TCCC timeout period [1/Fosc x scaler (IOCA0) x (256-TCCC cnt) x 2(CLK=4)]
When HP = 1 and IRE = 1, the TCCC counter scale uses the low-time
segments of the pulse generated by the Fcarrier frequency modulation.
NOTE
In IR mode:
■ Fcarrier = FT/ 2 { [1+decimal TCCC Counter value (IOC81)] x TCCC Scale (IOCA0) }
■ FT is system clock: FT = Fosc/1 (CLK=2)
FT = Fosc/2 (CLK=4)
Product Specification (V1.0) 12.01.2006
(This specification is subject to change without further notice)
• 65
EM78P341N/342N/343N
8-Bit Microprocessor with OTP ROM
6.9.3 Programming the Related Registers
When defining TCCX, refer to the operation of its related registers as shown in the
tables below.
TCCX Related Control Registers:
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
0x08
IOC80
0
0
CPOUT/0
COS1/0
COS0/0
0x09
IOC90
TCCBHE TCCBEN TCCBTS
/0
/0
/0
TCCBTE
/0
0
0x0A
IR CR
/IOCA0
TCCCSE TCCCS2 TCCCS1/ TCCCS0
/0
/0
0
/0
0x0F
IMR
/IOCF0
LPWTE/0 HPWTE/0 TCCCIE/0 TCCBIE/0 TCCAIE/0
Bit 2
Bit 1
TCCAEN TCCATS
/0
/0
Bit 0
TCCATE
/0
TCCCEN TCCCTS TCCCTE
/0
/0
/0
IRE/0
HF/0
LGP/0
IROUTE/0
EXIE/0
ICIE/0
TCIE/0
Bit 2
Bit 1
Bit 0
EXIF/0
ICIF/0
TCIF/0
Related TCCX Status/Data Registers:
Address
Name
Bit 7
Bit 6
0x0F
ISR/RF
LPWTF/0 HPWTF/0 TCCCIF/0 TCCBIF/0 TCCAIF/0
0x05
TCCA
/IOC51
TCCA7/0 TCCA6/0 TCCA5/0 TCCA4/0 TCCA3/0 TCCA2/0 TCCA1/0 TCCA0/0
0x06
TCCB
/IOC61
TCCB7/0 TCCB6/0 TCCB5/0 TCCB4/0 TCCB3/0 TCCB2/0 TCCB1/0 TCCB0/0
0x07
TCCBH
/IOC71
TCCBH7
/0
0x08
TCCC
/IOC81
TCCC7/0 TCCC6/0 TCCC5/0 TCCC4/0 TCCC3/0 TCCC2/0 TCCC1/0 TCCC0/0
TCCBH6
/0
Bit 5
TCCBH5
/0
Bit 4
Bit 3
TCCBH4
/0
TCCBH3
/0
TCCBH2
/0
TCCBH1
/0
TCCBH0
/0
6.10 Comparator
The EM78P342N/343N
Cin -
has one comparator
which has two analog
CMP
+
Cin+
inputs and one output.
CO
The comparator can be
employed to wake up the
system from sleep mode.
The Figure at right shows
Cin -
the comparator circuit.
Cin+
Output
10mV
Fig. 6.15 Comparator Operating Mode
66 •
Product Specification (V1.0) 12.01.2006
(This specification is subject to change without further notice)
EM78P341N/342N/343N
8-Bit Microprocessor with OTP ROM
6.10.1 External Reference Signal
The analog signal that is presented at Cin – is compared to the signal at Cin+. The
digital output (CO) of the comparator is adjusted accordingly by taking into
consideration the following notes:
NOTE
■ The reference signal must be between Vss and Vdd.
■ The reference voltage can be applied to either pin of the comparator.
■ Threshold detector applications may be of the same reference.
■ The comparator can operate from the same or different reference sources.
6.10.2 Comparator Outputs
„ The compared result is stored in the CMPOUT of IOC80.
„ The comparator outputs are sent to CO (P64) by programming Bit 4 & Bit 3
<COS1, COS0> of the IOC80 register to <1,0>. See table under Section 6.2.4,
IOC80 (Comparator and TCCA Control Registers) for Comparator/OP select bits
function description.
The following figure shows the Comparator Output block diagram.
To C0
From OP I/O
CMRD
EN
Q
EN
D
Q
D
To CMPOUT
RESET
To CPIF
CMRD
From other
comparator
Fig. 6-16 Comparator Output Configuration
Product Specification (V1.0) 12.01.2006
(This specification is subject to change without further notice)
• 67
EM78P341N/342N/343N
8-Bit Microprocessor with OTP ROM
6.10.3 Using a Comparator as an Operation Amplifier
The comparator can be used as an operation amplifier if a feedback resistor is
externally connected from the input to the output. In this case, the Schmitt trigger can
be disabled for power saving purposes, by setting Bit 4, Bit 3 <COS1, COS0> of the
IOC80 register to <1,1>. See table under Section 6.2.4, IOC80 (Comparator and TCCA
Control Registers) for Comparator/OP select bits function description.
NOTE
Under Operation Amplifier:
■ The CMPIE (IOCE0.4), CMPWE (RE.2), and CMPIF (RE.4) bits are invalid.
■ The comparator interrupt is invalid.
■ The comparator wake-up is invalid.
6.10.4 Comparator Interrupt
„ CMPIE (IOCE0.4) must be enabled for the “ENI” instruction to take effect
„ Interrupt is triggered whenever a change occurs on the comparator output pin
„ The actual change on the pin can be determined by reading the Bit CMPOUT,
IOC80<5>.
„ CMPIF (RE.4), the comparator interrupt flag, can only be cleared by software
6.10.5 Wake-up from Sleep Mode
„ If the CMPWE bit of the RE register is set to “1,” the comparator remains active and
the interrupt remains functional, even under SLEEP mode.
„ If a mismatch occurs, the change will wake up the device from SLEEP mode.
„ The power consumption should be taken into consideration for the benefit of energy
conservation.
„ If the function is unemployed during SLEEP mode, turn off the comparator before
entering into sleep mode.
The Comparator is considered completed as determined by:
1. COS1 and COS0 bits of IOC80 register setting selects Comparator.
2. CMPIF bit of RE register is set to “1”.
3. CMPWE bit of RE register is set to “1”. Wakes-up from Comparator (where it
remains in operation during sleep mode)
4. Wakes-up and executes the next instruction, if CMPIE bit of IOCE0 is enabled and
the “DISI” instruction is executed.
5. Wake-up and enters into Interrupt vector (address 0x00F), if ADIE bit of IOCE0 is
enabled and the “ENI” instruction is executed
6. Enters into Interrupt vector (address 0x00F), if CMPIE bit of IOCE0 is enabled and
the “ENI” instruction is executed.
68 •
Product Specification (V1.0) 12.01.2006
(This specification is subject to change without further notice)
EM78P341N/342N/343N
8-Bit Microprocessor with OTP ROM
6.11 Oscillator
6.11.1 Oscillator Modes
The EM78P341N/342N/343N can be operated in six different oscillator modes, such as
High Crystal oscillator mode 1 (HXT1), High Crystal oscillator mode 2 (HXT2), Low
Crystal oscillator mode 1 (LXT1), Low Crystal oscillator mode 2 (LXT2), External RC
oscillator mode (ERC), and RC oscillator mode with Internal RC oscillator mode (IRC).
You can select one of them by programming the OSC2, OCS1, and OSC0 in the CODE
Option register.
The Oscillator modes defined by OSC2, OCS1, and OSC0 are described below.
OSC2
OSC1
OSC0
1
Oscillator Modes
0
0
0
1
ERC (External RC oscillator mode); P70/OSCO acts as P70
ERC (External RC oscillator mode); P70/OSCO acts as OSCO
0
0
1
2
0
1
0
2
0
1
1
1
1
1
1
0
0
1
1
0
1
0
1
IRC (Internal RC oscillator mode); P70/OSCO acts as P70
IRC (Internal RC oscillator mode); P70/OSCO acts as OSCO
3
LXT1 (Frequency range of XT mode is 1MHz ~ 100kHz)
3
HXT1 (Frequency range of XT mode is 20MHz ~ 6MHz)
3
LXT2 (Frequency range of XT mode is 32kHz)
3
HXT2 (Frequency range of XT mode is 6MHz ~ 1MHz) (default)
1
In ERC mode, OSCI is used as oscillator pin. OSCO/P50 is defined by code option Word 0 Bit 6 ~ Bit 4.
2
In IRC mode, P55 is normal I/O pin. OSCO/P70 is defined by code option Word 0 Bit 6 ~ Bit 4.
3
In LXT1, LXT2, HXT1 and HXT2 modes; OSCI and OSCO are used as oscillator pins. These pins cannot
and should not be defined as normal I/O pins.
The maximum operating frequency limit of crystal/resonator at different VDDs, are as
follows:
Conditions
Two clocks
VDD
Max. Freq. (MHz)
1.7
4
3.0
16
4.0
20
6.11.2 Crystal Oscillator/Ceramic Resonators (Crystal)
The EM78P341N/342N/343N can be driven by an external clock signal through the
OSCI pin as illustrated below.
OSCI
OSCO
Fig. 6-17 External Clock Input Circuit
Product Specification (V1.0) 12.01.2006
(This specification is subject to change without further notice)
• 69
EM78P341N/342N/343N
8-Bit Microprocessor with OTP ROM
In most applications, Pin OSCI and Pin OSCO can be connected with a crystal or
ceramic resonator to generate oscillation. Fig. 6-18 below depicts such a circuit. The
same applies to the HXT1 mode, HTX2 mode, LXT1 mode and LXT2 mode.
C1
OSCI
Crystal
OSCO
RS
C2
Fig. 6-18 Crystal/Resonator Circuit
The following table provides the recommended values for C1 and C2. Since each
resonator has its own attribute, user should refer to the resonator specifications for the
appropriate values of C1 and C2. RS, a serial resistor, may be required for AT strip cut
crystal or low frequency mode.
Capacitor selection guide for crystal oscillator or ceramic resonators:
Oscillator Type
Ceramic Resonators
Frequency Mode
HXT
LXT
Crystal Oscillator
HXT
70 •
Frequency
C1 (pF)
C2 (pF)
455kHz
100~150
100~150
2.0 MHz
20~40
20~40
4.0 MHz
10~30
10~30
32.768kHz
25
15
100kHz
25
25
200kHz
25
25
455kHz
20~40
20~150
1.0 MHz
15~30
15~30
2.0 MHz
15
15
4.0 MHz
15
15
Product Specification (V1.0) 12.01.2006
(This specification is subject to change without further notice)
EM78P341N/342N/343N
8-Bit Microprocessor with OTP ROM
Circuit diagrams for serial and parallel modes Crystal/Resonator:
330
330
C
OSCI
7404
7404
7404
Crysta l
Fig. 6-19 Serial Mode Crystal/Resonator Circuit Diagram
4.7K
7404
10K
V dd
O SC I
10K
7404
10K
C rystal
C1
C2
Fig. 6-20 Parallel Mode Crystal/Resonator Circuit Diagram
6.11.3 External RC Oscillator Mode
For some applications that do not require
precise timing calculation, the RC
Vcc
oscillator (Fig. 6-21 at right) offers a cost-
Rext
effective solution. Nevertheless, it should
be noted that the frequency of the RC
oscillator is influenced by the supply
voltage, the values of the resistor (Rext),
OSCI
Cext
the capacitor (Cext), and even by the
operation temperature. Moreover, the
frequency also changes slightly from one
Fig. 6-21 External RC Oscillator Mode Circuit
chip to another due to manufacturing
process variations.
In order to maintain a stable system frequency, the values of the Cext should be no less
than 20pF, and that of Rext should be no greater than 1MΩ. If the frequency cannot be
kept within this range, the frequency can be affected easily by noise, humidity, and
leakage.
The smaller the Rext in the RC oscillator is, the faster its frequency will be. On the
contrary, for very low Rext values, for instance, 1 KΩ, the oscillator will become
unstable because the NMOS cannot correctly discharge the capacitance current.
Product Specification (V1.0) 12.01.2006
(This specification is subject to change without further notice)
• 71
EM78P341N/342N/343N
8-Bit Microprocessor with OTP ROM
Based on the above reasons, it must be kept in mind that all supply voltage, the
operation temperature, the components of the RC oscillator, the package types, and
the PCB layout have certain effects on the system frequency.
The RC Oscillator frequencies:
Cext
Rext
Average Fosc 5V, 25°C
3.3k
20 pF
100 pF
300 pF
Average Fosc 3V, 25°C
3.5 MHz
3.2 MHz
5.1k
2.5 MHz
2.3 MHz
10k
1.30 MHz
1.25 MHz
100k
140 KHz
140kHz
3.3k
1.27 MHz
1.21 MHz
5.1k
850kHz
820kHz
10k
450kHz
450kHz
100k
48kHz
50kHz
3.3k
560kHz
540kHz
5.1k
370kHz
360kHz
10k
196kHz
192kHz
100k
20kHz
20kHz
1
Note: : Measured based on DIP packages.
2
: The values are for design reference only.
3
: The frequency drift is ± 30%
6.11.4 Internal RC Oscillator Mode
The EM78P341N/342N/343N offers a versatile internal RC mode with default
frequency value of 4MHz. Internal RC oscillator mode has other frequencies (1MHz,
8MHz, and 455kHz) that can be set by Code Option (Word 1), RCM1, and RCM0. The
Table below describes the EM78P341N/342N/343N internal RC drift with voltage,
temperature, and process variations.
Internal RC Drift Rate (Ta=25°C, VDD=5V±5%, VSS=0V)
Internal
RC Frequency
Drift Rate
Temperature
(-40°C ~+85°C)
Voltage
(2.3V~5.5V)
Process
Total
4MHz
±5%
±5%
±4%
±14%
16MHz
±5%
±5%
±4%
±14%
1MHz
±5%
±5%
±4%
±14%
455MHz
±5%
±5%
±4%
±14%
Theoretical values are for reference only. Actual values may vary depending on the actual
process.
72 •
Product Specification (V1.0) 12.01.2006
(This specification is subject to change without further notice)
EM78P341N/342N/343N
8-Bit Microprocessor with OTP ROM
6.12 Power-on Considerations
Any microcontroller is not warranted to start operating properly before the power supply
stabilizes in steady state. The EM78P341N/342N/343N POR voltage range is 1.55 ~
1.7V. Under customer application, when power is switched OFF, Vdd must drop below
1.9V and remains at OFF state for 10µs before power can be switched ON again.
Subsequently, the EM78P341N/342N/343N will reset and work normally. The extra
external reset circuit will work well if Vdd rises fast enough (50ms or less). However,
under critical applications, extra devices are still required to assist in solving power-on
problems.
6.12.1 Programmable WDT Time-out Period
5
The Option word (WDTPS) is used to define the WDT time-out period (18ms or
6
4.5ms ). Theoretically, the range is from 4.5ms or 18ms. For most crystal or ceramic
resonators, the lower the operation frequency is, the longer is the required set-up time.
6.12.2 External Power-on Reset Circuit
The circuit shown in the following figure implements an external RC to produce a reset
pulse. The pulse width (time constant) should be kept long enough to allow the Vdd to
reach the minimum operating voltage. This circuit is used when the power supply has a
slow power rise time. Because the current leakage from the /RESET pin is about ±5µA,
it is recommended that R should not be greater than 40 K. This way, the voltage at Pin
/RESET is held below 0.2V. The diode (D) functions as a short circuit at power-down.
The “C” capacitor is discharged rapidly and fully. Rin, the current-limited resistor,
prevents high current discharge or ESD (electrostatic discharge) from flowing into Pin
/RESET.
Vdd
R
D
/RESET
Rin
C
Fig. 6-22 External Power-on Reset Circuit
5
6
VDD=5V, WDT time-out period = 16.5ms ± 30%.
VDD=3V, WDT time-out period = 18ms ± 30%.
VDD=5V, WDT time-out period = 4.2ms ± 30%.
VDD=3V, WDT time-out period = 4.5ms ± 30%.
Product Specification (V1.0) 12.01.2006
(This specification is subject to change without further notice)
• 73
EM78P341N/342N/343N
8-Bit Microprocessor with OTP ROM
6.12.3 Residual Voltage Protection
When the battery is replaced, device power (Vdd) is removed but the residual voltage
remains. The residual voltage may trip below Vdd minimum, but not to zero. This
condition may cause a poor power-on reset. Fig. 6-23 and Fig. 6-24 show how to
create a protection circuit against residual voltage.
Vdd
Vdd
33K
Q1
10K
/RESET
100K
1N4684
Fig. 6-23 Residual Voltage Protection Circuit 1
Vdd
Vdd
R1
Q1
/RESET
R3
R2
Fig. 6-24 Residual Voltage Protection Circuit 2
74 •
Product Specification (V1.0) 12.01.2006
(This specification is subject to change without further notice)
EM78P341N/342N/343N
8-Bit Microprocessor with OTP ROM
6.13 Code Option
EM78P341N/342N/343N has two CODE option words and one Customer ID word that
are not part of the normal program memory.
Word 0
Word1
Word 2
Bit 12 ~ Bit 0
Bit 12 ~ Bit 0
Bit12 ~ Bit 0
6.13.1 Code Option Register (Word 0)
Word 0
Bit 12 Bit 11 Bit 10 Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
−
−
−
LVR1 LVR0 TYPE1 TYPE0 CLKS ENWDTB OSC2 OSC1 OSC0 HLP
Bits 12~11 (LVR1 ~ LVR0): Low Voltage Reset enable bits
LVR1, LVR0
VDD Reset Level
11
10
01
00
VDD Release Level
NA (Power-on Reset) (Default)
2.7V
3.5V
4.0V
2.9V
3.7V
4.2V
Bits 10~9 (TYPE1 ~ TYPE0): Type selection for EM78P343N or EM78P342N or
EM78P341N or 108C.
TYPE 1, TYPE 0
VDD Reset Level
00
108C (8-pin)
01
EM78P341N (14-pin)
10
EM78P342N (18-pin)
11
EM78P343N (Default) (20-pin)
Bit 8 (CLKS):
Instruction period option bit
0 = two oscillator periods
1 = four oscillator periods (default)
Refer to Section 6.15 for Instruction Set
Bit 7 (ENWDTB):
Watchdog timer enable bit
0 = Enable
1 = Disable (default)
Product Specification (V1.0) 12.01.2006
(This specification is subject to change without further notice)
• 75
EM78P341N/342N/343N
8-Bit Microprocessor with OTP ROM
Bits 6, 5 & 4 (OSC2, OSC1 & OSC0): Oscillator Modes Selection bits
OSC2
OSC1
OSC0
1
Oscillator Modes
0
0
0
1
ERC (External RC oscillator mode); P70/OSCO acts as P70
ERC (External RC oscillator mode); P70/OSCO acts as OSCO
0
0
1
2
0
1
0
2
0
1
1
1
1
1
1
0
0
1
1
0
1
0
1
IRC (Internal RC oscillator mode); P70/OSCO acts as P70
IRC (Internal RC oscillator mode); P70/OSCO acts as OSCO
3
LXT1 (Frequency range of XT mode is 1MHz ~ 100kHz)
3
HXT1 (Frequency range of XT mode is 20MHz ~ 6MHz)
3
LXT2 (Frequency range of XT mode is 32kHz)
3
HXT2 (Frequency range of XT mode is 6MHz ~ 1MHz) (default)
1
In ERC mode, OSCI is used as oscillator pin. OSCO/P70 is defined by code option Word 0 Bit 6 ~ Bit 4.
2
In IRC mode, P55 is normal I/O pin. OSCO/P70 is defined by code option Word 0 Bit 6 ~ Bit 4.
3
In LXT1, LXT2, HXT1 and HXT2 modes; OSCI and OSCO are used as oscillator pins. These pins cannot
and should not be defined as normal I/O pins.
Bit 3 (HLP): Power consumption selection
0 = Low power consumption, applies to working frequency at 4MHz or
below 4MHz
1 = High power consumption, applies to working frequency above 4MHz
(Default)
Bits 2 ~ 0: Not used (reserved)
6.13.2 Code Option Register (Word 1)
Word 1
Bit 12 Bit 11 Bit 10
–
–
Bit 9
Bit 8
Bit 7
Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1
JMPTS RCOUT NRHL NRE CYES
C3
C2
C1
C0
Bit 0
RCM1 RCM0
Bits 12~11: Not used, (reserved). These bits are set to “1” all the time.
Bit 10 (JMPTS): Long Instruction enable
0 = Disable LCALL, LJMP instruction
1 = Enable LCALL, LJMP instruction.(default)
Bit 8 (RCOUT): System clock output enable bit in IRC or ERC mode
0 = OSCO pin is open drain
1 = OSCO output system clock (default)
Bit 8 (NRHL): Noise rejection high/low pulses define bit. INT pin is falling or rising
edge trigger
0 = Pulses equal to 8/fc is regarded as signal
1 = Pulses equal to 32/fc is regarded as signal (default)
NOTE
The noise rejection function is turned off under the LXT and sleep mode.
76 •
Product Specification (V1.0) 12.01.2006
(This specification is subject to change without further notice)
EM78P341N/342N/343N
8-Bit Microprocessor with OTP ROM
Bit 7 (NRE):
Noise rejection enable
0 = disable noise rejection
1 = enable noise rejection (default), but in Low Crystal oscillator
(LXT) mode, the noise rejection circuit is always disabled.
Bit 6 (CYES):
Instruction cycle selection bit
0 = one instruction cycle
1 = two instructions cycles (default)
Bit 5, 4, 3, & Bit 2 (C3, C2, C1, C0): Calibrator of internal RC mode
C3, C2, C1, & C0 must be set to “1” only (auto-calibration).
Bit 1 & Bit 0 (RCM1, RCM0): RC mode selection bits
RCM 1
RCM 0
Frequency (MHz)
1
1
4(Default)
1
0
16
0
1
1
0
0
455kHz
6.13.3 Customer ID Register (Word 2)
Word 2
Bit 12 Bit 11 Bit 10 Bit 9
–
–
–
–
Bit 8
Bit 7
Bit 6
Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
RESETENB
–
WDTPS
×
×
×
×
×
×
Bits 12 ~ 9: Not used (reserved). These bits are set to “1” all the time.
Bit 8 (RESETENB): P71/RESET pin select bit
1 = P71 is general purpose input pin or open-drain for output
Port (default)
0 = P71 set to /RESET pin
Bit 7: Not used (reserved). This bit is set to “1” all the time.
Bit 6 (WDTPS):
WDT Time-out Period Selection bit
WDT Time
Watchdog Timer*
1
18 ms (Default)
0
4.5 ms
*Theoretical values, for reference only
Bits 5 ~ 0: Customer’s ID code
Product Specification (V1.0) 12.01.2006
(This specification is subject to change without further notice)
• 77
EM78P341N/342N/343N
8-Bit Microprocessor with OTP ROM
6.14 Low Voltage Detector
During a power source unstable situation, like external power noise interference or
EMS test condition, will cause the power to vibrate fiercely. At the time the Vdd is
unsettled, it maybe below working voltage. When the system supply voltage Vdd is
below the working voltage, the IC kernel must keep all register status automatically.
6.14.1 Low Voltage Reset
LVR property is setting at code option Word 0, Bit 10,9 detail operation mode as
following :
Word 0
Bit 12 Bit 11 Bit 10 Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
−
−
−
LVR1 LVR0 TYPE1 TYPE0 CLKS ENWDTB OSC2 OSC1 OSC0 HLP
Bits 12~11 (LVR1 ~ LVR0): Low Voltage Reset enable bits.
LVR1, LVR0
VDD Reset Level
VDD Release Level
11
10
01
2.7V
3.5V
2.9V
3.7V
00
4.0V
4.2V
NA (Power-on Reset)
6.14.2 Low Voltage Detector
LVD property is setting at Register detail operation mode as following:
6.14.2.1 IOCD1 (LVD Control Register)
Bit
EM78P342L/343L
ICE342N
7
6
5
4
3
2
1
0
-
-
-
-
LVDIE
LVDEN
LVD1
LVD0
TYPE1
TYPE0
LVR1
LVR0
LVDIE
LVDEN
LVD1
LVD0
NOTE
■ IOCD1< 3 > register is both readable and writable
■ Individual interrupt is enabled by setting its associated control bit in the IOCD1< 4 >
to "1."
■ Global interrupt is enabled by the ENI instruction and is disabled by the DISI
instruction. Refer to Fig. 6-8 (Interrupt Input Circuit) under Section 6.6 (Interrupt).
Bit 3 (LVDIE): Low voltage Detector interrupt enable bit.
0 = Disable Low voltage Detector interrupt
1 = Enable Low voltage Detector interrupt
When the detect low level voltage state is used to enter an interrupt
vector or enter next instruction, the LVDIE bit must be set to “Enable“.
78 •
Product Specification (V1.0) 12.01.2006
(This specification is subject to change without further notice)
EM78P341N/342N/343N
8-Bit Microprocessor with OTP ROM
Bit 2 (LVDEN): Low Voltage Detector Enable bit
0 = Low voltage detector disable
1 = Low voltage detector enable
Bits 1~0 (LVD1:0): Low Voltage Detector level bits.
6.14.2.2
LVDEN
LVD1, LVD0
1
11
1
10
1
01
1
00
0
××
LVD voltage Interrupt Level
/LVD
Vdd ≤ 2.3V
0
Vdd > 2.3V
1
Vdd ≤ 3.3V
0
Vdd > 3.3V
1
Vdd ≤ 4.0V
Vdd > 4.0V
0
1
Vdd ≤ 4.5V
0
Vdd > 4.5V
1
NA
0
RE (Interrupt Status 2 & Wake-up Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
/LVD
LVDIF
ADIF
CMPIF
ADWE
CMPWE
ICWE
LVDWE
NOTE
■ RE < 6, 5, 4 > can be cleared by instruction but cannot be set.
■ IOCE0 is the interrupt mask register.
■ Reading RE will result to "logic AND" of RE and IOCE0.
Bit 7 (/LVD):
Low voltage Detector state. This is a read only bit. When the VDD pin
voltage is lower than LVD voltage interrupt level (selected by LVD1 and
LVD0), this bit will be cleared.
0 = Low voltage is detected.
1 = Low voltage is not detected or LVD function is disabled.
Bit 6 (LVDIF): Low Voltage Detector interrupt flag
LVDIF reset to “0” by software or hardware.
Bit 0 (LVDWE): Low Voltage Detect wake-up enable bit.
0 = Disable Low Voltage Detect wake-up.
1 = Enable Low Voltage Detect wake-up.
When the Low Voltage Detect is used to enter an interrupt vector or to
wake up the IC from sleep with Low Voltage Detect running, the
LVDWE bit must be set to “Enable“.
Product Specification (V1.0) 12.01.2006
(This specification is subject to change without further notice)
• 79
EM78P341N/342N/343N
8-Bit Microprocessor with OTP ROM
6.14.3 Programming Process
Follow these steps to obtain data from the LVD:
1. Write to the two bits (LVD1: LVD0) on the LVDCR register to define the LVD level.
2. Set the LVDWE bit, if the wake-up function is employed.
3. Set the LVDIE bit, if the interrupt function is employed.
4. Write “ENI” instruction, if the interrupt function is employed.
5. Set LVDEN bit to 1
6. Write “SLEP” instruction or Polling /LVD bit.
7. Clear the interrupt flag bit (LVDIF) when Low Voltage Detector interrupt occurred.
The internal LVD module uses the internal circuit, and when the code option is set to
enable the LVD module, the current consumption will increase to about 5µA.
During sleep mode, the LVD module continues to operate. If the device voltage drops
slowly and crosses the detect point, the LVDIF bit will be set and the device will wake
up from Sleep mode. The LVD interrupt flag is still set as the prior status.
When the system resets, the LVD flag will be cleared.
Figure 6-25 shows the LVD module to detect the external voltage situation.
When Vdd drops not below VLVD, LVDIF is kept at “0”. When Vdd drops below VLVD,
LVDIF is set to “1”. If global ENI is enabled, LVDIF will be set to “1”, the next instruction
will branch to an interrupt vector. The LVD interrupt flag is cleared to “0” by software.
When Vdds drops below VRESET and it is less than 80µs, the system will keep all the
register status and the system halts but oscillation is active. When Vdd drops below
VRESET and it is more than 80µs, a system reset will occur. Refer to Section 6.5.1 for
detailed RESET description.
LVDIF is cleared by software
Vdd
VLVD
VRESET
LVDIF
Internal
Reset
18ms
<LVR Voltage drop
>LVR Voltage drop
Vdd < Vreset not longer than 80us, the system still keeps on operating
System occur reset
Fig. 6-25 LVD Waveform Situation
80 •
Product Specification (V1.0) 12.01.2006
(This specification is subject to change without further notice)
EM78P341N/342N/343N
8-Bit Microprocessor with OTP ROM
6.15 Instruction Set
Each instruction in the instruction set is a 13-bit word divided into an OP code and one
or more operands. Normally, all instructions are executed within one single instruction
cycle (one instruction consists of two oscillator periods), unless the program counter is
changed by instructions "MOV R2,A," "ADD R2,A," or by instructions of arithmetic or
logic operation on R2 (e.g., "SUB R2,A," "BS(C) R2,6," "CLR R2," etc.). In this case,
these instructions need one or two instruction cycles as determined by the Code Option
Register CYES bit.
In addition, the instruction set has the following features:
1. Every bit of any register can be set, cleared, or tested directly.
2. The I/O registers can be regarded as general registers. That is, the same
instruction can operate on I/O registers.
The following symbols are used in the Instruction Set table:
Convention:
R = Register designator that specifies which one of the registers (including operation and general purpose
registers) is to be utilized by the instruction.
Bits 6 and 7 in R4 determine the selected register bank.
b = Bit field designator that selects the value for the bit located in the register R and which affects the
operation.
k = 8 or 10-bit constant or literal value
Binary Instruction
0
0
0
0
0
0
0
0
0
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0001
0001
0001
0000
0001
0010
0011
0100
rrrr
0000
0001
0010
Hex
0000
0001
0002
0003
0004
000r
0010
0011
0012
Mnemonic
NOP
DAA
CONTW
SLEP
WDTC
IOW R
ENI
DISI
RET
0 0000 0001 0011 0013
RETI
0
0
0
0
0
0
0
0
0
0
0
CONTR
IOR R
MOV R,A
CLRA
CLR R
SUB A,R
SUB R,A
DECA R
DEC R
OR A,R
OR R,A
0000
0000
0000
0000
0000
0001
0001
0001
0001
0010
0010
0001
0001
01rr
1000
11rr
00rr
01rr
10rr
11rr
00rr
01rr
0100
rrrr
rrrr
0000
rrrr
rrrr
rrrr
rrrr
rrrr
rrrr
rrrr
0014
001r
00rr
0080
00rr
01rr
01rr
01rr
01rr
02rr
02rr
Product Specification (V1.0) 12.01.2006
(This specification is subject to change without further notice)
Operation
No Operation
Decimal Adjust A
A → CONT
0 → WDT, Stop oscillator
0 → WDT
A → IOCR
Enable Interrupt
Disable Interrupt
[Top of Stack] → PC
[Top of Stack] → PC,
Enable Interrupt
CONT → A
IOCR → A
A→R
0→A
0→R
R-A → A
R-A → R
R-1 → A
R-1 → R
A ∨ VR → A
A ∨ VR → R
Status Affected
None
C
None
T, P
T, P
1
None
None
None
None
None
None
1
None
None
Z
Z
Z, C, DC
Z, C, DC
Z
Z
Z
Z
• 81
EM78P341N/342N/343N
8-Bit Microprocessor with OTP ROM
Binary Instruction
Mnemonic
Operation
Status Affected
Z
Z
Z
Z
Z, C, DC
Z, C, DC
Z
Z
Z
Z
Z
Z
None
None
rrrr
rrrr
rrrr
rrrr
rrrr
rrrr
rrrr
rrrr
rrrr
rrrr
rrrr
rrrr
rrrr
rrrr
02rr
02rr
03rr
03rr
03rr
03rr
04rr
04rr
04rr
04rr
05rr
05rr
05rr
05rr
AND A,R
AND R,A
XOR A,R
XOR R,A
ADD A,R
ADD R,A
MOV A,R
MOV R,R
COMA R
COM R
INCA R
INC R
DJZA R
DJZ R
0 0110 00rr rrrr
06rr
RRCA R
0 0110 01rr rrrr
06rr
RRC R
0 0110 10rr rrrr
06rr
RLCA R
0 0110 11rr rrrr
06rr
RLC R
0 0111 00rr rrrr
07rr
SWAPA R
0
0
0
0
0
0
0
07rr
07rr
07rr
0xxx
0xxx
0xxx
0xxx
SWAP R
JZA R
JZ R
BC R,b
BS R,b
JBC R,b
JBS R,b
1 00kk kkkk kkkk
1kkk
CALL k
1 01kk kkkk kkkk
1 1000 kkkk kkkk
1 1001 kkkk kkkk
1 1010 kkkk kkkk
1 1011 kkkk kkkk
1 1100 kkkk kkkk
1 1101 kkkk kkkk
1 1110 1000 kkkk
k kkkk kkkk kkkk
1 1110 1000 kkkk
k kkkk kkkk kkkk
1 1111 kkkk kkkk
1kkk
18kk
19kk
1Akk
1Bkk
1Ckk
1Dkk
JMP k
MOV A,k
OR A,k
AND A,k
XOR A,k
RETL k
SUB A,k
A&R→A
A&R→R
A⊕R→A
A⊕R→R
A+R→A
A+R→R
R→A
R→R
/R → A
/R → R
R+1 → A
R+1 → R
R-1 → A, skip if zero
R-1 → R, skip if zero
R(n) → A(n-1), R(0) → C,
C → A(7)
R(n) → R(n-1), R(0) → C,
C → R(7)
R(n) → A(n+1), R(7) → C,
C → A(0)
R(n) → R(n+1), R(7) → C,
C → R(0)
R(0-3) → A(4-7),
R(4-7) → A(0-3)
R(0-3) ↔ R(4-7)
R+1 → A, skip if zero
R+1 → R, skip if zero
0 → R(b)
1 → R(b)
if R(b)=0, skip
if R(b)=1, skip
PC+1 → [SP], (Page, k) →
PC
(Page, k) → PC
k→A
A∨k→A
A&k→A
A⊕k→A
k → A, [Top of Stack] → PC
k-A → A
1EAK
LCALL k
PC+1→[SP], k→PC
None
1EBK
LJMP k
k→PC
None
1Fkk
ADD A,k
k+A → A
Z, C, DC
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0010
0010
0011
0011
0011
0011
0100
0100
0100
0100
0101
0101
0101
0101
0111
0111
0111
100b
101b
110b
111b
Note:
1
2
3
82 •
Hex
10rr
11rr
00rr
01rr
10rr
11rr
00rr
01rr
10rr
11rr
00rr
01rr
10rr
11rr
01rr
10rr
11rr
bbrr
bbrr
bbrr
bbrr
rrrr
rrrr
rrrr
rrrr
rrrr
rrrr
rrrr
C
C
C
C
None
None
None
None
2
None
3
None
None
None
None
None
None
Z
Z
Z
None
Z, C, DC
This instruction is applicable to IOC50~IOCF0, IOC51 ~ IOCF1 only.
This instruction is not recommended for RF operation.
This instruction cannot operate under RF.
Product Specification (V1.0) 12.01.2006
(This specification is subject to change without further notice)
EM78P341N/342N/343N
8-Bit Microprocessor with OTP ROM
7
Absolute Maximum Ratings
Items
8
Rating
Temperature under bias
-40°C
to
85°C
Storage temperature
-65°C
to
150°C
Input voltage
Vss-0.3V
to
Vdd+0.5V
Output voltage
Vss-0.3V
to
Vdd+0.5V
Working Voltage
2.5V
to
5.5V
Working Frequency
DC
to
20MHz
DC Electrical Characteristics
Ta=25 °C, VDD=5.0V±5%, VSS=0V
Symbol
Parameter
Crystal: VDD to 5V
Fxt
Crystal: VDD to 3V
Condition
Two cycles with two clocks
Min
Typ
Max
Unit
DC
−
20
MHz
DC
−
8
MHz
kHz
ERC: VDD to 5V
R: 5.1KΩ, C: 100 pF
F±30%
830
F±30%
IRC: VDD to 5 V
8MHz,4MHz, 1MHz, 455kHz
F±30%
F
F±30%
IRC1
IRC:VDD to 5V
RCM0:RCM1=1:1
3.84
4.0
4.16
MHz
IRC2
IRC:VDD to 5V
RCM0:RCM1=1:0
7.68
8.0
8.32
MHz
IRC3
IRC:VDD to 5V
RCM0:RCM1=0:1
0.96
1.0
1.06
MHz
IRC4
kHz
Hz
IRC:VDD to 5V
RCM0:RCM1=0:0
436.8
455
473.2
Input High Threshold
VIHRC
Voltage (Schmitt Trigger )
OSCI in RC mode
−
3.5
−
V
VILRC
Input Low Threshold
Voltage (Schmitt Trigger )
OSCI in RC mode
−
1.5
−
V
IIL
Input Leakage Current for
input pins
VIN = VDD, VSS
-1
0
1
µA
VIH1
Input High Voltage
(Schmitt Trigger )
Ports 5, 6, 7
−
3.75
−
V
VIL1
Input Low Voltage
(Schmitt Trigger )
Ports 5, 6, 7
−
1.25
−
V
VIHT1
Input High Threshold
Voltage (Schmitt Trigger )
/RESET
−
2.0
−
V
VILT1
Input Low Threshold
Voltage (Schmitt Trigger )
/RESET
−
1.0
−
V
VIHT2
Input High Threshold
Voltage (Schmitt Trigger )
TCC, INT
−
3.75
−
V
VILT2
Input Low Threshold
Voltage (Schmitt Trigger )
TCC, INT
−
1.25
−
V
VIHX1
Clock Input High Voltage
OSCI in crystal mode
−
3.5
−
V
VILX1
Clock Input Low Voltage
OSCI in crystal mode
−
1.5
−
V
IOH1
Output High Voltage
(Ports 5, P60~66,P70)
VOH = VDD-0.5V
−
-3.7
−
mA
IOH2
Output High Voltage
(IR OUT (Port 67))
VOH = VDD-0.5V
−
-10
−
mA
Product Specification (V1.0) 12.01.2006
(This specification is subject to change without further notice)
• 83
EM78P341N/342N/343N
8-Bit Microprocessor with OTP ROM
Symbol
Parameter
IOL1
Output Low Voltage
(Ports 5, P60~66, P70)
Condition
Min
VOL = GND+0.5V
−
IOL2
Output Low Voltage
(IR OUT (Port 67))
VOL = GND+0.5V
−
IPH
Pull-high current
Pull-high active, input pin at VSS
-70
IPL
Pull-low current
Pull-low active, input pin at Vdd
ISB1
Power down current
ISB2
Power down current
ICC1
Typ
Max
Unit
10
−
mA
15
−
mA
-75
-80
µA
35
40
45
µA
All input and I/O pins at VDD,
output pin floating, WDT disabled
−
1.0
2.0
µA
All input and I/O pins at VDD,
output pin floating, WDT enabled
−
6.0
10
µA
Operating supply current /RESET= 'High', Fosc=32kHz
(Crystal type,CLKS="0"), output
at two clocks (VDD to
pin floating, WDT disabled
3V)
−
15
20
µA
ICC2
Operating supply current /RESET= 'High', Fosc=32kHz
(Crystal type,CLKS="0"), output
at two clocks (VDD to
pin floating, WDT enabled
3V)
−
15
25
µA
ICC3
/RESET= 'High', Fosc=4MHz
Operating supply current
(Crystal type, CLKS="0"), output
at two clocks
pin floating, WDT enabled
−
1.9
2.2
mA
ICC4
/RESET= 'High', Fosc=10MHz
Operating supply current
(Crystal type, CLKS="0"), output
at two clocks
pin floating, WDT enabled
−
3.0
3.5
mA
Note: 1. These parameters are hypothetical (not tested) and are provided for design reference use only.
2. Data under minimum, typical, & maximum (Min, Typ, & Max) columns are based on hypothetical results at 25°C. These
data are for design reference only.
8.1 AD Converter Characteristics
Vdd=2.5V to 5.5V, Vss=0V, Ta=25°C
Symbol
VAREF
VASS
VAI
Ivdd
Parameter
Condition
Analog reference voltage VAREF - VASS ≥ 2.5V
Analog input voltage
–
Min.
Typ.
Max.
Unit
2.5
–
Vdd
V
Vss
–
Vss
V
VASS
–
VAREF
V
750
850
1000
uA
–10
0
+10
uA
500
600
820
uA
200
250
300
uA
Analog supply current
Vdd=VAREF=5.0V, VASS =0.0V
(V referenced from Vdd)
Analog supply current
Vdd=VAREF=5.0V, VASS=0.0V
(V referenced from VREF)
IOP
OP current
Vdd=5.0V, OP used
Output voltage swing 0.2V to 4.8V
450
550
650
uA
RN
Resolution
Vdd=VAREF=5.0V, VASS =0.0V
10
11
–
Bits
LN
Linearity error
Vdd = 2.5 to 5.5V Ta=25°C
0
±4
±8
LSB
DNL
Differential nonlinear
error
Vdd = 2.5 to 5.5V Ta=25°C
0
±0.5
±0.9
LSB
FSE
Full scale error
Vdd=VAREF=5.0V, VASS =0.0V
±0
±4
±8
LSB
IAI1
IAI2
84 •
Ivref
Ivdd
IVref
Product Specification (V1.0) 12.01.2006
(This specification is subject to change without further notice)
EM78P341N/342N/343N
8-Bit Microprocessor with OTP ROM
Symbol
Parameter
Condition
Min.
Typ.
Max.
Unit
±0
±2
±4
LSB
0
8
10
KΩ
OE
Offset error
ZAI
Recommended
impedance of analog
voltage source
TAD
ADC clock period
Vdd=VAREF=5.0V, VASS =0.0V
4
–
–
us
TCN
AD conversion time
Vdd=VAREF=5.0V, VASS =0.0V
15
–
15
TAD
ADIV
ADC OP input voltage
range
Vdd=VAREF=5.0V, VASS =0.0V
0
–
VAREF
V
ADOV
ADC OP output voltage
swing
Vdd=VAREF=5.0V, VASS =0.0V,
RL=10KΩ
0
0.2
0.3
4.7
4.8
5
ADSR
ADC OP slew rate
Vdd=VAREF=5.0V, VASS =0.0V
0.1
0.3
–
V/us
Power Supply Rejection
Vdd=5.0V±0.5V
±0
–
±2
LSB
PSR
Vdd=VAREF=5.0V, VASS =0.0V
–
V
Note: 1. These parameters are hypothetical (not tested) and are provided for design reference use only.
2. There is no current consumption when ADC is off other than minor leakage current.
3. AD conversion result will not decrease when an increase of input voltage and no missing code will result.
4. These parameters are subject to change without further notice.
8.2 Comparator (OP) Characteristics
Vdd = 5.0V, Vss=0V, Ta=25°C
Symbol
Parameter
Condition
SR
Slew rate
IVR
Input voltage range
Vdd =5.0V, VSS =0.0V
OVS
Output voltage swing
Vd =5.0V, VSS =0.0V, RL=10KΩ
Iop
Supply current of OP
Ico
Supply current of Comparator
PSR
R
Vs
Power-supply Rejection
Ration for OP
Min.
Typ.
0.1
0.2
0
Max.
V/us
5
0
0.2
0.3
4.7
4.8
5
250
350
500
300
Vdd= 5.0V, VSS =0.0V
Operating range
50
60
2.5
Unit
V
V
uA
uA
70
dB
5.5
V
Note: 1. These parameters are hypothetical (not tested) and are provided for design reference use only.
Product Specification (V1.0) 12.01.2006
(This specification is subject to change without further notice)
• 85
EM78P341N/342N/343N
8-Bit Microprocessor with OTP ROM
8.3 Device Characteristics
The graphs below were derived based on a limited number of samples and they are
provided for reference only. Hence, the device characteristic shown herein cannot be
guaranteed as fully accurate. In these graphs, the data may be out of the specified
operating warranted range.
IRC OSC Frequency (VDD=3V)
9
Frequency (MHz) .
8
7
6
5
4
3
2
1
0
-40
-20
0
25
70
50
85
Temperature oC
Fig. 8-1 Internal RC OSC Frequency vs. Temperature, VDD=3V
IRC OSC Frequency (VDD=5V)
10
Frequency (M Hz) .
9
8
7
6
5
4
3
2
1
0
-40
-20
0
25
50
70
85
Temperature (℃)
Fig. 8-2 Internal RC OSC Frequency vs. Temperature, VDD=5V
86 •
Product Specification (V1.0) 12.01.2006
(This specification is subject to change without further notice)
EM78P341N/342N/343N
8-Bit Microprocessor with OTP ROM
9
AC Electrical Characteristic
Ta=-40 to 85 °C, VDD=5V±5%, VSS=0V
Symbol
Parameter
Conditions
Min
Type
Max
Unit
–
45
50
55
%
Crystal type
100
–
DC
ns
RC type
500
–
DC
ns
(Tins+20)/N*
–
–
ns
Dclk
Input CLK duty cycle
Tins
Instruction cycle time
(CLKS="0")
Ttcc
TCC input time period
Tdrh
Device reset hold time
Ta = 25°C
11.3
16.2
21.6
ms
Trst
/RESET pulse width
Ta = 25°C
2000
–
–
ns
Twdt
Watchdog timer duration
Ta = 25°C
11.3
16.2
21.6
ms
Tset
Input pin setup time
–
–
0
–
ns
Thold
Input pin hold time
–
15
20
25
ns
Tdelay
Output pin delay time
Cload=20pF
45
50
55
ns
Tdrc
ERC delay time
Ta = 25°C
1
3
5
ns
–
Note:1. *N = selected prescaler ratio
2. Twdt1: The Option word1 (WDTPS) is used to define the oscillator set-up time. WDT timeout
length is the same as set-up time (18ms).
3. Twdt2: The Option word1 (WDTPS) is used to define the oscillator set-up time. WDT timeout
length is the same as set-up time (4.5ms).
4. These parameters are hypothetical (not tested) and are provided for design reference only.
5. Data under minimum, typical, & maximum (Min, Typ, & Max) columns are based on hypothetical
results at 25°C. These data are for design reference use only.
6. The Watchdog timer duration is determined by code option Word1 (WDTPS).
Product Specification (V1.0) 12.01.2006
(This specification is subject to change without further notice)
• 87
EM78P341N/342N/343N
8-Bit Microprocessor with OTP ROM
10 Timing Diagrams
AC Test Input/Output Waveform
VDD-0.5V
0.75VDD
0.25VDD
TEST POINTS
0.75VDD
0.25VDD
GND+0.5V
AC Testing : Input is driven at VDD-0.5V for logic "1",and GND+0.5V for logic "0".Timing
measurements are made at 0.75VDD for logic "1",and 0.25VDD for logic "0".
RESET Timing (CLK="0")
NOP
Instruction 1
Executed
CLK
/RESET
Tdrh
TCC Input Timing (CLKS="0")
Tins
CLK
TCC
Ttcc
88 •
Product Specification (V1.0) 12.01.2006
(This specification is subject to change without further notice)
EM78P341N/342N/343N
8-Bit Microprocessor with OTP ROM
APPENDIX
A. Package Type
OTP MCU
Package Type
Pin Count
Package Size
EM78P341NP
DIP
14
300mil
EM78P341NM
SOP
14
150mil
EM78P342NP
DIP
18
300mil
EM78P342NM
SOP
18
300mil
EM78P343NP
DIP
20
300mil
EM78P343NM
SOP
20
300mil
SSOP
20
209mil
EM78P343NKM
B Packaging Configuration
B.1 14-Lead Plastic Dual in line (PDIP) — 300 mil
Product Specification (V1.0) 12.01.2006
(This specification is subject to change without further notice)
• 89
EM78P341N/342N/343N
8-Bit Microprocessor with OTP ROM
B.2 14-Lead Plastic Small Outline (SOP) — 150 mil
90 •
Product Specification (V1.0) 12.01.2006
(This specification is subject to change without further notice)
EM78P341N/342N/343N
8-Bit Microprocessor with OTP ROM
B.3 18-Lead Plastic Dual in line (PDIP) — 300 mil
Product Specification (V1.0) 12.01.2006
(This specification is subject to change without further notice)
• 91
EM78P341N/342N/343N
8-Bit Microprocessor with OTP ROM
B.4 18-Lead Plastic Small Outline (SOP) — 300 mil
92 •
Product Specification (V1.0) 12.01.2006
(This specification is subject to change without further notice)
EM78P341N/342N/343N
8-Bit Microprocessor with OTP ROM
B.5 20-Lead Plastic Shrink Small Outline (SSOP) — 209 mil
Product Specification (V1.0) 12.01.2006
(This specification is subject to change without further notice)
• 93
EM78P341N/342N/343N
8-Bit Microprocessor with OTP ROM
B.6 20-Lead Plastic Dual-in-line (PDIP) — 300 mil
94 •
Product Specification (V1.0) 12.01.2006
(This specification is subject to change without further notice)
EM78P341N/342N/343N
8-Bit Microprocessor with OTP ROM
B.7 20-Lead Plastic Small Outline (SOPP) — 300 mil
Product Specification (V1.0) 12.01.2006
(This specification is subject to change without further notice)
• 95
EM78P341N/342N/343N
8-Bit Microprocessor with OTP ROM
C Quality Assurance and Reliability
Test Category
Solderability
Test Conditions
Remarks
Solder temperature=245 ± 5°C, for 5 seconds up to the
stopper using a rosin-type flux
−
Step 1: TCT, 65°C (15mins)~150°C (15mins), 10 cycles
Step 2: Bake at 125°C, TD (durance)=24 hrs
Step 3: Soak at 30°C /60%，TD (durance)=192 hrs
Pre-condition
For SMD IC (such as
SOP, QFP, SOJ, etc)
Step 4: IR flow 3 cycles
(Pkg thickness ≥ 2.5mm or
3
Pkg volume ≥ 350mm ----225 ± 5°C)
(Pkg thickness ≤ 2.5mm or
3
Pkg volume ≤ 350mm ----240 ± 5°C )
Temperature cycle test
-65° (15mins)~150°C (15mins), 200 cycles
−
Pressure cooker test
TA =121°C, RH=100%, pressure=2 atm,
TD (durance) = 96 hrs
−
High temperature /
High humidity test
TA=85°C , RH=85%，TD (durance)=168 , 500 hrs
−
High-temperature
storage life
TA=150°C, TD (durance)=500, 1000 hrs
−
High-temperature
operating life
TA=125°C, VCC=Max. operating voltage,
TD (durance) =168, 500, 1000 hrs
−
Latch-up
TA=25°C, VCC=Max. operating voltage, 150mA/20V
−
ESD (HBM)
TA=25°C, ≥ ∣± 3KV∣
IP_ND,OP_ND,IO_ND
IP_NS,OP_NS,IO_NS
IP_PD,OP_PD,IO_PD,
ESD (MM)
TA=25°C, ≥ ∣± 300V∣
IP_PS,OP_PS,IO_PS,
VDD-VSS(+),VDD_VSS
(-)mode
C.1 Address Trap Detect
An address trap detect is one of the MCU embedded fail-safe functions that detects
MCU malfunction caused by noise or the like. Whenever the MCU attempts to fetch an
instruction from a certain section of ROM, an internal recovery circuit is auto started. If
a noise caused address error is detected, the MCU will repeat execution of the program
until the noise is eliminated. The MCU will then continue to execute the next program.
96 •
Product Specification (V1.0) 12.01.2006
(This specification is subject to change without further notice)