EPSON S1D13506

S1D13506 Color LCD/CRT/TV Controller
S1D13506
TECHNICAL MANUAL
Document Number: X25B-Q-001-06
Copyright © 2001 Epson Research and Development, Inc. All Rights Reserved.
Information in this document is subject to change without notice.You may download and use this document, but only for your own use in
evaluating Seiko Epson/EPSON products. You may not modify the document. Epson Research and Development, Inc. disclaims any
representation that the contents of this document are accurate or current. The Programs/Technologies described in this document may contain
material protected under U.S. and/or International Patent laws.
EPSON is a registered trademark of Seiko Epson Corporation. All other trademarks are the property of their respective owners.
Page 2
Epson Research and Development
Vancouver Design Center
THIS PAGE LEFT BLANK
S1D13506
X25B-Q-001-06
TECHNICAL MANUAL
Issue Date: 01/04/18
Epson Research and Development
Vancouver Design Center
Page 3
COMPREHENSIVE SUPPORT TOOL S
EPSON provides the designer and manufacturer a complete set of resources and tools for the development of LCD
Graphics Systems.
Documentation
• Technical manuals
• Evaluation/Demonstration board manual
Evaluation/Demonstration Board
•
•
•
•
•
•
•
Assembled and fully tested Graphics Evaluation/Demonstration board
Schematic of Evaluation/Demonstration board
Parts List
Installation Guide
CPU Independent Software Utilities
Evaluation Software
Windows CE Display Driver
Application Engineering Support
EPSON offers the following services through their Sales and Marketing Network:
• Sales Technical Support
• Customer Training
• Design Assistance
Application Engineering Support
Engineering and Sales Support is provided by:
Japan
Seiko Epson Corporation
Electronic Devices Marketing Division
421-8, Hino, Hino-shi
Tokyo 191-8501, Japan
Tel: 042-587-5812
Fax: 042-587-5564
http://www.epson.co.jp
Hong Kong
Epson Hong Kong Ltd.
20/F., Harbour Centre
25 Harbour Road
Wanchai, Hong Kong
Tel: 2585-4600
Fax: 2827-4346
TECHNICAL MANUAL
Issue Date: 01/04/18
North America
Epson Electronics America, Inc.
150 River Oaks Parkway
San Jose, CA 95134, USA
Tel: (408) 922-0200
Fax: (408) 922-0238
http://www.eea.epson.com
Taiwan
Epson Taiwan Technology
& Trading Ltd.
10F, No. 287
Nanking East Road
Sec. 3, Taipei, Taiwan
Tel: 02-2717-7360
Fax: 02-2712-9164
Europe
Epson Europe Electronics GmbH
Riesstrasse 15
80992 Munich, Germany
Tel: 089-14005-0
Fax: 089-14005-110
Singapore
Epson Singapore Pte., Ltd.
No. 1
Temasek Avenue #36-00
Millenia Tower
Singapore, 039192
Tel: 337-7911
Fax: 334-2716
S1D13506
X25B-Q-001-06
Page 4
Epson Research and Development
Vancouver Design Center
THIS PAGE LEFT BLANK
S1D13506
X25B-Q-001-06
TECHNICAL MANUAL
Issue Date: 01/04/18
ENERGY
S AV I N G
GRAPHICS
EPSON
S1D13506
S1D13506 COLOR LCD/CRT/TV CONTROLLER
March 2001
The S1D13506 is a color LCD/CRT/TV graphics controller interfacing to a wide range of CPUs and display devices.
The S1D13506 architecture is designed to meet the low cost, low power requirements of the embedded
markets, such as Mobile Communications, Hand-Held PC’s, and Office Automation.
The S1D13506 supports multiple CPUs, all LCD panel types, CRT, TV, and additionally provides a number of
differentiating features. Products requiring digital camera input can take advantage of the directly supported
WINNOV VideumCam™ digital interface. EPSON Independent Simultaneous Display allows the user to configure
two different images on two different displays, while the SwivelView™, Hardware Cursor, Ink Layer, and BitBLT
engine offer substantial performance benefits. These features, combined with the S1D13506’s Operating System
independence, make it an ideal display solution for a wide variety of applications.
■ FEATURES
• 16-bit EDO-DRAM or FPM-DRAM interface.
• Memory size options:
•
•
•
• SwivelView™: 90°, 180°, 270° hardware
rotation of displayed image.
• EPSON Independent Simultaneous Display:
512K bytes using one 256K×16 device.
2M bytes using one 1M×16 device.
Multiple CPU interface support.
Resolutions up to:
640x480 at a color depth of 16 bpp.
800x600 at a color depth of 16 bpp.
Display Support for:
4/8/16-bit passive panels.
9/12 TFT/D-TFD panels.
18-bit TFT/D-TFD to a depth of 64K colors.
CRT.
NTSC and PAL TV Output.
•
•
•
•
•
•
displays different images on different displays.
Virtual Display Support: displays images larger
than the panel size through the use of panning.
Hardware Cursor or full screen Ink Layer.
2D BitBLT Engine.
WINNOV Videum® Cam digital camera interface.
Software initiated Power Save Mode.
Operating System Independent.
■ SYSTEM BLOCK DIAGRAM
TV
EDO-DRAM
FPM-DRAM
Analog Out
CPU
OR
CRT
Control
Clock
S1D13506
AND
Digital Out
MediaPlug
Interface
X25B-C-001-05
Flat Panel
1
GRAPHICS
S1D13506
■ DESCRIPTION
Memory Interface
• 16-bit EDO-DRAM or FPM-DRAM interface.
Digital Video Camera Interface
• Built-in WINNOV Videum® Cam digital camera interface.
• Addressable as a single linear address space.
CPU Interface
• Supports the following interfaces:
EPSON E0C33
NEC MIPS VR41xx
Hitachi SH-4/SH-3
PC Card (PCMCIA)
ISA bus
Philips MIPS PR31500/PR31700
Motorola M68xxx
StrongARM (PC Card)
Motorola MPC821
Toshiba MIPS TX39xx
MPU with programmable READY
• CPU Write buffer.
Display Support
• LCD Panels: 4/8/16-bit passive LCD interface.
9/12-bit TFT/D-TFD.
18-bit TFT/D-TFD to a depth of 64K colors.
Display Modes
• 4/8/16 bit-per-pixel (bpp) support on LCD, CRT andTV.
• CRT:
• TV:
Embedded RAMDAC for direct analog CRT.
Composite/S-Video TV output.
NTSC/PAL support.
Flicker filter.
Luminance filter.
Chrominance filter.
• Maximum resolution of 800x600 at 16 bpp .
Power Down Modes
• Software initiated power save mode.
• LCD Power Sequencing.
• Up to 64 shades of gray on monochrome LCD panels using
FRM and Dithering.
• Up to 64K colors on passive LCD, active matrix TFT/D-TFD,
CRT and TV in 16 bpp modes.
•
SwivelView™: 90°, 180°, 270° hardware rotation of displayed
image.
• EPSON Independent Simultaneous Display (EISD): displays
different images on different displays.
• Virtual Display Support: displays images larger than the panel
size through the use of panning and scrolling.
• Hardware Cursor or full screen Ink Layer.
Acceleration
• 2D Engine including the following BitBLTs:
Write BLT
Move BLT
Solid Fill
Pattern Fill
Transparent Write BLT Transparent Move BLT
Read BLT
Color Expansion
Move BLT with Color Expansion
Operating Voltage
• 2.7 volts to 5.5 volts.
Package
• 128-pin QFP15.
.
CONTACT YOUR SALES REPRESENTATIVE FOR THESE COMPREHENSIVE DESIGN TOOLS
• S1D13506 Technical Manual • QNX Photon Display Driver
• S5U13506 Evaluation
• VXWorks UGL and WindML
Boards
Display Drivers
• CPU Independent Software • Windows CE Display Driver
Utilities
Japan
Seiko Epson Corporation
Electronic Devices Marketing Division
421-8, Hino, Hino-shi
Tokyo 191-8501, Japan
Tel: 042-587-5812
Fax: 042-587-5564
http://www.epson.co.jp
Singapore
Epson Singapore Pte., Ltd.
No. 1
Temasek Avenue #36-00
Millenia Tower
Singapore, 039192
Tel: 337-7911
Fax: 334-2716
North America
Epson Electronics America, Inc.
150 River Oaks Parkway
San Jose, CA 95134, USA
Tel: (408) 922-0200
Fax: (408) 922-0238
http://www.eea.epson.com
Europe
Epson Europe Electronics GmbH
Riesstrasse 15
80992 Munich, Germany
Tel: 089-14005-0
Fax: 089-14005-110
Taiwan
Epson Taiwan Technology
& Trading Ltd.
10F, No. 287
Nanking East Road
Sec. 3, Taipei, Taiwan
Tel: 02-2717-7360
Fax: 02-2712-9164
Hong Kong
Epson Hong Kong Ltd.
20/F., Harbour Centre
25 Harbour Road
Wanchai, Hong Kong
Tel: 2585-4600
Fax: 2827-4346
Copyright ©1998, 2001 Epson Research and Development, Inc. All rights reserved.
VDC
Information in this document is subject to change without notice. You may download and use this document, but only for your own use in evaluating Seiko Epson/EPSON products. You
may not modify the document. Epson Research and Development, Inc. disclaims any representation that the contents of this document are accurate or current. The Programs/Technologies
described in this document may contain material protected under U.S. and/or International Patent laws.
EPSON is a registered trademark of Seiko Epson Corporation. Microsoft, Windows, and the Windows Embedded Partner Logo are registered trademarks of Microsoft Corporation. Videum
is a registered trademark of WINNOV.
2
X25B-C-001-05
S1D13506 Color LCD/CRT/TV Controller
Hardware Functional Specification
Document Number: X25B-A-001-10
Copyright © 1999, 2001 Epson Research and Development, Inc. All Rights Reserved.
Information in this document is subject to change without notice.You may download and use this document, but only for your own use in
evaluating Seiko Epson/EPSON products. You may not modify the document. Epson Research and Development, Inc. disclaims any
representation that the contents of this document are accurate or current. The Programs/Technologies described in this document may contain
material protected under U.S. and/or International Patent laws.
EPSON is a registered trademark of Seiko Epson Corporation. All other trademarks are the property of their respective owners.
Page 2
Epson Research and Development
Vancouver Design Center
THIS PAGE LEFT BLANK
S1D13506
X25B-A-001-10
Hardware Functional Specification
Issue Date: 01/02/06
Epson Research and Development
Vancouver Design Center
Page 3
Table of Contents
1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
1.1 Scope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
1.2 Overview Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2
Features . . . . . . . .
2.1 Memory Interface .
2.2 CPU Interface . .
2.3 Display Support . .
2.4 Display Modes . .
2.5 Display Features .
2.6 Clock Source . . .
2.7 Acceleration . . .
2.8 MediaPlug Interface
2.9 Miscellaneous . .
3
Typical System Implementation Diagrams . . . . . . . . . . . . . . . . . . . . . . 21
4
Internal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
4.1 Block Diagram Showing Pipelines . . . . . . . . . . . . . . . . . . . . . . 27
5
Pins . . . . . . . . . . . . . . . . .
5.1 Pinout Diagram . . . . . . . .
5.2 Pin Description . . . . . . . .
5.2.1 Host Bus Interface . . . . . .
5.2.2 Memory Interface . . . . . .
5.2.3 LCD Interface . . . . . . . .
5.2.4 CRT Interface . . . . . . . .
5.2.5 Miscellaneous . . . . . . . .
5.3 Summary of Configuration Options
5.4 Multiple Function Pin Mapping .
5.5 CRT/TV Interface . . . . . . .
6
D.C. Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
7
A.C. Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.1 CPU Interface Timing . . . . . . . . . . . . . . . . . . . . . . .
7.1.1 Generic Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.1.2 Hitachi SH-4 Interface Timing . . . . . . . . . . . . . . . . . . . . . . .
7.1.3 Hitachi SH-3 Interface Timing . . . . . . . . . . . . . . . . . . . . . . .
7.1.4 MIPS/ISA Interface Timing (e.g. NEC VR41xx) . . . . . . . . . . . . . .
7.1.5 Motorola MC68K Bus 1 Interface Timing (e.g. MC68000) . . . . . . . .
7.1.6 Motorola MC68K Bus 2 Interface Timing (e.g. MC68030) . . . . . . . .
Hardware Functional Specification
Issue Date: 01/02/06
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
. . .
. .
. .
. .
. .
. .
. .
. .
. .
. .
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
. . .
. .
. .
. .
. .
. .
. .
. .
. .
. .
. . .
. .
. .
. . .
. . .
. . .
. . .
. . .
. .
. .
. .
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
. . .
. .
. .
. .
. .
. .
. .
. .
. .
. .
.
.
.
.
.
.
.
.
.
.
. . . . . .
. . . . .
. . . . .
. . . . . . .
. . . . . . .
. . . . . . .
. . . . . . .
. . . . . . .
. . . . .
. . . . .
. . . . .
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
. . . .
. . .
. . .
. . .
. . .
. . .
. . .
. . .
. . .
. . .
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
. . . . . . .
. . . . . .
. . . . . .
. . . . . . . .
. . . . . . . .
. . . . . . . .
. . . . . . . .
. . . . . . . .
. . . . . .
. . . . . .
. . . . . .
. . . .
. . .
. . .
. . .
. . .
. . .
. . .
. . .
. . .
. . .
. . .
. .
. .
. . .
. . .
. . .
. . .
. . .
. .
. .
. .
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
. . .
. . .
. . .
. . . .
. . . .
. . . .
. . . .
. . . .
. . .
. . .
. . .
. . . .
. . . .
. . . . .
. . . . .
. . . . .
. . . . .
. . . . .
. . . . .
18
18
18
19
19
19
20
20
20
20
28
28
29
29
35
37
38
38
39
40
44
48
48
48
50
52
54
56
58
S1D13506
X25B-A-001-10
Page 4
Epson Research and Development
Vancouver Design Center
7.2
7.3
7.4
7.5
7.6
7.7
8
7.1.7 Motorola PowerPC Interface Timing (e.g. MPC8xx, MC68040, Coldfire)
7.1.8 PC Card Timing (e.g. StrongARM) . . . . . . . . . . . . . . . . . . . .
7.1.9 Philips Interface Timing (e.g. PR31500/PR31700) . . . . . . . . . . . .
7.1.10 Toshiba Interface Timing (e.g. TX39xx) . . . . . . . . . . . . . . . . .
Clock Timing . . . . . . . . . . . . . . . . . . . . . . . . . .
7.2.1 Input Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.2.2 Internal Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Memory Interface Timing . . . . . . . . . . . . . . . . . . . . .
7.3.1 EDO-DRAM Read, Write, Read-Write Timing . . . . . . . . . . . . . .
7.3.2 EDO-DRAM CAS Before RAS Refresh Timing . . . . . . . . . . . . .
7.3.3 EDO-DRAM Self-Refresh Timing . . . . . . . . . . . . . . . . . . . .
7.3.4 FPM-DRAM Read, Write, Read-Write Timing . . . . . . . . . . . . . .
7.3.5 FPM-DRAM CAS Before RAS Refresh Timing . . . . . . . . . . . . .
7.3.6 FPM-DRAM Self-Refresh Timing . . . . . . . . . . . . . . . . . . . .
Power Sequencing . . . . . . . . . . . . . . . . . . . . . . . .
7.4.1 LCD Power Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . .
7.4.2 Power Save Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Display Interface . . . . . . . . . . . . . . . . . . . . . . . . .
7.5.1 Single Monochrome 4-Bit Panel Timing . . . . . . . . . . . . . . . . .
7.5.2 Single Monochrome 8-Bit Panel Timing . . . . . . . . . . . . . . . . .
7.5.3 Single Color 4-Bit Panel Timing . . . . . . . . . . . . . . . . . . . . .
7.5.4 Single Color 8-Bit Panel Timing (Format 1) . . . . . . . . . . . . . . .
7.5.5 Single Color 8-Bit Panel Timing (Format 2) . . . . . . . . . . . . . . .
7.5.6 Single Color 16-Bit Panel Timing . . . . . . . . . . . . . . . . . . . . .
7.5.7 Single Color 16-Bit Panel Timing with External Circuit . . . . . . . . .
7.5.8 Dual Monochrome 8-Bit Panel Timing . . . . . . . . . . . . . . . . . .
7.5.9 Dual Color 8-Bit Panel Timing . . . . . . . . . . . . . . . . . . . . . .
7.5.10 Dual Color 16-Bit Panel Timing . . . . . . . . . . . . . . . . . . . . .
7.5.11 Dual Color 16-Bit Panel Timing with External Circuit . . . . . . . . . .
7.5.12 TFT/D-TFD Panel Timing . . . . . . . . . . . . . . . . . . . . . . . . .
7.5.13 CRT Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TV Timing . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.6.1 TV Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MediaPlug Interface Timing . . . . . . . . . . . . . . . . . . . .
Registers . . . . . . . . . . . . . . . .
8.1 Initializing the S1D13506 . . . . .
8.1.1 Register/Memory Select Bit . . .
8.2 Register Mapping . . . . . . . .
8.3 Register Descriptions . . . . . . .
8.3.1 Basic Registers . . . . . . . . .
S1D13506
X25B-A-001-10
.
.
.
.
.
.
. . .
. .
. . .
. .
. .
. . .
. . . . . . .
. . . . . .
. . . . . . . .
. . . . . .
. . . . . .
. . . . . . . .
.
.
.
.
.
.
. . . . . . .
. . . . . .
. . . . . . . .
. . . . . .
. . . . . .
. . . . . . . .
. . .
. . .
. . .
. . .
. .
. . .
. . .
. .
. . .
. . .
. . .
. . .
. . .
. . .
. .
. . .
. . .
. .
. . .
. . .
. . .
. . .
. . .
. . .
. . .
. . .
. . .
. . .
. . .
. . .
. . .
. .
. . .
. .
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
. . . .
. . .
. . . .
. . .
. . .
. . . .
. . 60
. . 62
. . 64
. . 66
. .68
. . 68
. . 69
. . 70
. . 70
. . 72
. . 73
. . 74
. . 76
. . 77
. . 78
. . 78
. . 79
. .81
. . 81
. . 84
. . 87
. . 90
. . 93
. . 96
. . 99
. .102
. .105
. .108
. .111
. .114
. .117
. 119
. .119
. 123
.
.
.
.
.
.
124
124
.124
124
125
.125
Hardware Functional Specification
Issue Date: 01/02/06
Epson Research and Development
Vancouver Design Center
8.3.2
8.3.3
8.3.4
8.3.5
8.3.6
8.3.7
8.3.8
8.3.9
8.3.10
8.3.11
8.3.12
8.3.13
8.3.14
8.3.15
8.3.16
8.3.17
8.3.18
9
Page 5
General IO Pins Registers . . . . . . .
MD Configuration Readback Registers
Clock Configuration Registers . . . .
Memory Configuration Registers . . .
Panel Configuration Registers . . . . .
LCD Display Mode Registers . . . . .
CRT/TV Configuration Registers . . .
CRT/TV Display Mode Registers . . .
LCD Ink/Cursor Registers . . . . . . .
CRT/TV Ink/Cursor Registers . . . .
BitBlt Configuration Registers . . . .
Look-Up Table Registers . . . . . . .
Power Save Configuration Registers .
Miscellaneous Registers . . . . . . . .
Common Display Mode Register . . .
MediaPlug Register Descriptions . . .
BitBlt Data Registers Descriptions . .
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.126
.128
.128
.132
.135
.140
.145
.150
.153
.157
.161
.169
.170
.171
.172
.173
.177
2D BitBlt Engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
9.1 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
9.2 BitBlt Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
10 Display Buffer . . . . . . . . . . . .
10.1 Image Buffer . . . . . . . . .
10.2 Ink Layer/Hardware Cursor Buffers
10.3 Dual Panel Buffer . . . . . . .
.
.
.
.
. . .
. .
. .
. .
.
.
.
.
.
.
.
.
.
.
.
.
. . .
. .
. .
. .
.
.
.
.
.
.
.
.
.
.
.
.
. . .
. .
. .
. .
.
.
.
.
.
.
.
.
.
.
.
.
. . .
. .
. .
. .
.
.
.
.
.
.
.
.
.
.
.
.
. 181
. 182
. 182
. 182
11 Display Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
11.1 Display Mode Data Format . . . . . . . . . . . . . . . . . . . . . . . . . 183
11.2 Image Manipulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
12 Look-Up Table Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
12.1 Monochrome Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
12.2 Color Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
13 TV Considerations . . . . . . . . . . . . . . . . .
13.1 NTSC/PAL Operation . . . . . . . . . . . .
13.2 Clock Source . . . . . . . . . . . . . . . .
13.3 Filters . . . . . . . . . . . . . . . . . .
13.3.1 Chrominance Filter (REG[05Bh] bit 5) . . . .
13.3.2 Luminance Filter (REG[05Bh] bit 4) . . . . .
13.3.3 Anti-flicker Filter (REG[1FCh] bits [2:1]) . .
13.4 TV Output Levels . . . . . . . . . . . . . .
13.5 TV Image Display and Positioning . . . . . . .
Hardware Functional Specification
Issue Date: 01/02/06
. . .
. .
. .
. .
. . .
. . .
. . .
. .
. .
.
.
.
.
.
.
.
.
.
. . . . . .
. . . . .
. . . . .
. . . . .
. . . . . . .
. . . . . . .
. . . . . . .
. . . . .
. . . . .
.
.
.
.
.
.
.
.
.
. . . .
. . .
. . .
. . .
. . . .
. . . .
. . . .
. . .
. . .
. . . 188
. . . 188
. . . 188
. . . 189
. . . .189
. . . .189
. . . . 189
. . . 190
. . . 193
S1D13506
X25B-A-001-10
Page 6
Epson Research and Development
Vancouver Design Center
13.6 TV Cursor Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
14 Ink Layer/Hardware Cursor Architecture
14.1 Ink Layer/Hardware Cursor Buffers . .
14.2 Ink/Cursor Data Format . . . . . . .
14.3 Ink/Cursor Image Manipulation . . . .
14.3.1 Ink Image . . . . . . . . . . . . .
14.3.2 Cursor Image . . . . . . . . . . .
. . .
. .
. .
. .
. . .
. . .
.
.
.
.
.
.
. . . . . .
. . . . .
. . . . .
. . . . .
. . . . . . .
. . . . . . .
.
.
.
.
.
.
.
.
.
.
.
.
15 SwivelView™ . . . . . . . . . . . . . .
15.1 Concept . . . . . . . . . . . .
15.2 90° SwivelView™ . . . . . . . .
15.2.1 Register Programming . . . . . .
15.2.2 Physical Memory Requirement .
15.2.3 Limitations . . . . . . . . . . . .
15.3 180° SwivelView™ . . . . . . . .
15.3.1 Register Programming . . . . . .
15.3.2 Limitations . . . . . . . . . . . .
15.4 270° SwivelView™ . . . . . . . .
15.4.1 Register Programming . . . . . .
15.4.2 Physical Memory Requirement .
15.4.3 Limitations . . . . . . . . . . . .
. . .
. .
. .
. . .
. . .
. . .
. .
. . .
. . .
. .
. . .
. . .
. . .
. . . . . . .
. . . . . .
. . . . . .
. . . . . . . .
. . . . . . . .
. . . . . . . .
. . . . . .
. . . . . . . .
. . . . . . . .
. . . . . .
. . . . . . . .
. . . . . . . .
. . . . . . . .
.
.
.
.
.
.
.
.
.
.
.
.
.
. . . . . . .
. . . . . .
. . . . . .
. . . . . . . .
. . . . . . . .
. . . . . . . .
. . . . . .
. . . . . . . .
. . . . . . . .
. . . . . .
. . . . . . . .
. . . . . . . .
. . . . . . . .
.
.
.
.
.
.
.
.
.
.
.
.
.
. . . . . . . . . .
. . . . . . . .
. . . . . . . .
. . . . . . . .
. . . . . . . . . . .
. . . . . . . . . . .
. . .
. .
. .
. . .
. . .
. . .
. .
. . .
. . .
. .
. . .
. . .
. . .
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
196
196
197
198
.198
.198
. 200
. 200
. 200
. .201
. .202
. .204
. 205
. .205
. .206
. 206
. .206
. .207
. .208
16 EPSON Independent Simultaneous Display (EISD) . . . . . . . . . . . . . . . . . 209
16.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
16.2 Bandwidth Limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
17 MediaPlug Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
17.1 Revision Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
17.2 How to enable the MediaPlug Slave . . . . . . . . . . . . . . . . . . . . . 211
18 Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
18.1 Frame Rate Calculation . . . . . . . . . . . . . . . . . . . . . .
18.1.1 LCD Frame Rate Calculation . . . . . . . . . . . . . . . . . . . . . . .
18.1.2 CRT Frame Rate Calculation . . . . . . . . . . . . . . . . . . . . . . .
18.1.3 TV Frame Rate Calculation . . . . . . . . . . . . . . . . . . . . . . . .
18.2 Example Frame Rates . . . . . . . . . . . . . . . . . . . . . . .
18.2.1 Frame Rates for 640x480 with EISD Disabled . . . . . . . . . . . . . .
18.2.2 Frame Rates for 800x600 with EISD Disabled . . . . . . . . . . . . . .
18.2.3 Frame Rates for LCD and CRT (640x480) with EISD Enabled . . . . .
18.2.4 Frame Rates for LCD and CRT (800x600) with EISD Enabled . . . . .
18.2.5 Frame Rates for LCD and NTSC TV with EISD Enabled . . . . . . . .
18.2.6 Frame Rates for LCD and PAL TV with EISD Enabled . . . . . . . . .
19 Power Save Mode
S1D13506
X25B-A-001-10
. . .
. .
. . .
. . .
. . .
. .
. . .
. . .
. . .
. . .
. . .
. . .
.
.
.
.
.
.
.
.
.
.
.
.
. 212
. 212
. .212
. .213
. .214
. 215
. .215
. .216
. .217
. .218
. .219
. .220
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
Hardware Functional Specification
Issue Date: 01/02/06
Epson Research and Development
Vancouver Design Center
19.1
19.2
19.3
19.4
Display Modes . . . . . .
Power Save Mode . . . . .
Power Save Status Bits . . .
Power Save Mode Summary .
Page 7
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
20 Clocks . . . . . . . . . . . . . . . .
20.1 Clock Selection . . . . . . . .
20.2 Clock Descriptions . . . . . .
20.2.1 MCLK . . . . . . . . . . . .
20.2.2 LCD PCLK . . . . . . . . .
20.2.3 CRT/TV PCLK . . . . . . .
20.2.4 MediaPlug Clock . . . . . .
20.3 Clocks vs. Functions . . . . . .
.
.
.
.
.
.
.
.
. . .
. .
. .
. . .
. . .
. . .
. . .
. .
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
. . . . . .
. . . . .
. . . . .
. . . . . . .
. . . . . . .
. . . . . . .
. . . . . . .
. . . . .
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
. . . . . .
. . . . .
. . . . .
. . . . . . .
. . . . . . .
. . . . . . .
. . . . . . .
. . . . .
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
. . . .
. . .
. . .
. . . .
. . . .
. . . .
. . . .
. . .
.
.
.
.
.
.
.
.
.
.
.
.
. 221
. 221
. 221
. 222
. . 223
. . 223
. . 224
. . .224
. . .224
. . .224
. . .224
. . 225
21 Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226
Hardware Functional Specification
Issue Date: 01/02/06
S1D13506
X25B-A-001-10
Page 8
Epson Research and Development
Vancouver Design Center
THIS PAGE LEFT BLANK
S1D13506
X25B-A-001-10
Hardware Functional Specification
Issue Date: 01/02/06
Epson Research and Development
Vancouver Design Center
Page 9
List of Tables
Table 5-1: Host Bus Interface Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 5-2: Memory Interface Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 5-3: LCD Interface Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 5-4: CRT Interface Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 5-5: Miscellaneous Interface Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . .
Table 5-6: Summary of Power-On/Reset Options . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 5-7: CPU Interface Pin Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 5-8: Memory Interface Pin Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 5-9: LCD Interface Pin Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 5-10: MA11, MA10, MA9, and DRDY Pin Mapping . . . . . . . . . . . . . . . . . . . . . .
Table 5-11: MediaPlug Interface Pin Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 6-1: Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 6-2: Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 6-3: Electrical Characteristics for VDD = 5.0V typical. . . . . . . . . . . . . . . . . . . . .
Table 6-4: Electrical Characteristics for VDD = 3.3V typical. . . . . . . . . . . . . . . . . . . . .
Table 6-5: Electrical Characteristics for VDD = 3.0V typical. . . . . . . . . . . . . . . . . . . . .
Table 7-1: Generic Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 7-2: Hitachi SH-4 Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 7-3: Hitachi SH-3 Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 7-4: MIPS/ISA Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 7-5: Motorola MC68000 Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 7-6: Motorola MC68030 Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 7-7: Motorola PowerPC Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 7-8: PC Card Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 7-9: Philips Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 7-10: Toshiba Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 7-11: Clock Input Requirements for CLKI/CLKI2/BUSCLK divided down internally. . . . .
Table 7-12: Clock Input Requirements for CLKI or BUSCLK if used directly for MCLK1 . . . . .
Table 7-13: Internal Clock Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 7-14: EDO-DRAM Read, Write, Read-Write Timing . . . . . . . . . . . . . . . . . . . . . .
Table 7-15: EDO-DRAM CAS Before RAS Refresh Timing . . . . . . . . . . . . . . . . . . . . .
Table 7-16: EDO - DRAM Self-Refresh Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 7-17: FPM-DRAM Read, Write, Read-Write Timing . . . . . . . . . . . . . . . . . . . . . .
Table 7-18: FPM-DRAM CAS Before RAS Refresh Timing . . . . . . . . . . . . . . . . . . . . .
Table 7-19: FPM-DRAM Self-Refresh Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 7-20: LCD Panel Power-off/Power-on Timing . . . . . . . . . . . . . . . . . . . . . . . . .
Table 7-21: Power Save Mode Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Hardware Functional Specification
Issue Date: 01/02/06
29
35
37
38
38
39
40
41
42
43
43
45
45
45
46
47
49
51
53
55
57
59
61
63
65
67
68
68
69
71
72
73
75
76
77
78
80
S1D13506
X25B-A-001-10
Page 10
Table 7-22: Single Monochrome 4-Bit Panel A.C. Timing. . . . . . . . . .
Table 7-23: Single Monochrome 8-Bit Panel A.C. Timing. . . . . . . . . .
Table 7-24: Single Color 4-Bit Panel A.C. Timing . . . . . . . . . . . . . .
Table 7-25: Single Color 8-Bit Panel A.C. Timing (Format 1) . . . . . . . .
Table 7-26: Single Color 8-Bit Panel A.C. Timing (Format 2) . . . . . . . .
Table 7-27: Single Color 16-Bit Panel A.C. Timing . . . . . . . . . . . . .
Table 7-28: Single Color 16-Bit Panel (with External Circuit) A.C. Timing.
Table 7-29: Dual Monochrome 8-Bit Panel A.C. Timing . . . . . . . . . .
Table 7-30: Dual Color 8-Bit Panel A.C. Timing. . . . . . . . . . . . . . .
Table 7-31: Dual Color 16-Bit Panel A.C. Timing . . . . . . . . . . . . . .
Table 7-32: Dual Color 16-Bit Panel (with External Circuit) A.C. Timing .
Table 7-33: TFT/D-TFD A.C. Timing . . . . . . . . . . . . . . . . . . . .
Table 7-34: CRT A.C. Timing . . . . . . . . . . . . . . . . . . . . . . . .
Table 7-35: Horizontal Timing for NTSC/PAL . . . . . . . . . . . . . . .
Table 7-36: Vertical Timing for NTSC/PAL . . . . . . . . . . . . . . . . .
Table 7-37: MediaPlug A.C. Timing . . . . . . . . . . . . . . . . . . . . .
Table 8-1: Register Mapping with CS# = 0 and M/R# = 0 . . . . . . . . .
Table 8-2: MA[11:9]/GPIO[1:3] Pin Functionality . . . . . . . . . . . . .
Table 8-3: MCLK Source Select . . . . . . . . . . . . . . . . . . . . . . .
Table 8-4: LCD PCLK Divide Selection. . . . . . . . . . . . . . . . . . .
Table 8-5: LCD PCLK Source Selection. . . . . . . . . . . . . . . . . . .
Table 8-6: CRT/TV PCLK Divide Selection. . . . . . . . . . . . . . . . .
Table 8-7: CRT/TV PCLK Source Selection . . . . . . . . . . . . . . . .
Table 8-8: MediaPlug Clock Divide Selection. . . . . . . . . . . . . . . .
Table 8-9: Video Clock Source Selection . . . . . . . . . . . . . . . . . .
Table 8-10: Minimum Memory Timing Selection . . . . . . . . . . . . . .
Table 8-11: Memory Type Selection . . . . . . . . . . . . . . . . . . . . .
Table 8-12: Refresh Selection. . . . . . . . . . . . . . . . . . . . . . . . .
Table 8-13: DRAM Refresh Rate Selection . . . . . . . . . . . . . . . . .
Table 8-14: DRAM Timing Control Selection . . . . . . . . . . . . . . . .
Table 8-15: Panel Data Width Selection . . . . . . . . . . . . . . . . . . .
Table 8-16: Horizontal Display Width (Pixels) . . . . . . . . . . . . . . . .
Table 8-17: LCD FPLINE Polarity Selection. . . . . . . . . . . . . . . . .
Table 8-18: LCD FPFRAME Polarity Selection . . . . . . . . . . . . . . .
Table 8-19: Setting SwivelView Modes . . . . . . . . . . . . . . . . . . .
Table 8-20: LCD Bit-per-pixel Selection . . . . . . . . . . . . . . . . . . .
Table 8-21: LCD Pixel Panning Selection . . . . . . . . . . . . . . . . . .
Table 8-22: DAC Output Level Selection . . . . . . . . . . . . . . . . . .
Table 8-23: CRT/TV Bit-per-pixel Selection . . . . . . . . . . . . . . . . .
Table 8-24: CRT/TV Pixel Panning Selection . . . . . . . . . . . . . . . .
S1D13506
X25B-A-001-10
Epson Research and Development
Vancouver Design Center
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
. 83
. 86
. 89
. 92
. 95
. 98
.101
.104
.107
.110
.113
.116
.118
.121
.122
.123
.124
.126
.128
.129
.129
.130
.130
.130
.131
.131
.132
.132
.133
.134
.135
.136
.138
.140
.141
.141
.144
.149
.150
.152
Hardware Functional Specification
Issue Date: 01/02/06
Epson Research and Development
Vancouver Design Center
Table 8-25:
Table 8-26:
Table 8-27:
Table 8-28:
Table 8-29:
Table 8-30:
Table 8-31:
Table 8-32:
Table 8-33:
Table 8-34:
Table 8-35:
Table 8-36:
Table 8-37:
Table 8-38:
Table 8-39:
Table 8-40:
Table 8-41:
Table 10-1:
Table 13-1:
Table 13-2:
Table 13-3:
Table 13-4:
Table 13-5:
Table 13-6:
Table 14-1:
Table 14-2:
Table 15-1:
Table 17-1:
Table 18-1:
Table 18-2:
Table 18-3:
Table 18-4:
Table 18-5:
Table 18-6:
Table 19-1:
Table 20-1:
LCD Ink/Cursor Selection . . . . . . . . . . . . . . . . . . . .
LCD Ink/Cursor Start Address Encoding . . . . . . . . . . . .
CRT/TV Ink/Cursor Selection . . . . . . . . . . . . . . . . . .
CRT/TV Ink/Cursor Start Address Encoding . . . . . . . . . .
BitBlt Active Status . . . . . . . . . . . . . . . . . . . . . . .
BitBlt FIFO Data Available . . . . . . . . . . . . . . . . . . .
BitBlt ROP Code/Color Expansion Function Selection . . . . .
BitBlt Operation Selection. . . . . . . . . . . . . . . . . . . .
BitBlt Source Start Address Selection . . . . . . . . . . . . . .
LUT Mode Selection . . . . . . . . . . . . . . . . . . . . . .
Setting SwivelView Modes . . . . . . . . . . . . . . . . . . .
Display Mode Selection . . . . . . . . . . . . . . . . . . . . .
MediaPlug LCMD Read/Write Descriptions . . . . . . . . . .
Timeout Option Delay . . . . . . . . . . . . . . . . . . . . . .
Cable Detect and Remote Powered Status. . . . . . . . . . . .
MediaPlug CMD Read/Write Descriptions . . . . . . . . . . .
MediaPlug Commands. . . . . . . . . . . . . . . . . . . . . .
S1D13506 Addressing . . . . . . . . . . . . . . . . . . . . . .
Required Clock Frequencies for NTSC/PAL . . . . . . . . . .
NTSC/PAL SVideo-Y (Luminance) Output Levels. . . . . . .
NTSC/PAL SVideo-C (Chrominance) Output Levels. . . . . .
NTSC/PAL Composite Output Levels . . . . . . . . . . . . .
Minimum and Maximum Values for NTSC/PAL . . . . . . . .
Register Values for Example NTSC/PAL Images. . . . . . . .
Ink/Cursor Start Address Encoding . . . . . . . . . . . . . . .
Ink/Cursor Color Select . . . . . . . . . . . . . . . . . . . . .
Minimum DRAM Size Required for SwivelView™ . . . . . .
MediaPlug Interface Pin Mapping . . . . . . . . . . . . . . . .
Frame Rates for 640x480 with EISD Disabled . . . . . . . . .
Frame Rates for 800x600 with EISD Disabled . . . . . . . . .
Frame Rates for LCD and CRT (640x480) with EISD Enabled
Frame Rates for LCD and CRT (800x600) with EISD Enabled
Frame Rates for LCD and NTSC TV with EISD Enabled . . .
Frame Rates for LCD and PAL TV with EISD Enabled . . . .
Power Save Mode Summary. . . . . . . . . . . . . . . . . . .
Clocks vs. Functions . . . . . . . . . . . . . . . . . . . . . . .
Hardware Functional Specification
Issue Date: 01/02/06
Page 11
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.153
.154
.157
. 158
.161
.162
. 163
.164
.165
.169
.172
.172
.173
.173
.174
.175
.176
.181
. 188
. 190
. 191
.192
.194
.195
.196
.197
.204
.211
. 215
. 216
. 217
. 218
. 219
. 220
.222
.225
S1D13506
X25B-A-001-10
Page 12
Epson Research and Development
Vancouver Design Center
THIS PAGE LEFT BLANK
S1D13506
X25B-A-001-10
Hardware Functional Specification
Issue Date: 01/02/06
Epson Research and Development
Vancouver Design Center
Page 13
List of Figures
Figure 3-1:
Figure 3-2:
Figure 3-3:
Figure 3-4:
Figure 3-5:
Figure 3-6:
Figure 3-7:
Figure 3-8:
Figure 3-9:
Figure 3-10:
Figure 4-1:
Figure 5-1:
Figure 5-2:
Figure 7-1:
Figure 7-2:
Figure 7-3:
Figure 7-4:
Figure 7-5:
Figure 7-6:
Figure 7-7:
Figure 7-8:
Figure 7-9:
Figure 7-10:
Figure 7-11:
Figure 7-12:
Figure 7-13:
Figure 7-14:
Figure 7-15:
Figure 7-16:
Figure 7-17:
Figure 7-18:
Figure 7-19:
Figure 7-20:
Figure 7-21:
Figure 7-22:
Figure 7-23:
Figure 7-24:
Typical System Diagram (Generic Bus) . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Typical System Diagram (Hitachi SH-4 Bus) . . . . . . . . . . . . . . . . . . . . . . . 22
Typical System Diagram (Hitachi SH-3 Bus) . . . . . . . . . . . . . . . . . . . . . . . 22
Typical System Diagram (MC68K Bus 1, Motorola 16-Bit 68000) . . . . . . . . . . . . 23
Typical System Diagram (MC68K Bus 2, Motorola 32-Bit 68030) . . . . . . . . . . . . 23
Typical System Diagram (Motorola PowerPC Bus) . . . . . . . . . . . . . . . . . . . . 24
Typical System Diagram (NECVR41xx MIPS Bus) . . . . . . . . . . . . . . . . . . . . 24
Typical System Diagram (PC Card Bus) . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Typical System Diagram (Philips MIPS PR31500/PR31700 Bus). . . . . . . . . . . . . 25
Typical System Diagram (Toshiba MIPS TX3912 Bus) . . . . . . . . . . . . . . . . . . 26
S1D13506 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Pinout Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
External Circuitry for CRT/TV Interface. . . . . . . . . . . . . . . . . . . . . . . . . . 44
Generic Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Hitachi SH-4 Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Hitachi SH-3 Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
MIPS/ISA Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Motorola MC68000 Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Motorola MC68030 Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Motorola PowerPC Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
PC Card Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Philips Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Toshiba Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
CLKI Clock Input Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
EDO-DRAM Page Mode Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
EDO-DRAM Read-Write Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
EDO-DRAM CAS Before RAS Refresh Timing. . . . . . . . . . . . . . . . . . . . . . 72
EDO - DRAM Self-Refresh Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
FPM-DRAM Page Mode Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
FPM-DRAM Read-Write Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
FPM-DRAM CAS Before RAS Refresh Timing. . . . . . . . . . . . . . . . . . . . . . 76
FPM - DRAM Self-Refresh Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
LCD Panel Power-off/Power-on Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Power Save Mode Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Single Monochrome 4-Bit Panel Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Single Monochrome 4-Bit Panel A.C. Timing . . . . . . . . . . . . . . . . . . . . . . . 82
Single Monochrome 8-Bit Panel Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Hardware Functional Specification
Issue Date: 01/02/06
S1D13506
X25B-A-001-10
Page 14
Figure 7-25:
Figure 7-26:
Figure 7-27:
Figure 7-28:
Figure 7-29:
Figure 7-30:
Figure 7-31:
Figure 7-32:
Figure 7-33:
Figure 7-34:
Figure 7-35:
Figure 7-36:
Figure 7-37:
Figure 7-38:
Figure 7-39:
Figure 7-40:
Figure 7-41:
Figure 7-42:
Figure 7-43:
Figure 7-44:
Figure 7-45:
Figure 7-46:
Figure 7-47:
Figure 7-48:
Figure 7-49:
Figure 7-50:
Figure 7-51:
Figure 7-52:
Figure 7-53:
Figure 7-54:
Figure 10-1:
Figure 11-1:
Figure 11-2:
Figure 12-1:
Figure 12-2:
Figure 12-3:
Figure 13-1:
Figure 13-2:
Figure 13-3:
Figure 13-4:
S1D13506
X25B-A-001-10
Epson Research and Development
Vancouver Design Center
Single Monochrome 8-Bit Panel A.C. Timing . . . . . . . . . . . . . . . . . . . . . . . 85
Single Color 4-Bit Panel Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Single Color 4-Bit Panel A.C. Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Single Color 8-Bit Panel Timing (Format 1) . . . . . . . . . . . . . . . . . . . . . . . . 90
Single Color 8-Bit Panel A.C. Timing (Format 1) . . . . . . . . . . . . . . . . . . . . . 91
Single Color 8-Bit Panel Timing (Format 2) . . . . . . . . . . . . . . . . . . . . . . . . 93
Single Color 8-Bit Panel A.C. Timing (Format 2) . . . . . . . . . . . . . . . . . . . . . 94
Single Color 16-Bit Panel Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Single Color 16-Bit Panel A.C. Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . 97
16-Bit Single Color Panel Timing with External Circuit . . . . . . . . . . . . . . . . . . 99
External Circuit for Color Single 16-Bit Panel When the Media Plug is Enabled . . . . 100
Single Color 16-Bit Panel (with External Circuit) A.C. Timing . . . . . . . . . . . . . 100
Dual Monochrome 8-Bit Panel Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Dual Monochrome 8-Bit Panel A.C. Timing . . . . . . . . . . . . . . . . . . . . . . . 103
Dual Color 8-Bit Panel Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Dual Color 8-Bit Panel A.C. Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Dual Color 16-Bit Panel Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Dual Color 16-Bit Panel A.C. Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 109
16-Bit Dual Color Panel Timing with External Circuit. . . . . . . . . . . . . . . . . . 111
External Circuit for Color Dual 16-Bit Panel When the Media Plug is Enabled . . . . . 112
Dual Color 16-Bit Panel (with External Circuit) A.C. Timing . . . . . . . . . . . . . . 112
TFT/D-TFD Panel Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
TFT/D-TFD A.C. Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
CRT Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
CRT A.C. Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
NTSC Video Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
PAL Video Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Horizontal Timing for NTSC/PAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Vertical Timing for NTSC/PAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
MediaPlug A.C. Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Display Buffer Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
4/8/15/16 Bit-per-pixel Format Memory Organization . . . . . . . . . . . . . . . . . . 183
Image Manipulation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
4 Bit-Per-Pixel Monochrome Mode Data Output Path . . . . . . . . . . . . . . . . . . 185
4 Bit-Per-Pixel Color Mode Data Output Path . . . . . . . . . . . . . . . . . . . . . . 186
8 Bit-Per-Pixel Color Mode Data Output Path . . . . . . . . . . . . . . . . . . . . . . 187
NTSC/PAL SVideo-Y (Luminance) Output Levels . . . . . . . . . . . . . . . . . . . 190
NTSC/PAL SVideo-C (Chrominance) Output Levels . . . . . . . . . . . . . . . . . . 191
NTSC/PAL Composite Output Levels . . . . . . . . . . . . . . . . . . . . . . . . . . 192
NTSC/PAL Image Positioning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
Hardware Functional Specification
Issue Date: 01/02/06
Epson Research and Development
Vancouver Design Center
Figure 13-5:
Figure 14-1:
Figure 14-2:
Figure 14-3:
Figure 15-1:
Figure 20-1:
Figure 21-1:
Page 15
Typical Total Display and Visible Display Dimensions for NTSC and PAL . . . . . .
Ink/Cursor Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Unclipped Cursor Positioning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clipped Cursor Positioning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Relationship Between Screen Image and 90° Rotated Image in the Display Buffer . . .
Clock Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Mechanical Drawing QFP15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Hardware Functional Specification
Issue Date: 01/02/06
195
197
198
199
200
223
226
S1D13506
X25B-A-001-10
Page 16
Epson Research and Development
Vancouver Design Center
THIS PAGE LEFT BLANK
S1D13506
X25B-A-001-10
Hardware Functional Specification
Issue Date: 01/02/06
Epson Research and Development
Vancouver Design Center
Page 17
1 Introduction
1.1 Scope
This is the Hardware Functional Specification for the S1D13506 Color LCD/CRT/TV
Controller. Included in this document are timing diagrams, AC and DC characteristics,
register descriptions, and power management descriptions. This document is intended for
two audiences: Video Subsystem Designers and Software Developers.
This specification will be updated as appropriate. Please check the Epson Electronics
America Website at http://www.eea.epson.com for the latest revision of this document
before beginning any development.
We appreciate your comments on our documentation. Please contact us via email at
[email protected]
1.2 Overview Description
The S1D13506 is a color LCD/CRT/TV graphics controller interfacing to a wide range of
CPUs and display devices. The S1D13506 architecture is designed to meet the low cost,
low power requirements of the embedded markets, such as Mobile Communications,
Hand-Held PC’s, and Office Automation.
The S1D13506 supports multiple CPUs, all LCD panel types, CRT, TV, and additionally
provides a number of differentiating features. Products requiring digital camera input can
take advantage of the directly supported WINNOV VideumCam™ digital interface. The
EPSON Independent Simultaneous Display (EISD) capability allows the user to configure
two different images on two different displays, while the SviwelView™, Hardware Cursor,
Ink Layer, and BitBLT engine offer substantial performance benefits. These features,
combined with the S1D13506’s Operating System independence, make it an ideal display
solution for a wide variety of applications.
Hardware Functional Specification
Issue Date: 01/02/06
S1D13506
X25B-A-001-10
Page 18
Epson Research and Development
Vancouver Design Center
2 Features
2.1 Memory Interface
• 16-bit DRAM interface:
• EDO-DRAM up to 40MHz data rate (80M Bytes/s).
• FPM-DRAM up to 25MHz data rate (50M Bytes/s).
• Memory size options:
• 512K bytes using one 256K×16 device.
• 2M bytes using one 1M×16 device.
• A configuration register can be programmed to enhance performance by tailoring the
memory control output timing to the DRAM device.
• The complete 2M byte display buffer address space is directly and contiguously available through the 21-bit address bus.
2.2 CPU Interface
• Supports the following interfaces:
• Epson E0C33 (16-bit interface to 32-bit microprocessor).
• Hitachi SH-4 bus interface.
• Hitachi SH-3 bus interface.
• MIPS/ISA.
• Motorola MC68000 (16-bit interface to 16/32-bit microprocessor/microcontroller).
• Motorola MC68030 (16-bit interface to 16/32-bit microprocessor/microcontroller).
• Motorola PowerPC MPC82x (16-bit interface to 32-bit microprocessor).
• MPU bus interface with programmable READY.
• NEC MIPS VR41xx.
• PC Card (PCMCIA).
• Philips MIPS PR31500/31700.
• Toshiba MIPS TX39xx.
• StrongARM (PC Card).
• One-stage write buffer for minimum wait-state CPU writes.
• Registers are memory-mapped – the M/R# pin selects between display buffer and
register address space.
S1D13506
X25B-A-001-10
Hardware Functional Specification
Issue Date: 01/02/06
Epson Research and Development
Vancouver Design Center
Page 19
2.3 Display Support
• 4/8-bit monochrome or 4/8/16-bit color LCD interface for single-panel, single-drive
displays.
• 8-bit monochrome or 8/16-bit color LCD interface for dual-panel, dual-drive displays.
• Direct support for 9/12-bit TFT/D-TFD, 18-bit TFT/D-TFD is supported up to 64K
colors.
• Direct support for CRT up to 64K colors using Embedded RAMDAC.
• Direct support for NTSC/PAL TV output using Embedded RAMDAC.
2.4 Display Modes
• 4/8/15/16 bit-per-pixel (bpp) color depths.
• Up to 64 shades of gray on monochrome passive LCD panels using Frame Rate Modulation (FRM) and Dithering.
• Up to 32K/64K colors in 15/16 bpp modes on color passive LCD panels using dithering.
• Up to 64K colors on TFT/D-TFD, CRT and TV.
• 4/8 bit-per-pixel color depths are mapped using three 256x4 Look-Up Tables (LUT)
allowing 16/256 out of a possible 4096 colors.
• Separate LUTs for LCD and CRT/TV.
• 15/16 bit-per-pixel color depths are mapped directly, bypassing the LUT.
• Example Resolutions:
320 x 240 at a color depth of 16 bpp.
640 x 240 at a color depth of 16 bpp.
640 x 480 at a color depth of 16 bpp.
800 x 600 at a color depth of 16 bpp.
2.5 Display Features
• SwivelView™: 90°, 180°, 270° hardware rotation of display image.
• EPSON Independent Simultaneous Display (EISD): displays independent images on
different displays (CRT or TV and passive or TFT/D-TFD panel).
• Virtual Display Support: displays images larger than the panel size through the use of
panning and scrolling.
• Hardware Cursor/Ink Layer: separate 64x64x2 hardware cursor or 2-bit ink layer for
both LCD and CRT/TV.
• Double Buffering/Multi-pages: for smooth animation and instantaneous screen update.
Hardware Functional Specification
Issue Date: 01/02/06
S1D13506
X25B-A-001-10
Page 20
Epson Research and Development
Vancouver Design Center
2.6 Clock Source
• Memory clock can be derived from CLKI or BUSCLK pin. It can be internally divided
by 2.
• Pixel clock can be derived from CLKI, CLKI2, or BUSCLK pin. It can be internally
divided by 2, 3 or 4.
• Bus clock can be BUSCLK or (BUSCLK)/2, i.e. a 2x clock may be used.
2.7 Acceleration
• 2D Engine including the following 2 ROP BitBlts:
Write BLT.
Move BLT.
Solid Fill.
Pattern Fill.
Transparent Write BLT.
Transparent Move BLT.
Read BLT.
Color Expansion.
Move BLT with Color Expansion.
2.8 MediaPlug Interface
• Built-in WINNOV MediaPlug interface.
• Videum®Cam support at resolution of 320x240x256 color at 30fps.
2.9 Miscellaneous
• The memory data bus, MD[15:0], is used to configure the chip at power-on.
• Three General Purpose Input/Output pins, GPIO[3:1], are available if upper Memory
Address pins are not required for asymmetric DRAM support.
• Power save mode is initiated by software.
• Operating voltage from 2.7 volts to 5.5 volts.
• 128-pin QFP15 surface mount package.
S1D13506
X25B-A-001-10
Hardware Functional Specification
Issue Date: 01/02/06
Epson Research and Development
Vancouver Design Center
Page 21
3 Typical System Implementation Diagrams
For the pin mapping of each system implementation, see Table 5-7:, “CPU Interface Pin
Mapping,” on pag e40.
Oscillator
Oscillator
CLKI2
CLKI
.
Generic
BUS
BS#
FPDAT[7:4]
A0
A[27:21]
CSn#
Decoder
M/R#
CS#
FPSHIFT
FPFRAME
FPFRAME
A[20:1]
AB[20:1]
FPLINE
D[15:0]
DB[15:0]
DRDY
WE0#
WE0#
WE1#
WE1#
RD0#
RD#
RD1#
RD/WR#
RED,GREEN,BLUE
HRTC
RAS#
LCAS#
UCAS#
LCAS#
UCAS#
WE#
RAS#
MD[15:0]
VRTC
WE#
D[15:0]
BUSCLK
RESET#
MA[11:0]
BCLK
DRDY (MOD)
GPIOx
WAIT#
RESET#
LCD
Display
FPLINE
S1D13506
A[11:0]
WAIT#
4-bit
Single
L[3:0]
FPSHIFT
Power
VDD
IREF
CRT/TV
Display
IREF
1Mx16
FPM/EDO-DRAM
Figure 3-1: Typical System Diagram (Generic Bus)
Hardware Functional Specification
Issue Date: 01/02/06
S1D13506
X25B-A-001-10
Page 22
Epson Research and Development
Vancouver Design Center
Oscillator
CLKI
SH-4
BUS
Oscillator
CLKI2
.
VDD
M/R#
CSn#
CS#
A[20:1]
AB[20:1]
D[15:0]
DB[15:0]
FPDAT[7:4]
FPSHIFT
FPFRAME
FPFRAME
FPLINE
WE1#
WE1#
BS#
BS#
RD/WR#
DRDY
FPLINE
DRDY (MOD)
S1D13506
4-bit
Single
LCD
Display
GPIOx
RD/WR#
RD#
D[3:0]
FPSHIFT
Power
A0
A[21]
RD#
RAS#
LCAS#
UCAS#
LCAS#
UCAS#
WE#
RAS#
BUSCLK
RESET#
CRT/TV
Display
VRTC
WE#
CKIO
RESET#
MD[15:0]
HRTC
D[15:0]
RED,GREEN,BLUE
WAIT#
MA[8:0]
WE0#
RDY#
A[8:0]
WE0#
IREF
IREF
256Kx16
FPM/EDO-DRAM
Figure 3-2: Typical System Diagram (Hitachi SH-4 Bus)
Oscillator
CLKI
SH-3
BUS
Oscillator
CLKI2
.
VDD
M/R#
CSn#
CS#
A[20:1]
AB[20:1]
D[15:0]
DB[15:0]
FPDAT[7:0]
FPSHIFT
Single
FPFRAME
FPFRAME
LCD
Display
FPLINE
WE1#
BS#
RD/WR#
RD#
WE1#
BS#
8-bit
D[7:0]
FPSHIFT
DRDY
FPLINE
DRDY (MOD)
S1D13506
Power
A0
A[21]
GPIOx
RD/WR#
RD#
WE#
RAS#
LCAS#
UCAS#
RAS#
LCAS#
UCAS#
BUSCLK
RESET#
VRTC
WE#
CKIO
RESET#
MD[15:0]
HRTC
D[15:0]
RED,GREEN,BLUE
WAIT#
MA[8:0]
WE0#
A[8:0]
WE0#
WAIT#
IREF
CRT/TV
Display
IREF
256Kx16
FPM/EDO-DRAM
Figure 3-3: Typical System Diagram (Hitachi SH-3 Bus)
S1D13506
X25B-A-001-10
Hardware Functional Specification
Issue Date: 01/02/06
Epson Research and Development
Vancouver Design Center
Page 23
.
Oscillator
Oscillator
MC68000
BUS
Decoder
M/R#
Decoder
CS#
FPDAT[7:4]
UD[3:0]
FPDAT[3:0]
LD[3:0]
FPSHIFT
FPSHIFT
8-bit
Dual
FPFRAME
FPFRAME
LCD
Display
A[20:1]
AB[20:1]
FPLINE
D[15:0]
DB[15:0]
DRDY
LDS#
AB0
UDS#
WE1#
AS#
FPLINE
DRDY (MOD)
S1D13506
Power
A[23:21]
FC0, FC1
CLKI
RD#
WE0#
CLKI2
VDD
GPIOx
BS#
R/W#
RED,GREEN,BLUE
RD/WR#
DTACK#
UCAS#
UCAS#
RAS#
LCAS#
LCAS#
WE#
RAS#
MD[15:0]
VRTC
WE#
MA[11:0]
A[11:0]
BUSCLK
RESET#
D[15:0]
CLK
RESET#
CRT/TV
Display
HRTC
WAIT#
IREF
IREF
256Kx16
FPM/EDO-DRAM
Figure 3-4: Typical System Diagram (MC68K Bus 1, Motorola 16-Bit 68000)
.
Oscillator
Oscillator
M/R#
Decoder
CS#
FPDAT[8:0]
A[20:0]
AB[20:0]
D[31:16]
DB[15:0]
FPSHIFT
9-bit
FPFRAME
FPFRAME
TFT
Display
FPLINE
DS#
WE1#
AS#
BS#
R/W#
RD/WR#
DRDY
S1D13506
WE0#
RED,GREEN,BLUE
WAIT#
HRTC
LCAS#
UCAS#
LCAS#
UCAS#
RAS#
RAS#
WE#
VRTC
WE#
A[8:0]
D[15:0]
BUSCLK
RESET#
MD[15:0]
SIZ0
DSACK1#
MA[8:0]
RD#
CLK
FPLINE
DRDY (MOD)
GPIOx
SIZ1
RESET#
D[8:0]
FPSHIFT
Power
Decoder
CLKI
A[31:21]
FC0, FC1
CLKI2
MC68030
BUS
IREF
CRT/TV
Display
IREF
256Kx16
FPM/EDO-DRAM
Figure 3-5: Typical System Diagram (MC68K Bus 2, Motorola 32-Bit 68030)
Hardware Functional Specification
Issue Date: 01/02/06
S1D13506
X25B-A-001-10
Page 24
Epson Research and Development
Vancouver Design Center
Oscillator
Oscillator
M/R#
Decoder
CS#
FPSHIFT
FPSHIFT
16-bit
Single
FPFRAME
FPFRAME
LCD
Display
FPDAT[15:0]
A[11:31]
AB[20:0]
D[0:15]
DB[15:0]
D[15:0]
FPLINE
BI#
TS#
BS#
RD/WR#
RD/WR#
S1D13506
WE0#
RED,GREEN,BLUE
TA#
WAIT#
HRTC
CRT/TV
Display
UCAS#
UCAS#
RAS#
LCAS#
LCAS#
RAS#
WE#
VRTC
WE#
D[15:0]
A[8:0]
BUSCLK
RESET#
MD[15:0]
TSIZ1
MA[8:0]
RD#
RESET#
DRDY (MOD)
GPIOx
TSIZ0
CLKOUT
FPLINE
DRDY
WE1#
Power
Decoder
CLKI
A[0:10]
CLKI2
PowerPC
BUS
IREF
IREF
256Kx16
FPM/EDO-DRAM
Figure 3-6: Typical System Diagram (Motorola PowerPC Bus)
Oscillator
Oscillator
CLKI2
CLKI
.
MIPS
BUS
M/R#
Decoder
FPDAT[7:0]
CSn#
CS#
A[20:0]
AB[20:0]
D[15:0]
DB[15:0]
FPSHIFT
FPSHIFT
Single
FPFRAME
FPFRAME
LCD
Display
FPLINE
FPLINE
DRDY
MEMW#
WE0#
SBHE#
WE1#
MEMR#
DRDY (MOD)
S1D13506
GPIOx
RD#
VDD
RED,GREEN,BLUE
RD/WR#
BS#
WE#
RAS#
LCAS#
UCAS#
RAS#
LCAS#
UCAS#
MD[15:0]
VRTC
WE#
D[15:0]
BUSCLK
RESET#
MA[11:0]
BCLK
RESET
CRT/TV
Display
HRTC
WAIT#
A[11:0]
RDY
8-bit
D[7:0]
Power
A[25:21]
IREF
IREF
1Mx16
FPM/EDO-DRAM
Figure 3-7: Typical System Diagram (NECVR41xx MIPS Bus)
S1D13506
X25B-A-001-10
Hardware Functional Specification
Issue Date: 01/02/06
Epson Research and Development
Vancouver Design Center
Page 25
Oscillator
CLKI
PC Card
BUS
Oscillator
CLKI2
.
VDD
Decoder
A[25:21]
Decoder
M/R#
CS#
FPDAT[15:8]
UD[7:0]
FPDAT[7:0]
LD[7:0]
FPSHIFT
FPSHIFT
FPFRAME
FPFRAME
A[20:1]
AB[20:1]
FPLINE
D[15:0]
DB[15:0]
DRDY
WE#
WE0#
CE2#
WE1#
OE#
16-bit
Dual
LCD
Display
FPLINE
DRDY (MOD)
S1D13506
Power
A0
GPIOx
RD#
CE1#
RED,GREEN,BLUE
RD/WR#
WAIT#
RAS#
LCAS#
UCAS#
LCAS#
UCAS#
WE#
RAS#
MD[15:0]
D[15:0]
VRTC
WE#
MA[11:0]
BUSCLK
A[11:0]
RESET#
Oscillator
CRT/TV
Display
HRTC
WAIT#
RESET
IREF
IREF
1Mx16
FPM/EDO-DRAM
Figure 3-8: Typical System Diagram (PC Card Bus)
A[12:0]
D[23:16]
DB[15:8]
DB[7:0]
AB20
D[31:24]
ALE
/CARDREG
/CARDIORD
AB18
AB17
/CARDxCSH
WE1#
/CARDxCSL
RD/WR#
UD[3:0]
LD[3:0]
FPSHIFT
FPSHIFT
8-bit
Dual
FPFRAME
FPFRAME
LCD
Display
FPLINE
AB19
/CARDIOWR
FPDAT[7:4]
FPDAT[3:0]
DRDY
FPLINE
DRDY (MOD)
S1D13506
Power
M/R#
CS#
BS#
AB[16:13]
AB[12:0]
Oscillator
CLKI
PR31500
/PR31700
BUS
Oscillator
CLKI2
.
GPIOx
RAS#
LCAS#
UCAS#
RAS#
LCAS#
UCAS#
RESET#
VRTC
WE#
BUSCLK
RESET#
MD[15:0]
DCLKOUT
HRTC
WE#
WAIT#
D[15:0]
/CARDxWAIT
RED,GREEN,BLUE
MA[11:0]
RD#
WE0#
A[11:0]
/RD
/WE
IREF
CRT/TV
Display
IREF
1Mx16
FPM/EDO-DRAM
Figure 3-9: Typical System Diagram (Philips MIPS PR31500/PR31700 Bus)
Hardware Functional Specification
Issue Date: 01/02/06
S1D13506
X25B-A-001-10
Page 26
Epson Research and Development
Vancouver Design Center
CARDIORD*
AB18
CARDIOWR*
AB17
CARDxCSH*
WE1#
CARDxCSL*
RD/WR#
FPFRAME
FPFRAME
TFT
Display
DRDY
FPLINE
DRDY (MOD)
S1D13506
RAS#
LCAS#
UCAS#
UCAS#
VRTC
LCAS#
BUSCLK
RESET#
CRT/TV
Display
HRTC
WE#
WAIT#
RAS#
WE0#
CARDxWAIT*
MD[15:0]
RD#
RED,GREEN,BLUE
WE#
RD*
PON*
12-bit
GPIOx
WE*
DCLKOUT
FPSHIFT
FPLINE
AB19
D[11:0]
FPSHIFT
Power
DB[7:0]
AB20
D[15:0]
D[31:24]
ALE
CARDREG*
MA[11:0]
D[23:16]
FPDAT[11:0]
A[11:0]
A[12:0]
M/R#
CS#
BS#
AB[16:13]
AB[12:0]
DB[15:8]
Oscillator
CLKI
TX3912
BUS
Oscillator
CLKI2
.
IREF
IREF
1Mx16
FPM/EDO-DRAM
Figure 3-10: Typical System Diagram (Toshiba MIPS TX3912 Bus)
S1D13506
X25B-A-001-10
Hardware Functional Specification
Issue Date: 01/02/06
Epson Research and Development
Vancouver Design Center
Page 27
4 Internal Description
4.1 Block Diagram Showing Pipelines
DRAM
Camera
MediaPlug
I/F
Memory
Controller
Host
CPU
LCD
Pipeline
I/F
LCD
LUT
LCD
I/F
LCD
2D
Register
CRT/TV
Pipeline
CRT/TV
LUT
DAC
CRT
/TV
TV
Encoder
Power Save
Figure 4-1: S1D13506 Block Diagram
Hardware Functional Specification
Issue Date: 01/02/06
S1D13506
X25B-A-001-10
Page 28
Epson Research and Development
Vancouver Design Center
5 Pins
5.1 Pinout Diagram
96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
128
MA2
127
MA4
126
MA3
125
VSS
124
CLKI
123
TESTEN
122
CLKI2
121
VDD
120
FPFRAME
119
FPLINE
118
NC
117
DRDY
116
FPSHIFT
115
VSS
114
FPDAT0
113
FPDAT1
112
FPDAT2
111
FPDAT4
110
FPDAT3
109
FPDAT5
108
FPDAT6
107
FPDAT7
106
VSS
105
FPDAT8
104
FPDAT9
103
FPDAT10
102
FPDAT11
101
FPDAT12
100
FPDAT13
99
FPDAT14
98
FPDAT15
VSS
97
MA5
VDD
DACVSS
MA1
DACVDD
MA6
RED
MA0
IREF
MA7
MA10
DACVDD
MA8
GREEN
MA11
DACVDD
BLUE
MA9
DACVSS
VDD
HRTC
RAS#
VRTC
WE#
VDD
UCAS#
VSS
LCAS#
AB20
VSS
AB19
MD7
S1D13506
AB18
MD8
AB17
MD6
AB16
MD9
AB15
MD5
AB14
MD10
AB13
MD4
AB12
MD11
AB11
MD3
AB10
MD12
AB9
MD2
AB8
MD13
AB7
MD1
AB6
MD14
AB5
MD0
AB4
MD15
AB3
VDD
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
DB0
VSS
DB1
DB2
DB3
DB4
DB5
DB6
DB8
DB7
DB9
DB10
DB12
DB11
DB13
DB14
DB15
VSS
WAIT#
VDD
BUSCLK
8
RESET#
7
RD/WR#
WE1#
6
WE0#
5
BS#
4
RD#
3
M/R#
AB0
2
CS#
AB2
AB1
1
64
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
Figure 5-1: Pinout Diagram
128-pin QFP15 surface mount package
S1D13506
X25B-A-001-10
Hardware Functional Specification
Issue Date: 01/02/06
Epson Research and Development
Vancouver Design Center
Page 29
5.2 Pin Description
Key:
I
O
IO
A
P
C
CD
CS
COx
=
=
=
=
=
=
=
=
=
TSx
=
TSu
=
TSxD
=
CNx
CNxU
CNxD
=
=
=
Input
Output
Bi-Directional (Input/Output)
Analog
Power pin
CMOS level input
CMOS level input with pull down resistor (typical values of 50Ω/90ΚΩ at 5V/3.3V respectively)
CMOS level Schmitt input
CMOS output driver, x denotes driver type (1=4/-4mA, 2=8/-8mA, 3=12/-12mA @ 5V)
Tri-state CMOS output driver, x denotes driver type (1=4/-4mA, 2=8/-8mA, 3=12/-12mA @ 5V), x denotes
driver type (1=4/-4mA, 2=8/-8mA, 3=12/-12mA @ 5V)
TSx with pull up resistor (typical values of 100KΩ/180ΚΩ at 5V/3.3V respectively)
TSx with pull down resistor, x denotes driver type (1=4/-4mA, 2=8/-8mA, 3=12/-12mA @ 5V) (typical
values of 100KΩ/180ΚΩ at 5V/3.3V)
CMOS low-noise output driver, x denotes driver type (1=4/-4mA, 2=8/-8mA, 3=12/-12mA @ 5V)
CNx with pull up resistor, x denotes driver type (1=4/-4mA, 2=8/-8mA, 3=12/-12mA @ 5V)
CNx with pull down resistor, x denotes driver type (1=4/-4mA, 2=8/-8mA, 3=12/-12mA @ 5V)
5.2.1 Host Bus Interface
Table 5-1: Host Bus Interface Pin Descriptions
Pin Name
AB0
Type
I
Pin #
3
Cell
CS
RESET#
State
Hi-Z
Description
• For SH-3/SH-4 Bus, this pin must be connected to VSS or VDD.
• For MC68K Bus 1, this pin inputs the lower data strobe (LDS#).
• For MC68K Bus 2, this pin inputs system address bit 0 (A0).
• For Generic Bus, this pin must be connected to VSS or VDD.
• For MIPS/ISA Bus, this pin inputs system address bit 0 (SA0).
• For Philips PR31500/31700 Bus, this pin inputs system address bit
0 (A0).
• For Toshiba TX3912 Bus, this pin inputs system address bit 0 (A0).
• For PowerPC Bus, this pin inputs system address bit 31 (A31).
• For PC Card (PCMCIA) Bus, this pin must be connected to VSS or
VDD.
SeeTable 5-7:, “CPU Interface Pin Mapping,” on page 40 for summary.
See the respective AC Timing diagram for detailed functionality.
AB[12:1]
I
119-128,
1, 2
C
Hi-Z
• For PowerPC Bus, these pins input the system address bits 19
through 30 (A[19:30]).
• For all other busses, these pins input the system address bits 12
through 1 (A[12:1]).
See Table 5-7:, “CPU Interface Pin Mapping,” on page 40 for summary.
See the respective AC Timing diagram for detailed functionality.
Hardware Functional Specification
Issue Date: 01/02/06
S1D13506
X25B-A-001-10
Page 30
Epson Research and Development
Vancouver Design Center
Table 5-1: Host Bus Interface Pin Descriptions (Continued)
Pin Name
AB[16:13]
Type
I
Pin #
115-118
Cell
C
RESET#
State
Hi-Z
Description
• For Philips PR31500/31700 Bus, these pins are connected to VDD.
• For Toshiba TX3912 Bus, these pins are connected to VDD.
• For PowerPC Bus, these pins input the system address bits 15
through 18 (A[15:18]).
• For all other busses, these pins input the system address bits 16
through 13 (A[16:13]).
See Table 5-7:, “CPU Interface Pin Mapping,” on page 40 for summary.
See the respective AC Timing diagram for detailed functionality.
AB17
I
114
C
Hi-Z
• For Philips PR31500/31700 Bus, this pin inputs the IO write
command (/CARDIOWR).
• For Toshiba TX3912 Bus, this pin inputs the IO write command
(CARDIOWR*).
• For PowerPC Bus, this pin inputs the system address bit 14 (A14).
• For all other busses, this pin inputs the system address bit 17 (A17).
See Table 5-7:, “CPU Interface Pin Mapping,” on page 40 for summary.
See the respective AC Timing diagram for detailed functionality.
AB18
I
113
C
Hi-Z
• For Philips PR31500/31700 Bus, this pin inputs the IO read
command (/CARDIORD).
• For Toshiba TX3912 Bus, this pin inputs the IO read command
(CARDIORD*).
• For PowerPC Bus, this pin inputs the system address bit 13 (A13).
• For all other busses, this pin inputs the system address bit 18 (A18).
See Table 5-7:, “CPU Interface Pin Mapping,” on page 40 for summary.
See the respective AC Timing diagram for detailed functionality.
AB19
I
112
C
Hi-Z
• For Philips PR31500/31700 Bus, this pin inputs the card control
register access (/CARDREG).
• For Toshiba TX3912 Bus, this pin inputs the card control register
access (CARDREG*).
• For PowerPC Bus, this pin inputs the system address bit 12 (A12).
• For all other busses, this pin inputs the system address bit 19 (A19).
See Table 5-7:, “CPU Interface Pin Mapping,” on page 40 for summary.
See the respective AC Timing diagram for detailed functionality.
AB20
I
111
C
Hi-Z
• For the MIPS/ISA Bus, this pin inputs system address bit 20. Note
that for the ISA Bus, the unlatched LA20 must first be latched
before input to AB20.
• For Philips PR31500/31700 Bus, this pin inputs the address latch
enable (ALE).
• For Toshiba TX3912 Bus, this pin inputs the address latch enable
(ALE).
• For PowerPC Bus, this pin inputs the system address bit 11 (A11).
• For all other busses, this pin inputs the system address bit 20 (A20).
See Table 5-7:, “CPU Interface Pin Mapping,” on page 40 for summary.
See the respective AC Timing diagram for detailed functionality.
S1D13506
X25B-A-001-10
Hardware Functional Specification
Issue Date: 01/02/06
Epson Research and Development
Vancouver Design Center
Page 31
Table 5-1: Host Bus Interface Pin Descriptions (Continued)
Pin Name
Type
Pin #
Cell
RESET#
State
Description
These pins are the system data bus. For 8-bit bus modes, unused data
pins should be tied to VDD.
DB[15:0]
IO
16-31
C/TS2
Hi-Z
• For SH-3/SH-4 Bus, these pins are connected to D[15:0].
• For MC68K Bus 1, these pins are connected to D[15:0].
• For MC68K Bus 2, these pins are connected to D[31:16] for 32-bit
devices (e.g. MC68030) or D[15:0] for 16-bit devices (e.g.
MC68340).
• For Generic Bus, these pins are connected to D[15:0].
• For MIPS/ISA Bus, these pins are connected to SD[15:0].
• For Philips PR31500/31700 Bus, pins DB[15:8] are connected to
D[23:16] and pins DB[7:0] are connected to D[31:24].
• For Toshiba TX3912 Bus, pins DB[15:8] are connected to D[23:16]
and pins DB[7:0] are connected to D[31:24].
• For PowerPC Bus, these pins are connected to D[0:15].
• For PC Card (PCMCIA) Bus, these pins are connected to D[15:0].
See Table 5-7:, “CPU Interface Pin Mapping,” on page 40 for summary.
See the respective AC Timing diagram for detailed functionality.
This is a multi-purpose pin:
WE1#
IO
9
CS/TS
2
Hi-Z
• For SH-3/SH-4 Bus, this pin inputs the write enable signal for the
upper data byte (WE1#).
• For MC68K Bus 1, this pin inputs the upper data strobe (UDS#).
• For MC68K Bus 2, this pin inputs the data strobe (DS#).
• For Generic Bus, this pin inputs the write enable signal for the upper
data byte (WE1#).
• For MIPS/ISA Bus, this pin inputs the system byte high enable
signal (SBHE#).
• For Philips PR31500/31700 Bus, this pin inputs the odd byte access
enable signal (/CARDxCSH).
• For Toshiba TX3912 Bus, this pin inputs the odd byte access enable
signal (CARDxCSH*).
• For PowerPC Bus, this pin outputs the burst inhibit signal (BI#).
• For PC Card (PCMCIA) Bus, this pin inputs the card enable 2 signal
(CE2#).
See Table 5-7:, “CPU Interface Pin Mapping,” on page 40 for summary.
See the respective AC Timing diagram for detailed functionality.
M/R#
I
5
C
Hi-Z
• For Philips PR31500/31700 Bus, this pin is connected to VDD.
• For Toshiba TX3912 Bus, this pin is connected to V DD.
• For all other busses, this input pin is used to select between the
display buffer and register address spaces of the S1D13506. M/R#
is set high to access the display buffer and low to access the
registers. See Register Mapping.
See Table 5-7:, “CPU Interface Pin Mapping,” on page 40.
CS#
I
4
C
Hi-Z
• For Philips PR31500/31700 Bus, this pin is connected to VDD.
• For Toshiba TX3912 Bus, this pin is connected to V DD.
• For all other busses, this is the Chip Select input.
See Table 5-7:, “CPU Interface Pin Mapping,” on page 40. See the
respective AC Timing diagram for detailed functionality.
Hardware Functional Specification
Issue Date: 01/02/06
S1D13506
X25B-A-001-10
Page 32
Epson Research and Development
Vancouver Design Center
Table 5-1: Host Bus Interface Pin Descriptions (Continued)
Pin Name
Type
Pin #
Cell
RESET#
State
Description
This pin inputs the system bus clock. It is possible to apply a 2x clock
and divide it by 2 internally - see MD12 in Summary of Configuration
Options.
BUSCLK
I
13
C
Hi-Z
• For SH-3/SH-4 Bus, this pin is connected to CKIO.
• For MC68K Bus 1, this pin is connected to CLK.
• For MC68K Bus 2, this pin is connected to CLK.
• For Generic Bus, this pin is connected to BCLK.
• For MIPS/ISA Bus, this pin is connected to CLK.
• For Philips PR31500/31700 Bus, this pin is connected to DCLKOUT.
• For Toshiba TX3912 Bus, this pin is connected to DCLKOUT.
• For PowerPC Bus, this pin is connected to CLKOUT.
• For PC Card (PCMCIA) Bus, this pin is connected to an external
input clock source.
See Table 5-7:, “CPU Interface Pin Mapping,” on page 40 for summary.
See the respective AC Timing diagram for detailed functionality.
This is a multi-purpose pin:
BS#
I
6
CS
Hi-Z
• For SH-3/SH-4 Bus, this pin inputs the bus start signal (BS#).
• For MC68K Bus 1, this pin inputs the address strobe (AS#).
• For MC68K Bus 2, this pin inputs the address strobe (AS#).
• For Generic Bus, this pin is connected to VDD.
• For MIPS/ISA Bus, this pin is connected to VDD.
• For Philips PR31500/31700 Bus, this pin is connected to VDD.
• For Toshiba TX3912 Bus, this pin is connected to V DD.
• For PowerPC Bus, this pin inputs the Transfer Start signal (TS#).
• For PC Card (PCMCIA) Bus, this pin is connected to VDD.
See Table 5-7:, “CPU Interface Pin Mapping,” on page 40 for summary.
See the respective AC Timing diagram for detailed functionality.
This is a multi-purpose pin:
RD/WR#
I
10
CS
Hi-Z
• For SH-3/SH-4 Bus, this pin inputs the read write signal (RD/WR#).
The S1D13506 needs this signal for early decode of the bus cycle.
• For MC68K Bus 1, this pin inputs the read write signal (R/W#).
• For MC68K Bus 2, this pin inputs the read write signal (R/W#).
• For Generic Bus, this pin inputs the read command for the upper
data byte (RD1#).
• For MIPS/ISA Bus, this pin is connected to VDD.
• For Philips PR31500/31700 Bus, this pin inputs the even byte
access enable signal (/CARDxCSL).
• For Toshiba TX3912 Bus, this pin inputs the even byte access
enable signal (CARDxCSL*).
• For PowerPC Bus, this pin inputs the read write signal (RD/WR#).
• For PC Card (PCMCIA) Bus, this pin inputs the card enable 1 signal
(CE1#).
See Table 5-7:, “CPU Interface Pin Mapping,” on page 40 for summary.
See the respective AC Timing diagram for detailed functionality.
S1D13506
X25B-A-001-10
Hardware Functional Specification
Issue Date: 01/02/06
Epson Research and Development
Vancouver Design Center
Page 33
Table 5-1: Host Bus Interface Pin Descriptions (Continued)
Pin Name
Type
Pin #
Cell
RESET#
State
Description
This is a multi-purpose pin:
RD#
I
7
CS
Hi-Z
• For SH-3/SH-4 Bus, this pin inputs the read signal (RD#).
• For MC68K Bus 1, this pin is connected to V DD.
• For MC68K Bus 2, this pin inputs the bus size bit 1 (SIZ1).
• For Generic Bus, this pin inputs the read command for the lower
data byte (RD0#).
• For MIPS/ISA Bus, this pin inputs the memory read signal
(MEMR#).
• For Philips PR31500/31700 Bus, this pin inputs the memory read
command (/RD).
• For Toshiba TX3912 Bus, this pin inputs the memory read command
(RD*).
• For PowerPC Bus, this pin inputs the transfer size 0 signal (TSIZ0).
• For PC Card (PCMCIA) Bus, this pin inputs the output enable signal
(OE#).
See Table 5-7:, “CPU Interface Pin Mapping,” on page 40 for summary.
See the respective AC Timing diagram for detailed functionality.
This is a multi-purpose pin:
WE0#
I
8
CS
Hi-Z
• For SH-3/SH-4 Bus, this pin inputs the write enable signal for the
lower data byte (WE0#).
• For MC68K Bus 1, this pin must be connected to VDD
• For MC68K Bus 2, this pin inputs the bus size bit 0 (SIZ0).
• For Generic Bus, this pin inputs the write enable signal for the lower
data byte (WE0#).
• For MIPS/ISA Bus, this pin inputs the memory write signal
(MEMW#).
• For Philips PR31500/31700 Bus, this pin inputs the memory write
command (/WE).
• For Toshiba TX3912 Bus, this pin inputs the memory write
command (WE*).
• For PowerPC Bus, this pin inputs the Transfer Size 1 signal (TSIZ1).
• For PC Card (PCMCIA) Bus, this pin inputs the write enable signal
(WE#).
See Table 5-7:, “CPU Interface Pin Mapping,” on page 40 for summary.
See the respective AC Timing diagram for detailed functionality.
Hardware Functional Specification
Issue Date: 01/02/06
S1D13506
X25B-A-001-10
Page 34
Epson Research and Development
Vancouver Design Center
Table 5-1: Host Bus Interface Pin Descriptions (Continued)
Pin Name
Type
Pin #
Cell
RESET#
State
Description
The active polarity of the WAIT# output is configurable; the state of MD5
on the rising edge of RESET# defines the active polarity of WAIT# - see
“Summary of Configuration Options”.
WAIT#
O
15
TS2
Hi-Za
or
1b
or
0c
• For SH-3 Bus, this pin outputs the wait request signal (WAIT#); MD5
must be pulled low during reset by the internal pull-down resistor.
• For SH-4 Bus, this pin outputs the ready signal (RDY#); MD5 must
be pulled high during reset by an external pull-up resistor.
• For MC68K Bus 1, this pin outputs the data transfer acknowledge
signal (DTACK#); MD5 must be pulled high during reset by an
external pull-up resistor.
• For MC68K Bus 2, this pin outputs the data transfer and size
acknowledge bit 1 (DSACK1#); MD5 must be pulled high during
reset by an external pull-up resistor.
• For Generic Bus, this pin outputs the wait signal (WAIT#); MD5 must
be pulled low during reset by the internal pull-down resistor.
• For MIPS/ISA Bus, this pin outputs the IO channel ready signal
(IOCHRDY); MD5 must be pulled low during reset by the internal
pull-down resistor.
• For Philips PR31500/31700 Bus, this pin outputs the wait state
signal (/CARDxWAIT). MD5 must be pulled low during reset by the
internal pull-down resistor.
• For Toshiba TX3912 Bus, this pin outputs the wait state signal
(CARDxWAIT*). MD5 must be pulled low during reset by the
internal pull-down resistor.
• For PowerPC Bus, this pin outputs the transfer acknowledge signal
(TA#); MD5 must be pulled high during reset by an external pull-up
resistor.
• For PC Card (PCMCIA) Bus, this pin outputs the wait signal
(WAIT#); MD5 must be pulled low during reset by the internal pulldown resistor.
See Table 5-7:, “CPU Interface Pin Mapping,” on page 40 for summary.
See the respective AC Timing diagram for detailed functionality.
RESET#
I
11
CS
0
Active low input that clears all internal registers and forces all outputs to
their inactive states. Note that active high RESET signals must be
inverted before input to this pin.
a
When the MD configuration at RESET# is set such that WAIT# can be tristated.
the MD configuration at RESET# is set such that WAIT# is always driven and active low.
c
When the MD configuration at RESET# is set such that WAIT# is always driven and active high.
bWhen
S1D13506
X25B-A-001-10
Hardware Functional Specification
Issue Date: 01/02/06
Epson Research and Development
Vancouver Design Center
Page 35
5.2.2 Memory Interface
Table 5-2: Memory Interface Pin Descriptions
Pin Name
LCAS#
Type
O
Pin #
51
Cell
CO1
RESET#
State
1
Description
• For dual-CAS# DRAM, this is the column address strobe for the
lower byte (LCAS#).
• For single-CAS DRAM, this is the column address strobe (CAS#).
See Table 5-8:, “Memory Interface Pin Mapping,” on page 41 for
summary. See Memory Interface Timing on page 70 for detailed
functionality.
This is a multi-purpose pin:
UCAS#
O
52
CO1
1
• For dual-CAS# DRAM, this is the column address strobe for the
upper byte (UCAS#).
• For single-CAS# DRAM, this is the write enable signal for the
upper byte (UWE#).
See Table 5-8:, “Memory Interface Pin Mapping,” on page 41 for
summary. See Memory Interface Timing on page 70 for detailed
functionality.
WE#
O
53
CO1
1
RAS#
O
54
CO1
1
• For dual-CAS# DRAM, this is the write enable signal (WE#).
• For single-CAS# DRAM, this is the write enable signal for the lower
byte (LWE#).
See Table 5-8:, “Memory Interface Pin Mapping,” on page 41 for
summary. See Memory Interface Timing on page 70 for detailed
functionality.
Row address strobe - see Memory Interface Timing on page 70 for
detailed functionality.
Bi-directional memory data bus.
MD[15:0]
IO
34, 36, 38,
40, 42, 44,
46, 48, 49,
C/TS1D
47, 45, 43,
41, 39, 37,
35
Hi-Z
(pull 0)
During reset, these pins are inputs and their states at the rising edge of
RESET# are used to configure the chip - see Summary of
Configuration Options on page 39. Internal pull-down resistors (typical
values of 100KΩ/180ΚΩ at 5V/3.3V respectively) pull the reset states
to 0. External pull-up resistors can be used to pull the reset states to 1.
See Memory Interface Timing on page 70 for detailed functionality.
Hardware Functional Specification
Issue Date: 01/02/06
S1D13506
X25B-A-001-10
Page 36
Epson Research and Development
Vancouver Design Center
Table 5-2: Memory Interface Pin Descriptions (Continued)
Pin Name
Type
Pin #
Cell
RESET#
State
MA[8:0]
O
58, 60, 62,
64, 66, 67,
65, 63, 61
CO1
0
Description
Multiplexed memory address - see Memory Interface Timing on page
70 for detailed functionality.
This is a multi-purpose pin:
MA9
IO
56
C/TS1
0a
or
Hi-Zb
• For 2M byte DRAM, this is memory address bit 9 (MA9).
• For asymmetrical 512K byte DRAM, this is memory address bit 9
(MA9).
• For symmetrical 512K byte DRAM, this pin can be used as general
purpose IO pin 3 (GPIO3).
Note that unless configured otherwise, this pin defaults to an input and
must be driven to a valid logic level.
See Table 5-8:, “Memory Interface Pin Mapping,” on page 41 for
summary. See Memory Interface Timing on page 70 for detailed
functionality.
This is a multi-purpose pin:
MA10
IO
59
C/TS1
0c
or
Hi-Zd
• For asymmetrical 2M byte DRAM this is memory address bit 10
(MA10).
• For symmetrical 2M byte DRAM and all 512K byte DRAM this pin
can be used as general purpose IO pin 1 (GPIO1).
Note that unless configured otherwise, this pin defaults to an input and
must be driven to a valid logic level.
See Table 5-8:, “Memory Interface Pin Mapping,” on page 41 for
summary. See Memory Interface Timing on page 70 for detailed
functionality.
This is a multi-purpose pin:
MA11
IO
57
C/TS1
0e
or
Hi-Zf
or
1g
• For asymmetrical 2M byte DRAM this is memory address bit 11
(MA11).
• For symmetrical 2M byte DRAM and all 512K byte DRAM this pin
can be used as general purpose IO pin 2 (GPIO2).
Note that unless configured otherwise, this pin defaults to an input and
must be driven to a valid logic level.
See Table 5-8:, “Memory Interface Pin Mapping,” on page 41 for
summary. See Memory Interface Timing on page 70 for detailed
functionality.
This pin can also be configured as the MediaPlug power pin
VMPEPWR - see Table 5-10:, “MA11, MA10, MA9, and DRDY Pin
Mapping,” on page 43 for details.
a
When the MD configuration at RESET# is set such that MA9 is used as MA9.
the MD configuration at RESET# is set such that MA9 is used as GPIO3.
c
When the MD configuration at RESET# is set such that MA10 is used as MA10.
d
When the MD configuration at RESET# is set such that MA10 is used as GPIO1.
eWhen the MD configuration at RESET# is set such that MA11 is used as MA11.
f
When the MD configuration at RESET# is set such that MA11 is used as GPIO2.
g
When the MD configuration at RESET# is set such that MA11 is used as VMPEPWR.
bWhen
S1D13506
X25B-A-001-10
Hardware Functional Specification
Issue Date: 01/02/06
Epson Research and Development
Vancouver Design Center
Page 37
5.2.3 LCD Interface
Table 5-3: LCD Interface Pin Descriptions
Pin Name
FPDAT[8:0]
FPDAT9
FPDAT[13:10]
Type
O
O
IO
RESET#
State
Description
CN3
0
Panel data bus. Not all pins are used for some panels - see Table 5-9:,
“LCD Interface Pin Mapping,” on page 42 for details. Unused pins are
driven low. FPDAT[15:8] can be configured for MediaPlug interface see Table 5-11:, “MediaPlug Interface Pin Mapping,” on page 43 for
details.
CN3D
0a
or
Hi-Zb
Panel data bus. Not all pins are used for some panels - see Table 5-9:,
“LCD Interface Pin Mapping,” on page 42 for details. Unused pins are
driven low. FPDAT[15:8] can be configured for MediaPlug interface see Table 5-11:, “MediaPlug Interface Pin Mapping,” on page 43 for
details.
C/TS3U
0c
or
Hi-Zd
Panel data bus. Not all pins are used for some panels - see Table 5-9:,
“LCD Interface Pin Mapping,” on page 42 for details. Unused pins are
driven low. FPDAT[15:8] can be configured for MediaPlug interface see Table 5-11:, “MediaPlug Interface Pin Mapping,” on page 43 for
details.
Pin #
Cell
88, 86-79
89
93-90
FPDAT[15:14]
O
95,94
CN3
0
Panel data bus. Not all pins are used for some panels - see Table 5-9:,
“LCD Interface Pin Mapping,” on page 42 for details. Unused pins are
driven low. FPDAT[15:8] can be configured for MediaPlug interface see Table 5-11:, “MediaPlug Interface Pin Mapping,” on page 43 for
details.
FPFRAME
O
73
CN3
0
Frame pulse
FPLINE
O
74
CN3
0
Line pulse
FPSHIFT
O
77
CO3
0
Shift clock
This is a multi-purpose pin:
DRDY
O
76
CO3
0e
or
1f
• For TFT/D-TFD panels this is the display enable output (DRDY).
• For passive LCD with Format 1 interface this is the 2nd Shift Clock
(FPSHIFT2).
• For all other LCD panels this is the LCD backplane bias signal
(MOD).
See Table 5-9:, “LCD Interface Pin Mapping,” on page 42 and
REG[030h] for details.
This pin can also be configured as the MediaPlug power pin
VMPEPWR - see Table 5-10:, “MA11, MA10, MA9, and DRDY Pin
Mapping,” on page 43 for details.
aWhen
the MD configuration at RESET# is set such that FPDAT9 is used as FPDAT9.
When the MD configuration at RESET# is set such that FPDAT9 is used as VMPRCTL.
cWhen the MD configuration at RESET# is set such that FPDAT[13:10] is used as FPDAT[13:10].
d
When the MD configuration at RESET# is set such that FPDAT[13:10] is used as VMPD[3:0].
e
When the MD configuration at RESET# is set such that DRDY is used as DRDY (MOD).
fWhen the MD configuration at RESET# is set such that DRDY is used as VMPEPWR.
b
Hardware Functional Specification
Issue Date: 01/02/06
S1D13506
X25B-A-001-10
Page 38
Epson Research and Development
Vancouver Design Center
5.2.4 CRT Interface
Table 5-4: CRT Interface Pin Descriptions
Pin Name
Type
Pin #
Cell
RESET#
State
HRTC
O
107
CN3
0
Horizontal retrace signal for CRT
VRTC
O
108
CN3
0
Vertical retrace signal for CRT
Description
RED
O
100
A
no output
Analog output for CRT color Red / S-Video Luminance
current
GREEN
O
103
A
no output
Analog output for CRT color Green / Composite Video Out
current
BLUE
O
105
A
no output
Analog output for CRT color Blue / S-Video Chrominance
current
IREF
I
101
A
--
Current reference for DAC. This pin must be connected to V SS if the
DAC is not needed.
5.2.5 Miscellaneous
Table 5-5: Miscellaneous Interface Pin Descriptions
Pin Name
Type
Pin #
Cell
RESET#
State
Description
CLKI
I
69
C
--
Selectable input clock. Can be used for the internal pixel clock (PCLK),
memory clock (MCLK), and MediaPlug Clock.
CLKI2
I
71
C
--
Selectable input clock. Can be used for the internal pixel clock (PCLK)
and MediaPlug Clock.
TESTEN
I
70
CD
--
Test Enable. This pin should be connected to VSS for normal operation.
VDD
P
12, 33, 55,
72, 97, 109
P
--
VDD
DACVDD
P
99, 102, 104
P
--
DAC VDD
VSS
P
14, 32, 50,
68, 78, 87,
96, 110
P
--
VSS
DACVSS
P
98, 106
P
--
DAC VSS
NC
-
75
--
Not connected
S1D13506
X25B-A-001-10
Hardware Functional Specification
Issue Date: 01/02/06
Epson Research and Development
Vancouver Design Center
Page 39
5.3 Summary of Configuration Options
Table 5-6: Summary of Power-On/Reset Options
Pin Name
value of this pin at rising edge of RESET# is used to configure:(1/0)
1
MD0
0
Not used, value of this pin at rising edge of RESET# can be read at REG[00Ch] bit 0
Select Host Bus Interface as follows:
MD11,MD[3:1]
MD11
0
0
0
0
0
0
0
0
1
MD3
0
0
0
0
1
1
1
1
1
MD2
0
0
1
1
0
0
1
1
1
MD1
0
1
0
1
0
1
0
1
1
Host Bus
SH-4/SH-3 Bus interface
MC68K Bus 1
MC68K Bus 2
Generic
Reserved
MIPS/ISA
PowerPC
PC Card (PCMCIA)
Philips PR31500/PR31700 / Toshiba TX3912
MD4
Little Endian
Big Endian
MD5
WAIT# is active high (1 = insert wait state)
WAIT# is active low (0 = insert wait state)
MD[7:6]
Memory Address/GPIO configuration:
(See Table 5-10:, “MA11, MA10, MA9, and DRDY Pin Mapping,” on page 43)
00 = symmetrical 256K×16 DRAM. MA[8:0] = DRAM address. MA[11:9] can be used as GPIO2,1,3 pins.
01 = symmetrical 1M×16 DRAM. MA[9:0] = DRAM address. MA[11:10] can be used as GPIO2,1 pins.
10 = asymmetrical 256K×16 DRAM. MA[9:0] = DRAM address. MA[11:10] can be used as GPIO2,1 pins.
11 = asymmetrical 1M×16 DRAM. MA[11:0] = DRAM address.
MD8
Not used, value of this pin at rising edge of RESET# can be read at REG[00Dh] bit 0
MD9
Not used, value of this pin at rising edge of RESET# can be read at REG[00Dh] bit 1
MD10
Not Used, value of this pin at rising edge of RESET# can be read at REG[00Dh] bit 2
MD12
BUSCLK input divided by 2
BUSCLK input not divided
MD13
Configure FPDAT[15:8] for MediaPlug I/F. External
latches required to support 16-bit passive panels.
Support 16-bit passive panels directly
MD14
DRDY or MA11 is configured as MediaPlug power
down pin (VMPEPWR). (See Table 5-10:, “MA11,
MA10, MA9, and DRDY Pin Mapping,” on page 43)
DRDY is configured as a normal LCD I/F output pin.
MA11 is configured as either a memory address or
GPIO2. (See Table 5-10:, “MA11, MA10, MA9, and
DRDY Pin Mapping,” on page 43)
MD15
WAIT# is always driven
WAIT# is tristated when the chip is not accessed by the
host
Hardware Functional Specification
Issue Date: 01/02/06
S1D13506
X25B-A-001-10
Page 40
Epson Research and Development
Vancouver Design Center
5.4 Multiple Function Pin Mapping
Table 5-7: CPU Interface Pin Mapping
S1D13506
Pin
Names
Generic
Hitachi
SH-4/SH-3
MIPS/ISA
Motorola
MC68K
Bus 1
Motorola
MC68K
Bus 2
Motorola
PowerPC
PC Card
Philips
PR31500
/PR31700
Toshiba
TX3912
AB20
A20
A20
LatchA20
A20
A20
A11
A20
ALE
ALE
AB19
A19
A19
SA19
A19
A19
A12
A19
/CARDREG
CARDREG*
AB18
A18
A18
SA18
A18
A18
A13
A18
/CARDIORD
CARDIORD*
AB17
A17
A17
SA17
A17
A17
A14
A17
/CARDIOWR
CARDIOWR*
AB[16:13]
A[16:13]
A[16:13]
SA[16:13]
A[16:13]
A[16:13]
A[15:18]
A[16:13]
AB[12:1]
A[12:1]
A[12:1]
SA[12:1]
A[12:1]
A[12:1]
A[19:30]
A[12:1]
A[12:1]
A[12:1]
AB0
Connected
to VDD1
Connected to
VDD1
SA0
LDS#
A0
A31
Connected to
VDD1
A0
A0
DB[15:8]
D[15:0]
D[15:8]
SD[15:0]
D[15:8]
D[31:24]
D[0:7]
D[15:0]
D[23:16]
D[23:16]
DB[7:0]
D[7:0]
D[7:0]
SD[7:0]
D[7:0]
D[23:16]
D[8:15]
D[7:0]
D[31:24]
D[31:24]
WE1#
WE1#
WE1#
SBHE#
UDS#
DS#
BI
CE2#
/CARDxCSH
CARDxCSH*
Connected to VDD Connected to VDD
M/R#
External Decode
Connected to VDD Connected to VDD
CS#
External Decode
Connected to VDD Connected to VDD
BUSCLK
BS#
BCLK
Connected
to VDD
CKIO
BS#
CLK
Connected to
VDD
Connected to
External
Oscillator2
CLK
CLK
CLKOUT
AS#
AS#
TS
R/W#
R/W#
RD/WR
CE1#
/CARDxCSL
CARDxCSL*
SIZ1
TSIZ0
OE#
/RD
RD*
SIZ0
TSIZ1
WE#
/WE
WE*
Connected to
VDD
RD/WR#
RD1#
RD/WR#
RD#
RD0#
RD#
MEMR#
WE0#
WE0#
WE0#
MEMW#
WAIT#
WAIT#
RDY#
/WAIT#
IOCHRDY
DTACK#
DSACK1#
TA
WAIT#
RESET#
RESET#
RESET#
inverted
RESET
RESET#
RESET#
RESET#
inverted
RESET
VDD
Connected to
VDD
Connected to
VDD
DCLKOUT
DCLKOUT
Connected to VDD Connected to VDD
/CARDxWAIT CARDxWAIT*
RESET#
PON*
Note
All GPIO pins default to input on reset and unless programmed otherwise, must be connected to either VSS or IO VDD if not used.
Note
1
AB0 is not used internally for these busses and must be connected to either VSS or
VDD.
2
For further information on interfacing the S1D13506 to the PC Card bus, see Interfacing to the PC Card Bus, document number X25B-G-005-xx.
S1D13506
X25B-A-001-10
Hardware Functional Specification
Issue Date: 01/02/06
Epson Research and Development
Vancouver Design Center
Page 41
Table 5-8: Memory Interface Pin Mapping
S1D13506
Pin Names
FPM/EDO-DRAM
Sym 256Kx16
2-CAS#
2-WE#
Asym 256Kx16
2-CAS#
Sym 1Mx16
2-WE#
MD[15:0]
2-CAS#
2-WE#
Asym 1Mx16
2-CAS#
2-WE#
D[15:0]
MA[8:0]
A[8:0]
1
GPIO32
MA9
A9
MA101
GPIO12
MA111
GPIO22
UCAS#
UCAS#
UWE#
UCAS#
LCAS#
WE#
LCAS#
CAS#
WE#
LWE#
RAS#
A9
A10
A11
UWE#
UCAS#
UWE#
UCAS#
LCAS#
CAS#
WE#
LWE#
UWE#
LCAS#
CAS#
LCAS#
CAS#
WE#
LWE#
WE#
LWE#
RAS#
Note
1. For MA9, MA10, and MA11 functionality see Table 5-10:, “MA11, MA10, MA9,
and DRDY Pin Mapping,” on page 43.
2. All GPIO pins default to input on reset and unless programmed otherwise, should be
connected to either VSS or IO VDD if not used.
Hardware Functional Specification
Issue Date: 01/02/06
S1D13506
X25B-A-001-10
Page 42
Epson Research and Development
Vancouver Design Center
Table 5-9: LCD Interface Pin Mapping
Monochrome Passive
Panel
S1D13506
Pin
Names
Single
4-bit
8-bit
Color Passive Panel
Dual
Single
8-bit
4-bit
Single
Single
Format 1
Format 2
8-bit
8-bit
Color TFT/D-TFD Panel
Single
16-Bit
FPFRAME
FPFRAME
FPLINE
FPLINE
FPSHIFT
Dual
8-bit
16-bit
9-bit
12-bit
18-bit
FPSHIFT
DRDY
MOD
MOD
FPSHIFT2
DRDY
FPDAT0
driven 0
D0
LD0
driven 0
D0
D0
D0
LD0
LD0
R2
R3
R5
FPDAT1
driven 0
D1
LD1
driven 0
D1
D1
D1
LD1
LD1
R1
R2
R4
FPDAT2
driven 0
D2
LD2
driven 0
D2
D2
D2
LD2
LD2
R0
R1
R3
FPDAT3
driven 0
D3
LD3
driven 0
D3
D3
D3
LD3
LD3
G2
G3
G5
FPDAT4
D0
D4
UD0
D0
D4
D4
D4
UD0
UD0
G1
G2
G4
FPDAT5
D1
D5
UD1
D1
D5
D5
D5
UD1
UD1
G0
G1
G3
FPDAT6
D2
D6
UD2
D2
D6
D6
D6
UD2
UD2
B2
B3
B5
FPDAT7
D3
D7
UD3
D3
D7
D7
D7
UD3
UD3
B1
B2
B4
FPDAT8
driven 0 driven 0 driven 0 driven 0 driven 0 driven 0
D8
driven 0
LD4
B0
B1
B3
FPDAT9
driven 0 driven 0 driven 0 driven 0 driven 0 driven 0
D9
driven 0
LD5
driven 0
R0
R2
FPDAT10 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0
D10
driven 0
LD6
driven 0 driven 0
R1
FPDAT11 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0
D11
driven 0
LD7
driven 0
G2
FPDAT12 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0
D12
driven 0
UD4
driven 0 driven 0
G1
FPDAT13 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0
D13
driven 0
UD5
driven 0 driven 0
G0
FPDAT14 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0
D14
driven 0
UD6
driven 0
B2
FPDAT15 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0
D15
driven 0
UD7
driven 0 driven 0
G0
B0
B1
Note
DRDY and FPDAT[15:8] may be used by the MediaPlug interface when the MediaPlug
is enabled. For MediaPlug Interface pin mapping, see Table 5-11:.
Note
For FPDATxx to LCD interface hardware connections, refer to Section 7.5, “Display Interface” on page 81.
S1D13506
X25B-A-001-10
Hardware Functional Specification
Issue Date: 01/02/06
Epson Research and Development
Vancouver Design Center
Page 43
Table 5-10: MA11, MA10, MA9, and DRDY Pin Mapping
MD14, MD7, MD6
MA11
MA10
MA9
DRDY
000
GPIO2
GPIO1
GPIO3
DRDY
001
GPIO2
GPIO1
MA9
DRDY
010
GPIO2
GPIO1
MA9
DRDY
011
MA11
MA10
MA9
DRDY
100
VMPEPWR
GPIO1
GPIO3
DRDY
101
VMPEPWR
GPIO1
MA9
DRDY
110
VMPEPWR
GPIO1
MA9
DRDY
111
MA11
MA10
MA9
VMPEPWR
Table 5-11: MediaPlug Interface Pin Mapping
S1D13506 Pin Names
FPDAT8
FPDAT9
FPDAT10
FPDAT11
FPDAT12
FPDAT13
FPDAT14
FPDAT15
DRDY or MA111
IO Type
O
I
IO
IO
IO
IO
O
O
O
MediaPlug I/F (MD13=1 at RESET)
VMPLCTL
VMPRCTL
VMPD0
VMPD1
VMPD2
VMPD3
VMPCLK
VMPCLKN
VMPEPWR
Note
1
Either DRDY or MA11 may be used for VMPEPWR (see Table 5-10: “MA11, MA10,
MA9, and DRDY Pin Mapping”). If DRDY is required by the LCD interface and MA11
is required by the DRAM interface then VMPEPWR is not available.
Hardware Functional Specification
Issue Date: 01/02/06
S1D13506
X25B-A-001-10
Page 44
Epson Research and Development
Vancouver Design Center
5.5 CRT/TV Interface
The following figure shows external circuitry for the CRT/TV interface.
CRT/TV
(REG[05Bh] bit 3 = 0)
DAC VDD = 3.3V
IREF
CRT Only
(REG[05Bh] bit 3 =1)
OR
1.5kΩ
1%
9.2 mA
or
4.6 mA
9.2 mA
1kΩ
1%
DAC VSS
R
G
B
}
DAC VSS
1µF
4.6 mA
V+
2N2222
DAC VSS
DAC VSS
DAC VDD = 2.7V to 5.5V
R
69.8Ω
1%
150Ω
1%
1.5kΩ
1%
OR
4.6 mA
2N2222
150Ω
1%
DAC VDD = 3.3V
CRT Only
(REG[05Bh] bit 3 =1)
140Ω
1%
DAC VSS
LM334
V-
1kΩ
1%
DAC VSS
290Ω
1%
29Ω
1%
1N457
DAC VSS DAC VSS
To CRT/TV
150Ω
1%
DAC VSS
Figure 5-2: External Circuitry for CRT/TV Interface
Note
Example implementation only, individual characteristics of components may affect
actual IREF current.
S1D13506
X25B-A-001-10
Hardware Functional Specification
Issue Date: 01/02/06
Epson Research and Development
Vancouver Design Center
Page 45
6 D.C. Characteristics
Table 6-1: Absolute Maximum Ratings
Symbol
VDD
DAC VDD
VIN
VOUT
TSTG
TSOL
Parameter
Supply Voltage
Supply Voltage
Input Voltage
Output Voltage
Storage Temperature
Solder Temperature/Time
Rating
VSS - 0.3 to 6.0
VSS - 0.3 to 6.0
VSS - 0.3 to VDD + 0.5
VSS - 0.3 to VDD + 0.5
-65 to 150
260 for 10 sec. max at lead
Units
V
V
V
V
°C
°C
Table 6-2: Recommended Operating Conditions
Symbol
VDD
VIN
TOPR
Parameter
Supply Voltage
Input Voltage
Operating Temperature
Condition
VSS = 0 V
Min
2.7
VSS
-40
Typ
3.0/3.3/5.0
25
Max
5.5
VDD
85
Units
V
V
°C
Max
400
1
1
Units
uA
µA
µA
Table 6-3: Electrical Characteristics for VDD = 5.0V typical
Symbol
IDDS
IIZ
IOZ
Parameter
Quiescent Current
Input Leakage Current
Output Leakage Current
VOH
High Level Output Voltage
VOL
Low Level Output Voltage
VIH
VIL
High Level Input Voltage
Low Level Input Voltage
VT+
High Level Input Voltage
VT-
Low Level Input Voltage
VH1
Hysteresis Voltage
RPD
CI
CO
CIO
Pull Down Resistance
Input Pin Capacitance
Output Pin Capacitance
Bi-Directional Pin Capacitance
Hardware Functional Specification
Issue Date: 01/02/06
Condition
Quiescent Conditions
Min
Typ
-1
-1
VDD = min
-4mA (Type1),
IOL =
-8mA (Type2)
-12mA (Type3)
VDD = min
IOL =
4mA (Type1),
8mA (Type2)
12mA (Type3)
CMOS level, VDD = max
CMOS level, VDD = min
CMOS Schmitt,
VDD = 5.0V
CMOS Schmitt,
VDD = 5.0V
CMOS Schmitt,
VDD = 5.0V
VI = VDD
VDD - 0.4
V
0.4
V
1.0
V
V
4.0
V
3.5
0.8
V
0.3
V
50
100
200
12
12
12
kΩ
pF
pF
pF
S1D13506
X25B-A-001-10
Page 46
Epson Research and Development
Vancouver Design Center
Table 6-4: Electrical Characteristics for VDD = 3.3V typical
Symbol
IDDS
IIZ
IOZ
Parameter
Quiescent Current
Input Leakage Current
Output Leakage Current
VOH
High Level Output Voltage
VOL
Low Level Output Voltage
VIH
VIL
High Level Input Voltage
Low Level Input Voltage
VT+
High Level Input Voltage
VT-
Low Level Input Voltage
VH1
Hysteresis Voltage
RPD
CI
CO
CIO
Pull Down Resistance
Input Pin Capacitance
Output Pin Capacitance
Bi-Directional Pin Capacitance
S1D13506
X25B-A-001-10
Condition
Quiescent Conditions
Min
Typ
-1
-1
VDD = min
IOL =
-2mA (Type1),
-4mA (Type2)
-6mA (Type3)
VDD = min
IOL =
2mA (Type1),
4mA (Type2)
6mA (Type3)
CMOS level, VDD = max
CMOS level, VDD = min
CMOS Schmitt,
VDD = 3.3V
CMOS Schmitt,
VDD = 3.3V
CMOS Schmitt,
VDD = 3.3V
VI = VDD
Max
290
1
1
VDD - 0.3
Units
uA
µA
µA
V
0.3
V
0.8
V
V
2.4
V
2.2
0.6
V
0.1
V
90
180
360
12
12
12
kΩ
pF
pF
pF
Hardware Functional Specification
Issue Date: 01/02/06
Epson Research and Development
Vancouver Design Center
Page 47
Table 6-5: Electrical Characteristics for VDD = 3.0V typical
Symbol
IDDS
IIZ
IOZ
Parameter
Quiescent Current
Input Leakage Current
Output Leakage Current
VOH
High Level Output Voltage
VOL
Low Level Output Voltage
VIH
VIL
High Level Input Voltage
Low Level Input Voltage
VT+
High Level Input Voltage
VT-
Low Level Input Voltage
VH1
Hysteresis Voltage
RPD
CI
CO
CIO
Pull Down Resistance
Input Pin Capacitance
Output Pin Capacitance
Bi-Directional Pin Capacitance
Hardware Functional Specification
Issue Date: 01/02/06
Condition
Quiescent Conditions
Min
Typ
-1
-1
VDD = min
IOL =
-1.8mA (Type1),
-3.5mA (Type2)
-5mA (Type3)
VDD = min
IOL =
1.8mA (Type1),
3.5mA (Type2)
5mA (Type3)
CMOS level, VDD = max
CMOS level, VDD = min
CMOS Schmitt,
VDD = 3.0V
CMOS Schmitt,
VDD = 3.0V
CMOS Schmitt,
VDD = 3.0V
VI = VDD
Max
260
1
1
VDD - 0.3
Units
uA
µA
µA
V
0.3
V
0.8
V
V
2.3
V
2.0
0.5
V
0.1
V
100
200
400
12
12
12
kΩ
pF
pF
pF
S1D13506
X25B-A-001-10
Page 48
Epson Research and Development
Vancouver Design Center
7 A.C. Characteristics
Conditions:
VDD = 3.0V ± 10% and VDD = 5.0V ± 10%
TA = -40° C to 85° C
Trise and Tfall for all inputs must be < 5 ns (10% ~ 90%)
CL = 50pF (CPU Interface), unless noted
CL = 100pF (LCD Panel Interface)
CL = 10pF (Display Memory Interface)
CL = 10pF (CRT Interface)
7.1 CPU Interface Timing
7.1.1 Generic Timing
TCLK
t2
t3
CLK
t5
t4
A[20:1]
M/R#
t6
CS#
RD0#,RD1#
WE0#,WE1#
t7
t8
WAIT#
t10
t9
D[15:0](write)
t11
t12
t13
D[15:0](read)
Figure 7-1: Generic Timing
Note
The above timing diagram is not applicable if MD12 = 1 (BUSCLK divided by 2).
S1D13506
X25B-A-001-10
Hardware Functional Specification
Issue Date: 01/02/06
Epson Research and Development
Vancouver Design Center
Page 49
Table 7-1: Generic Timing
Symbol
fCLK
TCLK
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
t12
t13
Parameter
Clock frequency
Clock period
Clock pulse width high
Clock pulse width low
A[20:1], M/R# setup to first CLK where CS# = 0 and either RD0#,
RD1#= 0 or WE0#, WE1#= 0
A[20:1], M/R# hold from rising edge of either RD0#, RD1# or WE0#,
WE1#
CS# hold from rising edge of either RD0#, RD1# or WE0#, WE1#
Falling edge of either RD0#, RD1# or WE0#, WE1# to WAIT# driven low
Rising edge of either RD0#, RD1# or WE0#, WE1# to WAIT# tri-state
D[15:0] setup to third CLK where CS# = 0 and WE0#, WE1# = 0 (write
cycle)
D[15:0] hold (write cycle)
Falling edge RD0#, RD1# to D[15:0] driven (read cycle)
D[15:0] setup to rising edge WAIT# (read cycle)
Rising edge of RD0#, RD1# to D[15:0] tri-state (read cycle)
Hardware Functional Specification
Issue Date: 01/02/06
3.0V
Min
Max
50
1/fCLK
6
6
5.0V
Min
Max
50
1/fCLK
6
6
Units
MHz
ns
ns
ns
4
3
ns
0
0
ns
0
4
3
0
3
2
ns
ns
ns
21
14
13
7
0
0
ns
0
3
0
7
0
3
0
4
ns
ns
ns
ns
31
15
S1D13506
X25B-A-001-10
Page 50
Epson Research and Development
Vancouver Design Center
7.1.2 Hitachi SH-4 Interface Timing
TCKIO
t2
t3
CKIO
t5
t4
A[20:1], M/R#
RD/WR#
t6
t7
BS#
t17
t12
t8
CSn#
t10
t9
WEn#
RD#
t18
t12
t11
RDY#
t14
t13
D[15:0](write)
t15
t16
D[15:0](read)
Figure 7-2: Hitachi SH-4 Timing
Note
The above timing diagram is not applicable if MD12 = 1 (BUSCLK divided by 2).
Note
The SH-4 Wait State Control Register for the area in which the S1D13506 resides must
be set to a non-zero value. The SH-4 read-to-write idle cycle transition must be set to a
non-zero value (with reference to BUSCLK).
S1D13506
X25B-A-001-10
Hardware Functional Specification
Issue Date: 01/02/06
Epson Research and Development
Vancouver Design Center
Page 51
Table 7-2: Hitachi SH-4 Timing
Symbol
fCKIO
TCKIO
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
t12
t13
t14
t15
t16
t17
t18
1.
2.
Parameter
Clock frequency
Clock period
Clock pulse width low
Clock pulse width high
A[20:1], M/R#, RD/WR# setup to CKIO
A[20:1], M/R#, RD/WR# hold from CSn#
BS# setup
BS# hold
CSn# setup
Falling edge RD# to D[15:0] driven
CKIO to RDY# high
Falling edge CSn# to RDY# driven
CKIO to RDY# delay
D[15:0] setup to 2nd CKIO after BS# (write cycle)
D[15:0] hold (write cycle)
D[15:0] valid to RDY# falling edge (read cycle)
Rising edge RD# to D[15:0] tri-state (read cycle)
CSn# high setup to CKIO
Falling edge CKIO to RDY# tri-state
3.0V1
Min
Max
0
66
1/fCKIO
6
6
4
0
4
3
3
3
4
21
3
11
4
20
0
0
0
6
30
3
3
14
5.0V2
Min
Max
0
66
1/fCKIO
16
6
3
0
3
2
2
3
3
13
2
7
3
13
0
0
0
3
16
2
2
10
Units
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Two software WAIT states are required.
One software WAIT state is required.
Hardware Functional Specification
Issue Date: 01/02/06
S1D13506
X25B-A-001-10
Page 52
Epson Research and Development
Vancouver Design Center
7.1.3 Hitachi SH-3 Interface Timing
TCKIO
t2
t3
CKIO
t4
t5
A[20:1], M/R#
RD/WR#
t6
t7
BS#
t17
t12
t8
CSn#
t10
t9
WEn#
RD#
t12
t11
WAIT#
t14
t13
D[15:0](write)
t15
t16
D[15:0](read)
Figure 7-3: Hitachi SH-3 Timing
Note
The above timing diagram is not applicable if MD12 = 1 (BUSCLK divided by 2).
Note
The SH-3 Wait State Control Register for the area in which the S1D13506 resides must
be set to a non-zero value.
S1D13506
X25B-A-001-10
Hardware Functional Specification
Issue Date: 01/02/06
Epson Research and Development
Vancouver Design Center
Page 53
Table 7-3: Hitachi SH-3 Timing
Symbol
fCKIO
TCKIO
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
t12
t13
t14
t15
t16
t17
1.
2.
Parameter
Clock frequency
Clock period
Clock pulse width low
Clock pulse width high
A[20:1], M/R#, RD/WR# setup to CKIO
A[20:1], M/R#, RD/WR# hold from CSn#
BS# setup
BS# hold
CSn# setup
Falling edge RD# to D[15:0] driven
Rising edge CSn# to WAIT# tri-state
Falling edge CSn# to WAIT# driven
CKIO to WAIT# delay
D[15:0] setup to 2nd CKIO after BS# (write cycle)
D[15:0] hold (write cycle)
D[15:0] valid to WAIT# rising edge (read cycle)
Rising edge RD# to D[15:0] tri-state (read cycle)
CSn# high setup to CKIO
3.0V1
Min
Max
66
1/fCKIO
6
6
4
0
4
3
3
3
2
10
3
16
4
20
0
0
0
6
30
3
5.0V2
Min
Max
66
1/fCKIO
6
6
3
0
3
2
3
2
1
6
2
10
3
13
0
0
0
3
15
2
Units
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Two software WAIT states are required when fCKIO is greater than 33MHz.
One software WAIT state is required when fCKIO is greater than 33MHz.
Hardware Functional Specification
Issue Date: 01/02/06
S1D13506
X25B-A-001-10
Page 54
Epson Research and Development
Vancouver Design Center
7.1.4 MIPS/ISA Interface Timing (e.g. NEC VR41xx)
TBUSCLK
t2
t3
BUSCLK
t5
t4
LatchA20
SA[19:0]
M/R#, SBHE#
t6
CS#
MEMR#
MEMW#
t7
t8
IOCHRDY
t10
t9
SD[15:0](write)
t11
t12
t13
SD[15:0](read)
Figure 7-4: MIPS/ISA Timing
Note
The above timing diagram is not applicable if MD12 = 1 (BUSCLK divided by 2).
S1D13506
X25B-A-001-10
Hardware Functional Specification
Issue Date: 01/02/06
Epson Research and Development
Vancouver Design Center
Page 55
Table 7-4: MIPS/ISA Timing
3.0V
Symbol
fBUSCLK
TBUSCLK
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
t12
t13
Parameter
Min
Clock frequency
Clock period
1/fBUSCLK
Clock pulse width high
6
Clock pulse width low
6
LatchA20, SA[19:0], M/R#, SBHE# setup to first
BUSCLK where CS# = 0 and either MEMR# = 0 or
4
MEMW# = 0
LatchA20, SA[19:0], M/R#, SBHE# hold from rising edge
0
of either MEMR# or MEMW#
CS# hold from rising edge of either MEMR# or MEMW#
0
Falling edge of either MEMR# or MEMW# to IOCHRDY#
2
driven low
Rising edge of either MEMR# or MEMW# to IOCHRDY#
2
tri-state
SD[15:0] setup to third BUSCLK where CS# = 0
0
MEMW# = 0 (write cycle)
SD[15:0] hold (write cycle)
0
Falling edge MEMR# to SD[15:0] driven (read cycle)
4
SD[15:0] setup to rising edge IOCHRDY# (read cycle)
0
Rising edge of MEMR# toSD[15:0] tri-state (read cycle)
7
Hardware Functional Specification
Issue Date: 01/02/06
5.0V
Max
50
Min
Max
50
1/fBUSCLK
6
6
Units
MHz
ns
ns
ns
3
ns
0
ns
0
ns
17
2
10
ns
12
1
7
ns
31
0
ns
0
3
0
4
ns
ns
ns
ns
15
S1D13506
X25B-A-001-10
Page 56
Epson Research and Development
Vancouver Design Center
7.1.5 Motorola MC68K Bus 1 Interface Timing (e.g. MC68000)
TCLK
t2
t3
CLK
t4
t5
A[20:1]
M/R#
t6
CS#
t17
AS#
t11
UDS#
LDS#
t8
t7
R/W#
t9
t10
DTACK#
t12
t13
D[15:0](write)
t14
t15
t16
D[15:0](read)
Figure 7-5: Motorola MC68000 Timing
Note
The above timing diagram is not applicable if MD12 = 1 (BUSCLK divided by 2).
S1D13506
X25B-A-001-10
Hardware Functional Specification
Issue Date: 01/02/06
Epson Research and Development
Vancouver Design Center
Page 57
Table 7-5: Motorola MC68000 Timing
3.0V
Symbol
fCLK
TCLK
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
t12
t13
t14
t15
t16
t17
Parameter
Clock frequency
Clock period
Clock pulse width high
Clock pulse width low
A[20:1], M/R# setup to first CLK where CS# = 0 AS# = 0, and
either UDS#=0 or LDS# = 0
A[20:1], M/R# hold from AS#
CS# hold from AS#
R/W# setup to before to either UDS#=0 or LDS# = 0
R/W# hold from AS#
AS# = 0 and CS# = 0 to DTACK# driven high
AS# high to DTACK# high
First BCLK where AS# = 1 to DTACK# high impedance
D[15:0] valid to third CLK where CS# = 0 AS# = 0, and either
UDS#=0 or LDS# = 0 (write cycle)
D[15:0] hold from falling edge of DTACK# (write cycle)
Falling edge of UDS#=0 or LDS# = 0 to D[15:0] driven (read
cycle)
D[15:0] valid to DTACK# falling edge (read cycle)
UDS# and LDS# high to D[15:0] invalid/high impedance (read
cycle)
AS# high setup to CLK
Hardware Functional Specification
Issue Date: 01/02/06
Min
5.0V
Max
50
1/fCLK
6
6
1/fCLK
6
6
Units
MHz
ns
ns
ns
5
3
ns
0
0
10
0
1
4
3
0
0
10
0
1
3
2
ns
ns
ns
ns
ns
ns
ns
18
15
Min
Max
50
11
10
0
0
ns
0
0
ns
3
3
ns
0
0
ns
6
4
31
4
3
15
ns
ns
S1D13506
X25B-A-001-10
Page 58
Epson Research and Development
Vancouver Design Center
7.1.6 Motorola MC68K Bus 2 Interface Timing (e.g. MC68030)
TCLK
t2
t3
CLK
t5
t4
A[20:0]
SIZ[1:0] M/R#
t6
CS#
t17
AS#
t11
DS#
t7
t8
R/W#
t9
t10
DSACK1#
t12
t13
D[31:16](write)
t14
t15
t16
D[31:16](read)
Figure 7-6: Motorola MC68030 Timing
Note
The above timing diagram is not applicable if MD12 = 1 (BUSCLK divided by 2).
S1D13506
X25B-A-001-10
Hardware Functional Specification
Issue Date: 01/02/06
Epson Research and Development
Vancouver Design Center
Page 59
Table 7-6: Motorola MC68030 Timing
3.0V
Symbol
fCLK
TCLK
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
t12
t13
t14
t15
t16
t17
Parameter
Clock frequency
Clock period
Clock pulse width high
Clock pulse width low
A[20:0], SIZ[1:0], M/R# setup to first CLK where CS# = 0,
AS# = 0, and DS# = 0
A[20:0], SIZ[1:0], M/R# hold from AS#
CS# hold from AS#
R/W# setup to DS#
R/W# hold from AS#
AS# = 0 and CS# = 0 to DSACK1# driven high
AS# high to DSACK1# high
First BCLK where AS# = 1 to DSACK1# high impedance
D[31:16] valid to third CLK where CS# = 0, AS# = 0, and
DS# = 0 (write cycle)
D[31:16] hold from falling edge of DSACK1# (write cycle)
Falling edge of DS# = 0 to D[31:16] driven (read cycle)
D[31:16] valid to DSACK1# falling edge (read cycle)
DS# high to D[31:16] invalid/high impedance (read cycle)
AS# high setup to CLK
Hardware Functional Specification
Issue Date: 01/02/06
Min
5.0V
Max
50
1/fCLK
6
6
1/fCLK
6
6
Units
MHz
ns
ns
ns
5
3
ns
0
0
10
0
1
4
3
0
0
10
0
1
3
2
ns
ns
ns
ns
ns
ns
ns
18
15
Min
Max
50
12
14
0
0
ns
0
3
0
6
4
0
3
0
4
3
ns
ns
ns
ns
ns
31
15
S1D13506
X25B-A-001-10
Page 60
Epson Research and Development
Vancouver Design Center
7.1.7 Motorola PowerPC Interface Timing (e.g. MPC8xx, MC68040, Coldfire)
TCLKOUT
t2
t3
CLKOUT
t4
t5
A[11:31], RD/WR#
TSIZ[0:1], M/R#
t7
t6
CS#
t8
t9
TS#
t11
t10
t12
t13
t15
t16
TA#
t14
BI#
t17
t18
D[0:15](write)
t19
t20
t21
D[0:15](read)
Figure 7-7: Motorola PowerPC Timing
Note
The above timing diagram is not applicable if MD12 = 1 (BUSCLK divided by 2).
S1D13506
X25B-A-001-10
Hardware Functional Specification
Issue Date: 01/02/06
Epson Research and Development
Vancouver Design Center
Page 61
Table 7-7: Motorola PowerPC Timing
3.0V
Symbol
fCLKOUT
TCLKOUT
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
t12
t13
t14
t15
t16
t17
t18
t19
t20
t21
Parameter
Min
Clock frequency
Clock period
1/fCLKOUT
Clock pulse width low
6
Clock pulse width high
6
AB[11:31], RD/WR#, TSIZ[0:1], M/R# setup
0
AB[11:31], RD/WR#, TSIZ[0:1], M/R# hold
0
CS# setup
1
CS# hold
0
TS# setup
1
TS# hold
0
CLKOUT to TA# driven
2
CLKOUT to TA# low
3
CLKOUT to TA# high
3
negative edge CLKOUT to TA# tri-state
3
CLKOUT to BI# driven
3
CLKOUT to BI# high
3
negative edge CLKOUT to BI# tri-state
3
DB[15:0] setup to 2nd CLKOUT after TS# = 0 (write cycle)
0
DB[15:0] hold (write cycle)
0
CLKOUT to DB driven (read cycle)
3
DB[15:0] valid to TA# falling edge (read cycle)
0
CLKOUT to DB[15:0] tri-state (read cycle)
3
5.0V
Max
45
15
16
14
13
13
14
14
Min
1/fCLKOUT
6
6
0
0
0
1
1
1
1
2
2
2
2
2
2
0
0
2
0
2
Max
50
9
10
9
8
8
8
9
Units
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note
Output pin loading on DB[15:0], TA#, BI# is 10pF.
Hardware Functional Specification
Issue Date: 01/02/06
S1D13506
X25B-A-001-10
Page 62
Epson Research and Development
Vancouver Design Center
7.1.8 PC Card Timing (e.g. StrongARM)
TCLK
t2
t3
CLK
(provided externally)
t5
t4
A[20:1]
M/R#
CE1#, CE2#
t6
CS#
OE#
WE#
t7
t8
WAIT#
t10
t9
D[15:0](write)
t11
t12
t13
D[15:0](read)
Figure 7-8: PC Card Timing
Note
The above timing diagram is not applicable if MD12 = 1 (BUSCLK divided by 2).
S1D13506
X25B-A-001-10
Hardware Functional Specification
Issue Date: 01/02/06
Epson Research and Development
Vancouver Design Center
Page 63
Table 7-8: PC Card Timing
Symbol
fCLK
TCLK
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
t12
t13
Parameter
Clock frequency
Clock period
Clock pulse width high
Clock pulse width low
A[20:1], M/R# setup to first CLK where CE1# = 0 or CE2# = 0 and either
OE# = 0 or WE# = 0
A[20:1], M/R# hold from rising edge of either OE# or WE#
CS# hold from rising edge of either OE# or WE#
Falling edge of either OE# or WE# to WAIT# driven low
Rising edge of either OE# or WE# to WAIT# tri-state
D[15:0] setup to third CLK where CE1# = 0, CE2# = 0 and WE# = 0
(write cycle)
D[15:0] hold (write cycle)
Falling edge OE# to D[15:0] driven (read cycle)
D[15:0] setup to rising edge WAIT# (read cycle)
Rising edge of OE# to D[15:0] tri-state (read cycle)
Hardware Functional Specification
Issue Date: 01/02/06
3.0V
Min
Max
50
1/fCLK
6
6
5.0V
Min
Max
50
1/fCLK
6
6
Units
MHz
ns
ns
ns
4
3
ns
0
0
2
3
0
0
2
2
ns
ns
ns
ns
21
14
9
9
0
0
ns
0
10
0
7
0
8
0
5
ns
ns
ns
ns
34
17
S1D13506
X25B-A-001-10
Page 64
Epson Research and Development
Vancouver Design Center
7.1.9 Philips Interface Timing (e.g. PR31500/PR31700)
TDCLKOUT
t3
t2
DCLKOUT
t4
t5
ADDR[12:0]
t6
t7
ALE
t8
/CARDREG
/CARDxCSH
/CARDxCSL
/CARDIORD
/CARDIOWR
/WE /RD
t9
t10
/CARDxWAIT
t11
t12
D[31:16](write)
t13
t14
t15
D[31:16](read)
Figure 7-9: Philips Timing
S1D13506
X25B-A-001-10
Hardware Functional Specification
Issue Date: 01/02/06
Epson Research and Development
Vancouver Design Center
Page 65
Table 7-9: Philips Timing
3.0V
Symbol
fDCLKOUT Clock frequency
TDCLKOUT Clock period
Parameter
Min
5.0V
Max
75
Min
Max
75
1/fDCLKOUT
1/fDCLKOUT
Units
MHz
ns
t2
Clock pulse width low
6
6
ns
t3
Clock pulse width high
6
6
ns
t4
ADDR[12:0] setup to first CLK of cycle
10
10
ns
t5
ADDR[12:0] hold from command invalid
0
0
ns
t6
ADDR[12:0] setup to falling edge ALE
10
10
ns
t7
ADDR[12:0] hold from falling edge ALE
5
5
ns
t8
/CARDREG hold from command invalid
0
0
ns
t9
Falling edge of chip select to /CARDxWAIT driven
2
14
1
9
ns
t10
Command invalid to /CARDxWAIT tri-state
2
13
2
12
ns
t11
D[31:16] valid to first CLK of cycle (write cycle)
10
10
t12
D[31:16] hold from rising edge of /CARDxWAIT
0
0
t13
Chip select to D[31:16] driven (read cycle)
4
3
ns
t14
D[31:16] setup to rising edge /CARDxWAIT (read cycle)
0
0
ns
t15
Command invalid to D[31:16] tri-state (read cycle)
7
30
4
ns
16
ns
Note
If BUSCLK exceeds 37.5MHz, it must be divided by 2 using MD12 (see Table 5-6:,
“Summary of Power-On/Reset Options,” on page 39).
Hardware Functional Specification
Issue Date: 01/02/06
S1D13506
X25B-A-001-10
Page 66
Epson Research and Development
Vancouver Design Center
7.1.10 Toshiba Interface Timing (e.g. TX39xx)
TDCLKOUT
t3
t2
DCLKOUT
t4
t5
ADDR[12:0]
t6
t7
ALE
t8
CARDREG*
CARDxCSH*
CARDxCSL*
CARDIORD*
CARDIOWR*
WE* RD*
t9
t10
CARDxWAIT*
t11
t12
D[31:16](write)
t13
t14
t15
D[31:16](read)
Figure 7-10: Toshiba Timing
S1D13506
X25B-A-001-10
Hardware Functional Specification
Issue Date: 01/02/06
Epson Research and Development
Vancouver Design Center
Page 67
Table 7-10: Toshiba Timing
3.0V
Symbol
fDCLKOUT Clock frequency
TDCLKOUT Clock period
Parameter
Min
5.0V
Max
75
Min
Max
75
1/fDCLKOUT
1/fDCLKOUT
Units
MHz
ns
t2
Clock pulse width low
6
6
ns
t3
Clock pulse width high
6
6
ns
t4
ADDR[12:0] setup to first CLK of cycle
10
10
ns
t5
ADDR[12:0] hold from command invalid
0
0
ns
t6
ADDR[12:0] setup to falling edge ALE
10
10
ns
t7
ADDR[12:0] hold from falling edge ALE
5
5
ns
t8
CARDREG* hold from command invalid
0
0
ns
t9
Falling edge of chip select to CARDxWAIT* driven
2
14
1
9
ns
t10
Command invalid to CARDxWAIT* tri-state
2
13
2
12
ns
t11
D[31:16] valid to first CLK of cycle (write cycle)
10
10
t12
D[31:16] hold from rising edge of CARDxWAIT*
0
0
t13
Chip select to D[31:16] driven (read cycle)
4
3
ns
t14
D[31:16] setup to rising edge CARDxWAIT* (read cycle)
0
0
ns
t15
Command invalid to D[31:16] tri-state (read cycle)
7
30
4
ns
16
ns
Note
If BUSCLK exceeds 37.5MHz, it must be divided by 2 using MD12 (see Table 5-6:,
“Summary of Power-On/Reset Options,” on page 39).
Hardware Functional Specification
Issue Date: 01/02/06
S1D13506
X25B-A-001-10
Page 68
Epson Research and Development
Vancouver Design Center
7.2 Clock Timing
7.2.1 Input Clocks
t
t
PWH
PWL
90%
V
IH
VIL
10%
t
tr
T
f
OSC
Figure 7-11: CLKI Clock Input Requirements
Table 7-11: Clock Input Requirements for CLKI/CLKI2/BUSCLK divided down internally
Symbol
fOSC
TOSC
tPWH
tPWL
tf
tr
Parameter
Input Clock Frequency
Input Clock Period
Input Clock Pulse Width High
Input Clock Pulse Width Low
Input Clock Fall Time (10% - 90%)
Input Clock Rise Time (10% - 90%)
Min
Max
80
1/fOSC
5.6
5.6
5
5
Units
MHz
ns
ns
ns
ns
ns
Table 7-12: Clock Input Requirements for CLKI or BUSCLK if used directly for MCLK1
Symbol
Parameter
Min
Max
Units
40
MHz
fOSC
Input Clock Frequency
TOSC
Input Clock Period
1/fOSC
ns
Input Clock Pulse Width High
11.31
ns
Input Clock Pulse Width Low
11.31
ns
tPWH
tPWL
tf
Input Clock Fall Time (10% - 90%)
5
ns
tr
Input Clock Rise Time (10% - 90%)
5
ns
Note
1. MCLK must have a duty cycle of 50% ± 5%.
S1D13506
X25B-A-001-10
Hardware Functional Specification
Issue Date: 01/02/06
Epson Research and Development
Vancouver Design Center
Page 69
7.2.2 Internal Clocks
Table 7-13: Internal Clock Requirements
1.
Symbol
Parameter
Min
Max
Units
fMCLK
Memory Clock Frequency
0
40
MHz
fLCD PCLK
LCD Pixel Clock Frequency
0
40
MHz
fCRT/TV PCLK
CRT/TV Pixel Clock Frequency
0
Note 1
MHz
fMediaPlug Clock
MediaPlug Clock Frequency
0
10
MHz
The maximum CRT pixel clock is 40MHz.
The TV pixel clock for NTSC output is fixed at 14.318MHz.
The TV pixel clock for PAL output is fixed at 17.734MHz.
Hardware Functional Specification
Issue Date: 01/02/06
S1D13506
X25B-A-001-10
Page 70
Epson Research and Development
Vancouver Design Center
7.3 Memory Interface Timing
7.3.1 EDO-DRAM Read, Write, Read-Write Timing
t1
Memory
Clock
t2
RAS#
t3
t5
t4
t6
t1
t7
CAS#
t8
MA
t9
t10
t11 t10 t11
C1
R
C2
C3
t12
t13
WE# (read)
t15
t14
MD (read)
d1
t17
t16
d2
d3
t19
t18
WE#(write)
t20 t21
MD(write)
d1
d2
t22
d3
Figure 7-12: EDO-DRAM Page Mode Timing
Memory
Clock
t1
RAS#
t3
t5
t4
t6
t1
t7
CAS#
t8
MA
t9
t10 t11
C1
R
C2
C3
t12
C2
C1
t23
C3
t19
t24
WE#
t15
t14
MD(Read)
d1
t25
d2
t26
d3
t20 t21
MD(Write)
d1
t22
d2
d3
Figure 7-13: EDO-DRAM Read-Write Timing
S1D13506
X25B-A-001-10
Hardware Functional Specification
Issue Date: 01/02/06
Epson Research and Development
Vancouver Design Center
Page 71
Table 7-14: EDO-DRAM Read, Write, Read-Write Timing
Symbol
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
t12
t13
t14
t15
t16
t17
t18
t19
t20
t21
t22
t23
t24
t25
t26
Parameter
Memory clock period
Random read or write cycle time (REG[02Bh] bits 1-0 = 00)
Random read or write cycle time (REG[02Bh] bits 1-0 = 01)
Random read or write cycle time (REG[02Bh] bits 1-0 = 10)
RAS# precharge time (REG[02Ah] bits 1-0 = 00)
RAS# precharge time (REG[02Ah] bits 1-0 = 01)
RAS# precharge time (REG[02Ah] bits 1-0 = 10)
RAS# to CAS# delay time (REG[02Ah] bit 4 = 0 and bits 1-0
= 00 or 10)
RAS# to CAS# delay time (REG[02Ah] bit 4 = 1 and bits 1-0
= 00 or 10)
RAS# to CAS# delay time (REG[02Ah] bits 1-0 = 01)
CAS# precharge time
CAS# pulse width
RAS# hold time
Row address setup time (REG[02Ah] bits 1-0 = 00
Row address setup time (REG[02Ah] bits 1-0 = 01)
Row address setup time (REG[02Ah] bits 1-0 = 10)
Row address hold time (REG[02Ah] bits 1-0 = 00 or 10)
Row address hold time (REG[02Ah] bits 1-0 = 01)
Column address setup time
Column address hold time
Read Command setup (REG[02Ah] bit 4 = 0 and bits 1-0 =
00)
Read Command setup (REG[02Ah] bit 4 = 1 and bits 1-0 =
10)
Read Command setup (all other REG[02Ah] values)
Read Command hold (REG[02Ah] bit 4 = 0 and bits 1-0 = 00)
Read Command hold (REG[02Ah] bit 4 = 1 and bits 1-0 = 10)
Read Command hold (all other REG[02Ah] values)
Read data setup referenced from CAS#
Read data hold referenced from CAS#
Last read data setup referenced from RAS#
Bus turn-off from RAS#
Write command setup time
Write command hold time
Write Data setup time
Write Data hold time
MD tri-state
CAS# to WE# active during read-write cycle
Write command setup during read-write cycle
Last read data setup referenced from WE# during read-write
cycle
Bus tri-state from WE# during read-write cycle
Hardware Functional Specification
Issue Date: 01/02/06
Min
25
5 t1
4 t1
3 t1
2 t1
1.45 t1
t1
Max
Units
ns
ns
ns
ns
ns
ns
ns
2 t1 - 3
2 t1
ns
t1 - 3
t1
ns
1.45 t1 - 3
0.45 t1
0.45 t1 - 1
t1
2.45 t1 - 3
2 t1 - 3
1.45 t1 - 3
0.45 t1 - 1
t1 - 3
0.45 t1 - 3
0.45 t1 - 1
1.55 t1
ns
ns
ns
ns
ns
ns
ns
ns
ns
4.45 t1 - 1
ns
2.45 t1 - 1
3.45 t1 - 1
3.45 t1 - 1
1.45 t1 - 1
2.45 t1 - 1
4
2
3
2
0.45 t1 - 1
0.45 t1 - 1
0.45 t1 - 4
0.45 t1
0.45 t1
t1
1.45 t1 - 1
ns
0.55 t1 + 19
18
0
ns
ns
ns
ns
ns
ns
ns
ns
t1 - 6
ns
S1D13506
X25B-A-001-10
Page 72
Epson Research and Development
Vancouver Design Center
7.3.2 EDO-DRAM CAS Before RAS Refresh Timing
t1
Memory
Clock
t2
t3
RAS#
t4
t5
t6
CAS#
Figure 7-14: EDO-DRAM CAS Before RAS Refresh Timing
Table 7-15: EDO-DRAM CAS Before RAS Refresh Timing
Symbol
t1
t2
t3
t4
t5
t6
Parameter
Memory clock period
RAS# precharge time (REG[02Ah] bits 1-0 = 00)
RAS# precharge time (REG[02Ah] bits 1-0 = 01)
RAS# precharge time (REG[02Ah] bits 1-0 = 10)
RAS# pulse width (REG[02Bh] bits 1-0 = 00, REG[02Ah] bits 1-0 = 00)
RAS# pulse width (REG[02Bh] bits 1-0 = 00, REG[02Ah] bits 1-0 = 01)
RAS# pulse width (REG[02Bh] bits 1-0 = 00, REG[02Ah] bits 1-0 = 10)
RAS# pulse width (REG[02Bh] bits 1-0 = 01, REG[02Ah] bits 1-0 = 00)
RAS# pulse width (REG[02Bh] bits 1-0 = 01, REG[02Ah] bits 1-0 = 01)
RAS# pulse width (REG[02Bh] bits 1-0 = 01, REG[02Ah] bits 1-0 = 10)
RAS# pulse width (REG[02Bh] bits 1-0 = 10, REG[02Ah] bits 1-0 = 00)
RAS# pulse width (REG[02Bh] bits 1-0 = 10, REG[02Ah] bits 1-0 = 01)
RAS# pulse width (REG[02Bh] bits 1-0 = 10, REG[02Ah] bits 1-0 = 10)
CAS# precharge time (REG[02Ah] bits 1-0 = 00)
CAS# precharge time (REG[02Ah] bits 1-0 = 01 or 10)
CAS# setup time (REG[02Ah] bits 1-0 = 00 or 10)
CAS# setup time (REG[02Ah] bits 1-0 = 01)
CAS# hold to RAS# (REG[02Bh] bits 1-0 = 00, REG[02Ah] bits 1-0 = 00)
CAS# hold to RAS# (REG[02Bh] bits 1-0 = 00, REG[02Ah] bits 1-0 = 01)
CAS# hold to RAS# (REG[02Bh] bits 1-0 = 00, REG[02Ah] bits 1-0 = 10)
CAS# hold to RAS# (REG[02Bh] bits 1-0 = 01, REG[02Ah] bits 1-0 = 00)
CAS# hold to RAS# (REG[02Bh] bits 1-0 = 01, REG[02Ah] bits 1-0 = 01)
CAS# hold to RAS# (REG[02Bh] bits 1-0 = 01, REG[02Ah] bits 1-0 = 10)
CAS# hold to RAS# (REG[02Bh] bits 1-0 = 10, REG[02Ah] bits 1-0 = 00)
CAS# hold to RAS# (REG[02Bh] bits 1-0 = 10, REG[02Ah] bits 1-0 = 01)
CAS# hold to RAS# (REG[02Bh] bits 1-0 = 10, REG[02Ah] bits 1-0 = 10)
S1D13506
X25B-A-001-10
Min
Max
Units
25
ns
2 t1
1.45 t1
t1
3 t1 - 7
3.45 t1 - 1
4 t1 - 7
2 t1 - 7
2.45 t1 - 1
3 t1 - 7
t1 - 7
1.45 t1 - 1
2 t1 - 7
2 t1
t1
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
0.45 t1
ns
t1 - 4
ns
2.45 t1 - 4
3 t1
3.45 t1 - 4
1.45 t1 - 4
2 t1
2.45 t1 - 4
0.45 t1 - 4
t1
1.45 t1 - 4
ns
ns
ns
ns
ns
ns
ns
ns
ns
Hardware Functional Specification
Issue Date: 01/02/06
Epson Research and Development
Vancouver Design Center
Page 73
7.3.3 EDO-DRAM Self-Refresh Timing
MCLK can be stopped
(See Note)
t1
Memory
Clock
t2
RAS#
t3
t5
t4
CAS#
Figure 7-15: EDO - DRAM Self-Refresh Timing
Note
MCLK can be stopped. For timing see Section 7.4.2, “Power Save Mode” on page 79.
Table 7-16: EDO - DRAM Self-Refresh Timing
Symbol
Parameter
Min
t1
Memory clock period
RAS# precharge time (REG[02Ah] bits 1-0 = 00)
RAS# precharge time (REG[02Ah] bits 1-0 = 01)
RAS# precharge time (REG[02Ah] bits 1-0 = 10)
RAS# to CAS# precharge time (REG[02Ah] bits 1-0 = 00)
RAS# to CAS# precharge time (REG[02Ah] bits 1-0 = 01 or 10)
CAS# precharge time (REG[02Ah] bits 1-0 = 00)
CAS# precharge time (REG[02Ah] bits 1-0 = 01 or 10)
25
ns
2 t1
1.45 t1
t1
1.45 t1
0.45 t1
2 t1
t1
ns
ns
ns
ns
ns
ns
ns
CAS# setup time (REG[02Ah] bits 1-0 = 00 or 10)
0.45 t1
ns
t1 - 4
ns
t2
t3
t4
t5
CAS# setup time (REG[02Ah] bits 1-0 = 01)
Hardware Functional Specification
Issue Date: 01/02/06
Max
Units
S1D13506
X25B-A-001-10
Page 74
Epson Research and Development
Vancouver Design Center
7.3.4 FPM-DRAM Read, Write, Read-Write Timing
t1
Memory
Clock
t2
RAS#
t5
t4
t3
t6
t1
t7
CAS#
t8
MA
t9
t11 t10 t11
t10
R
C1
C2
C3
t12
t13
WE#(read)
t14
MD(read)
d1
d2
t15
d3
t16
t17
WE#(write)
t18 t19
MD(write)
d1
t20
d2
d3
Figure 7-16: FPM-DRAM Page Mode Timing
Memory
Clock
t1
RAS#
t5
t4
t3
t6
t1
t7
CAS#
t9
t8
MA
R
t10 t11
C2
C1
C3
C1
t12
t21
C2
C3
t16
t17
t18 t19
t20
WE#
t14
MD(read)
MD(write)
d1
t15
d2
d3
d1
d2
d3
Figure 7-17: FPM-DRAM Read-Write Timing
S1D13506
X25B-A-001-10
Hardware Functional Specification
Issue Date: 01/02/06
Epson Research and Development
Vancouver Design Center
Page 75
Table 7-17: FPM-DRAM Read, Write, Read-Write Timing
Symbol
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
t12
t13
Parameter
Memory clock
Random read or write cycle time (REG[02Bh] bits 1-0 = 00)
Random read or write cycle time (REG[02Bh] bits 1-0 = 01)
Random read or write cycle time (REG[02Bh] bits 1-0 = 10)
RAS# precharge time (REG[02Ah] bits 1-0 = 00)
RAS# precharge time (REG[02Ah] bits 1-0 = 01)
RAS# precharge time (REG[02Ah] bits 1-0 = 10)
RAS# to CAS# delay time (REG[02Ah] bit 4 = 0 and bits 1-0
= 00 or 10)
RAS# to CAS# delay time (REG[02Ah] bit 4 = 1 and bits 1-0
= 00 or 10)
RAS# to CAS# delay time (REG[02Ah] bit 4 = 0 and bits 1-0
= 01)
RAS# to CAS# delay time (REG[02Ah] bit 4 = 1 and bits 1-0
= 01)
CAS# precharge time
CAS# pulse width
RAS# hold time
Row address setup time (REG[02Ah] bits 1-0 = 00
Row address setup time (REG[02Ah] bits 1-0 = 01)
Row address setup time (REG[02Ah] bits 1-0 = 10)
Row address hold time (REG[02Ah] bits 1-0 = 00 or 10)
Row address hold time (REG[02Ah] bits 1-0 = 01)
Column address set-up time
Column address hold time
Read Command setup (REG[02Ah] bit 4 = 0 and bits 1-0 =
00)
Read Command setup (REG[02Ah] bit 4 = 1 and bits 1-0 =
01 or 10)
Read Command setup (all other REG[02Ah] values)
Read Command hold (REG[02Ah] bit 4 = 0 and bits 1-0 =
00)
Read Command hold (REG[02Ah] bit 4 = 1 and bits 1-0 = 01
or 10)
Read Command hold (all other REG[02Ah] values)
Min
40
5 t1
4 t1
3 t1
2 t1
1.45 t1
t1
Max
Units
ns
ns
ns
ns
ns
ns
ns
2.45 t1 - 3
2.55 t1
ns
1.45 t1 - 3
1.55 t1
ns
2 t1 - 3
2 t1
ns
t1 - 3
t1
ns
0.45 t1
0.45 t1 - 1
0.45 t1
2 t1 - 2
1.45 t1 - 2
t1 - 2
t1 - 3
0.45 t1 - 3
0.45 t1 - 3
0.45 t1 - 1
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
4.45 t1 - 1
ns
2.45 t1 - 1
ns
3.45 t1 - 1
ns
4 t1 - 1
ns
2 t1 - 1
ns
3 t1 - 1
ns
3
3
ns
ns
t14
Read data setup referenced from CAS#
t15
Read Data turn-off from CAS#
t16
Write command setup time
0.45 t1 - 1
ns
t17
Write command hold time
0.45 t1 - 1
ns
t18
Write Data setup time
0.45 t1 - 4
ns
t19
Write Data hold time
t20
t21
MD tri-state
CAS# to WE# active during read-write cycle
0.45 t1
0.45 t1
0.45 t1
Hardware Functional Specification
Issue Date: 01/02/06
0.55 t1 + 19
ns
ns
ns
S1D13506
X25B-A-001-10
Page 76
Epson Research and Development
Vancouver Design Center
7.3.5 FPM-DRAM CAS Before RAS Refresh Timing
t1
Memory
Clock
t2
t3
RAS#
t4
t5
t6
CAS#
Figure 7-18: FPM-DRAM CAS Before RAS Refresh Timing
Table 7-18: FPM-DRAM CAS Before RAS Refresh Timing
Symbol
t1
t2
t3
t4
t5
t6
Parameter
Min
Memory clock
RAS# precharge time (REG[02Ah] bits 1-0 = 00)
RAS# precharge time (REG[02Ah] bits 1-0 = 01 or 10)
RAS# pulse width (REG[02Bh] bits 1-0 = 00,
REG[02Ah] bits 1-0 = 00)
RAS# pulse width (REG[02Bh] bits 1-0 = 00,
REG[02Ah] bits 1-0 = 01 or 10)
RAS# pulse width (REG[02Bh] bits 1-0 = 01,
REG[02Ah] bits 1-0 = 00)
RAS# pulse width (REG[02Bh] bits 1-0 = 01,
REG[02Ah] bits 1-0 = 01 or 10)
RAS# pulse width (REG[02Bh] bits 1-0 = 10,
REG[02Ah] bits 1-0 = 00)
RAS# pulse width (REG[02Bh] bits 1-0 = 10,
REG[02Ah] bits 1-0 = 01 or 10)
CAS# precharge time (REG[02Ah] bits 1-0 = 00)
CAS# precharge time (REG[02Ah] bits 1-0 = 01 or 10)
40
ns
2.45 t1
1.45 t1
ns
ns
2.45 t1 - 7
ns
3.45 t1 - 7
ns
1.45 t1 - 7
ns
2.45 t1 - 7
ns
0.45 t1 - 7
ns
1.45 t1 - 7
ns
2 t1
t1
ns
ns
0.45 t1
ns
2.45 t1 - 4
ns
3.45 t1 - 4
ns
1.45 t1 - 4
ns
2.45 t1 - 4
ns
0.45 t1 - 4
ns
1.45 t1 - 4
ns
CAS# setup time
CAS# hold to RAS# (REG[02Bh] bits 1-0 = 00,
REG[02Ah] bits 1-0 = 00)
CAS# hold to RAS# (REG[02Bh] bits 1-0 = 00,
REG[02Ah] bits 1-0 = 01 or 10)
CAS# hold to RAS# (REG[02Bh] bits 1-0 = 01,
REG[02Ah] bits 1-0 = 00)
CAS# hold to RAS# (REG[02Bh] bits 1-0 = 01,
REG[02Ah] bits 1-0 = 01 or 10)
CAS# hold to RAS# (REG[02Bh] bits 1-0 = 10,
REG[02Ah] bits 1-0 = 00)
CAS# hold to RAS# (REG[02Bh] bits 1-0 = 10,
REG[02Ah] bits 1-0 = 01 or 10)
S1D13506
X25B-A-001-10
Max
Units
Hardware Functional Specification
Issue Date: 01/02/06
Epson Research and Development
Vancouver Design Center
Page 77
7.3.6 FPM-DRAM Self-Refresh Timing
MCLK can be stopped
(See Note)
t1
Memory
Clock
t2
RAS#
t3
t4
CAS#
Figure 7-19: FPM - DRAM Self-Refresh Timing
Note
MCLK can be stopped. For timing see Section 7.4.2, “Power Save Mode” on page 79.
Table 7-19: FPM-DRAM Self-Refresh Timing
Symbol
t1
t2
t3
t4
Parameter
Min
Max
Units
Memory clock
RAS# precharge time (REG[02Ah] bits 1-0 = 00)
RAS# precharge time (REG[02Ah] bits 1-0 = 01 or 10)
RAS# to CAS# precharge time (REG[02Ah] bits 1-0 = 00)
RAS# to CAS# precharge time (REG[02Ah] bits 1-0 = 01 or 10)
40
ns
2.45 t1
1.45 t1
2 t1
t1
ns
ns
ns
ns
CAS# setup time
0.45 t1
ns
Hardware Functional Specification
Issue Date: 01/02/06
S1D13506
X25B-A-001-10
Page 78
Epson Research and Development
Vancouver Design Center
7.4 Power Sequencing
7.4.1 LCD Power Sequencing
#RESET
LCD Enable Bit
(REG[1FCh] bit 0)
t1
t2
FPFRAME
t3
t4
FPLINE, FPSHIFT
FPDATA, DRDY
LCD Power Save
Status Bit
(REG[1F1h] bit 1)
t4
Figure 7-20: LCD Panel Power-off/Power-on Timing
Table 7-20: LCD Panel Power-off/Power-on Timing
Symbol
t1
t2
t3
t4
1.
Parameter
LCD Enable Bit high to FPFRAME active
FPFRAME inactive to LCD Power Save Status bit high
LCD Enable Bit high to FPLINE, FPSHIFT, FPDATA, DRDY active
LCD Enable Bit low to FPLINE, FPSHIFT, FPDATA, DRDY active and
LCD Power Save Status bit high
t4
Min
Max
TFPFRAME
5TFPFRAME
3TFPLINE
Units
ns
ns
ns
note 1
ns
= 130TFPFRAME for dual panels
= 65TFPFRAME for single panels
Note
Where TFPFRAME is the period of FPFRAME and TFPLINE is the period of FPLINE.
S1D13506
X25B-A-001-10
Hardware Functional Specification
Issue Date: 01/02/06
Epson Research and Development
Vancouver Design Center
Page 79
7.4.2 Power Save Mode
Power Save
Mode Enable Bit
(REG[1F0h] bit 0)
t1
t2
FPFRAME
t3
FPLINE, FPSHIFT
FPDATA, DRDY
t4
t6
t5
LCD Power Save
Status Bit
(REG[1F1h] bit 1)
t8
t7
Memory Controller
Power Save Status Bit
(REG[1F1h] bit 0)
allowed
Memory Access
not allowed
t9
allowed
Figure 7-21: Power Save Mode Timing
Note
Memory accesses cannot be performed after a Power Save Mode has been initiated.
Note
The Memory Controller Power Save Status Bit will go high only if the Refresh Select
Bits (REG[021h] bits 7-6) are set to Self-Refresh or No Refresh.
Hardware Functional Specification
Issue Date: 01/02/06
S1D13506
X25B-A-001-10
Page 80
Epson Research and Development
Vancouver Design Center
Table 7-21: Power Save Mode Timing
Symbol
t1
Power Save Mode Enable Bit high to FPFRAME inactive
t2
Power Save Mode Enable Bit low to FPFRAME active
Power Save Mode Enable Bit high to FPLINE, FPSHIFT, FPDATA,
DRDY inactive
Power Save Mode Enable Bit low to FPLINE, FPSHIFT, FPDATA, DRDY
active
Power Save Mode Enable Bit high to LCD Power Save Status Bit high
Power Save Mode Enable Bit low to LCD Power Save Status Bit low
Power Save Mode Enable Bit high to Memory Controller Power Save
Status Bit high (self-refresh or no refresh selected)
Power Save Mode Enable Bit low to Memory Controller Power Save
Status Bit low (self-refresh or no refresh selected)
Memory Controller Power Save Status Bit low to the earliest time where
memory access is allowed (self-refresh or no refresh selected)
t3
t4
t5
t6
t7
t8
t9
1.
Parameter
Min
Max
Units
TFPFRAME +
ns
TFPLINE
3TFPLINE
ns
129TFPFRAME +
ns
TFPLINE
128TFPFRAME
TFPFRAME
ns
129TFPRAME
TPCLK
ns
ns
note 1
ns
12TMCLK
ns
8TMCLK
ns
t14max = (1 DRAM refresh clock period) + 12 MCLK periods
Note
Where TFPFRAME is the period of FPFRAME, TFPLINE is the period of FPLINE,
TPCLK is the period of the pixel clock, and TMCLK is the period of the memory clock.
Note
The DRAM refresh clock period is programmed using REG[021h].
S1D13506
X25B-A-001-10
Hardware Functional Specification
Issue Date: 01/02/06
Epson Research and Development
Vancouver Design Center
Page 81
7.5 Display Interface
7.5.1 Single Monochrome 4-Bit Panel Timing
VDP
VNDP
FPFRAME
FPLINE
DRDY (MOD)
LINE1
FPDAT[7:4]
LINE2
LINE3
LINE4
LINE239 LINE240
LINE1
LINE2
FPLINE
DRDY (MOD)
HDP
HNDP
FPSHIFT
FPDAT7
1-1
1-5
1-317
FPDAT6
1-2
1-6
1-318
FPDAT5
1-3
1-7
1-319
FPDAT4
1-4
1-8
1-320
* Diagram drawn with 2 FPLINE vertical blank period
Example timing for a 320x240 panel
Figure 7-22: Single Monochrome 4-Bit Panel Timing
VDP
VNDP
HDP
HNDP
= Vertical Display Period
= Vertical Non-Display Period
= Horizontal Display Period
= Horizontal Non-Display Period
Hardware Functional Specification
Issue Date: 01/02/06
= (REG[039h] bits [1:0], REG[038h] bits [7:0]) + 1
= (REG[03Ah] bits [5:0]) + 1
= ((REG[032h] bits [6:0]) + 1) × 8 Ts
= ((REG[034h] bits [4:0]) + 1) × 8 Ts
S1D13506
X25B-A-001-10
Page 82
Epson Research and Development
Vancouver Design Center
t1
Sync Timing
t2
FPFRAME
t4
t3
FPLINE
t5
DRDY (MOD)
Data Timing
FPLINE
t6
t7
t9
t8
t10
t11
t12
FPSHIFT
t13
FPDAT[7:4]
t14
1
2
Figure 7-23: Single Monochrome 4-Bit Panel A.C. Timing
S1D13506
X25B-A-001-10
Hardware Functional Specification
Issue Date: 01/02/06
Epson Research and Development
Vancouver Design Center
Page 83
Table 7-22: Single Monochrome 4-Bit Panel A.C. Timing
Symbol
t1
t2
t3
t4
t5
t6a
t6b
t7a
t7b
t8
t9a
t9b
t10a
t10b
t11
t12
t13
t14
1.
Ts
2.
3.
4.
5.
t1
t4
t5
t6
6.
t9
Parameter
FPFRAME setup to FPLINE falling edge
FPFRAME hold from FPLINE falling edge
FPLINE pulse width
FPLINE period
DRDY (MOD) delay from FPLINE falling edge
FPSHIFT falling edge to FPLINE rising edge, 4 bpp or 8 bpp
FPSHIFT falling edge to FPLINE rising edge, 15/16 bpp
FPLINE falling edge to FPSHIFT falling edge, 4 bpp or 8 bpp
FPLINE falling edge to FPSHIFT falling edge, 15/16 bpp
FPSHIFT period
FPSHIFT falling edge to FPLINE falling edge, 4 bpp or 8 bpp
FPSHIFT falling edge to FPLINE falling edge, 15/16 bpp
FPLINE falling edge to FPSHIFT rising edge, 4 bpp or 8 bpp
FPLINE falling edge to FPSHIFT rising edge, 15/16 bpp
FPSHIFT pulse width high
FPSHIFT pulse width low
FPDAT[7:4] setup to FPSHIFT falling edge
FPDAT[7:4] hold to FPSHIFT falling edge
Min.
Setting
28
40
3
5
7
16
18
Typical
note 2
12
11
note 3
note 4
note 5
note 5
20
18
4
note 6
note 6
18
16
2
2
2
2
Max.
Setting
1268
1280
259
229
231
240
242
Units
Ts (note 1)
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
= LCD pixel clock period. LCD pixel clock frequency is LCD pixel clock source divided by 1, 2, 3 or 4
(see REG[014h]).
= t4 - 12
= [((REG[032h] bits [6:0]) + 1) × 8 + ((REG[034h] bits [4:0]) + 1) × 8]
= [((REG[034h] bits [4:0]) + 1) × 8 + 3]
= [((REG[034h] bits [4:0]) + 1) × 8 - 27] for 4 bpp or 8 bpp color depth
= [((REG[034h] bits [4:0]) + 1) × 8 - 25] for 15/16 bpp color depth
= [((REG[034h] bits [4:0]) + 1) × 8 - 16] for 4 bpp or 8 bpp color depth
= [((REG[034h] bits [4:0]) + 1) × 8 - 14] for 15/16 bpp color depth
Hardware Functional Specification
Issue Date: 01/02/06
S1D13506
X25B-A-001-10
Page 84
Epson Research and Development
Vancouver Design Center
7.5.2 Single Monochrome 8-Bit Panel Timing
VDP
VNDP
FPFRAME
FPLINE
DRDY (MOD)
LINE1
FPDAT[7:0]
LINE2
LINE3
LINE4
LINE479 LINE480
LINE1
LINE2
FPLINE
DRDY (MOD)
HDP
HNDP
FPSHIFT
FPDAT7
1-1
1-9
1-633
FPDAT6
1-2
1-10
1-634
FPDAT5
1-3
1-11
1-635
FPDAT4
1-4
1-12
1-636
FPDAT3
1-5
1-13
1-637
FPDAT2
1-6
1-14
1-638
FPDAT1
1-7
1-15
1-639
FPDAT0
1-8
1-16
1-640
* Diagram drawn with 2 FPLINE vertical blank period
Example timing for a 640x480 panel
Figure 7-24: Single Monochrome 8-Bit Panel Timing
VDP
VNDP
HDP
HNDP
= Vertical Display Period
= Vertical Non-Display Period
= Horizontal Display Period
= Horizontal Non-Display Period
S1D13506
X25B-A-001-10
= (REG[039h] bits [1:0], REG[038h] bits [7:0]) + 1
= (REG[03Ah] bits [5:0]) + 1
= ((REG[032h] bits [6:0]) + 1) × 8 Ts
= ((REG[034h] bits [4:0]) + 1) × 8 Ts
Hardware Functional Specification
Issue Date: 01/02/06
Epson Research and Development
Vancouver Design Center
Page 85
t1
t2
Sync Timing
FPFRAME
t4
t3
FPLINE
t5
DRDY (MOD)
Data Timing
FPLINE
t6
t7
t9
t8
t10
t11
t12
FPSHIFT
t13
FPDAT[7:0]
t14
1
2
Figure 7-25: Single Monochrome 8-Bit Panel A.C. Timing
Hardware Functional Specification
Issue Date: 01/02/06
S1D13506
X25B-A-001-10
Page 86
Epson Research and Development
Vancouver Design Center
Table 7-23: Single Monochrome 8-Bit Panel A.C. Timing
Symbol
t1
t2
t3
t4
t5
t6a
t6b
t7a
t7b
t8
t9a
t9b
t10a
t10b
t11
t12
t13
t14
1.
Ts
2.
3.
4.
5.
t1
t4
t5
t6
6.
t9
Parameter
FPFRAME setup to FPLINE falling edge
FPFRAME hold from FPLINE falling edge
FPLINE pulse width
FPLINE period
DRDY (MOD) delay from FPLINE falling edge
FPSHIFT falling edge to FPLINE rising edge, 4 bpp or 8 bpp
FPSHIFT falling edge to FPLINE rising edge, 15/16 bpp
FPLINE falling edge to FPSHIFT falling edge, 4 bpp or 8 bpp
FPLINE falling edge to FPSHIFT falling edge, 15/16 bpp
FPSHIFT period
FPSHIFT falling edge to FPLINE falling edge, 4 bpp or 8 bpp
FPSHIFT falling edge to FPLINE falling edge, 15/16 bpp
FPLINE falling edge to FPSHIFT rising edge, 4 bpp or 8 bpp
FPLINE falling edge to FPSHIFT rising edge, 15/16 bpp
FPSHIFT pulse width high
FPSHIFT pulse width low
FPDAT[7:0] setup to FPSHIFT falling edge
FPDAT[7:0] hold to FPSHIFT falling edge
Min.
Setting
28
40
3
7
9
18
20
Typical
note 2
12
11
note 3
note 4
note 5
note 5
22
20
8
note 6
note 6
18
16
4
4
4
4
Max.
Setting
1268
1280
259
231
233
242
244
Units
Ts (note 1)
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
= LCD pixel clock period. LCD pixel clock frequency is LCD pixel clock source divided by 1, 2, 3 or 4
(see REG[014h]).
= t4 - 12
= [((REG[032h] bits [6:0]) + 1) × 8 + ((REG[034h] bits [4:0]) + 1) × 8]
= [((REG[034h] bits [4:0]) + 1) × 8 + 3]
= [((REG[034h] bits [4:0]) + 1) × 8 - 25] for 4 bpp or 8 bpp color depth
= [((REG[034h] bits [4:0]) + 1) × 8 - 23] for 15/16 bpp color depth
= [((REG[034h] bits [4:0]) + 1) × 8 - 14] for 4 bpp or 8 bpp color depth
= [((REG[034h] bits [4:0]) + 1) × 8 - 12] for 15/16 bpp color depth
S1D13506
X25B-A-001-10
Hardware Functional Specification
Issue Date: 01/02/06
Epson Research and Development
Vancouver Design Center
Page 87
7.5.3 Single Color 4-Bit Panel Timing
VNDP
VDP
FPFRAME
FPLINE
DRDY (MOD)
LINE1
FPDAT[7:4]
LINE2
LINE3
LINE4
LINE479 LINE480
LINE1
LINE2
FPLINE
DRDY (MOD)
HDP
HNDP
FPSHIFT
FPDAT7
FPDAT6
FPDAT5
FPDAT4
1-R1
1-G2
1-B3
1-B319
1-G1
1-B2
1-R4
1-R320
1-B1
1-R3
1-G4
1-G320
1-R2
1-G3
1-B4
1-B320
* Diagram drawn with 2 FPLINE vertical blank period
Example timing for a 640x480 panel
Figure 7-26: Single Color 4-Bit Panel Timing
VDP
VNDP
HDP
HNDP
= Vertical Display Period
= Vertical Non-Display Period
= Horizontal Display Period
= Horizontal Non-Display Period
Hardware Functional Specification
Issue Date: 01/02/06
= (REG[039h] bits [1:0], REG[038h] bits [7:0]) + 1
= (REG[03Ah] bits [5:0]) + 1
= ((REG[032h] bits [6:0]) + 1) × 8 Ts
= ((REG[034h] bits [4:0]) + 1) × 8 Ts
S1D13506
X25B-A-001-10
Page 88
Epson Research and Development
Vancouver Design Center
t1
t2
Sync Timing
FPFRAME
t4
t3
FPLINE
t5
DRDY (MOD)
Data Timing
FPLINE
t6
t7
t9
t8
t10
t11
t12
FPSHIFT
t13
FPDAT[7:4]
t14
1
2
Figure 7-27: Single Color 4-Bit Panel A.C. Timing
S1D13506
X25B-A-001-10
Hardware Functional Specification
Issue Date: 01/02/06
Epson Research and Development
Vancouver Design Center
Page 89
Table 7-24: Single Color 4-Bit Panel A.C. Timing
Symbol
t1
t2
t3
t4
t5
t6a
t6b
t7a
t7b
t8
t9a
t9b
t10a
t10b
t11
t12
t13
t14
1.
Ts
2.
3.
4.
5.
t1
t4
t5
t6
6.
t9
Parameter
FPFRAME setup to FPLINE falling edge
FPFRAME hold from FPLINE falling edge
FPLINE pulse width
FPLINE period
DRDY (MOD) delay from FPLINE falling edge
FPSHIFT falling edge to FPLINE rising edge, 4 bpp or 8 bpp
FPSHIFT falling edge to FPLINE rising edge, 15/16 bpp
FPLINE falling edge to FPSHIFT falling edge, 4 bpp or 8 bpp
FPLINE falling edge to FPSHIFT falling edge, 15/16 bpp
FPSHIFT period
FPSHIFT falling edge to FPLINE falling edge, 4 bpp or 8 bpp
FPSHIFT falling edge to FPLINE falling edge, 15/16 bpp
FPLINE falling edge to FPSHIFT rising edge, 4 bpp or 8 bpp
FPLINE falling edge to FPSHIFT rising edge, 15/16 bpp
FPSHIFT pulse width high
FPSHIFT pulse width low
FPDAT[7:4] setup to FPSHIFT falling edge
FPDAT[7:4] hold from FPSHIFT falling edge
Min.
Setting
28
40
3
4.5
6.5
15.5
17.5
Typical
note 2
12
11
note 3
note 4
note 5
note 5
19.5
17.5
1
note 6
note 6
19
17
0.5
0.5
0.5
0.5
Max.
Setting
1268
1280
259
228.5
230.5
239.5
241.5
Units
Ts (note 1)
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
= LCD pixel clock period. LCD pixel clock frequency is LCD pixel clock source divided by 1, 2, 3 or 4
(see REG[014h]).
= t4 - 12
= [((REG[032h] bits [6:0]) + 1) × 8 + ((REG[034h] bits [4:0]) + 1) × 8]
= [((REG[034h] bits [4:0]) + 1) × 8 + 3]
= [((REG[034h] bits [4:0]) + 1) × 8 - 27.5] for 4 bpp or 8 bpp color depth
= [((REG[034h] bits [4:0]) + 1) × 8 - 25.5] for 15/16 bpp color depth
= [((REG[034h] bits [4:0]) + 1) × 8 - 16.5] for 4 bpp or 8 bpp color depth
= [((REG[034h] bits [4:0]) + 1) × 8 - 14.5] for 15/16 bpp color depth
Hardware Functional Specification
Issue Date: 01/02/06
S1D13506
X25B-A-001-10
Page 90
Epson Research and Development
Vancouver Design Center
7.5.4 Single Color 8-Bit Panel Timing (Format 1)
VNDP
VDP
FPFRAME
FPLINE
FPDAT[7:0]
LINE1
LINE2
LINE3
LINE4
LINE479
LINE480
LINE1
LINE2
FPLINE
HDP
HNDP
FPSHIFT
FPSHIFT2
FPDAT7
1-R1
1-G1
1-G6
1-B6
1-B11
1-R12
1-R636
FPDAT6
1-B1
1-R2
1-R7
1-G7
1-G12
1-B12
1-B636
FPDAT5
FPDAT4
1-G2
1-B2
1-B7
1-R8
1-R13
1-G13
1-G637
1-R3
1-G3
1-G8
1-B8
1-B13
1-R14
1-R638
FPDAT3
1-B3
1-R4
1-R9
1-G9
1-G14
1-B14
1-B638
FPDAT2
1-G4
1-B4
1-B9
1-R10
1-R15
1-G15
1-G639
FPDAT1
1-R5
1-G5
1-G10
1-B10
1-B15
1-R16
1-R640
FPDAT0
1-B5
1-R6
1-R11
1-G11
1-G16
1-B16
1-B640
* Diagram drawn with 2 FPLINE vertical blank period
Example timing for a 640x480 panel
Figure 7-28: Single Color 8-Bit Panel Timing (Format 1)
VDP
VNDP
HDP
HNDP
= Vertical Display Period
= Vertical Non-Display Period
= Horizontal Display Period
= Horizontal Non-Display Period
S1D13506
X25B-A-001-10
= (REG[039h] bits [1:0], REG[038h] bits [7:0]) + 1
= (REG[03Ah] bits [5:0]) + 1
= ((REG[032h] bits [6:0]) + 1) × 8 Ts
= ((REG[034h] bits [4:0]) + 1) × 8 Ts
Hardware Functional Specification
Issue Date: 01/02/06
Epson Research and Development
Vancouver Design Center
Page 91
t1
t2
Sync Timing
FPFRAME
t4
t3
FPLINE
Data Timing
FPLINE
t5
t6
t7
t9
t8
t11
t12
t13
FPSHIFT
t10
FPSHIFT2
t14
FPDAT[7:0]
t15
1
2
Figure 7-29: Single Color 8-Bit Panel A.C. Timing (Format 1)
Hardware Functional Specification
Issue Date: 01/02/06
S1D13506
X25B-A-001-10
Page 92
Epson Research and Development
Vancouver Design Center
Table 7-25: Single Color 8-Bit Panel A.C. Timing (Format 1)
Symbol
t1
t2
t3
t4
t5a
t5b
t6a
t6b
t7a
t7b
t8
t9a
t9b
t10a
t10b
t11a
t11b
t12
t13
t14
t15
1.
Ts
2.
3.
4.
t1
t4
t5
5.
t6
6.
t9
7.
t10
Max.
Min.
Units
Typical
Setting
Setting
FPFRAME setup to FPLINE falling edge
28
note 2
1268 Ts (note 1)
FPFRAME hold from FPLINE falling edge
12
Ts
FPLINE pulse width
11
Ts
FPLINE period
40
note 3
1280
Ts
FPSHIFT2 falling edge to FPLINE rising edge, 4 bpp or 8 bpp
5
note 4
229
Ts
FPSHIFT2 falling edge to FPLINE rising edge, 15/16 bpp
7
note 4
231
Ts
FPSHIFT falling edge to FPLINE rising edge, 4 bpp or 8 bpp
3
note 5
227
Ts
FPSHIFT falling edge to FPLINE rising edge, 15/16 bpp
5
note 5
229
Ts
FPLINE falling edge to FPSHIFT2 rising, FPSHIFT falling edge, 4/8 bpp
20
Ts
FPLINE falling edge to FPSHIFT2 rising, FPSHIFT falling edge, 15/16 bpp
18
Ts
FPSHIFT2, FPSHIFT period
4
Ts
FPSHIFT falling edge to FPLINE falling edge, 4 bpp or 8 bpp
14
note 6
238
Ts
FPSHIFT falling edge to FPLINE falling edge, 15/16 bpp
16
note 6
240
Ts
FPSHIFT2 falling edge to FPLINE falling edge, 4 bpp or 8 bpp
16
note 7
240
Ts
FPSHIFT2 falling edge to FPLINE falling edge, 15/16 bpp
18
note 7
242
Ts
FPLINE falling edge to FPSHIFT rising edge, 4 bpp or 8 bpp
18
Ts
FPLINE falling edge to FPSHIFT rising edge, 15/16 bpp
16
Ts
FPSHIFT2, FPSHIFT pulse width high
2
Ts
FPSHIFT2, FPSHIFT pulse width low
2
Ts
FPDAT[7:0] setup to FPSHIFT2 rising, FPSHIFT falling edge
1
Ts
FPDAT[7:0] hold from FPSHIFT2 rising, FPSHIFT falling edge
1
Ts
S1D13506
X25B-A-001-10
Parameter
= LCD pixel clock period. LCD pixel clock frequency is LCD pixel clock source divided by 1, 2, 3 or 4
(see REG[014h]).
= t4 - 12
= [((REG[032h] bits [6:0]) + 1) × 8 + ((REG[034h] bits [4:0]) + 1) × 8]
= [((REG[034h] bits [4:0]) + 1) × 8 - 27] for 4 bpp or 8 bpp color depth
= [((REG[034h] bits [4:0]) + 1) × 8 - 25] for 15/16 bpp color depth
= [((REG[034h] bits [4:0]) + 1) × 8 - 29] for 4 bpp or 8 bpp color depth
= [((REG[034h] bits [4:0]) + 1) × 8 - 27] for 15/16 bpp color depth
= [((REG[034h] bits [4:0]) + 1) × 8 - 18] for 4 bpp or 8 bpp color depth
= [((REG[034h] bits [4:0]) + 1) × 8 - 16] for 15/16 bpp color depth
= [((REG[034h] bits [4:0]) + 1) × 8 - 16] for 4 bpp or 8 bpp color depth
= [((REG[034h] bits [4:0]) + 1) × 8 - 14] for 15/16 bpp color depth
Hardware Functional Specification
Issue Date: 01/02/06
Epson Research and Development
Vancouver Design Center
Page 93
7.5.5 Single Color 8-Bit Panel Timing (Format 2)
VDP
VNDP
FPFRAME
FPLINE
DRDY (MOD)
LINE1
FPDAT[7:0]
LINE2
LINE3
LINE4
LINE479 LINE480
LINE1
LINE2
FPLINE
DRDY (MOD)
HDP
HNDP
FPSHIFT
FPDAT7
1-R1
1-B3
1-G6
1-G638
FPDAT6
1-G1
1-R4
1-B6
1-B638
FPDAT5
1-B1
1-G4
1-R7
1-R639
FPDAT4
1-R2
1-B4
1-G7
1-G639
FPDAT3
1-G2
1-R5
1-B7
1-B639
FPDAT2
1-B2
1-G5
1-R8
1-R640
FPDAT1
1-R3
1-B5
1-G8
1-G640
FPDAT0
1-G3
1-R6
1-B8
1-B640
* Diagram drawn with 2 FPLINE vertical blank period
Example timing for a 640x480 panel
Figure 7-30: Single Color 8-Bit Panel Timing (Format 2)
VDP
VNDP
HDP
HNDP
= Vertical Display Period
= Vertical Non-Display Period
= Horizontal Display Period
= Horizontal Non-Display Period
Hardware Functional Specification
Issue Date: 01/02/06
= (REG[039h] bits [1:0], REG[038h] bits [7:0]) + 1
= (REG[03Ah] bits [5:0]) + 1
= ((REG[032h] bits [6:0]) + 1) × 8 Ts
= ((REG[034h] bits [4:0]) + 1) × 8 Ts
S1D13506
X25B-A-001-10
Page 94
Epson Research and Development
Vancouver Design Center
t1
Sync Timing
t2
FPFRAME
t4
t3
FPLINE
t5
DRDY (MOD)
Data Timing
FPLINE
t6
t7
t9
t8
t10
t11
t12
FPSHIFT
t13
FPDAT[7:0]
t14
1
2
Figure 7-31: Single Color 8-Bit Panel A.C. Timing (Format 2)
S1D13506
X25B-A-001-10
Hardware Functional Specification
Issue Date: 01/02/06
Epson Research and Development
Vancouver Design Center
Page 95
Table 7-26: Single Color 8-Bit Panel A.C. Timing (Format 2)
Symbol
t1
t2
t3
t4
t5
t6a
t6b
t7a
t7b
t8
t9a
t9b
t10a
t10b
t11
t12
t13
t14
1.
Ts
2.
3.
4.
5.
t1
t4
t5
t6
6.
t9
Parameter
FPFRAME setup to FPLINE falling edge
FPFRAME hold from FPLINE falling edge
FPLINE pulse width
FPLINE period
DRDY (MOD) delay from FPLINE falling edge
FPSHIFT falling edge to FPLINE rising edge, 4 bpp or 8 bpp
FPSHIFT falling edge to FPLINE rising edge, 15/16 bpp
FPLINE falling edge to FPSHIFT falling edge, 4 bpp or 8 bpp
FPLINE falling edge to FPSHIFT falling edge, 15/16 bpp
FPSHIFT period
FPSHIFT falling edge to FPLINE falling edge, 4 bpp or 8 bpp
FPSHIFT falling edge to FPLINE falling edge, 15/16 bpp
FPLINE falling edge to FPSHIFT rising edge, 4 bpp or 8 bpp
FPLINE falling edge to FPSHIFT rising edge, 15/16 bpp
FPSHIFT pulse width high
FPSHIFT pulse width low
FPDAT[7:0] setup to FPSHIFT falling edge
FPDAT[7:0] hold to FPSHIFT falling edge
Min.
Setting
28
40
3
4
6
15
17
Typical
note 2
12
11
note 3
note 4
note 5
note 5
20
18
2
note 6
note 6
18
16
1
1
1
1
Max.
Setting
1268
1280
259
228
230
239
241
Units
Ts (note 1)
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
= LCD pixel clock period. LCD pixel clock frequency is LCD pixel clock source divided by 1, 2, 3 or 4
(see REG[014h]).
= t4 - 12
= [((REG[032h] bits [6:0]) + 1) × 8 + ((REG[034h] bits [4:0]) + 1) × 8]
= [((REG[034h] bits [4:0]) + 1) × 8 + 3]
= [((REG[034h] bits [4:0]) + 1) × 8 - 28] for 4 bpp or 8 bpp color depth
= [((REG[034h] bits [4:0]) + 1) × 8 - 26] for 15/16 bpp color depth
= [((REG[034h] bits [4:0]) + 1) × 8 - 17] for 4 bpp or 8 bpp color depth
= [((REG[034h] bits [4:0]) + 1) × 8 - 15] for 15/16 bpp color depth
Hardware Functional Specification
Issue Date: 01/02/06
S1D13506
X25B-A-001-10
Page 96
Epson Research and Development
Vancouver Design Center
7.5.6 Single Color 16-Bit Panel Timing
VDP
VNDP
FPFRAME
FPLINE
DRDY (MOD)
FPDAT[15:0]
LINE1
LINE2
LINE3
LINE4
LINE479
LINE480
LINE1
LINE2
FPLINE
DRDY (MOD)
HDP
HNDP
FPSHIFT
FPDAT15
1-R1
1-G6
1-B11
1-G635
FPDAT14
1-B1
1-R7
1-G12
1-G636
FPDAT13
1-G2
1-B7
1-R13
1-R637
FPDAT12
1-R3
1-G8
1-B13
1-B637
FPDAT11
1-B3
1-R9
1-G14
1-G638
FPDAT10
1-G4
1-B9
1-R15
1-R639
FPDAT9
1-R5
1-G10
1-B15
1-B639
FPDAT8
1-B5
1-R11
1-G16
1-G640
FPDAT7
1-G1
1-B6
1-R12
1-R636
FPDAT6
1-R2
1-G7
1-B12
1-B636
FPDAT5
1-B2
1-R8
1-G13
1-G637
FPDAT4
1-G3
1-B8
1-R14
1-R638
FPDAT3
1-R4
1-G9
1-B14
1-B638
FPDAT2
1-B4
1-R10
1-G15
1-G639
FPDAT1
1-G5
1-B10
1-R16
1-R640
FPDAT0
1-R6
1-G11
1-B16
1-B640
* Diagram drawn with 2 FPLINE vertical blank period
Example timing for a 640x480 panel
Figure 7-32: Single Color 16-Bit Panel Timing
VDP
VNDP
HDP
HNDP
= Vertical Display Period
= Vertical Non-Display Period
= Horizontal Display Period
= Horizontal Non-Display Period
S1D13506
X25B-A-001-10
= (REG[039h] bits [1:0], REG[038h] bits [7:0]) + 1
= (REG[03Ah] bits [5:0]) + 1
= ((REG[032h] bits [6:0]) + 1) × 8 Ts
= ((REG[034h] bits [4:0]) + 1) × 8 Ts
Hardware Functional Specification
Issue Date: 01/02/06
Epson Research and Development
Vancouver Design Center
Page 97
t1
Sync Timing
t2
FPFRAME
t4
t3
FPLINE
t5
DRDY (MOD)
Data Timing
FPLINE
t6
t7
t9
t8
t10
t12
t11
FPSHIFT
t13
FPDAT[15:0]
t14
1
2
Figure 7-33: Single Color 16-Bit Panel A.C. Timing
Hardware Functional Specification
Issue Date: 01/02/06
S1D13506
X25B-A-001-10
Page 98
Epson Research and Development
Vancouver Design Center
Table 7-27: Single Color 16-Bit Panel A.C. Timing
Symbol
t1
t2
t3
t4
t5
t6a
t6b
t7a
t7b
t8
t9a
t9b
t10a
t10b
t11
t12
t13
t14
1.
Ts
2.
3.
4.
5.
t1
t4
t5
t6
6.
t9
Parameter
FPFRAME setup to FPLINE falling edge
FPFRAME hold from FPLINE falling edge
FPLINE pulse width
FPLINE period
DRDY (MOD) delay from FPLINE falling edge
FPSHIFT falling edge to FPLINE rising edge, 4 bpp or 8 bpp
FPSHIFT falling edge to FPLINE rising edge, 15/16 bpp
FPLINE falling edge to FPSHIFT falling edge, 4 bpp or 8 bpp
FPLINE falling edge to FPSHIFT falling edge, 15/16 bpp
FPSHIFT period
FPSHIFT falling edge to FPLINE falling edge, 4 bpp or 8 bpp
FPSHIFT falling edge to FPLINE falling edge, 15/16 bpp
FPLINE falling edge to FPSHIFT rising edge, 4 bpp or 8 bpp
FPLINE falling edge to FPSHIFT rising edge, 15/16 bpp
FPSHIFT pulse width high
FPSHIFT pulse width low
FPDAT[15:0] setup to FPSHIFT falling edge
FPDAT[15:0] hold to FPSHIFT falling edge
S1D13506
X25B-A-001-10
Min.
Setting
28
40
3
5
7
16
18
Typical
note 2
12
11
note 3
note 4
note 5
note 5
21
19
5
note 6
note 6
18
16
2
2
2
2
Max.
Setting
1268
1280
259
229
231
240
242
Units
Ts (note 1)
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
= LCD pixel clock period. LCD pixel clock frequency is LCD pixel clock source divided by 1, 2, 3 or 4
(see REG[014h]).
= t4 - 12
= [((REG[032h] bits [6:0]) + 1) × 8 + ((REG[034h] bits [4:0]) + 1) × 8]
= [((REG[034h] bits [4:0]) + 1) × 8 + 3]
= [((REG[034h] bits [4:0]) + 1) × 8 - 27] for 4 bpp or 8 bpp color depth
= [((REG[034h] bits [4:0]) + 1) × 8 - 25] for 15/16 bpp color depth
= [((REG[034h] bits [4:0]) + 1) × 8 - 16] for 4 bpp or 8 bpp color depth
= [((REG[034h] bits [4:0]) + 1) × 8 - 14] for 15/16 bpp color depth
Hardware Functional Specification
Issue Date: 01/02/06
Epson Research and Development
Vancouver Design Center
Page 99
7.5.7 Single Color 16-Bit Panel Timing with External Circuit
VNDP
VDP
FPFRAME
FPLINE
DRDY (MOD)
S1D13506 OUTPUTS
FPDAT[15:0]
LINE 1
LINE 3
LINE 4
LINE 479
LINE 480
LINE 1
LINE 2
FPLINE
DRDY (MOD)
HDP
HNDP
FPSHIFT
FPDAT7
1 -R 1
1-G1
1 -B 6 3 5 1-R636
FPDAT6
1-B1
1-R2
1 -G 6 3 6 1-B636
FPDAT5
1-G2
1 -B 2
1-R 637
FPDAT4
1 -R 3
1-G3
1-B637 1 -R6 3 8
1 -G 6 3 7
FPDAT3
FPDAT2
1-B3
1-R4
1 -G 6 3 8 1 -B 6 3 8
1-G4
1-B4
1 - R 6 3 9 1 -G 6 3 9
FPDAT1
1 -R 5
1-G5
1 -B 6 3 9
FPDAT0
1-B5
1 -R 6
1-G640 1 - B 6 4 0
1-R1
1-G635
D15
16-bit PANEL INPUTS
LINE 2
1 -R6 4 0
D14
1 -B 1
1-G636
D13
1-G 2
1-R637
D12
1 -R 3
1 -B 6 3 7
D11
1-B3
1 -G 63 8
D10
1-G 4
1-R 639
D9
1-R5
1 -B 6 3 9
D8
1-B5
1-G640
D7
1-G1
1 -R 6 3 6
D6
1 -R 2
1 -B 6 3 6
D5
1 -B 2
1-G637
D4
1 -G 3
1-R638
D3
1 -R 4
1-B638
D2
1-B4
1-G639
D1
1-G5
1-R640
D0
1-R6
1-B640
* Diagram drawn with 2 FPLINE vertical blank period
Example timing for a 640x480 panel
Figure 7-34: 16-Bit Single Color Panel Timing with External Circuit
VDP
VNDP
HDP
HNDP
= Vertical Display Period
= Vertical Non-Display Period
= Horizontal Display Period
= Horizontal Non-Display Period
Hardware Functional Specification
Issue Date: 01/02/06
= (REG[039h] bits [1:0], REG[038h] bits [7:0]) + 1
= (REG[03Ah] bits [5:0]) + 1
= ((REG[032h] bits [6:0]) + 1) × 8 Ts
= ((REG[034h] bits [4:0]) + 1) × 8 Ts
S1D13506
X25B-A-001-10
Page 100
Epson Research and Development
Vancouver Design Center
D[7:0]
FPDAT[7:0]
D[15:8]
Q
D
TO 16-BIT
PANEL
FROM
S1D13506
FPSHIFT
CK
Figure 7-35: External Circuit for Color Single 16-Bit Panel When the Media Plug is Enabled
t1
Sync Timing
t2
FPFRAME
t4
t3
FPLINE
t5
DRDY (MOD)
Data Timing
FPLINE
t6
t7
t9
t8
t10
t12
t11
FPSHIFT
t13
FPDAT[7:0]
t14
1
t15
t16
2
3
4
Figure 7-36: Single Color 16-Bit Panel (with External Circuit) A.C. Timing
S1D13506
X25B-A-001-10
Hardware Functional Specification
Issue Date: 01/02/06
Epson Research and Development
Vancouver Design Center
Page 101
Table 7-28: Single Color 16-Bit Panel (with External Circuit) A.C. Timing
Symbol
t1
t2
t3
t4
t5
t6a
t6b
t7a
t7b
t8
t9a
t9b
t10a
t10b
t11
t12
t13
t14
t15
t16
1.
Ts
2.
3.
4.
5.
t1
t4
t5
t6
6.
t9
Parameter
FPFRAME setup to FPLINE falling edge
FPFRAME hold from FPLINE falling edge
FPLINE pulse width
FPLINE period
DRDY (MOD) delay from FPLINE falling edge
FPSHIFT falling edge to FPLINE rising edge, 4 bpp or 8 bpp
FPSHIFT falling edge to FPLINE rising edge, 15/16 bpp
FPLINE falling edge to FPSHIFT falling edge, 4 bpp or 8 bpp
FPLINE falling edge to FPSHIFT falling edge, 15/16 bpp
FPSHIFT period
FPSHIFT falling edge to FPLINE falling edge, 4 bpp or 8 bpp
FPSHIFT falling edge to FPLINE falling edge, 15/16 bpp
FPLINE falling edge to FPSHIFT rising edge, 4 bpp or 8 bpp
FPLINE falling edge to FPSHIFT rising edge, 15/16 bpp
FPSHIFT pulse width high
FPSHIFT pulse width low
FPDAT[7:0] setup to FPSHIFT rising edge
FPDAT[7:0] hold to FPSHIFT rising edge
FPDAT[7:0] setup to FPSHIFT falling edge
FPDAT[7:0] hold to FPSHIFT falling edge
Min.
Setting
28
40
3
5
7
16
18
Nominal
note 2
12
11
note 3
note 4
note 5
note 5
22
20
4
note 6
note 6
20
18
2
2
1
1
1
1
Max.
Setting
1268
1280
259
229
231
240
242
Units
Ts (note 1)
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
= LCD pixel clock period. LCD pixel clock frequency is LCD pixel clock source divided by 1, 2, 3 or 4
(see REG[014h]).
= t4 - 12
= [((REG[032h] bits [6:0]) + 1) × 8 + ((REG[034h] bits [4:0]) + 1) × 8]
= [((REG[034h] bits [4:0]) + 1) × 8 + 3]
= [((REG[034h] bits [4:0]) + 1) × 8 - 27] for 4 bpp or 8 bpp color depth
= [((REG[034h] bits [4:0]) + 1) × 8 - 25] for 15/16 bpp color depth
= [((REG[034h] bits [4:0]) + 1) × 8 - 16] for 4 bpp or 8 bpp color depth
= [((REG[034h] bits [4:0]) + 1) × 8 - 14] for 15/16 bpp color depth
Hardware Functional Specification
Issue Date: 01/02/06
S1D13506
X25B-A-001-10
Page 102
Epson Research and Development
Vancouver Design Center
7.5.8 Dual Monochrome 8-Bit Panel Timing
VNDP
VDP
FPFRAME
FPLINE
DRDY (MOD)
FPDAT[7:0]
LINE 1/241
LINE 2/242
LINE 3/243
LINE 4/244
LINE 239/479 LINE 240/480
LINE 1/241
LINE 2/242
FPLINE
DRDY (MOD)
HNDP
HDP
FPSHIFT
FPDAT7
1-1
1-5
1-637
FPDAT6
1-2
1-6
1-638
FPDAT5
1-3
1-7
1-639
FPDAT4
1-4
1-8
1-640
FPDAT3
241-1
241-5
241-637
FPDAT2
241-2
241-6
241-638
FPDAT1
241-3
241-7
241-639
FPDAT0
241-4
241-8
241-640
* Diagram drawn with 2 FPLINE vertical blank period
Example timing for a 640x480 panel
Figure 7-37: Dual Monochrome 8-Bit Panel Timing
VDP
VNDP
HDP
HNDP
= Vertical Display Period
= Vertical Non-Display Period
= Horizontal Display Period
= Horizontal Non-Display Period
S1D13506
X25B-A-001-10
= (REG[039h] bits [1:0], REG[038h] bits [7:1])
= (REG[03Ah] bits [5:0]) + 1
= ((REG[032h] bits [6:0]) + 1) × 8 Ts
= ((REG[034h] bits [4:0]) + 1) × 8 Ts
Hardware Functional Specification
Issue Date: 01/02/06
Epson Research and Development
Vancouver Design Center
Page 103
t1
Sync Timing
t2
FPFRAME
t3
t4
FPLINE
t5
DRDY (MOD)
Data Timing
FPLINE
t6
t7
t9
t8
t10
t12
t11
FPSHIFT
t13
FPDAT[7:0]
t14
1
2
Figure 7-38: Dual Monochrome 8-Bit Panel A.C. Timing
Hardware Functional Specification
Issue Date: 01/02/06
S1D13506
X25B-A-001-10
Page 104
Epson Research and Development
Vancouver Design Center
Table 7-29: Dual Monochrome 8-Bit Panel A.C. Timing
Symbol
t1
t2
t3
t4
t5
t6a
t6b
t7a
t7b
t8
t9a
t9b
t10a
t10b
t12
t11
t13
t14
1.
Ts
2.
3.
4.
5.
t1
t4
t5
t6
6.
t9
Parameter
FPFRAME setup to FPLINE falling edge
FPFRAME hold from FPLINE falling edge
FPLINE pulse width
FPLINE period
DRDY (MOD) delay from FPLINE falling edge
FPSHIFT falling edge to FPLINE rising edge, 4 bpp or 8 bpp
FPSHIFT falling edge to FPLINE rising edge, 15/16 bpp
FPLINE falling edge to FPSHIFT falling edge, 4 bpp or 8 bpp
FPLINE falling edge to FPSHIFT falling edge, 15/16 bpp
FPSHIFT period
FPSHIFT falling edge to FPLINE falling edge, 4 bpp or 8 bpp
FPSHIFT falling edge to FPLINE falling edge, 15/16 bpp
FPLINE falling edge to FPSHIFT rising edge, 4 bpp or 8 bpp
FPLINE falling edge to FPSHIFT rising edge, 15/16 bpp
FPSHIFT pulse width low
FPSHIFT pulse width high
FPDAT[7:0] setup to FPSHIFT falling edge
FPDAT[7:0] hold to FPSHIFT falling edge
S1D13506
X25B-A-001-10
Min.
Setting
28
40
3
13
15
24
26
Typical
note 2
12
11
note 3
note 4
note 5
note 5
12
10
4
note 6
note 6
10
8
2
2
2
2
Max.
Setting
1268
1280
259
237
239
248
250
Units
Ts (note 1)
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
= LCD pixel clock period. LCD pixel clock frequency is LCD pixel clock source divided by 1, 2, 3 or 4
(see REG[014h]).
= t4 - 12
= [((REG[032h] bits [6:0]) + 1) × 8 + ((REG[034h] bits [4:0]) + 1) × 8]
= [((REG[034h] bits [4:0]) + 1) × 8 + 3]
= [((REG[034h] bits [4:0]) + 1) × 8 - 19] for 4 bpp or 8 bpp color depth
= [((REG[034h] bits [4:0]) + 1) × 8 - 17] for 15/16 bpp color depth
= [((REG[034h] bits [4:0]) + 1) × 8 - 8] for 4 bpp or 8 bpp color depth
= [((REG[034h] bits [4:0]) + 1) × 8 - 6] for 15/16 bpp color depth
Hardware Functional Specification
Issue Date: 01/02/06
Epson Research and Development
Vancouver Design Center
Page 105
7.5.9 Dual Color 8-Bit Panel Timing
VNDP
VDP
FPFRAME
FPLINE
DRDY (MOD)
FPDAT[7:0]
LINE 1/241
LINE 2/242
LINE 3/243
LINE 4/244
LINE 239/479 LINE 240/480
LINE 1/241
LINE 2/242
FPLINE
DRDY (MOD)
HNDP
HDP
FPSHIFT
FPDAT7
1-R 1
1-G2
1-B3
1-R5
1-G6
1-B7
1-B 639
FPDAT6
1-G1
1-B2
1-R4
1-G5
1-B6
1-R8
1-R640
FPDAT5
1-B1
1-R 3
1-G4
1-B5
1-R7
1-G8
1-G640
1-R2
1-G 3
1-B4
1-R6
1-G7
1-B8
1-B640
FPDAT4
FPDAT3
241-R 1 241-G2 241-B 3 241-R5 241-G6 241-B7
2 41B639
FPDAT2
241-G1 24 1-B2 241-R 4 241-G 5 241-B6 241-R8
241R640
FPDAT1
241-B1 241-R3 241-G4 241-B5 241-R7 241-G8
241G640
FPDAT0
241-R 2 241-G3 241-B4 241-R 6 241-G7 241-B8
241B640
* Diagram drawn with 2 FPLINE vertical blank period
Example timing for a 640x480 panel
Figure 7-39: Dual Color 8-Bit Panel Timing
VDP
VNDP
HDP
HNDP
= Vertical Display Period
= Vertical Non-Display Period
= Horizontal Display Period
= Horizontal Non-Display Period
Hardware Functional Specification
Issue Date: 01/02/06
= ((REG[039h] bits [1:0], REG[038h] bits [7:0]) + 1) /2
= (REG[03Ah] bits [5:0]) + 1
= ((REG[032h] bits [6:0]) + 1) × 8 Ts
= ((REG[034h] bits [4:0]) + 1) × 8 Ts
S1D13506
X25B-A-001-10
Page 106
Epson Research and Development
Vancouver Design Center
t1
t2
Sync Timing
FPFRAME
t3
t4
FPLINE
t5
DRDY (MOD)
Data Timing
FPLINE
t6
t7
t9
t8
t10
t11
t12
FPSHIFT
t13
FPDAT[7:0]
t14
1
2
Figure 7-40: Dual Color 8-Bit Panel A.C. Timing
S1D13506
X25B-A-001-10
Hardware Functional Specification
Issue Date: 01/02/06
Epson Research and Development
Vancouver Design Center
Page 107
Table 7-30: Dual Color 8-Bit Panel A.C. Timing
Symbol
t1
t2
t3
t4
t5
t6a
t6b
t7a
t7b
t8
t9a
t9b
t10a
t10b
t11
t12
t13
t14
1.
Ts
2.
3.
4.
5.
t1
t4
t5
t6
6.
t9
Parameter
FPFRAME setup to FPLINE falling edge
FPFRAME hold from FPLINE falling edge
FPLINE pulse width
FPLINE period
DRDY (MOD) delay from FPLINE falling edge
FPSHIFT falling edge to FPLINE rising edge, 4 bpp or 8 bpp
FPSHIFT falling edge to FPLINE rising edge, 15/16 bpp
FPLINE falling edge to FPSHIFT falling edge, 4 bpp or 8 bpp
FPLINE falling edge to FPSHIFT falling edge, 15/16 bpp
FPSHIFT period
FPSHIFT falling edge to FPLINE falling edge, 4 bpp or 8 bpp
FPSHIFT falling edge to FPLINE falling edge, 15/16 bpp
FPLINE falling edge to FPSHIFT rising edge, 4 bpp or 8 bpp
FPLINE falling edge to FPSHIFT rising edge, 15/16 bpp
FPSHIFT pulse width high
FPSHIFT pulse width low
FPDAT[7:0] setup to FPSHIFT falling edge
FPDAT[7:0] hold to FPSHIFT falling edge
Min.
Setting
28
40
3
12
14
23
25
Typical
note 2
12
11
note 3
note 4
note 5
note 5
10.5
8.5
1
note 6
note 6
11
9
0.5
0.5
0.5
0.5
Max.
Setting
1268
1280
259
236
238
247
249
Units
Ts (note 1)
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
= LCD pixel clock period. LCD pixel clock frequency is LCD pixel clock source divided by 1, 2, 3 or 4
(see REG[014h]).
= t4 - 12
= [((REG[032h] bits [6:0]) + 1) × 8 + ((REG[034h] bits [4:0]) + 1) × 8]
= [((REG[034h] bits [4:0]) + 1) × 8 + 3]
= [((REG[034h] bits [4:0]) + 1) × 8 - 20] for 4 bpp or 8 bpp color depth
= [((REG[034h] bits [4:0]) + 1) × 8 - 18] for 15/16 bpp color depth
= [((REG[034h] bits [4:0]) + 1) × 8 - 9] for 4 bpp or 8 bpp color depth
= [((REG[034h] bits [4:0]) + 1) × 8 - 7] for 15/16 bpp color depth
Hardware Functional Specification
Issue Date: 01/02/06
S1D13506
X25B-A-001-10
Page 108
Epson Research and Development
Vancouver Design Center
7.5.10 Dual Color 16-Bit Panel Timing
VDP
VNDP
FPFRAME
FPLINE
DRDY (MOD)
FPDAT[15:0]
LINE 1/241
LINE 2/242
LINE 3/243
LINE 4/244
LINE 239/479 LINE 240/480
LINE 1/241
LINE 2/242
FPLINE
DRDY (MOD)
HNDP
HDP
FPSHIFT
FPDAT[15,7]
1-R1,
241-R1
1-B3,
2 41-B 3
1-G 63 8,
2 41-G 63 8
FPDAT[14,6]
1-G1,
24 1-G 1
1-R4,
2 41 -R 4
1-B 63 8,
241-B 638
FPDAT[13,5]
1-B1,
2 41-B 1
1-G 4,
2 41-G 4
1-R639 ,
241 -R639
FPDAT[12,4]
1-R2,
2 41-R 2
1-B4,
2 41-B 4
1-G 63 9,
2 41-G 63 9
FPDAT[11,3]
1-G2,
24 1-G 2
1-R5,
2 41 -R 5
1-B 63 9,
2 41-B63 9
FPDAT[10,2]
1-B2,
2 41-B 2
1-G 5,
2 41-G 5
1-R640 ,
241 -R640
FPDAT[9,1]
1-R3,
2 41-R 3
1-B 5,
2 41-B 5
1-G 640,
2 41-G 64 0
FPDAT[8,0]
1-G3,
24 1-G 3
1-R6,
2 41 -R 6
1-B 64 0,
2 41-B64 0
* Diagram drawn with 2 FPLINE vertical blank period
Example timing for a 640x480 panel
Figure 7-41: Dual Color 16-Bit Panel Timing
VDP
VNDP
HDP
HNDP
= Vertical Display Period
= Vertical Non-Display Period
= Horizontal Display Period
= Horizontal Non-Display Period
S1D13506
X25B-A-001-10
= ((REG[039h] bits [1:0], REG[038h] bits [7:0]) + 1) /2
= (REG[03Ah] bits [5:0]) + 1
= ((REG[032h] bits [6:0]) + 1) × 8 Ts
= ((REG[034h] bits [4:0]) + 1) × 8 Ts
Hardware Functional Specification
Issue Date: 01/02/06
Epson Research and Development
Vancouver Design Center
Page 109
t1
t2
Sync Timing
FPFRAME
t3
t4
FPLINE
t5
DRDY (MOD)
Data Timing
FPLINE
t6
t7
t9
t8
t10
t11
t12
FPSHIFT
t13
t14
1
2
FPDAT[15:0]
Figure 7-42: Dual Color 16-Bit Panel A.C. Timing
Hardware Functional Specification
Issue Date: 01/02/06
S1D13506
X25B-A-001-10
Page 110
Epson Research and Development
Vancouver Design Center
Table 7-31: Dual Color 16-Bit Panel A.C. Timing
Symbol
t1
t2
t3
t4
t5
t6a
t6b
t7a
t7b
t8
t9a
t9b
t10a
t10b
t11
t12
t13
t14
1.
Ts
2.
3.
4.
5.
t1
t4
t5
t6
6.
t9
Parameter
FPFRAME setup to FPLINE falling edge
FPFRAME hold from FPLINE falling edge
FPLINE pulse width
FPLINE period
DRDY (MOD) delay from FPLINE falling edge
FPSHIFT falling edge to FPLINE rising edge, 4 bpp or 8 bpp
FPSHIFT falling edge to FPLINE rising edge, 15/16 bpp
FPLINE falling edge to FPSHIFT falling edge, 4 bpp or 8 bpp
FPLINE falling edge to FPSHIFT falling edge, 15/16 bpp
FPSHIFT period
FPSHIFT falling edge to FPLINE falling edge, 4 bpp or 8 bpp
FPSHIFT falling edge to FPLINE falling edge, 15/16 bpp
FPLINE falling edge to FPSHIFT rising edge, 4 bpp or 8 bpp
FPLINE falling edge to FPSHIFT rising edge, 15/16 bpp
FPSHIFT pulse width high
FPSHIFT pulse width low
FPDAT[15:0] setup to FPSHIFT falling edge
FPDAT[15:0] hold to FPSHIFT falling edge
S1D13506
X25B-A-001-10
Min.
Setting
28
40
3
12
14
23
25
Typical
note 2
12
11
note 3
note 4
note 5
note 5
12
10
2
note 6
note 6
10
8
1
1
1
1
Max.
Setting
1268
1280
259
236
238
247
249
Units
Ts (note 1)
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
= LCD pixel clock period. LCD pixel clock frequency is LCD pixel clock source divided by 1, 2, 3 or 4
(see REG[014h]).
= t4 - 12
= [((REG[032h] bits [6:0]) + 1) × 8 + ((REG[034h] bits [4:0]) + 1) × 8]
= [((REG[034h] bits [4:0]) + 1) × 8 + 3]
= [((REG[034h] bits [4:0]) + 1) × 8 - 20] for 4 bpp or 8 bpp color depth
= [((REG[034h] bits [4:0]) + 1) × 8 - 18] for 15/16 bpp color depth
= [((REG[034h] bits [4:0]) + 1) × 8 - 9] for 4 bpp or 8 bpp color depth
= [((REG[034h] bits [4:0]) + 1) × 8 - 7] for 15/16 bpp color depth
Hardware Functional Specification
Issue Date: 01/02/06
Epson Research and Development
Vancouver Design Center
Page 111
7.5.11 Dual Color 16-Bit Panel Timing with External Circuit
VDP
VNDP
FPFRAME
FPLINE
DRDY (MOD)
LINE 1/241
FPDAT[15:0]
LINE 2/242
LINE 3/243
LINE 4/244
LINE 239/479 LINE 240/480
LINE 1/241
LINE 2/242
S1D13506 Outputs
FPLINE
DRDY (MOD)
FPSHIFT
FPDAT7
1 -R 1
1-G 2
1 -B 3
FPDAT6
1-G1
1-B2
1-R4
1-B 638 1-R 640
FPDAT5
1 -B 1
1 -R 3
1 -G 4
1 -R6 3 9
FPDAT4
1 -R 2
1-G3
1 -B 4
1 -G 6 3 9 1 -B 6 4 0
1 -G 6 3 8 1 -B 6 3 9
1-G640
241-R1 241-G2 241-B3
241G638
241B639
241-G1 241-B2 241-R4
241B638
241R640
FPDAT1
2 41 -B 1 2 4 1 -R 3
2 41 -B 4
241R639
241G 640
FPDAT0
2 4 1 -R 2 2 4 1-G 3
2 41 -B 4
241G 639
241B640
FPDAT3
FPDAT2
16-BIT PANEL INPUTS
HNDP
HDP
UD7
1 -R 1
UD6
1-G1
1-B638
UD5
1-B1
1-R639
UD4
1-R2
1-G639
UD3
1-G2
1 -B 6 3 9
UD2
1 -B 2
1-R 640
UD1
1-R3
1 -G 6 4 0
UD0
1-G 3
1 -B 6 4 0
LD7
241-R1
2 4 1 -G 6 3 8
LD6
241-G1
2 4 1 -B 6 3 8
1-G638
LD5
241-B1
2 4 1 -R 6 3 9
LD4
241-R2
2 4 1 -G 6 3 9
LD3
2 4 1-G 2
241B639
LD2
2 41 -B 2
241R 640
LD1
241-R3
241G 640
LD0
2 4 1-G 3
241B640
* Diagram drawn with 2 FPLINE vertical blank period
Example timing for a 640x480 panel
Figure 7-43: 16-Bit Dual Color Panel Timing with External Circuit
VDP
VNDP
HDP
HNDP
= Vertical Display Period
= Vertical Non-Display Period
= Horizontal Display Period
= Horizontal Non-Display Period
Hardware Functional Specification
Issue Date: 01/02/06
= ((REG[039h] bits [1:0], REG[038h] bits [7:0]) + 1) /2
= (REG[03Ah] bits [5:0]) + 1
= ((REG[032h] bits [6:0]) + 1) × 8 Ts
= ((REG[034h] bits [4:0]) + 1) × 8 Ts
S1D13506
X25B-A-001-10
Page 112
Epson Research and Development
Vancouver Design Center
UD[3:0]
LD[3:0]
FROM
S1D13506
FPDAT[7:4]
FPDAT[3:0]
FPSHIFT
UD[7:4]
LD[7:4]
Q
D
TO 16-BIT
PANEL
CK
Figure 7-44: External Circuit for Color Dual 16-Bit Panel When the Media Plug is Enabled
t1
Sync Timing
t2
FPFRAME
t4
t3
FPLINE
t5
DRDY (MOD)
Data Timing
FPLINE
t6
t7
t9
t8
t10
t12
t11
FPSHIFT
t13
FPDAT[7:0]
t14
1
t15
t16
2
3
4
Figure 7-45: Dual Color 16-Bit Panel (with External Circuit) A.C. Timing
S1D13506
X25B-A-001-10
Hardware Functional Specification
Issue Date: 01/02/06
Epson Research and Development
Vancouver Design Center
Page 113
Table 7-32: Dual Color 16-Bit Panel (with External Circuit) A.C. Timing
Symbol
t1
t2
t3
t4
t5
t6a
t6b
t7a
t7b
t8
t9a
t9b
t10a
t10b
t11
t12
t13
t14
t15
t16
1.
Ts
2.
3.
4.
5.
t1
t4
t5
t6
6.
t9
Parameter
FPFRAME setup to FPLINE falling edge
FPFRAME hold from FPLINE falling edge
FPLINE pulse width
FPLINE period
DRDY (MOD) delay from FPLINE falling edge
FPSHIFT falling edge to FPLINE rising edge, 4 bpp or 8 bpp
FPSHIFT falling edge to FPLINE rising edge, 15/16 bpp
FPLINE falling edge to FPSHIFT falling edge, 4 bpp or 8 bpp
FPLINE falling edge to FPSHIFT falling edge, 15/16 bpp
FPSHIFT period
FPSHIFT falling edge to FPLINE falling edge, 4 bpp or 8 bpp
FPSHIFT falling edge to FPLINE falling edge, 15/16 bpp
FPLINE falling edge to FPSHIFT rising edge, 4 bpp or 8 bpp
FPLINE falling edge to FPSHIFT rising edge, 15/16 bpp
FPSHIFT pulse width high
FPSHIFT pulse width low
FPDAT[7:0] setup to FPSHIFT rising edge
FPDAT[7:0] hold to FPSHIFT rising edge
FPDAT[7:0] setup to FPSHIFT falling edge
FPDAT[7:0] hold to FPSHIFT falling edge
Min.
Setting
28
40
3
12.5
14.5
23.5
25.5
Typical
note 2
12
11
note 3
note 4
note 5
note 5
12.5
10.5
2
note 6
note 6
11.5
9.5
1
1
0.5
0.5
0.5
0.5
Max.
Setting
1268
1280
259
236.5
238.5
247.5
249.5
Units
Ts (note 1)
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
= LCD pixel clock period. LCD pixel clock frequency is LCD pixel clock source divided by 1, 2, 3 or 4
(see REG[014h]).
= t4 - 12
= [((REG[032h] bits [6:0]) + 1) × 8 + ((REG[034h] bits [4:0]) + 1) × 8]
= [((REG[034h] bits [4:0]) + 1) × 8 + 3]
= [((REG[034h] bits [4:0]) + 1) × 8 - 19.5] for 4 bpp or 8 bpp color depth
= [((REG[034h] bits [4:0]) + 1) × 8 - 17.5] for 15/16 bpp color depth
= [((REG[034h] bits [4:0]) + 1) × 8 - 8.5] for 4 bpp or 8 bpp color depth
= [((REG[034h] bits [4:0]) + 1) × 8 - 6.5] for 15/16 bpp color depth
Hardware Functional Specification
Issue Date: 01/02/06
S1D13506
X25B-A-001-10
Page 114
Epson Research and Development
Vancouver Design Center
7.5.12 TFT/D-TFD Panel Timing
VNDP
VDP
FPFRAME
FPLINE
R[5:1], G[5:0], B[5:1]
LINE480
LINE1
LINE480
DRDY
FPLINE
HDP
HNDP1
HNDP2
FPSHIFT
DRDY
R[5:1]
G [5:0]
B[5:1]
1-1
1-2
1-640
1-1
1-2
1-640
1-1
1-2
1-640
Note: DRDY is used to indicate the first pixel
Example Timing for 640x480 panel
Figure 7-46: TFT/D-TFD Panel Timing
VDP
VNDP
HDP
HNDP
= Vertical Display Period
= Vertical Non-Display Period
= Horizontal Display Period
= Horizontal Non-Display Period
S1D13506
X25B-A-001-10
= (REG[039h] bits [1:0], REG[038h] bits [7:0]) + 1
= (REG[03Ah] bits [5:0]) + 1
= ((REG[032h] bits [6:0]) + 1) × 8 Ts
= HNDP1 + HNDP2 = ((REG[034h] bits [4:0]) + 1) × 8 Ts
Hardware Functional Specification
Issue Date: 01/02/06
Epson Research and Development
Vancouver Design Center
Page 115
t8
t9
FPFRAME
t12
FPLINE
t6
FPLINE
t15
t7
t17
DRDY
t14
t1
t2
t3
t11
t13
t16
FPSHIFT
t4
R[5:1]
G[5:0]
B[5:1]
t5
1
2
639
640
t10
Note: DRDY is used to indicate the first pixel
Figure 7-47: TFT/D-TFD A.C. Timing
Hardware Functional Specification
Issue Date: 01/02/06
S1D13506
X25B-A-001-10
Page 116
Epson Research and Development
Vancouver Design Center
Table 7-33: TFT/D-TFD A.C. Timing
Symbol
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
t12
t13
t14
t15a
t15b
t16
t17a
t17b
1.
Ts
2.
3.
4.
5.
6.
7.
8.
9.
t6
t7
t8
t9
t10
t12
t14
t15
Parameter
FPSHIFT period
FPSHIFT pulse width high
FPSHIFT pulse width low
data setup to FPSHIFT falling edge
data hold from FPSHIFT falling edge
FPLINE cycle time
FPLINE pulse width low
FPFRAME cycle time
FPFRAME pulse width low
horizontal display period
FPLINE setup to FPSHIFT falling edge
FPFRAME falling edge to FPLINE falling edge phase difference
DRDY to FPSHIFT falling edge setup time
DRDY pulse width
DRDY falling edge to FPLINE falling edge, 4 bpp or 8 bpp
DRDY falling edge to FPLINE falling edge, 15/16 bpp
DRDY hold from FPSHIFT falling edge
FPLINE Falling edge to DRDY active, 4 bpp or 8 bpp
FPLINE Falling edge to DRDY active, 15/16 bpp
10. t17
S1D13506
X25B-A-001-10
Min.
Setting
40
8
2
1
8
1
8
4
6
-6
-8
Typical
1
0.5
0.5
0.5
0.5
note 2
note 3
note 4
note 5
note 6
0.5
note 7
0.5
note 8
note 9
note 9
0.5
note 10
note 10
Max.
Setting
1280
128
1088
8
1024
249
1024
252
254
250
248
Units
Ts (note 1)
Ts
Ts
Ts
Ts
Ts
Ts
lines
lines
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
= LCD pixel clock period. LCD pixel clock frequency is LCD pixel clock source divided by 1, 2, 3 or 4
(see REG[014h]).
= [((REG[032h] bits [6:0]) + 1) × 8 + ((REG[034h] bits [4:0]) + 1) × 8]
= [((REG[036h] bits [3:0]) + 1) × 8]
= [((REG[039h] bits [1:0], REG[038h] bits [7:0]) + 1) + ((REG[03Ah] bits [5:0]) + 1)]
= [((REG[03Ch] bits [2:0]) + 1)]
= [((REG[032h] bits [6:0]) + 1) × 8]
= [(REG[035h] bits [4:0]) × 8 + 1]
= [((REG[032h] bits [6:0]) + 1) × 8]
= [(REG[035h] bits [4:0]) × 8 + 4] for 4 bpp or 8 bpp color depth
= [(REG[035h] bits [4:0]) × 8 + 6] for 15/16 bpp color depth
= [((REG[034h] bits [4:0]) + 1) × 8 - (REG[035h] bits [4:0]) × 8 - 4] for 4 bpp or 8 bpp color depth
= [((REG[034h] bits [4:0]) + 1) × 8 - (REG[035h] bits [4:0]) × 8 - 6] for 15/16 bpp color depth
Hardware Functional Specification
Issue Date: 01/02/06
Epson Research and Development
Vancouver Design Center
Page 117
7.5.13 CRT Timing
VNDP
VDP
VRTC
HRTC
RED,GREEN,BLUE
LINE480
LINE1
LINE480
HRTC
HDP
HNDP1
1-1
RED,GREEN,BLUE
1-2
HNDP2
1-640
Example Timing for 640x480 CRT
Figure 7-48: CRT Timing
VDP
VNDP
HDP
HNDP
= Vertical Display Period
= Vertical Non-Display Period
= Horizontal Display Period
= Horizontal Non-Display Period
= (REG[057h] bits [1:0], REG[056h] bits [7:0]) + 1
= (REG[058h] bits [5:0]) + 1
= ((REG[050h] bits [6:0]) + 1) × 8 Ts
= HNDP1 + HNDP2= ((REG[052h] bits [5:0]) + 1) × 8 Ts
Note
The signals RED, GREEN and BLUE are analog signals from the embedded DAC and represent
the color components which make up each pixel.
Hardware Functional Specification
Issue Date: 01/02/06
S1D13506
X25B-A-001-10
Page 118
Epson Research and Development
Vancouver Design Center
t1
t2
VRTC
t3
HRTC
Figure 7-49: CRT A.C. Timing
Table 7-34: CRT A.C. Timing
Symbol
t1
1.
2.
3.
Parameter
VRTC cycle time
Min.
Setting
Typical
Max.
Setting
Units
2
note 1
1152
lines
t2
VRTC pulse width low
1
note 2
8
lines
t3
VRTC falling edge to FPLINE falling edge phase difference
8
note 3
512
Ts
t1
t2
t3
S1D13506
X25B-A-001-10
= [((REG[057h] bits 1:0, REG[056h] bits 7:0) + 1) + ((REG[058h] bits 6:0) + 1)] lines
= [((REG[05Ah] bits 2:0) + 1)] lines
= [((REG[053h] bits 5:0) + 1) × 8] Ts
Hardware Functional Specification
Issue Date: 01/02/06
Epson Research and Development
Vancouver Design Center
Page 119
7.6 TV Timing
7.6.1 TV Output Timing
The overall NTSC and PAL video timing is shown in Figure 7-50: and Figure 7-51: respectively.
Register Programming:
Vertical Non-Display Period = 20
VRTC Start Position = 0
vertical blanking interval = 20 lines
261 262
1
2
3
4
Field 1
5
6
7
vertical sync
pulse interval
pre-equalizing
pulse interval
8
9
10
19
20
21
post-equalizing
pulse interval
start of field 1
VNDP
TV VRTC Start Position (field 1)
261
262 263
1
2
3
4
5
6
7
8
9
10
19
20
21
Field 2
start of field 2
VNDP
TV VRTC Start Position (field 2)
Start of Vertical Sync
Figure 7-50: NTSC Video Timing
Hardware Functional Specification
Issue Date: 01/02/06
S1D13506
X25B-A-001-10
Page 120
Epson Research and Development
Vancouver Design Center
Register Programming:
Vertical Non-Display Period = 26
VRTC Start Position = 0
Field 1
vertical blanking interval = 25 lines
620 621 622 623 624 625
1
2
3
vertical sync
pulse interval
pre-equalizing
pulse interval
4
5
6
7
21
22
23
24
post-equalizing
pulse interval
start of field 1
VNDP
TV VRTC Start Position (field 1)
308 309 310 311 312 313 314 315 316 317 318 319 320
334 335 336
Field 2
start of field 2
VNDP
TV VRTC Start Position (field 2)
620 621 622 623 624 625
1
2
3
4
5
6
7
21
22
23
24
Field 3
start of field 3
VNDP
TV VRTC Start Position (field 3)
308 309 310 311 312 313 314 315 316 317 318 319 320
334 335 336
Field 4
start of field 4
VNDP
TV VRTC Start Position (field 4)
Start of Vertical Sync
Figure 7-51: PAL Video Timing
S1D13506
X25B-A-001-10
Hardware Functional Specification
Issue Date: 01/02/06
Epson Research and Development
Vancouver Design Center
Page 121
IRE
100
Active
Line
20
0
Blanking
Level
40 IRE
-20
-40
t1
t2
t3
t4
t5
t6
t7
t8
t9
Blanking
Level
0
t10
Equalizing Pulse
Vertical Sync Pulse
t11
-40
Start of
Horizontal Sync
Figure 7-52: Horizontal Timing for NTSC/PAL
Table 7-35: Horizontal Timing for NTSC/PAL
Symbol
T4SC
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
1.
t1
2.
t5NTSC
3.
t5PAL
4.
6.
7.
t6NTSC
t6PAL
t7
Parameter
(4x Subcarrier clock) period
Front Porch
Horizontal Sync
Breezeway
Color Burst
Color Back Porch
Horizontal Blanking
Active Video
Line Period
Half Line Period
Equalizing Pulse
Vertical Serration
NTSC
69.841
note 1
67
9
39
note 2
note 4
note 6
910
455
33
67
PAL
56.387
note 1
83
16
44
note 3
note 5
note 6
1135
568 / 567
41
83
Units
ns
T4SC
T4SC
T4SC
T4SC
T4SC
T4SC
T4SC
T4SC
T4SC
T4SC
T4SC
= ((REG[053] bits[5:0]) + 1) x 8 - 7 (4 bpp, 8 bpp modes)
= ((REG[053] bits[5:0]) + 1) x 8 - 5 (15/16 bpp modes)
= (((REG[052] bits[5:0]) x 8) + 6) - (((REG[053] bits[5:0]) + 1) x 8) - 108 (4 bpp, 8 bpp modes)
= (((REG[052] bits[5:0]) x 8) + 6) - (((REG[053] bits[5:0]) + 1) x 8) - 110 (15/16 bpp modes)
= (((REG[052] bits[5:0]) x 8) + 7) - (((REG[053] bits[5:0]) + 1) x 8) - 136 (4 bpp, 8 bpp modes)
= (((REG[052] bits[5:0]) x 8) + 7) - (((REG[053] bits[5:0]) + 1) x 8) - 138 (15/16 bpp modes)
= ((REG[052] bits[5:0]) x 8) + 6
= ((REG[052] bits[5:0]) x 8) + 7
= ((REG[050] bits[6:0]) + 1) x 8
Important:
REG[050] and REG[052] must be programmed to satisfy the Line Period (t8).
For NTSC, (((REG[050] bits[6:0]) + 1) x 8) + (((REG[052] bits[5:0]) x 8) + 6) = 910.
For PAL, (((REG[050] bits[6:0]) + 1) x 8) + (((REG[052] bits[5:0]) x 8) + 7) = 1135.
Hardware Functional Specification
Issue Date: 01/02/06
S1D13506
X25B-A-001-10
Page 122
Epson Research and Development
Vancouver Design Center
909 (NTSC)
1134 (PAL)
0
Vertical
Non-Display
Period
t4
t2
Vertical
Sync
Odd
Field
1,3
Vertical
Display
Period
t1
Odd Lines (1, 3, 5, ...)
t5
Vertical
Non-Display
Period
t4
Vertical
Sync
t3
Even
Field
2,4
Vertical
Display
Period
t1
Even Lines (2, 4, 6, ...)
Horizontal Sync
Figure 7-53: Vertical Timing for NTSC/PAL
Table 7-36: Vertical Timing for NTSC/PAL
Symbol
TLINE
t1
t2
t3
t4
t5
1.
2.
3.
4.
t1
t2
t3
t4NTSC
5. t4PAL
Parameter
Line Period
Vertical Field Period
Vertical Blanking (Fields 1, 3)
Vertical Blanking (Fields 2, 4)
Vertical Sync Position
Frame Period
NTSC
63.55556
note 1
note 2
note 3
note 4
525
PAL
63.99964
note 1
note 2
note 3
note 5
625
Units
us
TLINE
TLINE
TLINE
TLINE
TLINE
= ({(REG[057] bits[1:0]), (REG[056] bits[7:0])} + 1) / 2
= ((REG[058] bits[6:0]) + 1) for fields 1 & 3
= ((REG[058] bits[6:0]) + 2) for fields 2 & 4
= ((REG[059] bits[6:0]) + 4)
for field 1
= ((REG[059] bits[6:0]) + 4.5) for field 2
= ((REG[059] bits[6:0]) + 5)
for field 1 and field 3
= ((REG[059] bits[6:0]) + 4.5) for field 2 and field 4
Important
REG[056], REG[057], and REG[058] must be programmed to satisfy the Frame Period (t5).
For NTSC, ({(REG[057] bits[1:0]), (REG[056] bits[7:0])} + 1) + ((REG[058] bits[6:0]) + 1) x 2 + 1) = 525
For PAL, ({(REG[057] bits[1:0]), (REG[056] bits[7:0])} + 1) + ((REG[058] bits[6:0]) + 1) x 2 + 1) = 625.
S1D13506
X25B-A-001-10
Hardware Functional Specification
Issue Date: 01/02/06
Epson Research and Development
Vancouver Design Center
Page 123
7.7 MediaPlug Interface Timing
T1
VMPCLK
t2
t2
t2
t2
VMPCLKN
t3
VMPDIN[3:0]
t4
VMPCTRL
t5
VMPLCTRL
t7
t6
VMPDout
Figure 7-54: MediaPlug A.C. Timing
Note
The above timing diagram assumes no load.
Table 7-37: MediaPlug A.C. Timing
Symbol
Parameter
Min
Max
T1
MediaPlug clock period
t2
VMPCLKN delay from VMPCLK
0
t3
Input data setup
6
t4
VMPCTRL setup
6
t5
Local control signal delay from VMPCLK falling
edge
2
ns
t6
Output data delay from VMPCLK falling edge
1
ns
t7
Output data tristate delay from VMPCLK falling
edge
14
ns
Hardware Functional Specification
Issue Date: 01/02/06
100
Units
ns
3
ns
ns
S1D13506
X25B-A-001-10
Page 124
Epson Research and Development
Vancouver Design Center
8 Registers
This section discusses how and where to access the S1D13506 registers. It also provides
detailed information about the layout and usage of each register.
8.1 Initializing the S1D13506
Before programming the S1D13506 registers, the Register/Memory Select bit
(REG[000h] bit 7) must be set.
8.1.1 Register/Memory Select Bit
At reset, the Register/Memory Select bit is set to 1. This means that only REG[000h] (readonly) and REG[001h] are accessible until a write to REG[001h] sets bit 7 to 0 making
all registers and memory accessible. When debugging a new hardware design, this can
sometimes give the appearance that the interface is not working, so it is important to
remember to clear this bit before proceeding with debugging.
8.2 Register Mapping
The S1D13506 registers are memory-mapped. When the system decodes the input pins as
CS# = 0 and M/R# = 0, the registers may be accessed. The register space is decoded by
A20-A0.
When A20 = 1 the BitBlt data register ports are decoded allowing the system to access the
display buffer through the 2D BitBlt engine using address lines A19-A0. When A20 = 0
and A12 = 0 the registers are decoded using A8-A0 as an index. When A20 = 0 and
A12 = 1 the MediaPlug register ports are decoded using A11-A0.
The MediaPlug register ports are defined only when configuration input MD13 = 1 on reset.
When MD13 = 0 on reset, A12 is always treated as 0 and the MediaPlug register space is
not available - see Table 5-6:, “Summary of Power-On/Reset Options,” on page 39.
Table 8-1: “Register Mapping with CS# = 0 and M/R# = 0” shows the decoding for each
register type.
Table 8-1: Register Mapping with CS# = 0 and M/R# = 0
Register Types (Range)
Address A20-A0 Decoding
BitBlt data registers (1M byte)
100000h to 1FFFFFh
MediaPlug registers (4K bytes)
1000h to 1FFFh
Main Registers (512 bytes)
0 to 1FFh
Note
The registers may be aliased within the allocated register space. If aliasing is
undesirable, the register space must be fully decoded.
S1D13506
X25B-A-001-10
Hardware Functional Specification
Issue Date: 01/02/06
Epson Research and Development
Vancouver Design Center
Page 125
8.3 Register Descriptions
8.3.1 Basic Registers
Revision Code Register
REG[000h]
RO
Product Code Product Code Product Code Product Code Product Code Product Code
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Revision
Code Bit 1
Revision
Code Bit 0
bits 7-2
Product Code Bits [5:0]
This is a read-only register that indicates the product code of the chip. The product code
for S1D13506 is 000100b.
bits 1-0
Revision Code Bits [1:0]
This is a read-only register that indicates the revision code of the chip. The revision code is
01b.
Miscellaneous Register
REG[001h]
Register/
Memory
Select
n/a
RW
n/a
n/a
n/a
Reserved
Reserved
Reserved
bit 7
Register Memory Select
At reset, the Register/Memory Select bit is set to 1. This means that only REG[000h]
(read-only) and REG[001h] are accessible until a write to REG[001h] sets bit 7 to 0
making all registers and memory accessible. When debugging a new hardware design,
this can sometimes give the appearance that the interface is not working, so it is important
to remember to clear this bit before proceeding with debugging.
bit 2
Reserved.
This bit must be set to 0.
bit 1
Reserved.
This bit must be set to 0.
bit 0
Reserved.
This bit must be set to 0.
Hardware Functional Specification
Issue Date: 01/02/06
S1D13506
X25B-A-001-10
Page 126
Epson Research and Development
Vancouver Design Center
8.3.2 General IO Pins Registers
General IO Pins Configuration Register
REG[004h]
Reserved
Reserved
bit 3
Reserved
RW
Reserved
GPIO3 Pin
IO Config.
GPIO2 Pin
IO Config.
GPIO1 Pin
IO Config.
Reserved
GPIO3 Pin IO Configuration
When this bit = 1, GPIO3 is configured as an output pin.
When this bit = 0 (default), GPIO3 is configured as an input pin.
Note
Note that MD[7:6] must be properly configured at the rising edge of RESET# to enable
GPIO3, otherwise GPIO3 will be used as MA[9] for the DRAM and this bit will have no
hardware effect. (See Table 8-2: “MA[11:9]/GPIO[1:3] Pin Functionality”).
bit 2
GPIO2 Pin IO Configuration
When this bit = 1, GPIO2 is configured as an output pin.
When this bit = 0 (default), GPIO2 is configured as an input pin.
Note
Note that MD[14] and MD[7:6] must be properly configured at the rising edge of RESET# to enable GPIO2, otherwise GPIO2 will be used as MA[11] for the DRAM or as
the MediaPlug VMPEPWR output and this bit will have no hardware effect. (See Table
8-2: “MA[11:9]/GPIO[1:3] Pin Functionality”).
bit 1
GPIO1 Pin IO Configuration
When this bit = 1, GPIO1 is configured as an output pin.
When this bit = 0 (default), GPIO1 is configured as an input pin.
Note
Note that MD[7:6] must be properly configured at the rising edge of RESET# to enable
GPIO1, otherwise GPIO1 will be used as MA[10] for the DRAM and this bit will have
no hardware effect. (See Table 8-2: “MA[11:9]/GPIO[1:3] Pin Functionality”).
Table 8-2: MA[11:9]/GPIO[1:3] Pin Functionality
S1D13506
X25B-A-001-10
Pin
MD[14] on
Reset
MD[7:6] on
Reset
MA[9]/GPIO3
MA[10]/GPIO1
MA[11]/GPIO2
0
00
GPIO3
GPIO1
GPIO2
0
01
MA9
GPIO1
GPIO2
0
10
MA9
GPIO1
GPIO2
0
11
MA9
MA10
MA11
1
00
GPIO3
GPIO1
VMPEPWR
1
01
MA9
GPIO1
VMPEPWR
1
10
MA9
GPIO1
VMPEPWR
1
11
MA9
MA10
MA11
Hardware Functional Specification
Issue Date: 01/02/06
Epson Research and Development
Vancouver Design Center
Page 127
General IO Pins Control Register
REG[008h]
Reserved
bit 3
Reserved
Reserved
RW
Reserved
GPIO3 Pin
IO Status
GPIO2 Pin
IO Status
GPIO1 Pin
IO Status
Reserved
GPIO3 Pin IO Status
When GPIO3 is configured as an output, writing a 1 to this bit drives GPIO3 high and
writing a 0 to this bit drives GPIO3 low.
When GPIO3 is configured as an input, a read from this bit returns the status of GPIO3.
Note
Note that MD[7:6] must be properly configured at the rising edge of RESET# to enable
GPIO3, otherwise GPIO3 will be used as MA9 for the DRAM and this bit will have no
hardware effect. (See Table 8-2: “MA[11:9]/GPIO[1:3] Pin Functionality”).
bit 2
GPIO2 Pin IO Status
When GPIO2 is configured as an output, writing a 1 to this bit drives GPIO2 high and
writing a 0 to this bit drives GPIO2 low.
When GPIO2 is configured as an input, a read from this bit returns the status of GPIO2.
Note
Note that MD[14] and MD[7:6] must be properly configured at the rising edge of RESET# to enable GPIO2, otherwise GPIO2 will be used as MA11 for the DRAM or as the
MediaPlug VMPEPWR output and this bit will have no hardware effect. (See Table 8-2:
“MA[11:9]/GPIO[1:3] Pin Functionality”).
bit 1
GPIO1 Pin IO Status
When GPIO1 is configured as an output, writing a 1 to this bit drives GPIO1 high and
writing a 0 to this bit drives GPIO1 low.
When GPIO1 is configured as an input, a read from this bit returns the status of GPIO1.
Note
Note that MD[7:6] must be properly configured at the rising edge of RESET# to enable
GPIO1, otherwise GPIO1 will be used as MA10 for the DRAM and this bit will have no
hardware effect. (See Table 8-2: “MA[11:9]/GPIO[1:3] Pin Functionality”).
Hardware Functional Specification
Issue Date: 01/02/06
S1D13506
X25B-A-001-10
Page 128
Epson Research and Development
Vancouver Design Center
8.3.3 MD Configuration Readback Registers
MD Configuration Status Register 0
REG[00Ch]
RO
MD[7]
MD[6]
MD[5]
MD[4]
MD[3]
MD[2]
MD[1]
MD[0]
Config. Status Config. Status Config. Status Config. Status Config. Status Config. Status Config. Status Config. Status
MD Configuration Status Register 1
REG[00Dh]
RO
MD[15]
MD[14]
MD[13]
MD[12]
MD[11]
MD[10]
MD[9]
MD[8]
Config. Status Config. Status Config. Status Config. Status Config. Status Config. Status Config. Status Config. Status
REG[00Ch] bits 7-0
REG[00Dh] bits 7-0
MD[15:0] Configuration Status Bits [15:0]
These read-only bits return the status of MD[15:0] at the rising edge of RESET#.
8.3.4 Clock Configuration Registers
Memory Clock Configuration Register
REG[010h]
n/a
bit 4
n/a
RW
MCLK
Divide Select
n/a
n/a
n/a
n/a
MCLK Source
Select
MCLK Divide Select
When this bit = 1, the internal memory clock frequency is half of the MCLK source frequency.
When this bit = 0, the memory clock frequency is equal to the MCLK source frequency.
The MCLK frequency should always be set to the maximum frequency allowed by the
DRAM. This provides maximum performance and minimizes overall system power
consumption.
bit 0
MCLK Source Select
When this bit = 1, the source for the internal MCLK is derived from BUSCLK.
When this bit = 0, the source for MCLK is derived from CLKI.
Table 8-3: MCLK Source Select
MCLK Source Select
MCLK Source
0
CLKI
1
BUSCLK
Note
The MCLK Divide Select bit must be set to 1 before changing the MCLK Source Select
bit.
Note
For further information on MCLK, refer to Section 20.2, “Clock Descriptions” on page
225.
S1D13506
X25B-A-001-10
Hardware Functional Specification
Issue Date: 01/02/06
Epson Research and Development
Vancouver Design Center
Page 129
LCD Pixel Clock Configuration Register
REG[014h]
n/a
LCD PCLK
Divide Select
Bit 1
n/a
bits 5-4
RW
LCD PCLK
Divide Select
Bit 0
n/a
n/a
LCD PCLK
LCD PCLK
Source Select Source Select
Bit 1
Bit 0
LCD PCLK Divide Select Bits [1:0]
These bits determine the divide used to generate the LCD pixel clock from the LCD pixel
clock source.
Table 8-4: LCD PCLK Divide Selection
LCD PCLK Divide Select Bits
LCD PCLK Source to LCD PCLK Frequency Ratio
00
1:1
01
2:1
10
3:1
11
4:1
bits 1-0
LCD PCLK Source Select Bits [1:0]
These bits determine the source of the LCD pixel clock for the LCD display.
Table 8-5: LCD PCLK Source Selection
LCD PCLK Source Select Bits
LCD PCLK Source
00
CLKI
01
BUSCLK
10
CLKI2
11
MCLK (see note)
Note
MCLK may be a previously divided down version of CLKI, CLKI2 or BUSCLK.
CRT/TV Pixel Clock Configuration Register
REG[018h]
CRT/TV
PCLK 2X
Enable
bit 7
CRT/TV
PCLK Divide
Select Bit 1
n/a
CRT/TV
PCLK Divide
Select Bit 0
RW
n/a
n/a
CRT/TV
PCLK Source
Select Bit 1
CRT/TV
PCLK Source
Select Bit 0
CRT/TV PCLK 2X Enable
This bit multiplies the CRT/TV pixel clock by 2.
This bit must be set to 1 when TV with flicker filter is enabled. See REG[1FCh] bits 2-0.
Hardware Functional Specification
Issue Date: 01/02/06
S1D13506
X25B-A-001-10
Page 130
Epson Research and Development
Vancouver Design Center
bits 5-4
CRT/TV PCLK Divide Select Bits[1:0]
These bits determine the divide used to generate the CRT/TV pixel clock from the
CRT/TV pixel clock source.
Table 8-6: CRT/TV PCLK Divide Selection
CRT/TV PCLK Divide Select Bits
CRT/TV PCLK Source to CRT/TV PCLK
Frequency Ratio
00
1:1
01
2:1
10
3:1
11
4:1
bits 1-0
CRT/TV PCLK Source Select Bits [1:0]
These bits determine the source of the CRT/TV pixel clock for the CRT/TV
display.
Table 8-7: CRT/TV PCLK Source Selection
CRT/TV PCLK Source Select Bits
CRT/TV PCLK Source
00
CLKI
01
BUSCLK
10
CLKI2
11
MCLK (see note)
Note
MCLK may be a previously divided down version of CLKI, CLKI2 or BUSCLK.
MediaPlug Clock Configuration Register
REG[01Ch]
n/a
bits 5-4
n/a
MediaPlug
Clock Divide
Select Bit 1
RW
MediaPlug
Clock Divide
Select Bit 0
n/a
n/a
MediaPlug
Clock Source
Select Bit 1
MediaPlug
Clock Source
Select Bit 0
MediaPlug Clock Divide Select Bits[1:0]
These bits determine the divide used to generate the MediaPlug Clock from the CRT/TV
pixel clock source.
Table 8-8: MediaPlug Clock Divide Selection
S1D13506
X25B-A-001-10
MediaPlug Clock Divide Select Bits
MediaPlug Clock Source to CRT/TV Pixel
Clock Frequency Ratio
00
1:1
01
2:1
10
3:1
11
4:1
Hardware Functional Specification
Issue Date: 01/02/06
Epson Research and Development
Vancouver Design Center
bits 1-0
Page 131
MediaPlug Clock Source Select Bits [1:0]
These bits determine the source of the MediaPlug Clock for the MediaPlug Interface.
See Section 7.7, “MediaPlug Interface Timing” on page 123 for AC Timing.
Table 8-9: Video Clock Source Selection
MediaPlug Clock Source Select Bits
MediaPlug Clock Source
00
CLKI
01
BUSCLK
10
CLKI2
11
MCLK (see note)
Note
MCLK may be a previously divided down version of CLKI, CLKI2 or BUSCLK.
CPU To Memory Wait State Select Register
REG[01Eh]
n/a
bits 1-0
n/a
n/a
RW
n/a
n/a
n/a
CPU to
Memory Wait
State Select
Bit 1
CPU to
Memory Wait
State Select
Bit 0
CPU to Memory Wait State Select Bits [1:0]
These bits are used to optimize the handshaking between the host interface and the memory controller. The bits should be set according to the relationship between BCLK and
MCLK (memory clock).
Note
BCLK can be either BUSCLK or BUSCLK ÷ 2 depending on the setting of MD12 (see
Table 5-6:, “Summary of Power-On/Reset Options,” on pag e39).
Failure to meet the following conditions may lead to system failure which is recoverable
only by RESET.
Table 8-10: Minimum Memory Timing Selection
Wait State Bits [1:0]
Condition
00
no restrictions
01
2 x period (MCLK) - 4ns > period(BCLK)
10
period(MCLK) - 4ns > period(BCLK)
11
Reserved
Hardware Functional Specification
Issue Date: 01/02/06
S1D13506
X25B-A-001-10
Page 132
Epson Research and Development
Vancouver Design Center
8.3.5 Memory Configuration Registers
Memory Configuration Register
REG[020h]
n/a
bits 1-0
n/a
RW
n/a
n/a
n/a
n/a
Memory Type Memory Type
Bit 1
Bit 0
Memory Type Bits [1:0]
These bits specify the memory type.
Table 8-11: Memory Type Selection
Memory Type Bits [1:0]
Memory Type
00
EDO-DRAM with 2-CAS#
01
FPM-DRAM with 2-CAS#
10
EDO-DRAM with 2-WE#
11
FPM-DRAM with 2-WE#
DRAM Refresh Rate Register
REG[021h]
Refresh
Select Bit 1
bits 7-6
Refresh
Select Bit 0
RW
n/a
n/a
DRAM
Refresh Rate
Bit 2
n/a
DRAM
Refresh Rate
Bit 1
DRAM
Refresh Rate
Bit 0
Refresh Select Bits [1:0]
These bits specify the type of DRAM refresh used while in power save mode.
Table 8-12: Refresh Selection
Refresh Select Bits [1:0]
DRAM Refresh Type
00
CBR Refresh
01
Self-Refresh
1X
No Refresh
Note
These bits should not be changed while power save mode is enabled.
S1D13506
X25B-A-001-10
Hardware Functional Specification
Issue Date: 01/02/06
Epson Research and Development
Vancouver Design Center
bits 2-0
Page 133
DRAM Refresh Rate Select Bits [2:0]
These bits specify the divide used to generate the DRAM refresh clock rate, which is equal
to 2(ValueOfTheseBits + 6), from the MCLK source (either BUSCLK or CLKI as determined
by REG[010h] bit 0).
Table 8-13: DRAM Refresh Rate Selection
DRAM Refresh
Rate Bits [2:0]
MCLK Source Divide
Amount
Refresh Rate for 40MHz
MCLK Source
DRAM Refresh
Time/256 cycles
000
64
625 kHz
0.4 ms
001
128
312 kHz
0.8 ms
010
256
156 kHz
1.6 ms
011
512
78 kHz
3.3 ms
100
1024
39 kHz
6.6 ms
101
2048
20 kHz
13.1 ms
110
4096
10 kHz
26.2 ms
111
8192
5 kHz
52.4 ms
Hardware Functional Specification
Issue Date: 01/02/06
S1D13506
X25B-A-001-10
Page 134
Epson Research and Development
Vancouver Design Center
DRAM Timing Control Register 0
REG[02Ah]
RW
DRAM Timing DRAM Timing DRAM Timing DRAM Timing DRAM Timing DRAM Timing DRAM Timing DRAM Timing
Control
Control
Control
Control
Control
Control
Control
Control
Register
Register
Register
Register
Register
Register
Register
Register
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
DRAM Timing Control Register 1
REG[02Bh]
n/a
n/a
REG[02Ah] bits 4-0
REG[02Bh] bits 1-0
RW
n/a
n/a
n/a
n/a
DRAM Timing DRAM Timing
Control
Control
Register
Register
Bit 9
Bit 8
DRAM Timing Control Bits [9:0]
The DRAM Timing Control registers must be set based on the type of DRAM, speed of
DRAM, and MCLK frequency used. The following table provides the optimal values
for each register.
Table 8-14: DRAM Timing Control Selection
DRAM Type
EDO
FPM
S1D13506
X25B-A-001-10
DRAM Speed
(ns)
50
50
60
50
60
70
50
60
70
80
50
60
70
80
50
60
50
60
70
80
MCLK
Frequency
(MHz)
40
33
30
25
20
25
20
DRAM Timing
Control Register 0
DRAM Timing
Control Register 1
01h
01h
01h
12h
01h
00h
12h
12h
01h
00h
12h
12h
12h
01h
12h
01h
12h
12h
11h
01h
01h
01h
01h
02h
01h
00h
02h
02h
01h
01h
02h
02h
02h
01h
02h
01h
02h
02h
02h
01h
Hardware Functional Specification
Issue Date: 01/02/06
Epson Research and Development
Vancouver Design Center
Page 135
8.3.6 Panel Configuration Registers
Panel Type Register
REG[030h]
EL Panel
Mode Enable
RW
Panel Data
Width Bit 1
n/a
Panel Data
Width Bit 0
Panel Data
Format Select
Color/Mono.
Panel Select
Dual/Single
Panel Select
TFT/ Passive
LCD Panel
Select
bit 7
EL Panel Mode Enable
When this bit = 1, the EL Panel support circuit is enabled.
When this bit = 0, there is no hardware effect.
This bit enables the S1D13506 built-in circuit for EL panels which require the Frame Rate
Modulation (FRM) to remain static for one frame after every 262143 frames (approximately 1 hour at 60Hz refresh). When this bit is enabled, the need for external circuitry to
perform the above function is eliminated.
bits 5-4
Panel Data Width Bits [1:0]
These bits select passive LCD/TFT/D-TFD panel data width size.
Table 8-15: Panel Data Width Selection
Panel Data Width Bits [1:0]
Passive LCD Panel Data
Width Size
TFT/D-TFD Panel Data Width
Size
00
4-bit
9-bit
01
8-bit
12-bit
10
16-bit
18-bit (64K color)
11
Reserved
Reserved
bit 3
Panel Data Format Select
When this bit = 1, 8-bit single color passive LCD panel data format 2 is selected. For AC
timing see Section 7.5.5, “Single Color 8-Bit Panel Timing (Format 2)” on page 93.
When this bit = 0, 8-bit single color passive LCD panel data format 1 is selected. For AC
timing see Section 7.5.4, “Single Color 8-Bit Panel Timing (Format 1)” on page 90.
bit 2
Color/Mono Panel Select
When this bit = 1, color LCD panel is selected.
When this bit = 0, monochrome LCD panel is selected.
bit 1
Dual/Single Panel Select
When this bit = 1, dual LCD panel is selected.
When this bit = 0, single LCD panel is selected.
bit 0
TFT/Passive LCD Panel Select
When this bit = 1, TFT/D-TFD panel is selected.
When this bit = 0, passive LCD panel is selected.
Hardware Functional Specification
Issue Date: 01/02/06
S1D13506
X25B-A-001-10
Page 136
Epson Research and Development
Vancouver Design Center
MOD Rate Register
REG[031h]
n/a
bits 5-0
RW
MOD Rate Bit MOD Rate Bit MOD Rate Bit MOD Rate Bit MOD Rate Bit MOD Rate Bit
5
4
3
2
1
0
n/a
MOD Rate Bits [5:0]
For a non-zero value these bits specify the number of FPLINE between toggles of the
MOD output signal (DRDY).
When these bits are all 0’s the MOD output signal toggles every FPFRAME. These bits
are for passive LCD panels only.
LCD Horizontal Display Width Register
REG[032h]
n/a
bits 6-0
RW
LCD
LCD
LCD
LCD
LCD
LCD
LCD
Horizontal
Horizontal
Horizontal
Horizontal
Horizontal
Horizontal
Horizontal
Display Width Display Width Display Width Display Width Display Width Display Width Display Width
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
LCD Horizontal Display Width Bits [6:0]
These bits specify the LCD panel horizontal display width, in 8 pixel resolution.
Horizontal display width in number of pixels = ((ContentsOfThisRegister)+ 1) × 8
The Horizontal Display Width has certain limitations on the values that may be used for
each type of LCD panel. Use of values that do not meet the limitations listed in the
following table will result in undefined behavior.
Table 8-16: Horizontal Display Width (Pixels)
Panel Type
Passive Single
Passive Dual
TFT
Horizontal Display Width (Pixels)
must be divisible by 16
must be divisible by 32
must be divisible by 8
Note
This register must be programmed such that REG[032h] ≥ 3 (32 pixels).
S1D13506
X25B-A-001-10
Hardware Functional Specification
Issue Date: 01/02/06
Epson Research and Development
Vancouver Design Center
Page 137
LCD Horizontal Non-Display Period Register
REG[034h]
n/a
n/a
bits 4-0
n/a
LCD
Horizontal
Non-Display
Period Bit 4
RW
LCD
Horizontal
Non-Display
Period Bit 3
LCD
Horizontal
Non-Display
Period Bit 2
LCD
Horizontal
Non-Display
Period Bit 1
LCD
Horizontal
Non-Display
Period Bit 0
LCD Horizontal Non-Display Period Bits [4:0]
These bits specify the LCD panel horizontal non-display period width in 8 pixel resolution.
Horiz. non-display period width in number of pixels = ((ContentsOfThisRegister) + 1) × 8
Note
This register must be programmed such that REG[032h] ≥ 3 (32 pixels).
Note
For TFT/D-TFD only:
REG[034h] + 1 ≥ (REG[035h] + 1) + (REG[036h] bits 3-0 + 1)
TFT FPLINE Start Position Register
REG[035h]
n/a
bits 4-0
n/a
n/a
RW
TFT FPLINE
Start Position
Bit 4
TFT FPLINE
Start Position
Bit 3
TFT FPLINE
Start Position
Bit 2
TFT FPLINE
Start Position
Bit 1
TFT FPLINE
Start Position
Bit 0
TFT FPLINE Start Position Bits [4:0]
For TFT/D-TFD panel only, these bits specify the delay, in 8 pixel resolution, from the
start of the horizontal non-display period to the leading edge of the FPLINE pulse.
For 4/8 bpp color depth:
FPLINE start position in number of pixels = [(ContentsOfThisRegister) x 8 + 4]
For 15/16 bpp color depth:
FPLINE start position in number of pixels = [(ContentsOfThisRegister) x 8 + 6]
Note
For TFT/D-TFD only:
REG[034h] + 1 ≥ (REG[035h] + 1) + (REG[036h] bits 3-0 + 1)
Hardware Functional Specification
Issue Date: 01/02/06
S1D13506
X25B-A-001-10
Page 138
Epson Research and Development
Vancouver Design Center
TFT FPLINE Pulse Width Register
REG[036h]
LCD FPLINE
Polarity
Select
n/a
bit 7
n/a
RW
TFT FPLINE
Pulse Width
Bit 3
n/a
TFT FPLINE
Pulse Width
Bit 2
TFT FPLINE
Pulse Width
Bit 1
TFT FPLINE
Pulse Width
Bit 0
LCD FPLINE Polarity Select
This bit selects the polarity of FPLINE for all LCD panels.
When this bit = 1, the FPLINE pulse is active high for TFT/D-TFD and active low for passive LCD.
When this bit = 0, the FPLINE pulse is active low for TFT/D-TFD and active high for passive LCD.
Table 8-17: LCD FPLINE Polarity Selection
LCD FPLINE Polarity Select
Passive LCD FPLINE Polarity
TFT FPLINE Polarity
0
active high
active low
1
active low
active high
bits 3-0
TFT FPLINE Pulse Width Bits [3:0]
For TFT/D-TFD panel only, these bits specify the pulse width of the FPLINE output signal in 8 pixel resolution.
FPLINE pulse width in number of pixels = ((ContentsOfThisRegister) + 1) × 8
The maximum FPLINE pulse width is 128 pixels.
Note
For TFT/D-TFD only:
REG[034h] + 1 ≥ (REG[035h] + 1) + (REG[036h] bits 3-0 + 1)
LCD Vertical Display Height Register 0
REG[038h]
LCD Vertical
Display
Height Bit 7
LCD Vertical
Display
Height Bit 6
LCD Vertical
Display
Height Bit 5
RW
LCD Vertical
Display
Height Bit 4
LCD Vertical
Display
Height Bit 3
LCD Vertical
Display
Height Bit 2
LCD Vertical
Display
Height Bit 1
LCD Vertical
Display
Height Bit 0
n/a
LCD Vertical
Display
Height Bit 9
LCD Vertical
Display
Height Bit 8
LCD Vertical Display Height Register 1
REG[039h]
n/a
n/a
n/a
RW
n/a
n/a
REG[038h] bits 7-0
LCD Vertical Display Height Bits [9:0]
REG[039h] bits 1-0
These bits specify the LCD panel vertical display height, in 1 line resolution.
Vertical display height in number of lines = (ContentsOfThisRegister) + 1
S1D13506
X25B-A-001-10
Hardware Functional Specification
Issue Date: 01/02/06
Epson Research and Development
Vancouver Design Center
Page 139
LCD Vertical Non-Display Period Register
REG[03Ah]
LCD Vertical
Non-Display
Period Status
(RO)
LCD Vertical
Non-Display
Period Bit 5
n/a
LCD Vertical
Non-Display
Period Bit 4
RW
LCD Vertical
Non-Display
Period Bit 3
LCD Vertical
Non-Display
Period Bit 2
LCD Vertical
Non-Display
Period Bit 1
LCD Vertical
Non-Display
Period Bit 0
bit 7
LCD Vertical Non-Display Period Status
This is a read-only status bit.
When a read from this bit = 1, a LCD panel vertical non-display period is occurring.
When a read from this bit = 0, the LCD panel output is in a vertical display period.
bits 5-0
LCD Vertical Non-Display Period Bits [5:0]
These bits specify the LCD panel vertical non-display period height in 1 line resolution.
Vertical non-display period height in number of lines = (ContentsOfThisRegister) + 1
Note
For TFT/D-TFD only:
(REG[03Ah] bits 5-0 + 1) ≥ (REG[03Bh] + 1) + (REG[03Ch] bits 2-0 + 1)
TFT FPFRAME Start Position Register
REG[03Bh]
n/a
bits 5-0
TFT
FPFRAME
Start Position
Bit 5
n/a
RW
TFT
FPFRAME
Start Position
Bit 4
TFT
FPFRAME
Start Position
Bit 3
TFT
FPFRAME
Start Position
Bit 2
TFT
FPFRAME
Start Position
Bit 1
TFT
FPFRAME
Start Position
Bit 0
TFT FPFRAME Start Position Bits [5:0]
For TFT/D-TFD panel only, these bits specify the delay in lines from the start of the vertical non-display period to the leading edge of the FPFRAME pulse.
FPFRAME start position in number of lines = (ContentsOfThisRegister) + 1
Note
For TFT/D-TFD only:
(REG[03Ah] bits 5-0 + 1) ≥ (REG[03Bh] + 1) + (REG[03Ch] bits 2-0 + 1)
Hardware Functional Specification
Issue Date: 01/02/06
S1D13506
X25B-A-001-10
Page 140
Epson Research and Development
Vancouver Design Center
TFT FPFRAME Pulse Width Register
REG[03Ch]
LCD
FPFRAME
Polarity
Select
n/a
bit 7
RW
n/a
n/a
n/a
TFT
FPFRAME
Pulse Width
Bit 2
TFT
FPFRAME
Pulse Width
Bit 1
TFT
FPFRAME
Pulse Width
Bit 0
LCD FPFRAME Polarity Select
This bit selects the polarity of FPFRAME for all LCD panels.
When this bit = 1, the FPFRAME pulse is active high for TFT/D-TFD and active low for
passive LCD.
When this bit = 0, the FPFRAME pulse is active low for TFT/D-TFD and active high for
passive LCD.
Table 8-18: LCD FPFRAME Polarity Selection
LCD FPFRAME Polarity Select
Passive LCD FPFRAME
Polarity
TFT FPFRAME Polarity
0
active high
active low
1
active low
active high
bits 2-0
TFT FPFRAME Pulse Width Bits [2:0]
For TFT/D-TFD panel only, these bits specify the pulse width of the FPFRAME output
signal in number of lines.
FPFRAME pulse width in number of lines = (ContentsOfThisRegister) + 1
Note
For TFT/D-TFD only:
(REG[03Ah] bits 5-0 + 1) ≥ (REG[03Bh] + 1) + (REG[03Ch] bits 2-0 + 1)
8.3.7 LCD Display Mode Registers
LCD Display Mode Register
REG[040h]
LCD Display
Blank
bit 7
n/a
RW
n/a
SwivelView™
Enable Bit 1
n/a
LCD Bit-perpixel Select
Bit 2
LCD Bit-perpixel Select
Bit 1
LCD Bit-perpixel Select
Bit 0
LCD Display Blank
When this bit = 1, the LCD display pipeline is disabled and all LCD data outputs are
forced to zero (i.e., the screen is blanked).
When this bit = 0, the LCD display pipeline is enabled.
Note
If a dual panel is used, the Dual Panel Buffer (REG[041h] bit 0) must be disabled (set to
1) before blanking the LCD display.
S1D13506
X25B-A-001-10
Hardware Functional Specification
Issue Date: 01/02/06
Epson Research and Development
Vancouver Design Center
bit 4
Page 141
SwivelView™ Enable Bit 1
When this bit = 1, the LCD display image is rotated 180° clockwise. Please refer to
Section 15, “SwivelView™” on page 201 for application and limitations.
When this bit = 0, there is no hardware effect.
This bit in conjunction with SwivelView™ Enable Bit 0 achieves the following hardware
rotations.
Table 8-19: Setting SwivelView Modes
SwivelView™ Modes
SwivelView Enable Bits
bits 2-0
Normal
SwivelView 90°
SwivelView 180°
SwivelView 270°
SwivelView Enable Bit 0
(REG[1FCh] bit 6)
0
1
0
1
SwivelView Enable Bit 1
(REG[040h] bit 4)
0
0
1
1
LCD Bit-per-pixel Select Bits [2:0]
These bits select the color depth (bit-per-pixel) for the displayed data.
Note
15/16 bpp color depths bypass the LUT. Passive panels are supported up to 32K/64K
colors (4096 colors if dithering disabled, see REG[041h] bit 1). TFT/D-TFD panels are
supported up to 32K/64K colors.
Table 8-20: LCD Bit-per-pixel Selection
Bit-per-pixel Select Bits [1:0]
Color Depth (bpp)
000
Reserved
001
Reserved
010
4 bpp
011
8 bpp
100
15 bpp
101
16 bpp
110-111
Reserved
Hardware Functional Specification
Issue Date: 01/02/06
S1D13506
X25B-A-001-10
Page 142
Epson Research and Development
Vancouver Design Center
LCD Miscellaneous Register
REG[041h]
n/a
bit 1
n/a
RW
n/a
n/a
n/a
n/a
Dithering
Disable
Dual Panel
Buffer Disable
Dithering Disable
When this bit = 1, dithering on the passive LCD panel for 15/16 bpp mode is disabled
allowing a maximum of 4096 colors (212) or 16 gray shades.
When this bit = 0, dithering on the passive LCD panel for 15/16 bpp mode is enabled
allowing a maximum of 64K colors (216) or 64 gray shades.
Note
This bit has no effect in 4/8 bpp modes where dithering is not supported.
All passive STN color panels are controlled using 3 bits for each pixel (RGB) for a total of
8 possible colors. LCD controllers use a combination of Frame Rate Modulation (FRM)
and dithering to achieve more than 8 colors per pixel. FRM can achieve 16 shades of color
for each RGB component resulting in a total of 4096 possible colors (16x16x16). Dithering
uses a 4 pixel square formation and applies a set of 4 hard-coded patterns for each of the 16
shades of color. This expands the original 16 shades of color from the FRM logic to 64
shades per RGB component which results in 256K colors per pixel (64x64x64).
For the S1D13506, 16 bpp is arranged as 5-6-5 RGB. In this mode, when dithering is
enabled, the LUT is bypassed and the original 16-bit data is used as a pointer into the 64
shades per color in the following manner.
(5-6-5 RGB) 32 possible Red, 64 possible Green, 32 possible Blue
This combination of FRM and dithering results in 256K colors/pixel, however, the 16 bpp
limitation of the S1D13506 limits this to 64K colors/pixel.
bit 0
Dual Panel Buffer Disable
This bit is used to disable the Dual Panel Buffer.
When this bit = 1, the Dual Panel Buffer is disabled.
When this bit = 0, the Dual Panel Buffer is enabled.
When a single panel is selected, the Dual Panel Buffer is automatically disabled and this
bit has no effect.
The Dual Panel Buffer is needed to fully support dual panels. Disabling the Dual Panel
Buffer will improve performance, reduce power consumption, and allow higher resolution/ color display modes than would otherwise be possible; however, disabling the Dual
Panel Buffer will reduce image contrast and overall display quality. This mode is not normally used except in special circumstances such as simultaneous display on a CRT/TV
and dual panel LCD. For details on Frame Rate Calculation, see Section 17.
S1D13506
X25B-A-001-10
Hardware Functional Specification
Issue Date: 01/02/06
Epson Research and Development
Vancouver Design Center
Page 143
LCD Display Start Address Register 0
REG[042h]
LCD Display
Start Address
Bit 7
LCD Display
Start Address
Bit 6
LCD Display
Start Address
Bit 5
RW
LCD Display
Start Address
Bit 4
LCD Display
Start Address
Bit 3
LCD Display
Start Address
Bit 2
LCD Display
Start Address
Bit 1
LCD Display Start Address Register 1
REG[043h]
LCD Display
Start Address
Bit 15
LCD Display
Start Address
Bit 14
LCD Display
Start Address
Bit 13
RW
LCD Display
Start Address
Bit 12
LCD Display
Start Address
Bit 11
LCD Display
Start Address
Bit 10
LCD Display
Start Address
Bit 9
LCD Display Start Address Register 2
REG[044h]
n/a
n/a
n/a
LCD Display
Start Address
Bit 0
LCD Display
Start Address
Bit 8
RW
n/a
LCD Display
Start Address
Bit 19
LCD Display
Start Address
Bit 18
LCD Display
Start Address
Bit 17
LCD Display
Start Address
Bit 16
REG[042h] bits 7-0
LCD Display Start Address Bits [19:0]
REG[043h] bits 7-0
This register forms the 20-bit address for the starting word of the LCD image in the display buffer.
REG[044h] bits 3-0
Note that this is a word address. An entry of 00000h into these registers represents the
first word of display memory, an entry of 00001h represents the second word of the display memory, and so on.
LCD Memory Address Offset Register 0
REG[046h]
LCD Memory
Address
Offset Bit 7
LCD Memory
Address
Offset Bit 6
LCD Memory
Address
Offset Bit 5
RW
LCD Memory
Address
Offset Bit 4
LCD Memory
Address
Offset Bit 3
LCD Memory
Address
Offset Bit 2
LCD Memory
Address
Offset Bit 1
LCD Memory
Address
Offset Bit 0
n/a
LCD Memory
Address
Offset Bit 10
LCD Memory
Address
Offset Bit 9
LCD Memory
Address
Offset Bit 8
LCD Memory Address Offset Register 1
REG[047h]
n/a
REG[046h] bits 7-0
REG[047h] bits 2-0
n/a
n/a
RW
n/a
LCD Memory Address Offset Bits [10:0]
These bits are the LCD display’s 11-bit address offset from the starting word of line “n” to
the starting word of line “n + 1”.
A virtual image can be formed by setting this register to a value greater than the width of
the display. The displayed image is a window into the larger virtual image.
Hardware Functional Specification
Issue Date: 01/02/06
S1D13506
X25B-A-001-10
Page 144
Epson Research and Development
Vancouver Design Center
LCD Pixel Panning Register
REG[048h]
n/a
n/a
RW
n/a
n/a
Reserved
Reserved
LCD Pixel
Panning Bit 1
LCD Pixel
Panning Bit 0
bits 3-2
Reserved.
Must be set to 0.
bits 1-0
LCD Pixel Panning Bits [1:0]
This register is used to control the horizontal pixel panning of the LCD display. The display can be panned to the left by programming its respective Pixel Panning Bits to a nonzero value. This value represents the number of pixels panned. The maximum pan value is
dependent on the display mode as shown in the table below.
Table 8-21: LCD Pixel Panning Selection
Color Depth (bpp)
Screen 2 Pixel Panning Bits Used
4 bpp
Bits [1:0]
8 bpp
Bit 0
15/16 bpp
---
Smooth horizontal panning can be achieved by a combination of this register and the LCD
Display Start Address register.
LCD Display FIFO High Threshold Control Register
REG[04Ah]
n/a
bits 5-0
LCD Display
FIFO High
Threshold
Bit 5
n/a
LCD Display
FIFO High
Threshold
Bit 4
RW
LCD Display
FIFO High
Threshold
Bit 3
LCD Display
FIFO High
Threshold
Bit 2
LCD Display
FIFO High
Threshold
Bit 1
LCD Display
FIFO High
Threshold
Bit 0
LCD Display FIFO High Threshold Bits [5:0]
These bits are used to optimize the display memory request arbitration. When this register
is set to 00h, the threshold is automatically set in hardware. However, programming may
be required if screen corruption is present (see Section 18.2, “Example Frame Rates” on
page 216).
Note
This register does not need to be used in single display modes and may only be required
in some display modes where two displays are active (see Section 16.2, “Bandwidth
Limitation” on page 211).
S1D13506
X25B-A-001-10
Hardware Functional Specification
Issue Date: 01/02/06
Epson Research and Development
Vancouver Design Center
Page 145
LCD Display FIFO Low Threshold Control Register
REG[04Bh]
n/a
LCD Display
FIFO Low
Threshold
Bit 5
n/a
bits 5-0
LCD Display
FIFO Low
Threshold
Bit 4
RW
LCD Display
FIFO Low
Threshold
Bit 3
LCD Display
FIFO Low
Threshold
Bit 2
LCD Display
FIFO Low
Threshold
Bit 1
LCD Display
FIFO Low
Threshold
Bit 0
LCD Display FIFO Low Threshold Bits [5:0]
When this register is set to 00h, the threshold is automatically set in hardware. If it
becomes necessary to adjust REG[04Ah] from its default value, then the following
formula must be maintained:
REG[04Bh] > REG[04Ah] and REG[04Bh] ≤ 3Ch
8.3.8 CRT/TV Configuration Registers
CRT/TV Horizontal Display Width Register
REG[050h]
n/a
RW
CRT/TV
CRT/TV
CRT/TV
CRT/TV
CRT/TV
CRT/TV
CRT/TV
Horizontal
Horizontal
Horizontal
Horizontal
Horizontal
Horizontal
Horizontal
Display Width Display Width Display Width Display Width Display Width Display Width Display Width
Bit 0
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
bits 6-0
CRT/TV Horizontal Display Width Bits [6:0]
These bits specify the CRT/TV horizontal display width, in 8 pixel resolution.
Horizontal display width in number of pixels = ((ContentsOfThisRegister)+ 1) × 8
CRT/TV Horizontal Non-Display Period Register
REG[052h]
n/a
bits 5-0
CRT/TV
Horizontal
Non-Display
Period Bit 5
n/a
CRT/TV
Horizontal
Non-Display
Period Bit 4
RW
CRT/TV
Horizontal
Non-Display
Period Bit 3
CRT/TV
Horizontal
Non-Display
Period Bit 2
CRT/TV
Horizontal
Non-Display
Period Bit 1
CRT/TV
Horizontal
Non-Display
Period Bit 0
CRT/TV Horizontal Non-Display Period Bits [5:0]
These bits specify the CRT/TV horizontal non-display period width in 8 pixel resolution.
Horizontal non-display period width in number of pixels =
((ContentsOfThisRegister) + 1) × 8 for CRT mode
(ContentsOfThisRegister) × 8 + 6 for TV mode with NTSC output
(ContentsOfThisRegister) × 8 + 7 for TV mode with PAL output
Note
For CRT mode, the recommended minimum value which should be programmed into
this register is 3 (32 pixels).
Note
REG[052h] + 1 ≥ (REG[053h] + 1) + (REG[054h] bits 3-0 + 1)
Hardware Functional Specification
Issue Date: 01/02/06
S1D13506
X25B-A-001-10
Page 146
Epson Research and Development
Vancouver Design Center
CRT/TV HRTC Start Position Register
REG[053h]
n/a
CRT/TV
HRTC Start
Position Bit 5
n/a
bits 5-0
RW
CRT/TV
HRTC Start
Position Bit 4
CRT/TV
HRTC Start
Position Bit 3
CRT/TV
HRTC Start
Position Bit 2
CRT/TV
HRTC Start
Position Bit 1
CRT/TV
HRTC Start
Position Bit 0
CRT/TV HRTC Start Position Bits [5:0]
For CRT/TV, these bits specify the delay, in 8 pixel resolution, from the start of the horizontal non-display period to the leading edge of the HRTC pulse.
The following equations can be used to determine the HRTC start position in number of
pixels for each display type:
HRTC start position in number of pixels=:
[(ContentsOfThisRegister) x 8 + 3] for CRT with 4/8 bpp color depth
[(ContentsOfThisRegister) x 8 + 5] for CRT in 15/16 bpp color depth
[((ContentsOfThisRegister) + 1) x 8 - 7] for TV-NTSC in 4/8 bpp color depth
[((ContentsOfThisRegister) + 1) x 8 - 5] for TV-NTSC in 15/16 bpp color depth
[((ContentsOfThisRegister) + 1) x 8 - 7] for TV-PAL in 4/8 bpp color depth
[((ContentsOfThisRegister) + 1) x 8 - 5] for TV-PAL in 15/16 bpp color depth
Note
REG[052h] + 1 ≥ (REG[053h] + 1) + (REG[054h] bits 3-0 + 1)
CRT HRTC Pulse Width Register
REG[054h]
CRT HRTC
Polarity
Select
bit 7
n/a
n/a
RW
n/a
CRT HRTC
Pulse Width
Bit 3
CRT HRTC
Pulse Width
Bit 2
CRT HRTC
Pulse Width
Bit 1
CRT HRTC
Pulse Width
Bit 0
CRT HRTC Polarity Select
This bit selects the polarity of HRTC for CRTs.
When this bit = 1, the HRTC pulse is active high.
When this bit = 0, the HRTC pulse is active low.
Note
For NTSC/PAL modes, this bit must be set to 0b.
bits 3-0
CRT HRTC Pulse Width Bits [3:0]
These bits specify the pulse width of the CRT HRTC output signal in 8 pixel resolution.
HRTC pulse width in number of pixels = ((ContentsOfThisRegister) + 1) × 8
Note
For NTSC/PAL modes, these bits must be set to 0000b.
Note
REG[052h] + 1 ≥ (REG[053h] + 1) + (REG[054h] bits 3-0 + 1)
S1D13506
X25B-A-001-10
Hardware Functional Specification
Issue Date: 01/02/06
Epson Research and Development
Vancouver Design Center
Page 147
CRT/TV Vertical Display Height Register 0
REG[056h]
CRT/TV
Vertical
Display
Height Bit 7
CRT/TV
Vertical
Display
Height Bit 6
CRT/TV
Vertical
Display
Height Bit 5
RW
CRT/TV
Vertical
Display
Height Bit 4
CRT/TV
Vertical
Display
Height Bit 3
CRT/TV
Vertical
Display
Height Bit 2
CRT/TV
Vertical
Display
Height Bit 1
CRT/TV
Vertical
Display
Height Bit 0
CRT/TV Vertical Display Height Register 1
REG[057h]
n/a
n/a
n/a
RW
n/a
n/a
n/a
CRT/TV
Vertical
Display
Height Bit 9
REG[056h] bits 7-0
CRT/TV Vertical Display Height Bits [9:0]
REG[057h] bits 1-0
These bits specify the CRT/TV vertical display height, in 1 line resolution.
CRT/TV
Vertical
Display
Height Bit 8
Vertical display height in number of lines = (ContentsOfThisRegister) + 1
CRT/TV Vertical Non-Display Period Register
REG[058h]
CRT/TV
Vertical NonDisplay
Period Status
(RO)
CRT/TV
Vertical NonDisplay
Period Bit 6
CRT/TV
Vertical NonDisplay
Period Bit 5
CRT/TV
Vertical NonDisplay
Period Bit 4
RW
CRT/TV
Vertical NonDisplay
Period Bit 3
CRT/TV
Vertical NonDisplay
Period Bit 2
CRT/TV
Vertical NonDisplay
Period Bit 1
CRT/TV
Vertical NonDisplay
Period Bit 0
bit 7
CRT/TV Vertical Non-Display Period Status
This is a read-only status bit.
When a read from this bit = 1, a CRT/TV vertical non-display period is occurring.
When a read from this bit = 0, the CRT/TV output is in a vertical display period.
bits 6-0
CRT/TV Vertical Non-Display Period Bits [6:0]
These bits specify the CRT/TV vertical non-display period height in 1 line resolution.
Vertical non-display period height in number of lines = (ContentsOfThisRegister) + 1
Note
(REG[058h] bits 5-0 + 1) ≥ (REG[059h] + 1) + (REG[05Ah] bits 2-0 + 1)
Hardware Functional Specification
Issue Date: 01/02/06
S1D13506
X25B-A-001-10
Page 148
Epson Research and Development
Vancouver Design Center
CRT/TV VRTC Start Position Register
REG[059h]
n/a
CRT/TV
VRTC Start
Position Bit 6
bits 6-0
CRT/TV
VRTC Start
Position Bit 5
RW
CRT/TV
VRTC Start
Position Bit 4
CRT/TV
VRTC Start
Position Bit 3
CRT/TV
VRTC Start
Position Bit 2
CRT/TV
VRTC Start
Position Bit 1
CRT/TV
VRTC Start
Position Bit 0
CRT/TV VRTC Start Position Bits [6:0]
For CRT/TV, these bits specify the delay in lines from the start of the vertical non-display
period to the leading edge of the VRTC pulse.
VRTC start position in number of lines = (ContentsOfThisRegister) + 1
Note
(REG[058h] bits 5-0 + 1) ≥ (REG[059h] + 1) + (REG[05Ah] bits 2-0 + 1)
CRT/TV VRTC Pulse Width Register
REG[05Ah]
CRT VRTC
Polarity
Select
bit 7
n/a
n/a
RW
n/a
n/a
CRT VRTC
Pulse Width
Bit 2
CRT VRTC
Pulse Width
Bit 1
CRT VRTC
Pulse Width
Bit 0
CRT VRTC Polarity Select
This bit selects the polarity of VRTC for CRT.
When this bit = 1, the VRTC pulse is active high.
When this bit = 0, the VRTC pulse is active low.
Note
For PAL/NTSC, this bit must be set to 0b.
bits 2-0
CRT VRTC Pulse Width Bits [2:0]
These bits specify the pulse width of the CRT VRTC output signal in number of lines.
VRTC pulse width in number of lines = (ContentsOfThisRegister) + 1
Note
For NTSC/PAL modes, these bits should be set to 000b.
Note
(REG[058h] bits 5-0 + 1) ≥ (REG[059h] + 1) + (REG[05Ah] bits 2-0 + 1)
S1D13506
X25B-A-001-10
Hardware Functional Specification
Issue Date: 01/02/06
Epson Research and Development
Vancouver Design Center
Page 149
CRT/TV Output Control Register
REG[05Bh]
n/a
RW
TV
Chrominance
Filter Enable
n/a
TV
Luminance
Filter Enable
DAC Output
Level Select
n/a
TV S-Video/
TV
Composite
PAL/NTSC
Output Select Output Select
bit 5
TV Chrominance Filter Enable
When this bit = 1, the TV chrominance filter is enabled.
When this bit = 0, there is no hardware effect.
The chrominance filter adjusts the color of the TV by limiting the bandwidth of the
chrominance signal (reducing cross-luminance distortion). This reduces the “ragged
edges” seen at boundaries between sharp color transitions. This filter is most useful for
composite video output.
bit 4
TV Luminance Filter Enable
When this bit = 1, the TV luminance filter is enabled.
When this bit = 0, there is no hardware effect.
The luminance filter adjusts the brightness of the TV by limiting the bandwidth of the
luminance signal (reducing cross-chrominance distortion). This reduces the “rainbowlike” colors at boundaries between sharp luminance transitions. This filter is most useful
for composite video output.
bit 3
DAC Output Level Select
This bit should be set based on the conditions in the following table. When this bit is set to
1 it allows IREF to be reduced. For an example implementation of the required external
CRT/TV circuitry, see Figure 5-2: “External Circuitry for CRT/TV Interface,” on page 44.
Table 8-22: DAC Output Level Selection
LCD
Supported
x
x
CRT
Not Supported
Supported
Supported
x
TV
Not Supported
Not Supported
Supported
REG[05Bh] bit 3
x
1
0
IREF (mA)
x
4.6
9.2
= don’t care
bit 1
TV S-Video/Composite Output Select
When this bit = 1, S-Video TV signal output is selected.
When this bit = 0, Composite TV signal output is selected.
bit 0
TV PAL/NTSC Output Select
When this bit = 1, PAL format TV signal output is selected.
When this bit = 0, NTSC format TV signal output is selected.
This bit must be set to 0 when CRT mode is enabled.
Hardware Functional Specification
Issue Date: 01/02/06
S1D13506
X25B-A-001-10
Page 150
Epson Research and Development
Vancouver Design Center
8.3.9 CRT/TV Display Mode Registers
CRT/TV Display Mode Register
REG[060h]
CRT/TV
Display Blank
n/a
RW
n/a
n/a
n/a
CRT/TV Bitper-pixel
Select Bit 2
CRT/TV Bitper-pixel
Select Bit 1
CRT/TV Bitper-pixel
Select Bit 0
bit 7
CRT/TV Display Blank
When this bit = 1 the CRT/TV display pipeline is disabled and all CRT/TV data outputs
are forced to zero (i.e., the screen is blanked).
When this bit = 0 the CRT/TV display pipeline is enabled.
bits 2-0
CRT/TV Bit-per-pixel Select Bits [2:0]
These bits select the bit-per-pixel for the displayed data.
Note
15/16 bpp color depths bypass the LUT.
Table 8-23: CRT/TV Bit-per-pixel Selection
S1D13506
X25B-A-001-10
Bit-per-pixel Select Bits [2:0]
Color Depth (bpp)
000
Reserved
001
Reserved
010
4 bpp
011
8 bpp
100
15 bpp
101
16 bpp
110-111
Reserved
Hardware Functional Specification
Issue Date: 01/02/06
Epson Research and Development
Vancouver Design Center
Page 151
CRT/TV Display Start Address Register 0
REG[062h]
CRT/TV
Display Start
Address
Bit 7
CRT/TV
Display Start
Address
Bit 6
CRT/TV
Display Start
Address
Bit 5
RW
CRT/TV
Display Start
Address
Bit 4
CRT/TV
Display Start
Address
Bit 3
CRT/TV
Display Start
Address
Bit 2
CRT/TV
Display Start
Address
Bit 1
CRT/TV Display Start Address Register 1
REG[063h]
CRT/TV
Display Start
Address
Bit 15
CRT/TV
Display Start
Address
Bit 14
CRT/TV
Display Start
Address
Bit 13
RW
CRT/TV
Display Start
Address
Bit 12
CRT/TV
Display Start
Address
Bit 11
CRT/TV
Display Start
Address
Bit 10
CRT/TV
Display Start
Address
Bit 9
CRT/TV
Display Start
Address
Bit 8
CRT/TV
Display Start
Address
Bit 19
CRT/TV
Display Start
Address
Bit 18
CRT/TV
Display Start
Address
Bit 17
CRT/TV
Display Start
Address
Bit 16
CRT/TV Display Start Address Register 2
REG[064h]
n/a
n/a
REG[062h] bits 7-0
REG[063h] bits 7-0
RW
n/a
n/a
CRT/TV Start Address Bits [19:0]
This register forms the 20-bit address for the starting word of the CRT/TV image in the
display buffer. Note that this is a word address. An entry of 00000h into these registers
represents the first word of display memory, an entry of 00001h represents the second
word of the display memory, and so on.
REG[064h] bits 3-0
CRT/TV Memory Address Offset Register 0
REG[066h]
CRT/TV
Memory
Address
Offset Bit 7
CRT/TV
Memory
Address
Offset Bit 6
CRT/TV
Memory
Address
Offset Bit 5
RW
CRT/TV
Memory
Address
Offset Bit 4
CRT/TV
Memory
Address
Offset Bit 3
CRT/TV
Memory
Address
Offset Bit 2
CRT/TV
Memory
Address
Offset Bit 1
CRT/TV Memory Address Offset Register 1
REG[067h]
n/a
REG[066h] bits 7-0
REG[067h] bits 2-0
CRT/TV
Display Start
Address
Bit 0
n/a
n/a
CRT/TV
Memory
Address
Offset Bit 0
RW
n/a
n/a
CRT/TV
Memory
Address
Offset Bit 10
CRT/TV
Memory
Address
Offset Bit 9
CRT/TV
Memory
Address
Offset Bit 8
CRT/TV Memory Address Offset Bits [10:0]
These bits are the CRT/TV display’s 11-bit address offset from the starting word of line
“n” to the starting word of line “n + 1”. A virtual image can be formed by setting this
register to a value greater than the width of the display. The displayed image is a window
into the larger virtual image.
Hardware Functional Specification
Issue Date: 01/02/06
S1D13506
X25B-A-001-10
Page 152
Epson Research and Development
Vancouver Design Center
CRT/TV Pixel Panning Register
REG[068h]
n/a
n/a
RW
n/a
n/a
Reserved
Reserved
CRT/TV Pixel
Panning Bit 1
CRT/TV Pixel
Panning Bit 0
bits 3-2
Reserved.
Must be set to 0.
bits 1-0
CRT/TV Pixel Panning Bits [1:0]
This register is used to control the horizontal pixel panning of the CRT/TV display. The
display can be panned to the left by programming its respective Pixel Panning Bits to a
non-zero value. This value represents the number of pixels panned. The maximum pan
value is dependent on the display mode as shown in the table below.
Table 8-24: CRT/TV Pixel Panning Selection
Color Depth (bpp)
Screen 2 Pixel Panning Bits Used
4 bpp
Bits [1:0]
8 bpp
Bit 0
15/16 bpp
---
Smooth horizontal panning can be achieved by a combination of this register and the
CRT/TV Display Start Address register.
CRT/TV Display FIFO High Threshold Control Register
REG[06Ah]
n/a
bits 5-0
CRT/TV
Display FIFO
High
Threshold
Bit 5
n/a
CRT/TV
Display FIFO
High
Threshold
Bit 4
CRT/TV
Display FIFO
High
Threshold
Bit 3
RW
CRT/TV
Display FIFO
High
Threshold
Bit 2
CRT/TV
Display FIFO
High
Threshold
Bit 1
CRT/TV
Display FIFO
High
Threshold
Bit 0
CRT/TV Display FIFO High Threshold Bits [5:0]
These bits are used to optimize the display memory request arbitration. When this register
is set to 00h, the threshold is automatically set in hardware. However, programming may
be required if screen corruption is present (see Section 18.2, “Example Frame Rates” on
page 216).
Note
This register does not need to be used in single display modes and may only be required
in some display modes where two displays are active (see Section 16.2, “Bandwidth
Limitation” on page 211).
S1D13506
X25B-A-001-10
Hardware Functional Specification
Issue Date: 01/02/06
Epson Research and Development
Vancouver Design Center
Page 153
CRT/TV Display FIFO Low Threshold Control Register
REG[06Bh]
n/a
CRT/TV
Display FIFO
Low
Threshold
Bit 5
n/a
bits 5-0
CRT/TV
Display FIFO
Low
Threshold
Bit 4
RW
CRT/TV
Display FIFO
Low
Threshold
Bit 3
CRT/TV
Display FIFO
Low
Threshold
Bit 2
CRT/TV
Display FIFO
Low
Threshold
Bit 1
CRT/TV
Display FIFO
Low
Threshold
Bit 0
CRT/TV Display FIFO Low Threshold Bits [5:0]
When this register is set to 00h, the threshold is automatically set in hardware. If it
becomes necessary to adjust REG[04Ah] from its default value, then the following
formula must be maintained:
REG[04Bh] > REG[04Ah] and REG[04Bh] ≤ 3Ch
8.3.10 LCD Ink/Cursor Registers
LCD Ink/Cursor Control Register
REG[070h]
n/a
bits 1-0
n/a
RW
n/a
n/a
n/a
n/a
LCD
Ink/Cursor
Mode
Bit 1
LCD
Ink/Cursor
Mode
Bit 0
LCD Ink/Cursor Control Bits [1:0]
These bits enable the LCD Ink/Cursor circuitry.
Table 8-25: LCD Ink/Cursor Selection
LCD Ink/Cursor Bits [1:0]
Mode
00
Inactive
01
Cursor
10
Ink
11
Reserved
Note
While in Ink mode, the Cursor X & Y Position registers must be set to 00h.
Hardware Functional Specification
Issue Date: 01/02/06
S1D13506
X25B-A-001-10
Page 154
Epson Research and Development
Vancouver Design Center
LCD Ink/Cursor Start Address Register
REG[071h]
RW
LCD
LCD
LCD
LCD
LCD
LCD
LCD
LCD
Ink/Cursor
Ink/Cursor
Ink/Cursor
Ink/Cursor
Ink/Cursor
Ink/Cursor
Ink/Cursor
Ink/Cursor
Start Address Start Address Start Address Start Address Start Address Start Address Start Address Start Address
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
bits 7-0
LCD Ink/Cursor Start Address Bits [7:0]
Encoded bits defining the start address for the LCD Ink/Cursor. For Cursor modes, a start
address of 0 should be valid for most applications. For Ink or special Cursor modes, the
start address should be set at an address location that does not conflict with the display
memory of Dual Panel Buffer, which always takes the top M memory locations in bytes,
where
M = (Panel Height x Panel Width / 16) x c, c = 1 for monochrome, 4 for color panel.
Table 8-26: LCD Ink/Cursor Start Address Encoding
LCD Ink/Cursor Start Address Bits [7:0]
Start Address
0
Memory Size - 1024
n = 255...1
Memory Size - n x 8192
Note
The effect of this register takes place at the next LCD vertical non-display period.
Note
See Section 10, “Display Buffer” on page 182 for display buffer organization.
LCD Cursor X Position Register 0
REG[072h]
RW
LCD Cursor X LCD Cursor X LCD Cursor X LCD Cursor X LCD Cursor X LCD Cursor X LCD Cursor X LCD Cursor X
Position
Position
Position
Position
Position
Position
Position
Position
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
LCD Cursor X Position Register 1
REG[073h]
LCD Cursor X
Sign
n/a
n/a
RW
n/a
n/a
n/a
LCD Cursor X LCD Cursor X
Position
Position
Bit 9
Bit 8
REG[073h] bit 7
LCD Cursor X Sign
When this bit = 1, it defines the LCD Cursor X Position register to be a negative number.
The negative number shall not exceed 63 decimal.
When this bit = 0, it defines the LCD Cursor X Position register to be a positive number.
REG[072h] bits 7-0
REG[073h] bits 1-0
LCD Cursor X Position Bits [9:0]
A 10-bit register that defines the horizontal position of the LCD Cursor’s top left hand
corner in pixel units. This register is only valid when Cursor has been selected in the LCD
Ink/Cursor select registers.
S1D13506
X25B-A-001-10
Hardware Functional Specification
Issue Date: 01/02/06
Epson Research and Development
Vancouver Design Center
Page 155
LCD Cursor Y Position Register 0
REG[074h]
RW
LCD Cursor Y LCD Cursor Y LCD Cursor Y LCD Cursor Y LCD Cursor Y LCD Cursor Y LCD Cursor Y LCD Cursor Y
Position
Position
Position
Position
Position
Position
Position
Position
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
LCD Cursor Y Position Register 1
REG[075h]
LCD Cursor Y
Sign
n/a
n/a
RW
n/a
n/a
n/a
LCD Cursor Y LCD Cursor Y
Position
Position
Bit 9
Bit 8
REG[075h] bit 7
LCD Cursor Y Sign
When this bit = 1, it defines the LCD Cursor Y Position register to be a negative number.
The negative number shall not exceed 63 decimal.
When this bit = 0, it defines the LCD Cursor Y Position register to be a positive number.
REG[074h] bits 7-0
REG[075h] bits 1-0
LCD Cursor Y Position Bits [9:0]
A 10-bit register that defines the vertical position of the LCD Cursor’s top left hand corner
in pixel units. This register is only valid when Cursor has been selected in the LCD
Ink/Cursor select registers.
Note
The effect of REG[072h] through REG[074h] takes place only after REG[075h] is written and at the next LCD vertical non-display period.The effect of REG[075h] takes
place at the next LCD vertical non-display period.
LCD Ink/Cursor Blue Color 0 Register
REG[076h]
n/a
n/a
bits 4-0
n/a
RW
LCD
Ink/Cursor
Blue Color 0
Bit 4
LCD
Ink/Cursor
Blue Color 0
Bit 3
LCD
Ink/Cursor
Blue Color 0
Bit 2
bits 5-0
LCD
Ink/Cursor
Blue Color 0
Bit 0
LCD Ink/Cursor Blue Color 0 Bits[4:0]
These bits define the blue LCD Ink/Cursor color 0.
LCD Ink/Cursor Green Color 0 Register
REG[077h]
n/a
LCD
Ink/Cursor
Blue Color 0
Bit 1
RW
LCD
LCD
LCD
LCD
LCD
LCD
Ink/Cursor
Ink/Cursor
Ink/Cursor
Ink/Cursor
Ink/Cursor
Ink/Cursor
Green Color 0 Green Color 0 Green Color 0 Green Color 0 Green Color 0 Green Color 0
Bit 3
Bit 2
Bit 1
Bit 0
Bit 5
Bit 4
n/a
LCD Ink/Cursor Green Color 0 Bits[5:0]
These bits define the green LCD ink/Cursor color 0.
Hardware Functional Specification
Issue Date: 01/02/06
S1D13506
X25B-A-001-10
Page 156
Epson Research and Development
Vancouver Design Center
LCD Ink/Cursor Red Color 0 Register
REG[078h]
n/a
n/a
bits 4-0
n/a
RW
LCD
Ink/Cursor
Red Color 0
Bit 4
LCD
Ink/Cursor
Red Color 0
Bit 3
LCD
Ink/Cursor
Red Color 0
Bit 2
LCD
Ink/Cursor
Red Color 0
Bit 1
LCD Ink/Cursor Red Color 0 Bits[4:0]
These bits define the red LCD Ink/Cursor color 0.
LCD Ink/Cursor Blue Color 1 Register
REG[07Ah]
n/a
n/a
bits 4-0
n/a
RW
LCD
Ink/Cursor
Blue Color 1
Bit 4
LCD
Ink/Cursor
Blue Color 1
Bit 3
LCD
Ink/Cursor
Blue Color 1
Bit 2
LCD
Ink/Cursor
Blue Color 1
Bit 1
n/a
bits 5-0
RW
LCD
LCD
LCD
LCD
LCD
LCD
Ink/Cursor
Ink/Cursor
Ink/Cursor
Ink/Cursor
Ink/Cursor
Ink/Cursor
Green Color 1 Green Color 1 Green Color 1 Green Color 1 Green Color 1 Green Color 1
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
LCD Ink/Cursor Green Color 1 Bits[5:0]
These bits define the green LCD Ink/Cursor color 1.
LCD Ink/Cursor Red Color 1 Register
REG[07Ch]
n/a
bits 4-0
S1D13506
X25B-A-001-10
LCD
Ink/Cursor
Blue Color 1
Bit 0
LCD Ink/Cursor Blue Color 1 Bits[4:0]
These bits define the blue LCD Ink/Cursor color 1.
LCD Ink/Cursor Green Color 1 Register
REG[07Bh]
n/a
LCD
Ink/Cursor
Red Color 0
Bit 0
n/a
n/a
RW
LCD
Ink/Cursor
Red Color 1
Bit 4
LCD
Ink/Cursor
Red Color 1
Bit 3
LCD
Ink/Cursor
Red Color 1
Bit 2
LCD
Ink/Cursor
Red Color 1
Bit 1
LCD
Ink/Cursor
Red Color 1
Bit 0
LCD Ink/Cursor Red Color 1 Bits[4:0]
These bits define the red LCD Ink/Cursor color 1.
Hardware Functional Specification
Issue Date: 01/02/06
Epson Research and Development
Vancouver Design Center
Page 157
LCD Ink/Cursor FIFO High Threshold Register
REG[07Eh]
n/a
n/a
bits 5-0
n/a
n/a
RW
LCD
Ink/Cursor
FIFO High
Threshold
Bit 3
LCD
Ink/Cursor
FIFO High
Threshold
Bit 2
LCD
Ink/Cursor
FIFO High
Threshold
Bit 1
LCD
Ink/Cursor
FIFO High
Threshold
Bit 0
LCD Ink/Cursor FIFO High Threshold Bits [3:0]
These bits are used to optimize the display memory request arbitration for the Hardware
Cursor/Ink Layer. When this register is set to 00h, the threshold is automatically set in
hardware.
8.3.11 CRT/TV Ink/Cursor Registers
CRT/TV Ink/Cursor Control Register
REG[080h]
n/a
bits 1-0
n/a
n/a
RW
n/a
n/a
n/a
CRT/TV
Ink/Cursor
Mode
Bit 1
CRT/TV
Ink/Cursor
Mode
Bit 0
CRT/TV Ink/Cursor Control Bits [1:0]
These bits enable the CRT/TV Ink/Cursor circuitry.
Table 8-27: CRT/TV Ink/Cursor Selection
CRT/TV Ink/Cursor Bits [1:0]
Mode
00
Inactive
01
Cursor
10
Ink
11
Reserved
Note
During Ink mode, the Cursor X & Y Position registers must be programmed to zero.
Hardware Functional Specification
Issue Date: 01/02/06
S1D13506
X25B-A-001-10
Page 158
Epson Research and Development
Vancouver Design Center
CRT/TV Ink/Cursor Start Address Register
REG[081h]
RW
CRT/TV
CRT/TV
CRT/TV
CRT/TV
CRT/TV
CRT/TV
CRT/TV
CRT/TV
Ink/Cursor
Ink/Cursor
Ink/Cursor
Ink/Cursor
Ink/Cursor
Ink/Cursor
Ink/Cursor
Ink/Cursor
Start Address Start Address Start Address Start Address Start Address Start Address Start Address Start Address
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
bits 7-0
CRT/TV Ink/Cursor Start Address Bits [7:0]
Encoded bits defining the start address for the CRT/TV Ink/Cursor. For Cursor modes, a
start address of 0 should be valid for most applications. For Ink or special Cursor modes,
the start address should be set at an address location that does not conflict with the display
memory of Dual Panel Buffer, which always takes the top M memory locations in bytes,
where
M = (Panel Height x Panel Width / 16) x c, c = 1 for monochrome, 4 for color panel.
Table 8-28: CRT/TV Ink/Cursor Start Address Encoding
CRT/TV Ink/Cursor Start Address Bits [7:0]
Start Address
0
Memory Size - 1024
n = 255...1
Memory Size - n x 8192
Note
The effect of this register takes place at the next CRT/TV vertical non-display period.
Note
See Section 10, “Display Buffer” on page 182 for display buffer organization.
CRT/TV Cursor X Position Register 0
REG[082h]
CRT/TV
Cursor X
Position Bit 7
CRT/TV
Cursor X
Position Bit 6
CRT/TV
Cursor X
Position Bit 5
RW
CRT/TV
Cursor X
Position Bit 4
CRT/TV
Cursor X
Position Bit 3
CRT/TV
Cursor X
Position Bit 2
CRT/TV
Cursor X
Position Bit 1
CRT/TV Cursor X Position Register 1
REG[083h]
CRT/TV
Cursor X Sign
REG[083h] bit 7
S1D13506
X25B-A-001-10
n/a
n/a
CRT/TV
Cursor X
Position Bit 0
RW
n/a
n/a
n/a
CRT/TV
Cursor X
Position Bit 9
CRT/TV
Cursor X
Position Bit 8
CRT/TV Cursor X Sign
When this bit = 1, it defines the CRT/TV Cursor X Position register to be a negative number. The negative number shall not exceed 63 decimal.
When this bit = 0, it defines the CRT/TV Cursor X Position register to be a positive number.
Hardware Functional Specification
Issue Date: 01/02/06
Epson Research and Development
Vancouver Design Center
REG[082h] bits 7-0
REG[083h] bits 1-0
Page 159
CRT/TV Cursor X Position Bits [9:0]
A 10-bit register that defines the horizontal position of the CRT/TV Cursor’s top left hand
corner in pixel units. This register is only valid when Cursor has been selected in the
CRT/TV Ink/Cursor select registers.
CRT/TV Cursor Y Position Register 0
REG[084h]
CRT/TV
Cursor Y
Position Bit 7
CRT/TV
Cursor Y
Position Bit 6
CRT/TV
Cursor Y
Position Bit 5
RW
CRT/TV
Cursor Y
Position Bit 4
CRT/TV
Cursor Y
Position Bit 3
CRT/TV
Cursor Y
Position Bit 2
CRT/TV
Cursor Y
Position Bit 1
CRT/TV Cursor Y Position Register 1
REG[085h]
CRT/TV
Cursor Y Sign
n/a
CRT/TV
Cursor Y
Position Bit 0
RW
n/a
n/a
n/a
n/a
CRT/TV
Cursor Y
Position Bit 9
CRT/TV
Cursor Y
Position Bit 8
REG[084h] bit 7
CRT/TV Cursor YSign
When this bit = 1, it defines the CRT/TV Cursor Y Position register as a negative number.
The negative number shall not exceed 63 decimal.
When this bit = 0, it defines the CRT/TV Cursor Y Position register as a positive number.
REG[084h] bits 7-0
REG[085h] bits 1-0
CRT/TV Cursor Y Position Bits [9:0]
A 10-bit register that defines the vertical position of the CRT/TV Cursor’s top left hand
corner in pixel units. This register is only valid when Cursor has been selected in the
CRT/TV Ink/Cursor select registers.
Note
The effect of REG[082h] through REG[084h] takes place only after REG[085h]is written to and at the next CRT/TV vertical non-display period.The effect of REG[085h]
takes place at the next CRT/TV vertical non-display period.
CRT/TV Ink/Cursor Blue Color 0 Register
REG[086h]
n/a
bits 4-0
n/a
n/a
CRT/TV
Ink/Cursor
Blue Color 0
Bit 4
RW
CRT/TV
Ink/Cursor
Blue Color 0
Bit 3
CRT/TV
Ink/Cursor
Blue Color 0
Bit 2
CRT/TV
Ink/Cursor
Blue Color 0
Bit 1
CRT/TV
Ink/Cursor
Blue Color 0
Bit 0
CRT/TV Ink/Cursor Blue Color 0 Bits[4:0]
These bits define the blue CRT/TV Ink/Cursor color 0.
Hardware Functional Specification
Issue Date: 01/02/06
S1D13506
X25B-A-001-10
Page 160
Epson Research and Development
Vancouver Design Center
CRT/TV Ink/Cursor Green Color 0 Register
REG[087h]
n/a
n/a
bits 5-0
RW
CRT/TV
CRT/TV
CRT/TV
CRT/TV
CRT/TV
CRT/TV
Ink/Cursor
Ink/Cursor
Ink/Cursor
Ink/Cursor
Ink/Cursor
Ink/Cursor
Green Color 0 Green Color 0 Green Color 0 Green Color 0 Green Color 0 Green Color 0
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
CRT/TV Ink/Cursor Green Color 0 Bits[5:0]
These bits define the green CRT/TV Ink/Cursor color 0.
CRT/TV Ink/Cursor Red Color 0 Register
REG[088h]
n/a
n/a
bits 4-0
RW
CRT/TV
Ink/Cursor
Red Color 0
Bit 4
n/a
CRT/TV
Ink/Cursor
Red Color 0
Bit 3
CRT/TV
Ink/Cursor
Red Color 0
Bit 2
CRT/TV
Ink/Cursor
Red Color 0
Bit 1
CRT/TV
Ink/Cursor
Red Color 0
Bit 0
CRT/TV
Ink/Cursor
Blue Color 1
Bit 1
CRT/TV
Ink/Cursor
Blue Color 1
Bit 0
CRT/TV Ink/Cursor Red Color 0 Bits[4:0]
These bits define the red CRT/TV Ink/Cursor color 0.
CRT/TV Ink/Cursor Blue Color 1 Register
REG[08Ah]
n/a
n/a
bits 4-0
n/a
RW
CRT/TV
Ink/Cursor
Blue Color 1
Bit 4
CRT/TV
Ink/Cursor
Blue Color 1
Bit 3
CRT/TV
Ink/Cursor
Blue Color 1
Bit 2
CRT/TV Ink/Cursor Blue Color 1 Bits[4:0]
These bits define the blue CRT/TV Ink/Cursor color 1.
CRT/TV Ink/Cursor Green Color 1 Register
REG[08Bh]
n/a
n/a
bits 5-0
RW
CRT/TV
CRT/TV
CRT/TV
CRT/TV
CRT/TV
CRT/TV
Ink/Cursor
Ink/Cursor
Ink/Cursor
Ink/Cursor
Ink/Cursor
Ink/Cursor
Green Color 1 Green Color 1 Green Color 1 Green Color 1 Green Color 1 Green Color 1
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
CRT/TV Ink/Cursor Green Color 1 Bits[5:0]
These bits define the green CRT/TV Ink/Cursor color 1.
CRT/TV Ink/Cursor Red Color 1 Register
REG[08Ch]
n/a
bits 4-0
S1D13506
X25B-A-001-10
n/a
n/a
RW
CRT/TV
Ink/Cursor
Red Color 1
Bit 4
CRT/TV
Ink/Cursor
Red Color 1
Bit 3
CRT/TV
Ink/Cursor
Red Color 1
Bit 2
CRT/TV
Ink/Cursor
Red Color 1
Bit 1
CRT/TV
Ink/Cursor
Red Color 1
Bit 0
CRT/TV Ink/Cursor Red Color 1 Bits[4:0]
These bits define the red CRT/TV Ink/Cursor color 1.
Hardware Functional Specification
Issue Date: 01/02/06
Epson Research and Development
Vancouver Design Center
Page 161
CRT/TV Ink/Cursor FIFO High Threshold Register
REG[08Eh]
n/a
bits 5-0
n/a
n/a
RW
CRT/TV
Ink/Cursor
FIFO High
Threshold
Bit 3
n/a
CRT/TV
Ink/Cursor
FIFO High
Threshold
Bit 2
CRT/TV
Ink/Cursor
FIFO High
Threshold
Bit 1
CRT/TV
Ink/Cursor
FIFO High
Threshold
Bit 0
CRT/TV Ink/Cursor FIFO High Threshold Bits [5:0]
These bits are used to optimize the display memory request arbitration for the Hardware
Cursor/Ink Layer. When this register is set to 00h, the threshold is automatically set in
hardware.
8.3.12 BitBlt Configuration Registers
BitBlt Control Register 0
REG[100h]
BitBlt Active
Status
bits 7
RW
BitBlt FIFO
Not Empty
Status (RO)
BitBlt FIFO
Half Full
Status (RO)
BitBlt FIFO
Full
Status (RO)
n/a
n/a
BitBlt
Destination
Linear Select
BitBlt Source
Linear Select
BitBlt Active Status
This register bit has two data paths, one for write, the other for read.
Write Data Path
When software writes a one to this bit, it will initiate the 2D operation.
Read Data Path
The read back of this register indicates the status of the 2D engine.
When a read from this bit = 1, the 2D engine is busy.
When a read from this bit = 0, the 2D engine is idle and is ready for the next operation.
.
Table 8-29: BitBlt Active Status
BitBlt Active Status
State
Write
Read
0
0
Idle
0
1
Reserved
1
0
Initiating operation
1
1
Operation in progress
Hardware Functional Specification
Issue Date: 01/02/06
S1D13506
X25B-A-001-10
Page 162
bit 6
Epson Research and Development
Vancouver Design Center
BitBlt FIFO Not-Empty Status
This is a read-only status bit.
When this bit = 1, the BitBlt FiFO has at least one data.
When this bit = 0, the BitBlt FIFO is empty.
To reduce system memory read latency, software can monitor this bit prior to a BitBlt read
burst operation.
The following table shows the number of data available in BitBlt FIFO under different
status conditions.
Table 8-30: BitBlt FIFO Data Available
BitBlt FIFO Half
BitBlt FIFO Full
Full Status
Status (REG[100h]
(REG[100h] Bit 5)
Bit 4)
BitBlt FIFO Not
Empty Status
(REG[100h] Bit 6)
Number of Data
available in BitBlt
FIFO
0
0
0
0
0
0
1
1 to 6
0
1
1
7 to 14
1
1
1
15 to 16
bit 5
BitBlt FIFO Half Full Status
This is a read-only status bit.
Software can use this bit to optimize BitBlt write burst operations.
When this bit = 1, the BitBlt FIFO is half full or greater than half full.
When this bit = 0, the BitBlt FIFO is less than half full.
bit 4
BitBlt FIFO Full Status
This is a read-only status bit.
Software can use this bit to optimize BitBlt write burst operations.
When this bit = 1, the BitBlt FIFO is full.
When this bit = 0, the BitBlt FIFO is not full.
bit 1
BitBlt Destination Linear Select
When this bit = 1, the Destination Blit is stored as a contiguous linear block of memory.
When this bit = 0, the Destination Blit is stored as a rectangular region of memory.
The BitBlt Memory Address Offset (REG[10Ch], REG[10Dh]) determines the address
offset from the start of one line to the next line.
bit 0
BitBlt Source Linear Select
When this bit = 1, the Source Blit is stored as a contiguous linear block of memory.
When this bit = 0, the Source Blit is stored as a rectangular region of memory.
The BitBlt Memory Address Offset (REG[10Ch], REG[10Dh]) determines the address
offset from the start of one line to the next line.
S1D13506
X25B-A-001-10
Hardware Functional Specification
Issue Date: 01/02/06
Epson Research and Development
Vancouver Design Center
Page 163
BitBlt Control Register 1
REG[101h]
n/a
RW
n/a
n/a
Reserved
n/a
n/a
n/a
bit 4
Reserved.
Must be set to 0.
bit 0
BitBlt Color Format Select
This bit selects the color format that the 2D operation is applied to.
When this bit = 0, 8 bpp (256 color) format is selected.
When this bit = 1, 16 bpp (64K color) format is selected.
BitBlt ROP Code/Color Expansion Register
REG[102h]
n/a
n/a
bits 3-0
n/a
BitBlt Color
Format Select
RW
BitBlt ROP
Code
Bit 3
n/a
BitBlt ROP
Code
Bit 2
BitBlt ROP
Code
Bit 1
BitBlt ROP
Code
Bit 0
BitBlt Raster Operation Code/Color Expansion Bits [3:0]
ROP Code for Write Blit and Move Blit. Bits 2-0 also specify the start bit position for
Color Expansion.
Table 8-31: BitBlt ROP Code/Color Expansion Function Selection
BitBlt ROP Code Bits [3:0]
Boolean Function for Write
Blit and Move Blit
Boolean Function for
Pattern Fill
Start Bit Position for Color
Expansion
0000
0 (Blackness)
0 (Blackness)
bit 0
0001
~S . ~D or ~(S + D)
~P . ~D or ~(P + D)
bit 1
0010
~S . D
~P . D
bit 2
0011
~S
~P
bit 3
0100
S . ~D
P . ~D
bit 4
0101
~D
~D
bit 5
0110
S^D
P^D
bit 6
0111
~S + ~D or ~(S . D)
~P + ~D or ~(P . D)
bit 7
1000
S.D
P.D
bit 0
1001
~(S ^ D)
~(P ^ D)
bit 1
1010
D
D
bit 2
1011
~S + D
~P + D
bit 3
1100
S
P
bit 4
1101
S + ~D
P + ~D
bit 5
1110
S+D
P+D
bit 6
1111
1 (Whiteness)
1 (Whiteness)
bit 7
Note
S = Source, D = Destination, P = Pattern.
Hardware Functional Specification
Issue Date: 01/02/06
S1D13506
X25B-A-001-10
Page 164
Epson Research and Development
Vancouver Design Center
BitBlt Operation Register
REG[103h]
n/a
bits 3-0
n/a
RW
n/a
n/a
BitBlt
Operation
Bit 3
BitBlt
Operation
Bit 2
BitBlt
Operation
Bit 1
BitBlt
Operation
Bit 0
BitBlt Operation Bits [3:0]
Specifies the 2D Operation to be carried out based on the following table:
Table 8-32: BitBlt Operation Selection
BitBlt Operation Bits [3:0]
Blit Operation
0000
Write Blit with ROP.
0001
Read Blit.
0010
Move Blit in positive direction with ROP.
0011
Move Blit in negative direction with ROP.
0100
Transparent Write Blit.
0101
Transparent Move Blit in positive direction.
0110
Pattern Fill with ROP.
0111
Pattern Fill with transparency.
1000
Color Expansion.
1001
Color Expansion with transparency.
1010
Move Blit with Color Expansion.
1011
Move Blit with Color Expansion and transparency.
1100
Solid Fill.
Other combinations
Reserved
Note
The BitBlt operations Pattern Fill with ROP and Pattern Fill with transparency require a
BitBlt width ≥ 2. The BitBlt width is set in REG[110h], REG[111h].
S1D13506
X25B-A-001-10
Hardware Functional Specification
Issue Date: 01/02/06
Epson Research and Development
Vancouver Design Center
Page 165
BitBlt Source Start Address Register 0
REG[104h]
RW
BitBlt Source BitBlt Source BitBlt Source BitBlt Source BitBlt Source BitBlt Source BitBlt Source BitBlt Source
Start Address Start Address Start Address Start Address Start Address Start Address Start Address Start Address
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
BitBlt Source Start Address Register 1
REG[105h]
RW
BitBlt Source BitBlt Source BitBlt Source BitBlt Source BitBlt Source BitBlt Source BitBlt Source BitBlt Source
Start Address Start Address Start Address Start Address Start Address Start Address Start Address Start Address
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
BitBlt Source Start Address Register 2
REG[106h]
n/a
n/a
REG[104h] bits 7-0
REG[105h] bits 7-0
REG[106h] bits 4-0
n/a
RW
BitBlt Source BitBlt Source
Start Address Start Address
Bit 20
Bit 19
BitBlt Source
Start
Bit 18
BitBlt Source
Start Address
Bit 17
BitBlt Source
Start Address
Bit 16
BitBlt Source Start Address Bits [20:0]
A 21-bit register that specifies the source start address for the BitBlt operation.
If data is sourced from the CPU, then bit 0 is used for byte alignment within a 16-bit word
and the other address bits are ignored. In pattern fill operation, the BitBlt Source Start
Address is defined by the following equation:
Value programmed to the Source Start Address Register =
Pattern Base Address + Pattern Line Offset + Pixel Offset.
The following table shows how Source Start Address Register is defined for 8 and 16 bpp color depths.
Table 8-33: BitBlt Source Start Address Selection
Color Format
Pattern Base Address[20:0]
Pattern Line Offset[2:0]
Pixel Offset[3:0]
8 bpp
BitBlt Source Start Address[20:6],
6’b0
BitBlt Source Start
Address[5:3]
1’b0, BitBlt Source Start
Address[2:0]
16 bpp
BitBlt Source Start Address[20:7],
7’b0
BitBlt Source Start
Address[6:4]
BitBlt Source Start
Address[3:0]
Hardware Functional Specification
Issue Date: 01/02/06
S1D13506
X25B-A-001-10
Page 166
Epson Research and Development
Vancouver Design Center
BitBlt Destination Start Address Register 0
REG[108h]
RW
BitBlt
BitBlt
BitBlt
BitBlt
BitBlt
BitBlt
BitBlt
BitBlt
Destination
Destination
Destination
Destination
Destination
Destination
Destination
Destination
Start Address Start Address Start Address Start Address Start Address Start Address Start Address Start Address
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
BitBlt Destination Start Address Register 1
REG[109h]
RW
BitBlt
BitBlt
BitBlt
BitBlt
BitBlt
BitBlt
BitBlt
BitBlt
Destination
Destination
Destination
Destination
Destination
Destination
Destination
Destination
Start Address Start Address Start Address Start Address Start Address Start Address Start Address Start Address
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
BitBlt Destination Start Address Register 2
REG[10Ah]
n/a
n/a
REG[108h] bits 7-0
REG[109h] bits 7-0
REG[10Ah] bits 4-0
n/a
RW
BitBlt
BitBlt
BitBlt
BitBlt
BitBlt
Destination
Destination
Destination
Destination
Destination
Start Address Start Address Start Address Start Address Start Address
Bit 20
Bit 19
Bit 18
Bit 17
Bit 16
BitBlt Destination Start Address Bits [20:0]
A 21-bit register that specifies the destination start address for the BitBlt operation.
BitBlt Memory Address Offset Register 0
REG[10Ch]
RW
BitBlt Memory BitBlt Memory BitBlt Memory BitBlt Memory BitBlt Memory BitBlt Memory BitBlt Memory BitBlt Memory
Address
Address
Address
Address
Address
Address
Address
Address
Offset Bit 7
Offset Bit 6
Offset Bit 5
Offset Bit 4
Offset Bit 3
Offset Bit 2
Offset Bit 1
Offset Bit 0
BitBlt Memory Address Offset Register 1
REG[10Dh]
n/a
n/a
REG[10Ch] bits 7-0
REG[10Dh] bits 2-0
n/a
RW
n/a
n/a
BitBlt Memory BitBlt Memory BitBlt Memory
Address
Address
Address
Offset Bit 10
Offset Bit 9
Offset Bit 8
BitBlt Memory Address Offset Bits [10:0]
These bits are the display’s 11-bit address offset from the starting word of line “n” to the
starting word of line “n + 1”. They are used only for address calculation when the Blit is
configured as a rectangular region of memory. They are not used for the displays.
BitBlt Width Register 0
REG[110h]
BitBlt Width
Bit 7
S1D13506
X25B-A-001-10
BitBlt Width
Bit 6
RW
BitBlt Width
Bit 5
BitBlt Width
Bit 4
BitBlt Width
Bit 3
BitBlt Width
Bit 2
BitBlt Width
Bit 1
BitBlt Width
Bit 0
Hardware Functional Specification
Issue Date: 01/02/06
Epson Research and Development
Vancouver Design Center
Page 167
BitBlt Width Register 1
REG[111h]
n/a
RW
n/a
REG[110h] bits 7-0
REG[111h] bits 1-0
n/a
n/a
n/a
n/a
BitBlt Width
Bit 9
BitBlt Width
Bit 8
BitBlt Width Bits [9:0]
A 10-bit register that specifies the BitBlt width in pixels -1.
Note
The BitBlt operations Pattern Fill with ROP and Pattern Fill with transparency require a
BitBlt width ≥ 2.
BitBlt Height Register 0
REG[112h]
BitBlt Height
Bit 7
BitBlt Height
Bit 6
RW
BitBlt Height
Bit 5
BitBlt Height
Bit 4
BitBlt Height
Bit 3
BitBlt Height
Bit 2
BitBlt Height
Bit 1
BitBlt Height Register 1
REG[113h]
n/a
REG[112h] bits 7-0
REG[113h] bits 1-0
n/a
BitBlt Height
Bit 0
RW
n/a
n/a
n/a
n/a
BitBlt Height
Bit 9
BitBlt Height
Bit 8
BitBlt Height Bits [9:0]
A 10-bit register that specifies the BitBlt height in lines -1.
Hardware Functional Specification
Issue Date: 01/02/06
S1D13506
X25B-A-001-10
Page 168
Epson Research and Development
Vancouver Design Center
BitBlt Background Color Register 0
REG[114h]
BitBlt
Background
Color
Bit 7
BitBlt
Background
Color
Bit 6
BitBlt
Background
Color
Bit 5
RW
BitBlt
Background
Color
Bit 4
BitBlt
Background
Color
Bit 3
BitBlt
Background
Color
Bit 2
BitBlt
Background
Color
Bit 1
BitBlt Background Color Register 1
REG[115h]
BitBlt
Background
Color
Bit 15
BitBlt
Background
Color
Bit 14
REG[114h] bits 7-0
REG[115h] bits 15-8
BitBlt
Background
Color
Bit 13
RW
BitBlt
Background
Color
Bit 12
BitBlt
Background
Color
Bit 11
BitBlt
Background
Color
Bit 10
BitBlt
Background
Color
Bit 9
BitBlt
Foreground
Color
Bit 6
BitBlt
Foreground
Color
Bit 5
RW
BitBlt
Foreground
Color
Bit 4
BitBlt
Foreground
Color
Bit 3
BitBlt
Foreground
Color
Bit 2
BitBlt
Foreground
Color
Bit 1
BitBlt
Foreground
Color
Bit 0
BitBlt
Foreground
Color
Bit 12
BitBlt
Foreground
Color
Bit 11
BitBlt
Foreground
Color
Bit 10
BitBlt
Foreground
Color
Bit 9
BitBlt
Foreground
Color
Bit 8
BitBlt Foreground Color Register 1
REG[119h]
BitBlt
Foreground
Color
Bit 15
BitBlt
Foreground
Color
Bit 14
REG[118h] bits 7-0
REG[119h] bits 7-0
S1D13506
X25B-A-001-10
BitBlt
Background
Color
Bit 8
BitBlt Background Color Bits [15:0]
A 16-bit register that specifies the BitBlt background color for Color Expansion or key
color for Transparent Blit. For 16 bpp mode (REG[101h] bit 0 = 1), all 16 bits are used.
For 8 bpp mode (REG[101h] bit 0 = 0), only bits 7-0 are used.
BitBlt Foreground Color Register 0
REG[118h]
BitBlt
Foreground
Color
Bit 7
BitBlt
Background
Color
Bit 0
BitBlt
Foreground
Color
Bit 13
RW
BitBlt Foreground Color Bits [15:0]
A 16-bit register that specifies the BitBlt foreground color for Color Expansion or Solid
Fill. For 16 bpp mode (REG[101h] bit 0 = 1), all 16 bits are used. For 8 bpp mode
(REG[101h] bit 0 = 0), only bits 7-0 are used.
Hardware Functional Specification
Issue Date: 01/02/06
Epson Research and Development
Vancouver Design Center
Page 169
8.3.13 Look-Up Table Registers
Note
Accessing the LCD Look-Up Table (LUT) requires an active LCD PCLK and accessing
the CRT/TV LUT requires an active CRT/TV PCLK. Additionally, access to the
LUT registers is not permitted during power save mode. For further information on the
clocks, see Section 20, “Clocks” on page 224.
Look-Up Table Mode Register
REG[1E0h]
n/a
bits 1-0
n/a
RW
n/a
n/a
n/a
LUT Mode Bit
1
n/a
LUT Mode Bit
0
Look-Up Table Mode Bits [1:0]
These bits determine which of the Look-Up Tables (LCD and CRT/TV) are accessible by
REG[1E2h] and REG[1E4h].
Table 8-34: LUT Mode Selection
LUT Mode Bits [1:0]
Read
Write
00
LCD LUT
LCD and CRT/TV LUT’s
01
LCD LUT
LCD LUT
10
CRT/TV LUT
CRT/TV LUT
11
Reserved
Reserved
Look-Up Table Address Register
REG[1E2h]
LUT Address
Bit 7
bits 7-0
LUT Address
Bit 6
LUT Address
Bit 5
RW
LUT Address
Bit 4
LUT Address
Bit 3
LUT Address
Bit 2
LUT Address
Bit 1
LUT Address
Bit 0
LUT Address Bits [7:0]
These 8 bits control a pointer into the Look-Up Tables (LUT). The S1D13506 has three
256-position, 4-bit wide LUTs, one for each of red, green, and blue – refer to Section 12,
“Look-Up Table Architecture” on page 186 for details.
This register selects which LUT entry is read/write accessible through the LUT Data Register (REG[1E4h]). Writing the LUT Address Register automatically sets the pointer to the
Red LUT. Accesses to the LUT Data Register automatically increment the pointer.
For example, writing a value 03h into the LUT Address Register sets the pointer to R[3].
A subsequent access to the LUT Data Register accesses R[3] and moves the pointer onto
G[3]. Subsequent accesses to the LUT Data Register move the pointer onto B[3], R[4],
G[4], B[4], R[5], etc.
Note
The RGB data is inserted into the LUT after the Blue data is written, i.e. all three colors
must be written before the LUT is updated.
Hardware Functional Specification
Issue Date: 01/02/06
S1D13506
X25B-A-001-10
Page 170
Epson Research and Development
Vancouver Design Center
Look-Up Table Data Register
REG[1E4h]
LUT Data
Bit 3
LUT Data
Bit 2
bits 7-4
RW
LUT Data
Bit 1
LUT Data
Bit 0
n/a
n/a
n/a
n/a
LUT Data Bits [3:0]
This register is used to read/write the RGB Look-Up Tables. This register accesses the
entry at the pointer controlled by the Look-Up Table Address Register (REG[1E2h]).
Accesses to the Look-Up Table Data Register automatically increment the pointer.
Note
The RGB data is inserted into the LUT after the Blue data is written, i.e. all three colors
must be written before the LUT is updated.
8.3.14 Power Save Configuration Registers
Power Save Configuration Register
REG[1F0h]
n/a
n/a
n/a
RW
Reserved
n/a
n/a
n/a
bit 4
Reserved.
This bit must be set to 0.
bit 0
Power Save Mode Enable
When this bit = 1, the software initiated power save mode is enabled.
When this bit = 0, the software initiated power save mode is disabled.
Power Save
Mode Enable
Power Save Status Register
REG[1F1h]
n/a
bit 1
n/a
RO
n/a
n/a
n/a
n/a
LCD Power
Save Status
Memory
Controller
Power Save
Status
LCD Power Save Status
This bit indicates the power save state of the LCD panel.
When this bit = 1, the panel is powered down.
When this bit = 0, the panel is powered up, or in transition of powering up or down.
Note
When this bit reads a 1, the system may safely shut down the LCD pixel clock source.
S1D13506
X25B-A-001-10
Hardware Functional Specification
Issue Date: 01/02/06
Epson Research and Development
Vancouver Design Center
bit 0
Page 171
Memory Controller Power Save Status
This bit indicates the power save state of the memory controller.
When this bit = 1, the memory controller is powered down and is either in self refresh or
no refresh mode.
When this bit = 0, the memory controller is powered up and is either in CBR refresh or
normal mode.
Note
When this bit reads a 1, the system may safely shut down the memory clock source.
8.3.15 Miscellaneous Registers
CPU-to-Memory Access Watchdog Timer Register
REG[1F4h]
n/a
bits 5-0
Mem. Access
Watchdog
Timer bit 5
n/a
Mem. Access
Watchdog
Timer bit 4
RW
Mem. Access
Watchdog
Timer bit 3
Mem. Access
Watchdog
Timer bit 2
Mem. Access
Watchdog
Timer bit 1
Mem. Access
Watchdog
Timer bit 0
CPU-to-Memory Access Watchdog Timer
A non-zero value in this register enables the watchdog timer for CPU-to-memory access.
When enabled, any CPU-to-memory access cycle will be completed successfully within a
time determined by the following equation:
Maximum CPU-to-memory access cycle time = (8n + 7) × Tbclk + 13 × Tmclk
where:
n = A non-zero value in this register
Tbclk = Bus clock period, or Bus clock period x 2 (if MD12 = 1, see
Table 5-6: on page 39)
Tmclk = Memory clock period
This function is required by some busses which time-out if the cycle duration exceeds a
certain time period. This function is not intended to arbitrarily shorten the
CPU-to-memory access cycle time in order gain higher CPU bandwidth. Doing so may
significantly reduce the available display refresh bandwidth which may cause display
corruption. This register does not affect CPU-to-register access or blit access.
Hardware Functional Specification
Issue Date: 01/02/06
S1D13506
X25B-A-001-10
Page 172
Epson Research and Development
Vancouver Design Center
8.3.16 Common Display Mode Register
Display Mode Register
REG[1FCh]
RW
SwivelView™
Enable Bit 0
n/a
bit 6
n/a
n/a
Display Mode
Select Bit 2
n/a
Display Mode
Select Bit 1
Display Mode
Select Bit 0
SwivelView™ Enable Bit 0
When this bit = 1, the LCD display image is rotated 90° clockwise. Please refer to Section
15, “SwivelView™” on page 201 for application and limitations.
When this bit = 0, there is no hardware effect.
This bit in conjunction with SwivelView™ Enable Bit 1 achieves the following hardware
rotations.
Table 8-35: Setting SwivelView Modes
SwivelView™ Modes
SwivelView Enable Bits
Normal
SwivelView 90°
SwivelView 180°
SwivelView 270°
SwivelView Enable Bit 0
(REG[1FCh] bit 6)
0
1
0
1
SwivelView Enable Bit 1
(REG[040h] bit 4)
0
0
1
1
bits 2-0
Display Mode Select Bits [2:0]
These bits select the display model according to the following table. The LCD display
mode is enabled/disabled using bit 0. Programming this bit from a 0 to a 1 starts the
power-on sequence. Programming this bit from a 1 to a 0 starts the power-off sequence.
Table 8-36: Display Mode Selection
Display Mode Select Bits [2:0]
Display Mode Enabled
000
no display
001
LCD only
010
CRT only
011
EISD (CRT and LCD)
100
TV with flicker filter off
101
EISD (TV with flicker filter off and LCD)
110
TV with flicker filter on
111
EISD (TV with flicker filter on and LCD)
Note
REG[018h] bit 7 must be set to 1 when the flicker filter is enabled.
Note
The Flicker Filter reduces the “flickering” effect seen on interlaced displays by averaging adjacent lines on the TV display. This “flickering” is caused by sharp vertical image
transitions that occur over one line (1 vertical pixel). For example, one pixel high lines,
edges of window boxes, etc. Flickering occurs because these high resolution lines are effectively displayed at half the refresh frequency due to interlacing.
S1D13506
X25B-A-001-10
Hardware Functional Specification
Issue Date: 01/02/06
Epson Research and Development
Vancouver Design Center
Page 173
8.3.17 MediaPlug Register Descriptions
The S1D13506 has built-in support for Winnov’s MediaPlug connection designed for video
cameras. The following registers are used to control the connection and accept data from
the camera. The MediaPlug registers decode A11-A0 and require A20 = 0 and A12 = 1. The
MediaPlug registers are 16-bit wide. Byte access to the MediaPlug registers is not allowed.
For further information, see Section 17, “MediaPlug Interface” on page 212.
Note
The MediaPlug control registers must not be accessed while Power Save Mode is
enabled (REG[1F0h] bit 0 = 1).
MediaPlug LCMD Register
REG[1000h]
RW
LCMD Bit 7
LCMD Bit 6
LCMD Bit 5
LCMD Bit 4
LCMD Bit 3
LCMD Bit 2
LCMD Bit 1
LCMD Bit 0
LCMD Bit 15
LCMD Bit 14
LCMD Bit 13
LCMD Bit 12
LCMD Bit 11
LCMD Bit 10
LCMD Bit 9
LCMD Bit 8
REG[1000h] bits 15-0 MediaPlug LCMD Bits [15:0]
A 16-bit register for setting and detecting various modes of operation of the MediaPlug
Local Slave. This register is handled differently for reads and writes. The following table
shows the MediaPlug description of the LCMD Register. See bit descriptions for details.
Table 8-37: MediaPlug LCMD Read/Write Descriptions
Data
D15
D14
Write
TO[2:0]
Read
TO[2:0]
bits 15-14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
IC
MC
P
W
0b
IC
MC
P
W
Xxxxxxxxxx
00b
Rev[3:0]
Rstat[2:0]
Timeout Option (MediaPlug Parameter TO)
These bits select the timeout delay in MediaPlug clock cycles:
Table 8-38: Timeout Option Delay
Timeout Option
Bits[15:14]
Timeout (MediaPlug clock cycles)
00
1023 (default)
01
64
10
128
11
64
bits 13-12
A read from these bits will always return 00b.
A write to these bits has no hardware effect.
bits 11-8
MediaPlug IC Revision (MediaPlug Parameter Rev)
The revision for this MediaPlug IC is “0011b”.
A write to these bits has no hardware effect.
Hardware Functional Specification
Issue Date: 01/02/06
S1D13506
X25B-A-001-10
Page 174
Epson Research and Development
Vancouver Design Center
bit 7
Cable Detected Status (MediaPlug Parameter Rstat)
The cable detected status as determined by the MPD(1) pin.
When this bit = 0, a MediaPlug cable is connected.
When this bit = 1, a MediaPlug cable is not detected.
A write to this bit has no hardware effect.
bit 6
A read from this bit will always return 0b.
A write to this bit has no hardware effect.
bit 5
Remote Powered Status (MediaPlug Parameter Rstat)
The remote powered status as determined by the RCTRL pin.
When this bit = 0, the remote is not powered.
When this bit = 1, the remote is powered and connected.
A write to this bit has no hardware effect.
Table 8-39: Cable Detect and Remote Powered Status
Cable Detected Remote Powered
Status [bit 7]
Status [bit 5]
Status
0
0
cable connected but remote not powered
0
1
cable connected and remote powered
1
x
cable not connected
bit 4
A read from this bit will always return 0b.
A write to this bit has no hardware effect.
bit 3
MediaPlug Interface Clock Enable (MediaPlug Parameter IC)
When this bit = 0, the MediaPlug interface clock is enabled (default).
When this bit = 1, the MediaPlug interface clock is disabled.
bit 2
MediaPlug Clock (MediaPlug Parameter MC)
When this bit = 0, the MediaPlug cable clock is disabled (default).
When this bit = 1, the MediaPlug cable clock is enabled.
bit 1
Power Enable to Remote (MediaPlug Parameter P)
When this bit = 0, power to remote is off (default).
When this bit =1, power to remote is on.
bit 0
Watchdog Disable (MediaPlug Parameter W)
When this bit = 0, the MediaPlug watchdog is enabled (default).
When this bit = 1, the MediaPlug watchdog is disabled.
MediaPlug Reserved LCMD Register
REG[1002h]
RW
LCMD Bit 23
LCMD Bit 22
LCMD Bit 21
LCMD Bit 20
LCMD Bit 19
LCMD Bit 18
LCMD Bit 17
LCMD Bit 16
LCMD Bit 31
LCMD Bit 30
LCMD Bit 29
LCMD Bit 28
LCMD Bit 27
LCMD Bit 26
LCMD Bit 25
LCMD Bit 24
S1D13506
X25B-A-001-10
Hardware Functional Specification
Issue Date: 01/02/06
Epson Research and Development
Vancouver Design Center
Page 175
REG[1002h] bits 15-0 MediaPlug Reserved LCMD Bits [15:0]
This register is not implemented and is reserved for future expansion of the LCMD register. A write to this register has no hardware effect. A read from this register always return
0000h.
MediaPlug CMD Register
REG[1004h]
RW
CMD Bit 7
CMD Bit 6
CMD Bit 5
CMD Bit 4
CMD Bit 3
CMD Bit 2
CMD Bit 1
CMD Bit 0
CMD Bit 15
CMD Bit 14
CMD Bit 13
CMD Bit 12
CMD Bit 11
CMD Bit 10
CMD Bit 9
CMD Bit 8
REG[1002h] bits 15-0 MediaPlug CMD Bits [15:0]
A 16-bit register for setting the MediaPlug commands. This register is handled differently
for reads and writes. The following table shows the MediaPlug description of the CMD
Register. See bit descriptions for details.
Table 8-40: MediaPlug CMD Read/Write Descriptions
Data
D15
D14
D
T
D13
Write
Read
D12
D11
D10
D9
D8
I[12:0]
D7
D6
D5
D4
D3
D2
D1
D0
C[2:0]
I[10:0]
C[2:0]
bit 15
Dirty Bit (MediaPlug Parameter D)
This bit is set by the hardware when the command register is written.
It is cleared by hardware by the following conditions:
1. Remote-Reset (After this command has been acknowledged by remote.
2. End_Stream (After this command has been acknowledged by remote.
3. Write to DATA register if the CCC field is Write_Reg.
4. Read to DATA register if the CCC field is Read_Reg.
It is also set when the Remote Machine loses power or the cable is disconnected.
bit 14
Timeout Bit (MediaPlug Parameter T)
It is set when Watchdog is enabled and MediaPlug read or write cycle takes longer than
64, 128, 1024 cycles of MediaPlug clock depending on LCMD register settings.
It is also set when the remote is not powered.
It is cleared at the beginning of every command write by the host.
bits 13-3
Index Field (MediaPlug Parameter I)
This field is the address presented by the remote to the remote function. MediaPlug transmits the entire 16-bits of the first word of the command Register as written, but I12 (D15)
and I11 (D14) are hidden from readback by the dirty bit and Watchdog error bit.
Hardware Functional Specification
Issue Date: 01/02/06
S1D13506
X25B-A-001-10
Page 176
Epson Research and Development
Vancouver Design Center
bit 2-0
Command Field (MediaPlug Parameter C)
Selects the command as follows:
Table 8-41: MediaPlug Commands
Command Field
[bits 2:0]
Command
000
Remote-Reset: Hardware reset of remote.
001
Stream-End: Indicates end of data streaming operation.
010
Write-Register: Write remote register INDEX[5:0] with DATA.
011
Read-Register: Read remote register INDEX[5:0] to DATA.
100
Write_Stream: Begin streaming data to the remote.
101
NOP: The command is sent across the MediaPlug. There is no other effect.
110
NOP: The command is sent across the MediaPlug. There is no other effect.
111
Read-Stream: Begin streaming data from the remote.
MediaPlug Reserved CMD Register
REG[1006h]
RW
CMD Bit 23
CMD Bit 22
CMD Bit 21
CMD Bit 20
CMD Bit 19
CMD Bit 18
CMD Bit 17
CMD Bit 16
CMD Bit 31
CMD Bit 30
CMD Bit 29
CMD Bit 28
CMD Bit 27
CMD Bit 26
CMD Bit 25
CMD Bit 24
REG[1006h] bits 15-0 MediaPlug Reserved CMD Bits [15:0]
This register is not implemented and is reserved for future expansion of the CMD register.
A write to this register has no hardware effect. A read from this register always return
0000h.
MediaPlug Data Register
REG[1008h] to REG[1FFEh], even address
RW
Data Bit 7
Data Bit 6
Data Bit 5
Data Bit 4
Data Bit 3
Data Bit 2
Data Bit 1
Data Bit 0
Data Bit 15
Data Bit 14
Data Bit 13
Data Bit 12
Data Bit 11
Data Bit 10
Data Bit 9
Data Bit 8
Data Register bits 15-0 MediaPlug Data Bits [15:0]
A 16-bit register used for read/write and streaming read/write of MediaPlug data. This
register is loosely decoded from 1008h to 1FFEh so that the port may be accessed using
DWORD block transfer instructions.
S1D13506
X25B-A-001-10
Hardware Functional Specification
Issue Date: 01/02/06
Epson Research and Development
Vancouver Design Center
Page 177
8.3.18 BitBlt Data Registers Descriptions
The BitBlt data registers decode A19-A0 and require A20 = 1. The BitBlt data registers are
16-bit wide. Byte access to the BitBlt data registers is not allowed.
BitBlt Data Register 0
A20-A0 = 100000h-1FFFFEh, even address
RW
Data Bit 7
Data Bit 6
Data Bit 5
Data Bit 4
Data Bit 3
Data Bit 2
Data Bit 1
Data Bit 0
Data Bit 15
Data Bit 14
Data Bit 13
Data Bit 12
Data Bit 11
Data Bit 10
Data Bit 9
Data Bit 8
Data Register bits 15-0 BitBlt Data Bits [15:0]
A 16-bit register that specifies the BitBlt data. This register is loosely decoded from
100000h to 1FFFFEh.
Hardware Functional Specification
Issue Date: 01/02/06
S1D13506
X25B-A-001-10
Page 178
Epson Research and Development
Vancouver Design Center
9 2D BitBlt Engine
The S1D13506 has a built-in 2D BitBlt engine which increases the performance of Bit
Block Transfers (BitBlt). This section will discuss the BitBlt engine design and functionality.
9.1 Functional Description
The 2D BitBlt engine is designed using a 16-bit architecture. It implements a 16-bit data
bus and supports both 8 and 16 bit-per-pixel color depths. The design does not support
VGA planar mode.
The BitBlt engine supports rectangular and linear addressing modes for source and destination in a positive direction for all BitBlt operations except the move blit which also
supports in negative direction.
The BitBlt operations support byte alignment of all types. The BitBlt engine has a dedicated
BitBlt IO access space allowing it to support multi-tasking applications. This allows the
BitBlt engine to support simultaneous BitBlt and CPU read/write operations.
9.2 BitBlt Operations
Note
For details on the operation of the BitBlt registers, see Section 8.3.12, “BitBlt Configuration Registers” on page 161.
Write Blit
The Write Blit provides 16, two operand, ROP functions.
Move Blit
The Move Blit provides 16, two operand, ROP functions and is supported in both a positive
and negative direction.
Read Blit
The Read Blit supports bit block transfers from the display buffer to the host. No ROP
function is applied.
S1D13506
X25B-A-001-10
Hardware Functional Specification
Issue Date: 01/02/06
Epson Research and Development
Vancouver Design Center
Page 179
Solid Fill
The Solid Fill Blit fills a specified blit area with a solid color as defined in the Foreground
Color Register. In 8 bpp mode, only the low byte of the Foreground Color is used for solid
fill.
Pattern Fill
The Pattern Fill Blit fills a specified blit area with an 8 pixel by 8 line pattern in full color
defined in off-screen display buffer. The pattern data has to be stored in a contiguous
address (i.e. for 8 and 16 bpp, the pattern data will occupy 64 and 128 bytes respectively
starting from the base address).
Any pixel within the 8x8 pattern can be used to start the fill area. The least significant bits
of the source address start register are used to specify the starting pixel.
The 2D engine can detects the end of each line and continues from the beginning of the next
line. When the last line of pattern is encountered, the first line of the pattern will be drawn
on the following line.
Supports two full 16-bit operand ROP functions.
Note
The BitBlt operation Pattern Fill with ROP requires a BitBlt width ≥ 2. The BitBlt width
is set in REG[110h], REG[111h].
Transparent Pattern Fill
The Transparent Pattern Fill fills a specified blit area with an 8 pixel by 8 line pattern in full
color defined in off-screen display buffer. The pattern data has to be stored in a contiguous
address (i.e. for 8 and 16 bpp, the pattern data will occupy 64 and 128 bytes respectively
starting from the base address).
When the pattern color is equal to the key color, which is defined in Background Color
Register, the destination area is not updated. In 8 bpp mode, only the low byte of the key
color is used for comparison.
For this blit no raster operation is applied.
Note
The BitBlt operation Pattern Fill with transparency requires a BitBlt width ≥ 2. The
BitBlt width is set in REG[110h], REG[111h].
Transparent Write Blit
The Transparent Write Blit supports bit block transfers from the host to display buffer.
Hardware Functional Specification
Issue Date: 01/02/06
S1D13506
X25B-A-001-10
Page 180
Epson Research and Development
Vancouver Design Center
When the source color is equal to key color, which is defined in Background Color
Register, the destination area is not updated. In 8 bpp mode, only the low byte of the key
color is used for comparison.
For this blit no raster operation is applied.
S1D13506
X25B-A-001-10
Hardware Functional Specification
Issue Date: 01/02/06
Epson Research and Development
Vancouver Design Center
Page 181
Transparent Move Blit
The Transparent Move Blit supports bit block transfers from display buffer to display
buffer in positive direction only.
When the source color is equal to key color, which is defined in Background Color
Register, the destination area is not updated. In 8 bpp mode, only the low byte of key color
is used for comparison.
For this blit no raster operation is applied.
Color Expansion
The Color Expansion Blit expands the host’s monochrome data to 8 or 16 bpp color format.
A 1 expands to the color defined in the Foreground Color Register. In 8 bpp mode, only the
low byte of the Foreground Color Register is used.
A 0 expands to the color defined in the Background Color Register. In 8 bpp mode, only
the low byte of the Background Color Register is used. If background transparency is
enabled, then the destination color will remain untouched.
The host will be continuously feeding a 16-bit data package. When the end of the line is
reached, any unused bits will be discarded. The data for the next line will be taken from the
next data package. The low byte write data will be used first for the operation. Each bit is
serially expanded to the destination data starting from MSB (Bit 7) to LSB (Bit 0).
This blit supports any bit alignment, but supports in a positive direction only.
Move Blit with Color Expansion
The Move Blit with Color Expansion expands off-screen source’s monochrome data to 8
or 16 bpp color format.
A 1 expands to the color defined in the Foreground Color Register.
A 0 expands to the color defined in the Background Color Register. If background transparency is enabled, then the destination color will remain untouched.
In 8 bpp mode, only the low byte of the Foreground Color Register and Background Color
Register are used for color expansion. The low byte write data will be used first for the
operation. Each bit is serially expanded to the destination data starting from MSB (Bit 7) to
LSB (Bit 0).
This blit supports byte alignment only and supports in a positive direction only.
Hardware Functional Specification
Issue Date: 01/02/06
S1D13506
X25B-A-001-10
Page 182
Epson Research and Development
Vancouver Design Center
10 Display Buffer
The system addresses the display buffer through the CS#, M/R#, and AB[20:0] input pins.
When CS# = 0 and M/R# = 1, the display buffer is addressed by bits AB[20:0]. See the table
below:
Table 10-1: S1D13506 Addressing
CS#
M/R#
Access
Register access - see Section 8.2, “Register Mapping” on
page 124.
• REG[000h] is addressed when AB[12:0] = 0
• REG[001h] is addressed when AB[12:0] = 1
• REG[n] is addressed when AB[12:0] = n
0
0
0
1
Memory access: the 2M byte display buffer is addressed by
AB[20:0]
1
X
S1D13506 not selected
The display buffer address space is always 2M bytes. However, the physical display buffer
may be either 512K bytes or 2M bytes – see Section 5.3, “Summary of Configuration
Options” on page 39.
A 512K byte display buffer is replicated in the 2M byte address space – see Figure 10-1:
“Display Buffer Addressing,” on page 182.
The display buffer can contain an image buffer, one or more Ink Layer/Hardware Cursor
buffers, and a Dual Panel Buffer.
512K Byte Buffer
AB[20:0]
2M Byte Buffer
000000h
Image Buffer
Ink/Cursor Buffer
Dual Panel Buffer
Image Buffer
07FFFFh
080000h
Image Buffer
Ink/Cursor Buffer
Dual Panel Buffer
Image Buffer
Ink/Cursor Buffer
Dual Panel Buffer
Image Buffer
Ink/Cursor Buffer
Dual Panel Buffer
0FFFFFh
100000h
17FFFFh
180000h
Ink/Cursor Buffer
1FFFFFh
Dual Panel Buffer
Figure 10-1: Display Buffer Addressing
S1D13506
X25B-A-001-10
Hardware Functional Specification
Issue Date: 01/02/06
Epson Research and Development
Vancouver Design Center
Page 183
10.1 Image Buffer
The image buffer contains the formatted display mode data – see Section 11.1, “Display
Mode Data Format” on page 184.
The displayed image(s) may occupy only a portion of this space; the remaining area may
be used for multiple images – possibly for animation or general storage. Section 11,
“Display Configuration” on page 184 for the relationship between the image buffer and the
displayed image.
10.2 Ink Layer/Hardware Cursor Buffers
The Ink Layer/Hardware Cursor buffers contain formatted image data for the Ink Layer and
Hardware Cursor.
There may be several Ink Layer/Hardware Cursor images stored in the display buffer but
only one may be active at any given time.
For details see Section 14, “Ink Layer/Hardware Cursor Architecture” on page 197.
10.3 Dual Panel Buffer
In dual panel mode a buffer is required and allocated by hardware. With this Dual Panel
Buffer enabled, the top of the display buffer is allocated to the Dual Panel Buffer. The size
of the Dual Panel Buffer is a function of the panel resolution and whether the panel is color
or monochrome:
Dual Panel Buffer Size (in bytes) = (panel width x panel height) x factor / 16
where factor: = 4 for color panel
= 1 for monochrome panel
Note
Calculating the size of the Dual Panel Buffer is required to avoid overwriting the
Hardware Cursor/Ink Layer buffer.
Example 1: For a 640x480 8 bpp color panel the Dual Panel Buffer size is 75K bytes. In a
512K byte display buffer, the Dual Panel Buffer resides from 6D400h to
7FFFFh. In a 2M byte display buffer, the Dual Panel Buffer resides from
1ED400h to 1FFFFFh.
Hardware Functional Specification
Issue Date: 01/02/06
S1D13506
X25B-A-001-10
Page 184
Epson Research and Development
Vancouver Design Center
11 Display Configuration
11.1 Display Mode Data Format
The following diagrams show the display mode data formats for a little endian system:
.
4 bpp:
bit 7
bit 0
Byte 0
A0
B0
C0
D0
A1
B1
C1
D1
Byte 1
A2
B2
C2
D2
A3
B3
C3
D3
Byte 2
A4
B4
C4
D4
A5
B5
C5
D5
Host Address
P0 P1 P2 P3 P4 P5 P6 P7
Pn = (An, Bn, Cn, Dn)
Panel Display
Display Buffer
8 bpp:
bit 7
bit 0
G0
H0
A0
B0
C0
D0
E0
F0
Byte 1
A1
B1
C1
D1
E1
F1
G1
H1
Byte 2
A2
B2
C2
D2
E2
F2
G2
H2
Byte 0
Host Address
P0 P1 P2 P3 P4 P5 P6 P7
Pn = (An, Bn, Cn, Dn,En, Fn, Gn, Hn)
Panel Display
Display Buffer
15 bpp:
5-5-5 RGB
bit 7
bit 0
Byte 0
G02 G01 G00 B04 B03 B02 B01 B00
Byte 1
R04 R03 R02 R01 R00 G04 G03
Byte 2
G12 G11 G10 B14 B13 B12 B11 B10
Byte 3
R14 R13 R12 R11 R10 G14 G13
Host Address
P0 P1 P2 P3 P4 P5 P6 P7
Pn = (Rn4-0, Gn 4-0, Bn4-0)
Panel Display
Display Buffer
16 bpp:
5-6-5 RGB
bit 7
2
G0
1
0
3
bit 0
2
1
B0
4
G 03
G0
Byte 1
R04
Byte 2
G12 G11 G10 B14 B13 B12 B11 B10
Byte 3
R14 R13 R12 R11 R10 G15 G14 G13
Host Address
G0
R02
R0
1
B0
R0
0
B0
G0
5
B0
G0
P0 P1 P2 P3 P4 P5 P6 P7
0
Byte 0
R03
B0
4
Pn = (Rn4-0, Gn 5-0, Bn4-0)
Panel Display
Display Buffer
Figure 11-1: 4/8/15/16 Bit-per-pixel Format Memory Organization
Note
1. The Host-to-Display mapping shown here is for a little endian system.
2. For 15/16 bit-per-pixel formats, Rn, Gn, Bn represent the red, green, and blue color
components.
S1D13506
X25B-A-001-10
Hardware Functional Specification
Issue Date: 01/02/06
Epson Research and Development
Vancouver Design Center
Page 185
11.2 Image Manipulation
The figure below shows how the screen image is stored in the image buffer and positioned
on the LCD display. The screen image on the CRT/TV is manipulated similarly. When
EISD is enabled (see Section 16, “EPSON Independent Simultaneous Display (EISD)” on
page 210), the images on the LCD and on the CRT/TV are independent of each other.
• For LCD: REG[047h], REG[046h] defines the width of the virtual image.
For CRT/TV: REG[067h], REG[066h] defines the width of the virtual image.
• For LCD: REG[044h], REG[043h], REG[042h] defines the starting word of the
displayed image.
For CRT/TV: REG[064h], REG[063h], REG[062h] defines the starting word of the
displayed image.
• For LCD: REG[048h] defines the starting pixel within the starting word.
For CRT/TV: REG[068h] defines the starting pixel within the starting word.
• For LCD: REG[032h] defines the width of the LCD display.
For CRT/TV: REG[050h] defines the width of the CRT/TV display.
• For LCD: REG[039h], REG[038h] defines the height of the LCD display.
For CRT/TV: REG[057h], REG[056h] defines the height of the CRT/TV display.
Image Buffer
LCD Display
Starting Word
(REG[044h], REG[043h], REG[042h])
Starting Pixel of Word (REG[048h])
Height of LCD Display ((REG[039h], REG[038h])+1) lines
Screen
Line 0
Line 1
Screen
Width of LCD Display ((REG[032h]+1)×8) pixels
Width of Virtual Image
(REG[047h], REG[046h])
Figure 11-2: Image Manipulation
Hardware Functional Specification
Issue Date: 01/02/06
S1D13506
X25B-A-001-10
Page 186
Epson Research and Development
Vancouver Design Center
12 Look-Up Table Architecture
The following depictions are intended to show the display data output path only.
12.1 Monochrome Modes
The green LUT is used for all monochrome modes.
4 Bit-Per-Pixel Monochrome Mode
Green Look-Up Table 256x4
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
4-bit Gray Data
FC
FD
FE
FF
4 bit-per-pixel data
from Image Buffer
Figure 12-1: 4 Bit-Per-Pixel Monochrome Mode Data Output Path
S1D13506
X25B-A-001-10
Hardware Functional Specification
Issue Date: 01/02/06
Epson Research and Development
Vancouver Design Center
Page 187
12.2 Color Modes
4 Bit-Per-Pixel Color
Red Look-Up Table 256x4
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
4-bit Red Data
FC
FD
FE
FF
Green Look-Up Table 256x4
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
4-bit Green Data
FC
FD
FE
FF
Blue Look-Up Table 256x4
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
4-bit Blue Data
FC
FD
FE
FF
4 bit-per-pixel data
from Image Buffer
Figure 12-2: 4 Bit-Per-Pixel Color Mode Data Output Path
Hardware Functional Specification
Issue Date: 01/02/06
S1D13506
X25B-A-001-10
Page 188
Epson Research and Development
Vancouver Design Center
8 Bit-Per-Pixel Color
Red Look-Up Table 256x4
00
01
02
03
04
05
06
07
F8
F9
FA
FB
FC
FD
FE
FF
Green Look-Up Table 256x4
00
01
02
03
04
05
06
07
F8
F9
FA
FB
FC
FD
FE
FF
Blue Look-Up Table 256x4
00
01
02
03
04
05
06
07
F8
F9
FA
FB
FC
FD
FE
FF
0000
0000
0000
0000
0000
0000
0000
0000
0000
0001
0010
0011
0100
0101
0110
0111
1111
1111
1111
1111
1111
1111
1111
1111
1000
1001
1010
1011
1100
1101
1110
1111
0000
0000
0000
0000
0000
0000
0000
0000
0000
0001
0010
0011
0100
0101
0110
0111
1111
1111
1111
1111
1111
1111
1111
1111
1000
1001
1010
1011
1100
1101
1110
1111
0000
0000
0000
0000
0000
0000
0000
0000
0000
0001
0010
0011
0100
0101
0110
0111
1111
1111
1111
1111
1111
1111
1111
1111
1000
1001
1010
1011
1100
1101
1110
1111
4-bit Red Data
4-bit Green Data
4-bit Blue Data
8 bit-per-pixel data
from Image Buffer
Figure 12-3: 8 Bit-Per-Pixel Color Mode Data Output Path
15/16 Bit-Per-Pixel Color Modes
The LUT is bypassed and the color data is directly mapped for these color depths– See
“Display Configuration” on page 184.
S1D13506
X25B-A-001-10
Hardware Functional Specification
Issue Date: 01/02/06
Epson Research and Development
Vancouver Design Center
Page 189
13 TV Considerations
13.1 NTSC/PAL Operation
NTSC or PAL video is supported in either composite or S-video format. Filters may be
enabled to reduce the distortion associated with displaying high resolution computer
images on an interlaced TV display. The image can be vertically and horizontally
positioned on the TV. Additionally, a dedicated Hardware Cursor (independent from the
LCD display) is supported.
13.2 Clock Source
The required clock frequencies for NTSC/PAL are given in the following table:
Table 13-1: Required Clock Frequencies for NTSC/PAL
TV Format
NTSC
PAL
Hardware Functional Specification
Issue Date: 01/02/06
Required Clock Frequency
14.318180 MHz (3.579545 MHz subcarrier)
17.734475 MHz (4.43361875 MHz subcarrier)
S1D13506
X25B-A-001-10
Page 190
Epson Research and Development
Vancouver Design Center
13.3 Filters
When displaying computer images on a TV, several image distortions are likely to arise:
• cross-luminance distortion.
• cross-chrominance distortion.
• flickering.
These distortions are caused by the high-resolution nature of computer images which
typically contain sharp color transitions, and sharp luminance transitions (e.g., high
contrast one pixel wide lines and fonts, window edges, etc.). Three filters are available to
reduce these distortions.
13.3.1 Chrominance Filter (REG[05Bh] bit 5)
The chrominance filter adjusts the color of the TV by limiting the bandwidth of the chrominance signal (reducing cross-luminance distortion). This reduces the “ragged edges” seen
at boundaries between sharp color transitions. This filter is controlled using REG[05Bh]
bit 5 and is most useful for composite video output.
13.3.2 Luminance Filter (REG[05Bh] bit 4)
The luminance filter adjusts the brightness of the TV by limiting the bandwidth of the
luminance signal (reducing cross-chrominance distortion). This reduces the “rainbow-like”
colors at boundaries between sharp luminance transitions. This filter is controlled using
REG[05Bh] bit 4 and is most useful for composite video output.
13.3.3 Anti-flicker Filter (REG[1FCh] bits [2:1])
The “flickering” effect seen on interlaced displays is caused by sharp vertical image transitions that occur over one line (1 vertical pixel). For example, one pixel high lines, edges of
window boxes, etc. Flickering occurs because these high resolution lines are effectively
displayed at half the refresh frequency due to interlacing. The anti-flicker filter averages
adjacent lines on the TV display to reduce flickering. This filter is controlled using the
Display Mode register (REG[1FCh] bits [2:1]).
S1D13506
X25B-A-001-10
Hardware Functional Specification
Issue Date: 01/02/06
Epson Research and Development
Vancouver Design Center
Page 191
13.4 TV Output Levels
Vwhite
Vyellow
Vcyan
Vgreen
Vmagenta
Vred
Vblue
Vblank
Vblack
Vsync
Figure 13-1: NTSC/PAL SVideo-Y (Luminance) Output Levels
Table 13-2: NTSC/PAL SVideo-Y (Luminance) Output Levels
Symbol
Vwhite
Vyellow
Vcyan
Vgreen
Vmagenta
Vred
Vblue
Vblack
Vblanking
Vsync
Parameter
White
Yellow
Cyan
Green
Magenta
Red
Blue
Black
Blanking
Sync Tip
RGB
1F
1F
00
00
1F
1F
00
00
3F 1F
3F 00
3F 1F
3F 00
00 1F
00 00
00 1F
00 00
N.A.
N.A.
NTSC / PAL
(mv)
996
923
798
725
608
536
410
338
284
0
NTSC / PAL
(IRE)
99.5
89
72
62
45
35
17
7.3
0
-40
Note
RGB values assume a 16 bpp color depth with 5-6-5 pixel packing.
Hardware Functional Specification
Issue Date: 01/02/06
S1D13506
X25B-A-001-10
Page 192
Epson Research and Development
Vancouver Design Center
V1red
V1cyan
V1green
V1magenta
V1yellow
V1blue
V2yellow
V2blue
V1burst
Vblanking
V2burst
V2green
V2magenta
V2cyan
V2red
Figure 13-2: NTSC/PAL SVideo-C (Chrominance) Output Levels
Table 13-3: NTSC/PAL SVideo-C (Chrominance) Output Levels
Symbol
V1burst
V1yellow
V1cyan
V1green
V1magenta
V1red
V1blue
Vblanking
V2burst
V2yellow
V2cyan
V2green
V2magenta
V2red
V2blue
Parameter
Burst positive peak
Yellow positive peak
Cyan positive peak
Green positive peak
Magenta positive peak
Red positive peak
Blue positive peak
Blanking
Burst negative peak
Yellow negative peak
Cyan negative peak
Green negative peak
Magenta negative peak
Red negative peak
Blue negative peak
RGB
N.A.
3F 00
3F 1F
3F 00
00 1F
00 00
00 1F
N.A.
N.A.
1F 3F 00
00 3F 1F
00 3F 00
1F 00 1F
1F 00 00
00 00 1F
1F
00
00
1F
1F
00
NTSC / PAL
(mv)
552 / 541
700
815
751
751
815
700
410
268 / 279
121
5
70
70
5
121
NTSC / PAL
(IRE)
Note
RGB values assume a 16 bpp color depth with 5-6-5 pixel packing.
S1D13506
X25B-A-001-10
Hardware Functional Specification
Issue Date: 01/02/06
Epson Research and Development
Vancouver Design Center
Page 193
V1 yellow
V1cyan
V1green
Vwhite
V2yellow
V1magenta
V2cyan
V1red
V2green
V3yellow
V2magenta
V1blue
V2red
V1burst
Vblank
V2blue
V3cyan
Vblack
V3green
V2burst
Vsync
V3magenta
V3red
V3blue
Figure 13-3: NTSC/PAL Composite Output Levels
Table 13-4: NTSC/PAL Composite Output Levels
Symbol
V1yellow
V1cyan
V1green
V1magenta
V1red
V1blue
Vwhite
V2yellow
V2cyan
V2green
V2magenta
V2red
V2blue
Vblack
V3yellow
V3cyan
V3green
V3magenta
V3red
V3blue
Vblank
V1burst
V2burst
Vsync
Parameter
Yellow chrominance positive peak
Cyan chrominance positive peak
Green chrominance positive peak
Magenta chrominance positive peak
Red chrominance positive peak
Blue chrominance positive peak
White luminance level
Yellow luminance level
Cyan luminance level
Green luminance level
Magenta luminance level
Red luminance level
Blue luminance level
Black luminance level
Yellow chrominance negative peak
Cyan chrominance negative peak
Green chrominance negative peak
Magenta chrominance negative peak
Red chrominance negative peak
Blue chrominance negative peak
Blank Level
Burst positive peak
Burst negative peak
Sync Tip
RGB
1F 3F 00
00 3F 1F
00 3F 00
1F 00 1F
1F 00 00
00 00 1F
1F 3F 1F
1F 3F 00
00 3F 1F
00 3F 00
1F 00 1F
1F 00 00
00 00 1F
00 00 00
1F 3F 00
00 3F 1F
00 3F 00
1F 00 1F
1F 00 00
00 00 1F
N.A.
N.A.
N.A.
N.A.
NTSC / PAL (mv) NTSC / PAL (IRE)
1211
130
1202
128
1065
109
948
93
939
92
699
58
995
99
923
89
797
72
725
62
608
45
535
35
411
18
338
7.3
634
49
392
15
384
14
267
-2.6
130
-22
122
-23
284
0
426 / 415
20 / 18
142 / 153
-20 / -19
0
-40
Note
RGB values assume a 16 bpp color depth with 5-6-5 pixel packing.
Hardware Functional Specification
Issue Date: 01/02/06
S1D13506
X25B-A-001-10
Page 194
Epson Research and Development
Vancouver Design Center
13.5 TV Image Display and Positioning
This section describes how to setup and position an image to be displayed on a TV. Figure
13-4: “NTSC/PAL Image Positioning,” on page 195 shows an image positioned on the TV
display with the related programmable parameters. The TV display area is shaded.
The size of the display image determines the register values for the Horizontal Display
Period, Horizontal Non-Display Period, Vertical Display Period, and Vertical Non-Display
Period. The maximum and minimum values for these registers are given in Table 13-5:
“Minimum and Maximum Values for NTSC/PAL”. The line period and frame period determined by these registers must also satisfy the following equations:
NTSC:
(((REG[050] bits[6:0]) + 1) x 8) + (((REG[052] bits[5:0]) x 8) + 6) = 910
({(REG[057] bits[1:0]), (REG[056] bits[7:0])}+1) + ((REG[058] bits[6:0])+1)x2+1) = 525
PAL:
(((REG[050] bits[6:0]) + 1) x 8) + (((REG[052] bits[5:0]) x 8) + 7) = 1135
({(REG[057] bits[1:0]), (REG[056] bits[7:0])}+1) + ((REG[058] bits[6:0])+1)x2+1) = 625
The HRTC Start Position and VRTC Start Position registers position the image horizontally
and vertically. The maximum and minimum register values for these registers are given in
Table 13-5: “Minimum and Maximum Values for NTSC/PAL”. Increasing the HRTC Start
Position will move the image left, while increasing the VRTC Start Position will move the
image up.
S1D13506
X25B-A-001-10
Hardware Functional Specification
Issue Date: 01/02/06
Epson Research and Development
Vancouver Design Center
Page 195
t1
t2
t3
t6
t5
Vertical
Sync
Odd
Field
1, 3
t4 / 2
Image
Odd Lines (1, 3, 5, ...)
t6
Vertical
Sync
t5 + 1TLINE
Even
Field
2, 4
t4 / 2
Even Lines (2, 4, 6, ...)
t3
0
909 (NTSC)
1134 (PAL)
Horizontal Sync
Figure 13-4: NTSC/PAL Image Positioning
The maximum Horizontal and Vertical Display Widths shown in Table 13-5: “Minimum
and Maximum Values for NTSC/PAL” include display areas that are normally hidden by
the edges of the TV. The visible display dimensions are shown in Figure 13-5: “Typical
Total Display and Visible Display Dimensions for NTSC and PAL,” on page 196 as a
guideline. The actual visible display area for a particular TV may differ slightly from those
dimensions given. Table 13-6: “Register Values for Example NTSC/PAL Images” lists
register values for some example images.
Table 13-5: Minimum and Maximum Values for NTSC/PAL
Symbol
t1
t2
t3
t4
t5
t6
Parameter
TV Horizontal Non-Display Period
TV Horizontal Display Width
TV HRTC Start Position
TV Vertical Display Height
TV Vertical Non-Display Period
TV VRTC Start Position
Hardware Functional Specification
Issue Date: 01/02/06
Register(s)
52
50
53
57, 56
58
59
NTSC
min
max
158
510
400
752
25
t2 - 158
396
484
20
64
0
t5 - 20
PAL
min
215
624
25
496
26
0
max
511
920
t2 - 215
572
64
t5 - 26
Units
T4SC
T4SC
T4SC
TLINE
TLINE
TLINE
S1D13506
X25B-A-001-10
Page 196
Epson Research and Development
Vancouver Design Center
Total Display
752 x 484
Total Display
920 x 572
Visible Display
696 x 436
Visible Display
856 x 518
NTSC
PAL
Figure 13-5: Typical Total Display and Visible Display Dimensions for NTSC and PAL
Note
For most implementations, the visible display does not equal the total display. The total
display dimensions and the visible display dimensions must be determined for each
specific implementation.
Table 13-6: Register Values for Example NTSC/PAL Images
Parameter
Register
TV Horizontal Display Width
TV Horizontal Non-Display Period
TV HRTC Start Position
50
52
53
57
56
58
59
TV Vertical Display Height
TV Vertical Non-Display Period
TV VRTC Start Position
NTSC
PAL
752x484 696x436 640x480 920x572 856x518 800x572 640x480
5Dh
56h
4Fh
72h
6Ah
63h
4Fh
13h
1Ah
21h
1Ah
22h
29h
3Dh
02h
04h
08h
02h
05h
09h
13h
01h
01h
01h
02h
02h
02h
01h
E3h
B3h
DFh
3Bh
05h
3Bh
DFh
13h
2Bh
15h
19h
34h
19h
47h
00h
0Ch
01h
00h
0Dh
00h
16h
13.6 TV Cursor Operation
See Section 14, “Ink Layer/Hardware Cursor Architecture” on page 197.
S1D13506
X25B-A-001-10
Hardware Functional Specification
Issue Date: 01/02/06
Epson Research and Development
Vancouver Design Center
Page 197
14 Ink Layer/Hardware Cursor Architecture
14.1 Ink Layer/Hardware Cursor Buffers
The Ink Layer/Hardware Cursor buffers contain formatted image data for the Ink Layer or
Hardware Cursor. There may be several Ink Layer/Hardware Cursor images stored in the
display buffer but only one may be active at any given time. The active Ink Layer/Hardware
Cursor buffer is selected by the Ink/Cursor Start Address register (REG[071h] for LCD,
REG[081h] for CRT/TV). This register defines the start address for the active Ink/Cursor
buffer. The Ink/Cursor buffer must be positioned where it does not conflict with the image
buffer and Dual Panel Buffer. The start address for the Ink/Cursor buffer is programmed as
shown in the following table.
Table 14-1: Ink/Cursor Start Address Encoding
Ink/Cursor Start
Address Bits [7:0]
Start Address (Bytes)
0
Display Buffer Size - 1024
Comments
This default value is suitable for a cursor
when there is no Dual Panel Buffer.
These positions can be used to:
n = 255...1
Display Buffer Size (n × 8192)
• position an Ink buffer at the top of the
display buffer;
• position an Ink buffer between the image
and Dual Panel Buffers;
• position a Cursor buffer between the
image and Dual Panel Buffers;
• select from a multiple of Cursor buffers.
The Ink/Cursor image is stored contiguously. The address offset from the starting word of
line n to the starting word of line n+1 is calculated as follows:
LCD Ink Address Offset (words) = REG[032h] + 1
CRT/TV Ink Address Offset (words) = REG[050h] + 1
LCD or CRT/TV Cursor Address Offset (words) = 8
Hardware Functional Specification
Issue Date: 01/02/06
S1D13506
X25B-A-001-10
Page 198
Epson Research and Development
Vancouver Design Center
14.2 Ink/Cursor Data Format
The Ink/Cursor image is always 2 bit-per-pixel. The following diagram shows the
Ink/Cursor data format for a little endian system.
2-bpp:
bit 7
bit 0
Byte 0
A0
B0
A1
B1
A2
B2
A3
B3
Byte 1
A4
B4
A5
B5
A6
B6
A7
B7
P0 P1 P2 P3 P4 P5 P6 P7
Pn = (An, Bn)
Panel Display
Host Address
Ink/Cursor Buffer
Figure 14-1: Ink/Cursor Data Format
The image data for pixel n, (An,Bn), selects the color for pixel n as follows.
Table 14-2: Ink/Cursor Color Select
(An,Bn)
Color
00
Color 0
Ink/Cursor Color 0 Register, (REG[078h], REG[077h],
REG[076h] for LCD, REG[088h], REG[087h], REG[086h] for
CRT/TV)
01
Color 1
Ink/Cursor Color 1 Register, (REG[07Ah],
REG[07Bh],REG[07Ah] for LCD, REG[08Ah], REG[08Bh],
REG[08Ah] for CRT/TV)
10
Background
11
Inverted Background
S1D13506
X25B-A-001-10
Comments
Ink/Cursor is transparent – show background
Ink/Cursor is transparent – show inverted background
Hardware Functional Specification
Issue Date: 01/02/06
Epson Research and Development
Vancouver Design Center
Page 199
14.3 Ink/Cursor Image Manipulation
14.3.1 Ink Image
The Ink image should always start at the top left pixel, i.e. Cursor X Position and Cursor Y
Position registers should always be set to zero. The width and height of the ink image are
automatically calculated to completely cover the display.
14.3.2 Cursor Image
The Cursor image size is always 64 x 64 pixels. The Cursor X Position and Cursor Y
Position registers specify the position of the top left pixel. The following diagram shows
how to position an unclipped cursor.
P(0;0)
P(x;y)
P(x+63;y)
P(x;y+63)
P(x+63;y+63)
Figure 14-2: Unclipped Cursor Positioning
where
For LCD:
x = (REG[073h] bits [1:0], REG[072h]) and REG[073h] bit 7 = 0
y = (REG[075h] bits [1:0], REG[074h]) and REG[075h] bit 7 = 0
For CRT/TV:
x = (REG[083h] bits [1:0], REG[082h]) and REG[083h] bit 7 = 0
y = (REG[085h] bits [1:0], REG[084h]) and REG[085h] bit 7 = 0
The following diagram shows how to position a cursor that is clipped at the top and left
sides of the display.
Hardware Functional Specification
Issue Date: 01/02/06
S1D13506
X25B-A-001-10
Page 200
Epson Research and Development
Vancouver Design Center
P(-x;-y)
P(0;0)
P(63-x;63-y)
Figure 14-3: Clipped Cursor Positioning
where
For LCD:
x = (REG[073h] bits [1:0], REG[072h]) <= 63 and REG[073h] bit 7 = 1
y = (REG[075h] bits [1:0], REG[074h]) <= 63 and REG[075h] bit 7 = 1
For CRT/TV:
x = (REG[083h] bits [1:0], REG[082h]) <= 63 and REG[083h] bit 7 = 1
y = (REG[085h] bits [1:0], REG[084h]) <= 63 and REG[085h] bit 7 = 1
S1D13506
X25B-A-001-10
Hardware Functional Specification
Issue Date: 01/02/06
Epson Research and Development
Vancouver Design Center
Page 201
15 SwivelView™
15.1 Concept
Most computer displays are refreshed in landscape – from left to right and top to bottom.
Computer images are stored in the same manner. SwivelView™ is designed to rotate the
displayed image on an LCD by 90°, 180°, or 270° in a clockwise direction. The rotation is
done in hardware and is transparent to the user for all display buffer reads and writes. By
processing the rotation in hardware, SwivelView™ offers a performance advantage over
software rotation of the displayed image.
15.2 90° SwivelView™
90° SwivelView™ uses a 1024 × 1024 pixel virtual window. The following figures show
how the display buffer memory map changes in 90° SwivelView™. The display is
refreshed in the following sense: C–A–D–B. The application image is written to the
S1D13506 in the following sense: A–B–C–D. The S1D13506 rotates and stores the
application image in the following sense: C–A–D–B, the same sense as display refresh.
The user can read/write to the display buffer naturally, without the need to rotate the image
first in software. The registers that control the panning and scrolling of the panel window
are designed for a landscape window. However, it is still possible to pan and scroll the
portrait window in 90° SwivelView™, but the user must program these registers somewhat
differently (See Section 15.2.1, “Register Programming” on page 202).
1024 pixels
B
portrait
window
H
B
D
W
1024 pixels
display
start
address
portrait
window
A
C
A
1024 pixels
W
D
C
H
Image seen by the user
Rotated image in the display buffer
Figure 15-1: Relationship Between Screen Image and 90° Rotated Image in the Display Buffer
Hardware Functional Specification
Issue Date: 01/02/06
S1D13506
X25B-A-001-10
Page 202
Epson Research and Development
Vancouver Design Center
Note
W is the width of the LCD panel in number of pixels, (or the height of the portrait window in number of lines).
H is the height of the panel in number of lines, (or the width of the portrait window in
number of pixels).
Note
The image must be written with a 1024 pixel offset between adjacent lines (1024 bytes
for 8 bpp mode or 2048 bytes for 15/16 bpp mode) and the display start address must be
calculated (see below).
15.2.1 Register Programming
Enabling 90° Rotation on CPU Read/Write to Display Buffer
Set SwivelView™ Enable bit 0 to 1. All CPU accesses to the display buffer are translated
to provide 90° clockwise rotation of the display image. SwivelView™ Enable bit 1 should
be set to 0.
Memory Address Offset
The LCD Memory Address Offset register (REG[046h], REG[047h]) must be set for a
1024 pixel offset:
LCD Memory Address Offset (words)
= 1024
for 15/16 bpp mode
= 512
for 8 bpp mode
Display Start Address
As seen in Figure 15-1: “Relationship Between Screen Image and 90° Rotated Image in the
Display Buffer,” on page 201, the Display Start Address is determined by the location of
the image corner “C”, and it is generally non-zero. The LCD Display Start Address register
(REG[042h], REG[043h], REG[044h]) must be set accordingly.
LCD Display Start Address (words)
= (1024 - W)
= (1024 - W) / 2
for 15/16 bpp mode
for 8 bpp mode
where W is the width of the panel in number of pixels.
S1D13506
X25B-A-001-10
Hardware Functional Specification
Issue Date: 01/02/06
Epson Research and Development
Vancouver Design Center
Page 203
Horizontal Panning
Horizontal panning is achieved by changing the LCD Display Start Address register:
• Increase/decrease LCD Display Start Address register by 1024 (15/16 bpp mode) or 512
(8 bpp mode) pans the display window to the right/left by 1 pixel.
The amount the display window can be panned to the right is limited to 1024 pixels and
limited by the amount of physical memory installed.
Vertical Scrolling
Vertical scrolling is achieved by changing the LCD Display Start Address register and/or
the LCD Pixel Panning register:
• Increment/decrement LCD Display Start Address register in 8 bpp mode scrolls the
display window up/down by 2 lines.
• Increment/decrement LCD Display Start Address register in 15/16 bpp mode scrolls the
display window up/down by 1 line.
• Increment/decrement LCD Pixel Panning register in 8 bpp mode scrolls the display
window up/down by 1 line.
15.2.2 Physical Memory Requirement
Because the user must now deal with a 1024×1024 virtual display, the amount of image
buffer required for a particular display mode has increased. The minimum amount of image
buffer required is:
Minimum Required Image Buffer (bytes)
= (1024 × H) × 2
for 15/16 bpp mode
= (1024 × H)
for 8 bpp mode
where H is the height of the panel in number of lines.
This minimum amount is required to display a 90° SwivelView™ image without panning;
scrolling, however, is permissible. The degree an image can be panned depends on the
amount of physical memory installed and how much of that is used by the Dual Panel
Buffer, Ink Layer, or Hardware Cursor. An image cannot be panned outside the 1024×1024
virtual display. Often it cannot be panned within the entire virtual display because part of
the virtual display memory may be taken up by the Dual Panel Buffer, Ink Layer, Hardware
Cursor, or even the CRT/TV display buffer.
Hardware Functional Specification
Issue Date: 01/02/06
S1D13506
X25B-A-001-10
Page 204
Epson Research and Development
Vancouver Design Center
The Dual Panel Buffer is used for dual panel mode. Its memory requirement is:
Dual Panel Buffer (bytes)
=(W × H) / 4
=(W × H) / 16
for color mode
for monochrome mode
where W is the width of the panel in number of pixels, and H is the height of the panel in
number of lines.
The Dual Panel Buffer is always located at the end of the physical memory.
The Hardware Cursor or Ink Layer also takes up memory. If this memory is > 1KB, it must
be located at an 8KB boundary, otherwise it may be located at the last 1KB area. The
Hardware Cursor or Ink Layer must not overlap the image buffer or the Dual Panel Buffer.
The following table summarizes the DRAM size requirement for 90° SwivelView™ for
different panel sizes and display modes. Note that DRAM size for the S1D13506 is limited
to either 512K byte or 2M byte. The calculation is based on the minimum required image
buffer size and the Dual Panel Buffer size. The Hardware Cursor/Ink Layer may or may not
fit within this minimum DRAM configuration – this is noted in the table. The hardware
cursor requires only 1KB of memory and so may resides at the last 1KB area if there is no
Dual Panel Buffer, otherwise it must reside at an 8KB boundary. The 2-bit ink layer
requires (W × H) / 4 bytes of memory; it must reside at an 8KB boundary. The table shows
only one possible Hardware Cursor/Ink Layer location – at the highest possible location
without interfering with the Dual Panel Buffer. It is also assumed that CRT/TV is not used.
S1D13506
X25B-A-001-10
Hardware Functional Specification
Issue Date: 01/02/06
Epson Research and Development
Vancouver Design Center
Page 205
Table 15-1: Minimum DRAM Size Required for SwivelView™
Panel Size
Panel Type
Color
320 × 240
Single
Mono
Color
Single
Mono
640 × 480
Color
Dual
Mono
Color
Single
Mono
800 × 600
Color
Dual
Mono
Display
Mode
Min. Image
Buffer Size
8 bpp
240KB
15/16 bpp
480KB
8 bpp
240KB
15/16 bpp
480KB
8 bpp
480KB
15/16 bpp
960KB
8 bpp
480KB
15/16 bpp
960KB
8 bpp
480KB
15/16 bpp
960KB
8 bpp
480KB
15/16 bpp
960KB
8 bpp
600KB
15/16 bpp
1.2MB
8 bpp
600KB
15/16 bpp
1.2MB
8 bpp
600KB
15/16 bpp
1.2MB
8 bpp
600KB
15/16 bpp
1.2MB
Dual Panel
Buffer Size
Minimum
DRAM Size
0KB
512KB
Ink/Cursor
Buffer Size
Ink/Cursor
Location
18.75KB/1KB
488KB/511KB
--/511KB
0KB
75KB
18.75KB
2MB
1968KB/2047KB
512KB
2MB
--/511KB
75KB/1KB
1968KB/2047KB
1896KB/1968KB
512KB
--/488KB
1952KB/2024KB
0KB
1928KB/2047KB
2MB
117.19KB/1KB
117.19KB
1808KB/1928KB
29.30KB
1896KB/2016KB
Where KB = 1024 bytes and MB = 1024KB
15.2.3 Limitations
The following limitations apply to 90° SwivelView™:
• Only 8/15/16 bpp modes are supported – 4 bpp mode is not supported.
• Hardware cursor and ink images are not rotated – software rotation must be used.
SwivelView™ Enable bit 0 must be set to 0 when the user is accessing the Hardware
Cursor or the Ink Layer buffer.
• CRT/TV mode is not supported. SwivelView™ Enable bit 0 must be set to 0 when the
user is accessing the CRT/TV display buffer.
• 90° SwivelView™ does not support BitBlts.
Hardware Functional Specification
Issue Date: 01/02/06
S1D13506
X25B-A-001-10
Page 206
Epson Research and Development
Vancouver Design Center
15.3 180° SwivelView™
180° SwivelView™ is accomplished by fetching the display buffer image in the reverse
address direction, starting at the bottom-right corner of the image. Unlike 90°
SwivelView™, the 180° SwivelView™ image is not rotated in the display buffer. The
image is simply displayed 180° clockwise rotated. Furthermore, a virtual window is not
required and all color depths (4/8/15/16 bpp) are supported.
15.3.1 Register Programming
Reverse Display Buffer Fetching Address Direction
Set SwivelView™ Enable bit 1 to 1. During screen refresh, the direction of the address for
display buffer fetching is reversed. This setting does not affect CPU to display buffer access
in any way. SwivelView™ Enable bit 0 should be set to 0.
Display Start Address
The Display Start Address must be programmed to be at the bottom-right corner of the
image, since the display is now refreshed in the reverse direction. The LCD Display Start
Address register (REG[042h], REG[043h], REG[044h]) must be set accordingly.
LCD Display Start Address (words)
= (MA_Offset × H) − (MA_Offset − W) − 1
= (MA_Offset × H) − (MA_Offset − W/2) − 1
= (MA_Offset × H) − (MA_Offset − W/4) − 1
for 15/16 bpp mode
for 8 bpp mode
for 4 bpp mode
where H is the height of the panel in number of lines, W is the width of the panel in number
of pixels, and MA_Offset is the LCD Memory Address Offset.
Horizontal Panning
Horizontal panning works in the same way as when SwivelView™ is not enabled, except
that the effect of the LCD Pixel Panning register is reversed:
• Increment/decrement LCD Display Start Address register pans the display window to
the right/left.
• Increment/decrement LCD Pixel Panning register pans the display window to the
left/right.
Vertical Panning
Vertical panning works in the same way as when SwivelView™ is not enabled:
• Increase/decrease LCD Display Start Address register by one memory address offset
scrolls the display window down/up by 1 line.
S1D13506
X25B-A-001-10
Hardware Functional Specification
Issue Date: 01/02/06
Epson Research and Development
Vancouver Design Center
Page 207
15.3.2 Limitations
The following limitations apply to 180° SwivelView™:
• Hardware Cursor and Ink Layer images are not rotated – software rotation must be used.
• CRT/TV mode is not supported.
• 180° SwivelView™ does not support all BitBlts.
15.4 270° SwivelView™
270° SwivelView™ is a combination of 90° SwivelView™ and 180° SwivelView™. The
image stored in the display buffer is 90° rotated, and the image is further 180° rotated
during screen refresh, resulting in a 270° rotated display image. The user must use a 1024
× 1024 pixel virtual window as in 90° SwivelView™. See Figure 15-1: “Relationship
Between Screen Image and 90° Rotated Image in the Display Buffer,” on page 201.
15.4.1 Register Programming
Enabling 90° Rotation on CPU Read/Write to Display Buffer
Set SwivelView™ Enable bit 0 to 1. All CPU access to the display buffer is translated to
provide 90° clockwise rotation of the display image.
Reverse Display Buffer Fetching Address Direction
Set SwivelView™ Enable bit 1 to 1. During screen refresh, the direction of the address for
display buffer fetching is reversed. This setting does not affect CPU to display buffer access
in any way.
Memory Address Offset
The LCD Memory Address Offset register (REG[046h], REG[047h]) must be set for a
1024 pixel offset.
LCD Memory Address Offset (words)
= 1024
for 15/16 bpp mode
= 512
for 8 bpp mode
Hardware Functional Specification
Issue Date: 01/02/06
S1D13506
X25B-A-001-10
Page 208
Epson Research and Development
Vancouver Design Center
Display Start Address
The Display Start Address must be programmed to be at the bottom-right corner of the
image, since the display is now refreshed in the reverse direction. The LCD Display Start
Address register (REG[042h], REG[043h], REG[044h]) must be set accordingly.
LCD Display Start Address (words)
= ((LCD Memory Address Offset) × H) − 1
where H is the height of the panel in number of lines.
Horizontal Panning
Horizontal panning is achieved by changing the LCD Display Start Address register. It
works in the same way as in 90° SwivelView™ mode:
• Increase/decrease LCD Display Start Address register by 1024 (15/16 bpp mode) or 512
(8 bpp mode) pans the display window to the right/left by 1 pixel.
The amount the display window can be panned to the right is limited to 1024 pixels and
limited by the amount of physical memory installed.
Vertical Scrolling
Vertical scrolling is achieved by changing the LCD Display Start Address register and/or
the LCD Pixel Panning register. It works in the same way as in 90° SwivelView™ mode,
except that the effect of the LCD Pixel Panning register is reversed:
• Increment/decrement LCD Display Start Address register in 8 bpp mode scrolls the
display window up/down by 2 lines.
• Increment/decrement LCD Display Start Address register in 15/16 bpp mode scrolls the
display window up/down by 1 line.
• Increment/decrement LCD Pixel Panning register in 8 bpp mode scrolls the display
window down/up by 1 line.
15.4.2 Physical Memory Requirement
270° SwivelView™ mode has the same physical memory requirement as in 90°
SwivelView™ mode.
S1D13506
X25B-A-001-10
Hardware Functional Specification
Issue Date: 01/02/06
Epson Research and Development
Vancouver Design Center
Page 209
15.4.3 Limitations
The following limitations apply to 270° SwivelView™:
• Only 8/15/16 bpp modes are supported – 4 bpp mode is not supported.
• Hardware Cursor and Ink Layer images are not rotated – software rotation must be used.
SwivelView™ Enable bit 0 must be set to 0 when the user is accessing the Hardware
Cursor or the Ink Layer memory.
• CRT/TV mode is not supported. SwivelView™ Enable bit 0 must be set to 0 when the
user is accessing the CRT/TV display buffer.
• 270° SwivelView™ does not support BitBlts.
Hardware Functional Specification
Issue Date: 01/02/06
S1D13506
X25B-A-001-10
Page 210
Epson Research and Development
Vancouver Design Center
16 EPSON Independent Simultaneous Display (EISD)
16.1 Introduction
EPSON Independent Simultaneous Display (EISD) allows the S1D13506 to display
independent images on two different displays (LCD panel and CRT or TV). The LCD panel
timings and mode setup are programmed through the Panel Configuration Registers
(REG[03Xh]) and the LCD Display Mode Registers (REG[04Xh]). The CRT/TV timings
and mode setup are programmed through the CRT/TV Configuration Registers
(REG[05Xh]) and the CRT/TV Display Mode Registers (REG[06Xh]). The Ink Layer or
Hardware Cursor can also be independently controlled on the two displays. The LCD
Ink/Cursor Registers (REG[07Xh]) control the Ink/Cursor on the LCD display; the
CRT/TV Ink/Cursor Registers (REG[08Xh]) control the Ink/Cursor on the CRT or TV.
Each display uses its own Look-Up Table (LUT), although there is only one set of LUT
Registers (REG[1E0h], REG[1E2h], REG[1E4h]). Use the LUT Mode Register
(REG[1E0h]) to select access to the LCD and/or CRT/TV LUTs.
The pixel clock source for the two displays may also be independent. Use the Clock Configuration Registers (REG[014h], REG[018h]) to select the LCD pixel clock source and the
CRT/TV pixel clock source, respectively. Typically, CLKI2 is used for the CRT/TV
display, while CLKI is used for the LCD display. Memory clock may come from CLKI or
BUSCLK.
To display different images on the LCD and CRT/TV, the two images should reside in nonoverlapping areas of the display buffer, and the display start addresses point to the corresponding areas. The display buffer is mapped to the CPU address AB[20:0] linearly.
Example 1: Assuming a 2M byte display buffer, the LCD image may locate in the first 1M
byte of the display buffer (AB[20:0] = 000000h-0FFFFFh), and the CRT/TV
image may locate in the second 1M byte of the display
buffer (AB[20:0] = 100000h-1FFFFFh).
The LCD and CRT/TV may display identical images by setting the display start addresses
for the LCD and the CRT/TV to the same address. In this case only one image is needed in
the display buffer. However, the display pipelines are still independent so the same image
is fetched twice from the display buffer; once for the LCD refresh and once for the CRT/TV
refresh.
S1D13506
X25B-A-001-10
Hardware Functional Specification
Issue Date: 01/02/06
Epson Research and Development
Vancouver Design Center
Page 211
16.2 Bandwidth Limitation
When EISD is enabled, the LCD and CRT/TV displays must share the total bandwidth
available to the S1D13506. The result is that display modes with a high resolution or color
depth may not be supported. In some cases, Ink Layers may not be possible on one or both
of the displays. EISD increases the total demand for display refresh bandwidth and reduces
CPU bandwidth, resulting in lower CPU performance.
In a few cases when EISD is enabled, the default LCD and CRT/TV Display FIFO High
Threshold Control register values are not optimally set, causing display problems with one
or both of the displays. This condition may be corrected by adjusting the values of the LCD
and CRT/TV Display FIFO High Threshold Control registers (REG[04Ah] for LCD and
REG[06Ah] for CRT/TV).
When the FIFO High Threshold Control register is set to 00h (default), the following
settings are used:
• 11h for 4 bpp mode
• 21h for 8 bpp mode
• 23h for 15/16 bpp mode
Changing this register to a non-zero value sets the high threshold FIFO level to this value.
This register may not exceed 59 decimal. The high threshold FIFO level controls how often
display fetch requests are issued by the FIFO. In general, a higher high threshold FIFO level
increases the bandwidth to that display pipe, and a lower level reduces it.
Most display problems may be corrected by increasing the associated high threshold FIFO
level for that display. However, because the total available bandwidth is fixed, this change
may create display problem for the other display. In this case, reducing the high threshold
FIFO level for the other display instead may work. Sometimes, a combination of these two
methods is required. Correcting EISD display problems by adjusting the FIFO High
Threshold Control registers is mostly a trial-and-error process. While the user is free to
experiment with these registers, recommended FIFO level settings for some of the more
common EISD modes requiring non-default FIFO level settings are listed in Section 18.2,
“Example Frame Rates” on page 216.
Hardware Functional Specification
Issue Date: 01/02/06
S1D13506
X25B-A-001-10
Page 212
Epson Research and Development
Vancouver Design Center
17 MediaPlug Interface
Winnov's MediaPlug Slave interface has been incorporated into the S1D13506. The
MediaPlug Slave follows the Specification For Winnov MediaPlug Slave, Local module,
Document Rev 0.3 with the following exceptions.
17.1 Revision Code
The MediaPlug Slave Revision Code can be determined by reading bits 11:8 of the LCMD
register. The revision code for this implementation is 0011b.
17.2 How to enable the MediaPlug Slave
The MediaPlug Slave interface uses the upper eight pins of the LCD data bus
(FPDAT[15:8]) for the data bus, clock, and control lines. When pin MD13 is high at the
rising edge of RESET#, FPDAT[15:8] are dedicated to the MediaPlug interface.
Table 17-1: MediaPlug Interface Pin Mapping
S1D13506
Pin Names
IO Type
MediaPlug I/F
FPDAT8
O
VMPLCTL
FPDAT9
I
VMPRCTL
FPDAT10
IO
VMPD0
FPDAT11
IO
VMPD1
FPDAT12
IO
VMPD2
FPDAT13
IO
VMPD3
FPDAT14
O
VMPCLK
FPDAT15
O
VMPCLKN
DRDY or MA11
O
VMPEPWR
Note
If MediaPlug is enabled, any 16-bit LCD panel must use an external circuit to support
FPDAT[15:8].
Either pin MA11 or pin DRDY can be configured as the MediaPlug power control output,
VMPEPWR. This is selected by the states of MD14, MD7, MD6 at the rising edge of
RESET# - see Table 5-6:, “Summary of Power-On/Reset Options,” on pag e39.
VMPEPWR is controlled by bit 1 of the MediaPlug LCMD register.
S1D13506
X25B-A-001-10
Hardware Functional Specification
Issue Date: 01/02/06
Epson Research and Development
Vancouver Design Center
Page 213
18 Clocking
18.1 Frame Rate Calculation
18.1.1 LCD Frame Rate Calculation
The maximum LCD frame rate is calculated using the following formula.
LCD PCLKmax
max. LCD Frame Rate = --------------------------------------------------------------------------------------------------------LVDP
( LHDP + LHNDP ) ×  ---------------- + LVNDP
 n

Where:
LCD PCLKmax= maximum LCD pixel clock frequency
LVDP
= LCD Vertical Display Height
= (REG[039h] bits [1:0], REG[038h] bits [7:0]) + 1
LVNDP
= LCD Vertical Non-Display Period
= REG[03Ah] bits [5:0] + 1
LHDP
= LCD Horizontal Display Width
= (REG[032h] bits [6:0] + 1) x 8Ts
LHNDP
= LCD Horizontal Non-Display Period
= (REG[034h] bits [4:0] + 1) x 8Ts
Ts
= minimum LCD pixel clock (LPCLK) period
n
= 1 for single panel
= 2 for dual panel
Hardware Functional Specification
Issue Date: 01/02/06
S1D13506
X25B-A-001-10
Page 214
Epson Research and Development
Vancouver Design Center
18.1.2 CRT Frame Rate Calculation
The maximum CRT frame rate is calculated using the following formula.
CRT PCLK max
max. CRT Frame Rate = --------------------------------------------------------------------------------------------------------( CHDP + CHNDP ) × ( CVDP + CVNDP )
Where:
CRT PCLKmax= maximum CRT pixel clock frequency
S1D13506
X25B-A-001-10
CVDP
= CRT Vertical Display Height
= (REG[057h] bits [1:0], REG[056h] bits [7:0]) + 1
CVNDP
= CRT Vertical Non-Display Period
= REG[058h] bits [6:0] + 1
CHDP
= CRT Horizontal Display Width
= (REG[050h] bits [6:0] + 1) x 8Ts
CHNDP
= CRT Horizontal Non-Display Period
= (REG[052h] bits [5:0] + 1) x 8Ts
Ts
= minimum CRT pixel clock (CPCLK) period
Hardware Functional Specification
Issue Date: 01/02/06
Epson Research and Development
Vancouver Design Center
Page 215
18.1.3 TV Frame Rate Calculation
The maximum TV frame rate is calculated using the following formula.
TV PCLK max
max. TV Frame Rate = ---------------------------------------------------------------------------------------------------------------------( THDP + THNDP ) × ( TVDP + TVNDP + 0.5 )
Where:
TV PCLKmax= maximum TV pixel clock frequency
TVDP
= TV Vertical Display Height
= (REG[057h] bits [1:0], REG[056h] bits [7:0]) + 1
TVNDP
= TV Vertical Non-Display Period
= REG[058h] bits [6:0] + 1
THDP
= TV Horizontal Display Width
= (REG[050h] bits [6:0] + 1) x 8Ts
THNDP
= TV Horizontal Non-Display Period
= (REG[052h] bits [5:0] x 8Ts) + 6 for NTSC output
= (REG[052h] bits [5:0] x 8Ts) + 7 for PAL output
Ts
= minimum TV pixel clock (TPCLK) period
Hardware Functional Specification
Issue Date: 01/02/06
S1D13506
X25B-A-001-10
Page 216
Epson Research and Development
Vancouver Design Center
18.2 Example Frame Rates
For all example frame rates the following conditions apply:
• Dual panel buffer is enabled for dual panel.
• TV flicker filter is enabled for TV.
• MCLK is 40MHz.
18.2.1 Frame Rates for 640x480 with EISD Disabled
Table 18-1: Frame Rates for 640x480 with EISD Disabled
LCD Type
Ink
(pixels)
(lines)
640
480
No
640
No
640
No
No
Passive
Single / TFT
Mono Passive
Dual
Color Passive
Dual
Passive
Single / TFT
Mono Passive
Dual
Color Passive
Dual
Horiz Vert
Res Res
max
max min min Frame
CRT/
bpp PCLK HNDP VNDP Rate
TV
(MHz) (pixels) (lines)
Ink
(Hz)
Horiz Vert
Res Res
(pixels)
(lines)
bpp
PCLK HNDP VNDP Frame
Rate
(MHz) (pixels) (lines) (MHz)
4
40
56
1
119
--
--
--
--
--
--
--
--
--
480
8
40
64
1
118
--
--
--
--
--
--
--
--
--
480
16
34
56
1
101
--
--
--
--
--
--
--
--
--
640
480
4
40
64
1
235
--
--
--
--
--
--
--
--
--
No
640
480
8
40
72
1
233
--
--
--
--
--
--
--
--
--
No
640
480
16
27
56
1
161
--
--
--
--
--
--
--
--
--
No
640
480
4
35
64
1
206
--
--
--
--
--
--
--
--
--
No
640
480
8
33
64
1
194
--
--
--
--
--
--
--
--
--
No
640
480
16
23
48
1
138
--
--
--
--
--
--
--
--
--
Yes
640
480
4
40
56
1
119
--
--
--
--
--
--
--
--
--
Yes
640
480
8
40
64
1
118
--
--
--
--
--
--
--
--
--
Yes
640
480
16
30
48
1
90
--
--
--
--
--
--
--
--
--
Yes
640
480
4
39
64
1
229
--
--
--
--
--
--
--
--
--
Yes
640
480
8
31
56
1
184
--
--
--
--
--
--
--
--
--
Yes
640
480
16
22
48
1
132
--
--
--
--
--
--
--
--
--
Yes
640
480
4
31
56
1
184
--
--
--
--
--
--
--
--
--
Yes
640
480
8
26
48
1
156
--
--
--
--
--
--
--
--
--
Yes
640
480
16
20
40
1
122
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
CRT
No
640
480
4
36
192
29
85
--
--
--
--
--
--
--
--
--
--
CRT
No
640
480
8
36
192
29
85
--
--
--
--
--
--
--
--
--
--
CRT
No
640
480
16
36
192
29
85
--
--
--
--
--
--
--
--
--
--
NTSC TV
No
640
480
4
14.32 270
22
62
--
--
--
--
--
--
--
--
--
--
NTSC TV
No
640
480
8
14.32 270
22
62
--
--
--
--
--
--
--
--
--
--
NTSC TV
No
640
480
16
14.32 270
22
62
--
--
--
--
--
--
--
--
--
--
PAL TV
No
640
480
4
17.73 495
72
56
--
--
--
--
--
--
--
--
--
--
PAL TV
No
640
480
8
17.73 495
72
56
--
--
--
--
--
--
--
--
--
--
PAL TV
No
640
480
16
17.73 495
72
56
= Example Frame Rates with Ink Layer Enabled
S1D13506
X25B-A-001-10
Hardware Functional Specification
Issue Date: 01/02/06
Epson Research and Development
Vancouver Design Center
Page 217
Table 18-1: Frame Rates for 640x480 with EISD Disabled (Continued)
LCD Type
Ink
Horiz Vert
Res Res
(pixels)
(lines)
max
max min min Frame
CRT/
bpp PCLK HNDP VNDP Rate
TV
(MHz) (pixels) (lines)
Ink
(Hz)
Horiz Vert
Res Res
(pixels)
(lines)
bpp
PCLK HNDP VNDP Frame
Rate
(MHz) (pixels) (lines) (MHz)
--
--
--
--
--
--
--
--
--
--
CRT
Yes
640
480
4
36
192
29
85
--
--
--
--
--
--
--
--
--
--
CRT
Yes
640
480
8
36
192
29
85
--
--
--
--
--
--
--
--
--
--
CRT
Yes
640
480
16
31.5
200
20
75
--
--
--
--
--
--
--
--
--
--
NTSC TV
Yes
640
480
4
14.32 270
22
62
--
--
--
--
--
--
--
--
--
--
NTSC TV
Yes
640
480
8
14.32 270
22
62
--
--
--
--
--
--
--
--
--
--
NTSC TV
Yes
640
480
16
14.32 270
22
62
--
--
--
--
--
--
--
--
--
--
PAL TV
Yes
640
480
4
17.73 495
72
56
--
--
--
--
--
--
--
--
--
--
PAL TV
Yes
640
480
8
17.73 495
72
56
--
--
--
--
--
--
--
--
--
--
PAL TV
Yes
640
480
16
17.73 495
72
56
= Example Frame Rates with Ink Layer Enabled
18.2.2 Frame Rates for 800x600 with EISD Disabled
Table 18-2: Frame Rates for 800x600 with EISD Disabled
LCD Type
Color Passive
Dual
Color Passive
Dual
Ink
Horiz Vert
Res Res
(pixels)
(lines)
No
800
600
No
800
No
800
Yes
max min min max CRT/
bpp PCLK HNDP VNDP Frame
Rate
TV
(MHz) (pixels) (lines)
Ink
(Hz)
Horiz Vert
Res Res
(pixels)
(lines)
bpp
PCLK HNDP VNDP Frame
Rate
(MHz) (pixels) (lines) (MHz)
4
40
64
1
153
--
--
--
--
--
--
--
--
--
600
8
33
64
1
126
--
--
--
--
--
--
--
--
--
600
16
23
48
1
90
--
--
--
--
--
--
--
--
--
800
600
4
31
56
1
120
--
--
--
--
--
--
--
--
--
Yes
800
600
8
26
48
1
101
--
--
--
--
--
--
--
--
--
Yes
800
600
16
20
40
1
79
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
CRT
No
800
600
4
40
256
28
60
--
--
--
--
--
--
--
--
--
--
CRT
No
800
600
8
40
256
28
60
--
--
--
--
--
--
--
--
--
--
CRT
No
800
600
16
36
224
25
56
--
--
--
--
--
--
--
--
--
--
CRT
Yes
800
600
4
40
256
28
60
--
--
--
--
--
--
--
--
--
--
CRT
Yes
800
600
8
40
256
28
60
--
--
--
--
--
--
--
--
--
--
CRT
Yes
800
600
16
31.5
224
25
49
= Example Frame Rates with Ink Layer Enabled
Hardware Functional Specification
Issue Date: 01/02/06
S1D13506
X25B-A-001-10
Page 218
Epson Research and Development
Vancouver Design Center
18.2.3 Frame Rates for LCD and CRT (640x480) with EISD Enabled
Table 18-3: Frame Rates for LCD and CRT (640x480) with EISD Enabled
LCD Type
Ink
Horiz Vert
Res Res
max
max min min Frame
CRT/
bpp PCLK HNDP VNDP Rate
TV
(MHz) (pixels) (lines)
Ink
Horiz Vert
Res Res
bpp
PCLK( HNDP VNDP Frame
Rate
MHz) (pixels) (lines) (MHz)
(pixels)
(lines)
No
320
240
16
9.7
40
1
111
CRT
No
640
240
16
9.7
40
1
59
No
640
480
4
40
112
1
No
640
480
8
27
96
1
Color Passive
Dual
No
640
480
8
18
72
TFT
No
800
600
8
27
Color Passive
Dual
No
800
600
4
27
No
800
600
8
18
72
1
68
CRT
No
640
480
8
25.175 160
44
60
Passive
Single / TFT
Yes
640
480
4
32
88
1
91
CRT
No
640
480
4
25.175 160
44
60
Yes
640
480
8
20
72
1
58
CRT
No
640
480
8
25.175 160
44
60
Mono Passive
Dual
Yes
640
480
4
25
80
1
144
CRT
No
640
480
4
25.175 160
44
60
Yes
640
480
8
17
64
1
100
CRT
No
640
480
8
25.175 160
44
60
Yes
640
480
4
22
64
1
129
CRT
No
640
480
4
25.175 160
44
60
Yes
640
480
8
15
56
1
89
CRT
No
640
480
8
25.175 160
44
60
Yes
800
600
4
22
64
1
84
CRT
No
640
480
4
25.175 160
44
60
Passive
Single / TFT
Color Passive
Dual
(pixels)
(lines)
No
640
480
16
25.175 160
44
60
CRT
No
640
480
16
25.175 160
44
60
110
CRT
No
640
480
4
25.175 160
44
60
76
CRT
No
640
480
8
25.175 160
44
60
1
104
CRT
No
640
480
8
25.175 160
44
60
96
1
50
CRT
No
640
480
8
25.175 160
44
60
80
1
101
CRT
No
640
480
4
25.175 160
44
60
(Hz)
No
640
240
8
20
72
1
116
CRT
Yes
640
480
8
25.175 160
44
60
No
640
480
4
32
88
1
91
CRT
Yes
640
480
4
25.175 160
44
60
No
640
480
8
20
72
1
58
CRT
Yes
640
480
8
25.175 160
44
60
No
640
480
4
24
72
1
139
CRT
Yes
640
480
4
25.175 160
44
60
No
640
480
8
16
64
1
94
CRT
Yes
640
480
8
25.175 160
44
60
No
640
480
4
21
64
1
123
CRT
Yes
640
480
4
25.175 160
44
60
No
640
480
8
14
56
1
83
CRT
Yes
640
480
8
25.175 160
44
60
No
800
600
4
21
64
1
80
CRT
Yes
640
480
4
25.175 160
44
60
Passive
Single / TFT
Yes
640
240
8
16
56
1
95
CRT
Yes
640
480
8
25.175 160
44
60
Yes
640
480
4
24
64
1
70
CRT
Yes
640
480
4
25.175 160
44
60
Mono Passive
Dual
Yes
640
480
4
20
64
1
117
CRT
Yes
640
480
4
25.175 160
44
60
Yes
640
480
8
13
56
1
77
CRT
Yes
640
480
8
25.175 160
44
60
Yes
640
480
4
17
56
1
101
CRT
Yes
640
480
4
25.175 160
44
60
Yes
640
480
8
12
48
1
72
CRT
Yes
640
480
8
25.175 160
44
60
Yes
800
600
4
17
56
1
66
CRT
Yes
640
480
4
25.175 160
44
60
Passive
Single / TFT
Mono Passive
Dual
Color Passive
Dual
Color Passive
Dual
= Example Frame Rates with Ink Layer Enabled
S1D13506
X25B-A-001-10
Hardware Functional Specification
Issue Date: 01/02/06
Epson Research and Development
Vancouver Design Center
Page 219
18.2.4 Frame Rates for LCD and CRT (800x600) with EISD Enabled
Table 18-4: Frame Rates for LCD and CRT (800x600) with EISD Enabled
LCD Type
Passive
Single / TFT
Ink
Horiz Vert
Res Res
max
max min min Frame
CRT/
bpp PCLK HNDP VNDP Rate
TV
(MHz) (pixels) (lines)
(pixels)
(lines)
No
640
240
8
20
72
1
116
CRT
No
640
480
4
40
112
1
110
Ink
Horiz Vert
Res Res
bpp
PCLK HNDP VNDP Frame
Rate
(MHz) (pixels) (lines) (MHz)
(pixels)
(lines)
No
800
600
8
40
256
28
60
CRT
No
800
600
4
40
256
28
60
(Hz)
No
640
480
8
20
72
1
58
CRT
No
800
600
8
40
256
28
60
Color Passive
Dual 1
No
640
480
8
13
56
1
77
CRT
No
800
600
8
40
256
28
60
Color Passive
Dual
No
800
600
4
24
72
1
91
CRT
No
800
600
4
40
256
28
60
Color Passive
Dual 2
No
800
600
8
15
56
1
58
CRT
No
800
600
8
40
256
28
60
TFT3
No
800
600
8
30
72
28
54
CRT
No
800
600
8
40
256
28
60
Passive
Single / TFT
Yes
640
240
8
15
56
1
89
CRT
No
800
600
8
40
256
28
60
Yes
640
480
4
29
80
1
83
CRT
No
800
600
4
40
256
28
60
Mono Passive
Dual
Yes
640
480
4
23
72
1
134
CRT
No
800
600
4
40
256
28
60
Yes
640
480
8
11
56
1
65
CRT
No
800
600
8
40
256
28
60
Yes
640
480
4
19
56
1
113
CRT
No
800
600
4
40
256
28
60
No
640
240
4
27
72
1
157
CRT
Yes
800
600
4
40
256
28
60
No
640
240
8
13
48
1
78
CRT
Yes
800
600
8
40
256
28
60
No
640
480
4
27
72
1
78
CRT
Yes
800
600
4
40
256
28
60
No
640
480
4
21
64
1
123
CRT
Yes
800
600
4
40
256
28
60
Color Passive
Dual
No
640
480
4
17
56
1
101
CRT
Yes
800
600
4
40
256
28
60
No
640
480
8
8.8
40
1
53
CRT
Yes
800
600
8
40
256
28
60
Passive
Single / TFT
Yes
640
240
4
20
56
1
119
CRT
Yes
800
600
4
40
256
28
60
Color Passive
Dual
Passive
Single / TFT
Mono Passive
Dual
Yes
640
480
4
20
56
1
59
CRT
Yes
800
600
4
40
256
28
60
Mono Passive
Dual
Yes
640
480
4
17
56
1
101
CRT
Yes
800
600
4
40
256
28
60
Color Passive
Dual
Yes
640
480
4
14
48
1
84
CRT
Yes
800
600
4
40
256
28
60
= Example Frame Rates with Ink Layer Enabled
The FIFO values for these display modes must be set as follows:
1. REG[04Ah] must be set to 1Ah.
2. REG[04Ah] must be set to Fh.
3. REG[04Ah], REG[06Ah] must be set to 30h. REG[04Bh], REG[06Bh] must be set to 32h.
Hardware Functional Specification
Issue Date: 01/02/06
S1D13506
X25B-A-001-10
Page 220
Epson Research and Development
Vancouver Design Center
18.2.5 Frame Rates for LCD and NTSC TV with EISD Enabled
Table 18-5: Frame Rates for LCD and NTSC TV with EISD Enabled
LCD Type
Passive
Single / TFT
Ink
Horiz Vert
Res Res
max
max min min Frame
CRT/
bpp PCLK HNDP VNDP Rate
TV
(MHz) (pixels) (lines)
(pixels)
(lines)
No
320
240
16
5.3
32
1
62
NTSC TV
No
640
240
16
9
32
1
55
No
640
480
4
31
120
1
No
640
480
8
18
88
1
Ink
Horiz Vert
Res Res
bpp
PCLK HNDP VNDP Frame
Rate
(MHz) (pixels) (lines) (MHz)
(pixels)
(lines)
No
640
480
16
14.32 270
22
62
NTSC TV
No
640
480
16
14.32 270
22
62
84
NTSC TV
No
640
480
4
14.32 270
22
62
51
NTSC TV
No
640
480
8
14.32 270
22
62
(Hz)
Mono Passive
Dual
No
640
480
4
25
104
1
139
NTSC TV
No
640
480
4
14.32 270
22
62
No
640
480
8
15
80
1
86
NTSC TV
No
640
480
8
14.32 270
22
62
Color Passive
Dual
No
640
480
4
21
88
1
119
NTSC TV
No
640
480
4
14.32 270
22
62
No
640
480
8
13
72
1
75
NTSC TV
No
640
480
8
14.32 270
22
62
Color Passive
Dual
No
800
600
8
13
72
1
49
NTSC TV
No
640
480
8
14.32 270
22
62
Passive
Single / TFT
Yes
640
480
4
24
96
1
67
NTSC TV
No
640
480
4
14.32 270
22
62
Mono Passive
Dual
Yes
640
480
4
20
80
1
115
NTSC TV
No
640
480
4
14.32 270
22
62
Yes
640
480
8
12
64
1
70
NTSC TV
No
640
480
8
14.32 270
22
62
Color Passive
Dual
Yes
640
480
4
17
72
1
99
NTSC TV
No
640
480
4
14.32 270
22
62
Yes
640
480
8
11
64
1
64
NTSC TV
No
640
480
8
14.32 270
22
62
No
640
240
4
19
72
1
110
NTSC TV
Yes
640
480
4
14.32 270
22
62
No
640
240
8
12
64
1
70
NTSC TV
Yes
640
480
8
14.32 270
22
62
No
640
480
4
19
72
1
55
NTSC TV
Yes
640
480
4
14.32 270
22
62
No
640
480
4
16
64
1
94
NTSC TV
Yes
640
480
4
14.32 270
22
62
No
640
480
8
10
56
1
59
NTSC TV
Yes
640
480
8
14.32 270
22
62
No
640
480
4
14
56
1
83
NTSC TV
Yes
640
480
4
14.32 270
22
62
No
640
480
8
9.3
48
1
56
NTSC TV
Yes
640
480
8
14.32 270
22
62
Passive
Single / TFT
Yes
640
240
4
16
64
1
94
NTSC TV
Yes
640
480
4
14.32 270
22
62
Yes
640
240
8
10
56
1
59
NTSC TV
Yes
640
480
8
14.32 270
22
62
Mono Passive
Dual
Yes
640
480
4
14
56
1
83
NTSC TV
Yes
640
480
4
14.32 270
22
62
Yes
640
480
8
9
48
1
54
NTSC TV
Yes
640
480
8
14.32 270
22
62
Yes
640
480
4
12
48
1
72
NTSC TV
Yes
640
480
4
14.32 270
22
62
Passive
Single / TFT
Mono Passive
Dual
Color Passive
Dual
Color Passive
Dual
= Example Frame Rates with Ink Layer Enabled
S1D13506
X25B-A-001-10
Hardware Functional Specification
Issue Date: 01/02/06
Epson Research and Development
Vancouver Design Center
Page 221
18.2.6 Frame Rates for LCD and PAL TV with EISD Enabled
Table 18-6: Frame Rates for LCD and PAL TV with EISD Enabled
LCD Type
Ink
No
Passive
Single / TFT No
Horiz Vert
Res Res
max
max min min Frame
CRT/
bpp PCLK HNDP VNDP Rate
TV
(MHz) (pixels) (lines)
(pixels)
(lines)
640
480
4
31
120
1
84
PAL TV
640
480
8
18
88
1
51
Ink
Horiz Vert
Res Res
bpp
PCLK HNDP VNDP Frame
Rate
(MHz) (pixels) (lines) (MHz)
(pixels)
(lines)
No
640
480
4
17.73 495
72
56
PAL TV
No
640
480
8
17.73 495
72
56
(Hz)
Mono Passive No
Dual
No
640
480
4
25
104
1
139
PAL TV
No
640
480
4
17.73 495
72
56
640
480
8
15
80
1
86
PAL TV
No
640
480
8
17.73 495
72
56
No
640
480
4
21
88
1
119
PAL TV
No
640
480
4
17.73 495
72
56
Color Passive
No
Dual
640
480
8
13
72
1
75
PAL TV
No
640
480
8
17.73 495
72
56
No
800
600
8
16
72
1
60
PAL TV
No
640
480
8
17.73 495
72
56
No
800
600
8
23
88
1
43
PAL TV
No
640
480
8
17.73 495
72
56
Passive
Yes
Single / TFT
640
480
4
24
96
1
67
PAL TV
No
640
480
4
17.73 495
72
56
Mono Passive Yes
Dual
Yes
640
480
4
20
80
1
115
PAL TV
No
640
480
4
17.73 495
72
56
640
480
8
12
64
1
70
PAL TV
No
640
480
8
17.73 495
72
56
Color Passive Yes
Dual
Yes
640
480
4
17
72
1
99
PAL TV
No
640
480
4
17.73 495
72
56
640
480
8
11
64
1
64
PAL TV
No
640
480
8
17.73 495
72
56
TFT
No
640
240
4
19
72
1
110
PAL TV
Yes
640
480
4
17.73 495
72
56
Passive
No
Single / TFT
640
240
8
12
64
1
70
PAL TV
Yes
640
480
8
17.73 495
72
56
No
640
480
4
19
72
1
55
PAL TV
Yes
640
480
4
17.73 495
72
56
Mono Passive No
Dual
No
640
480
4
16
64
1
94
PAL TV
Yes
640
480
4
17.73 495
72
56
640
480
8
10
56
1
59
PAL TV
Yes
640
480
8
17.73 495
72
56
640
480
4
14
56
1
83
PAL TV
Yes
640
480
4
17.73 495
72
56
640
480
8
9.3
48
1
56
PAL TV
Yes
640
480
8
17.73 495
72
56
Yes
Passive
Single / TFT Yes
640
240
4
16
64
1
94
PAL TV
Yes
640
480
4
17.73 495
72
56
640
240
8
10
56
1
59
PAL TV
Yes
640
480
8
17.73 495
72
56
Mono Passive Yes
Dual
Yes
640
480
4
14
56
1
83
PAL TV
Yes
640
480
4
17.73 495
72
56
640
480
8
9
48
1
54
PAL TV
Yes
640
480
8
17.73 495
72
56
Color Passive Yes
Dual
640
480
4
12
48
1
72
PAL TV
Yes
640
480
4
17.73 495
72
56
Color Passive No
Dual
No
= Example Frame Rates with Ink Layer Enabled
Hardware Functional Specification
Issue Date: 01/02/06
S1D13506
X25B-A-001-10
Page 222
Epson Research and Development
Vancouver Design Center
19 Power Save Mode
The S1D13506 has been designed for very low-power applications. During normal
operation, internal clock networks are dynamically disabled when not required. Similarly,
the LCD and/or CRT/TV pipelines are shut down when not required in the selected display
mode. Additionally, the S1D13506 has a software initiated power save mode.
19.1 Display Modes
The S1D13506 resets with both displays inactive, i.e. neither the LCD nor CRT/TV
pipelines are active. The displays are independently enabled/disabled by REG[1FCh] bits
2-0: the CRT/TV is instantaneously enabled/disabled by these bits; the LCD is powered
up/down according to the sequences in Section 7.4, “Power Sequencing” on page 78.
19.2 Power Save Mode
Power save mode is invoked by setting REG[1F0h] bit 0 to 1. In power save mode, both
displays are disabled: the CRT/TV is instantaneously disabled; the LCD is powered down
according to the sequences in Section 7.4, “Power Sequencing” on page 78. Access to
memory is not allowed and the memory controller merely refreshes the memory in the
method selected by REG[021h]. Register access is allowed.
19.3 Power Save Status Bits
LCD Power Save Status bit
The LCD Power Save Status bit (REG[1F1h] bit 0), when 1, indicates that the panel is
powered down. When this bit is 0, the panel is powered up, or in transition of powering up
or down. The system may disable the LCD pixel clock source when this bit is 1. This bit is
1 after chip reset.
Memory Controller Power Save Status bit
The Memory Controller Power Save Status bit (REG[1F1h] bit 1, when 1, indicates that the
DRAM interface is powered down - the DRAM is either in self-refresh mode or completely
idle. This condition occurs shortly after power save mode is invoked, provided Self-Refresh
or No Refresh is pre-selected (see REG[021h] bits 7-6); this condition will never occur if
CBR Refresh is selected. When this bit is 0, the DRAM interface is active. The system may
disable the memory clock source when this bit is 1. This bit is 0 after chip reset.
S1D13506
X25B-A-001-10
Hardware Functional Specification
Issue Date: 01/02/06
Epson Research and Development
Vancouver Design Center
Page 223
19.4 Power Save Mode Summary
Table 19-1: Power Save Mode Summary
Function
LCD Disabled
CRT/TV Disabled
Power Save Mode
Enabled
LCD Display Active?
no
--
No
CRT/TV Display Active?
--
no
No
Register Access Possible?
Yes
Yes
Yes
Memory Access Possible?
Yes
Yes
No
--
Yes
LCD LUT Access Possible?
Yes
CRT/TV LUT Access Possible?
--
1
Yes
2
Yes
LCD interface
Forced Low
--
Forced Low
CRT/TV interface
--
No Output Current
No Output Current
DRAM interface
Active
Active
Refresh Only3
Host Interface
Active
Active
Active
Note
1. LCD pixel clock required.
2. CRT/TV pixel clock required.
3. Selectable; may observe CBR refresh, self-refresh or no refresh at all.
Hardware Functional Specification
Issue Date: 01/02/06
S1D13506
X25B-A-001-10
Page 224
Epson Research and Development
Vancouver Design Center
20 Clocks
20.1 Clock Selection
The following diagram provides a logical representation of the S1D13506 internal clocks.
CLKI
BUSCLK
CLKI2
0
0
1
÷2
MCLK
1
00
REG[010h] bit 0
REG[014h] bit 4
01
00
10
11
÷2
01
÷3
10
÷4
11
LCD PCLK
REG[014h] bits 1,0
REG[014h] bits 5,4
00
00
01
10
÷2
11
÷3
01
x2
10
Enable
÷4
CRT/TV
PCLK
11
REG[018h] bits 1,0
REG[018h] bit 7
00
REG[018h] bits 5,4
01
00
10
11
÷2
01
÷3
10
÷4
11
MediaPlug
Clock
REG[01Ch] bits 1,0
REG[01Ch] bits 5,4
Figure 20-1: Clock Selection
S1D13506
X25B-A-001-10
Hardware Functional Specification
Issue Date: 01/02/06
Epson Research and Development
Vancouver Design Center
Page 225
20.2 Clock Descriptions
20.2.1 MCLK
MCLK should be configured as close to its maximum (40MHz) as possible. The S1D13506
contains sophisticated clock management, therefore, very little power is saved by reducing
the MCLK frequency.
The frequency of MCLK is directly proportional to the bandwidth of the video memory.
The bandwidth available to the CPU (for screen updates) is that left over after screen refresh
takes its share. CPU bandwidth can be seriously reduced when the MCLK frequency is
reduced, especially for high-resolution, high-color modes where screen refresh has high
bandwidth requirements.
20.2.2 LCD PCLK
LCD PCLK should be chosen to match the optimum frame rate of the panel. See Section
18, “Clocking” on page 213 for details on the relationship between PCLK and frame rate,
and for the maximum supportable PCLK frequencies for any given video mode.
Some flexibility is possible in the selection of PCLK. Panels typically have a range of
permissible frame rates making it possible to choose a higher PCLK frequency and adjust
the horizontal non-display period (see REG[052h]) to bring the frame-rate down to its
optimal value.
20.2.3 CRT/TV PCLK
TVs and older CRTs usually have very precise frequency requirements, so it may be
necessary to dedicate one of the clock inputs to this function. More recent CRTs work
within a range of frequencies, so it may be possible to support them with BUSCLK or
MCLK.
TV mode with flicker filter requires PCLK to be twice (2x) the standard NTSC
(14.xxxMHz) and PAL (17.xxxMHz) clocks. A clock multiplier is used to create this clock,
REG[018h] bit 7 is used to enable it. Note that the clock 2x clock could also be used for
CRT support.
20.2.4 MediaPlug Clock
The MediaPlug Clock must be twice (2x) the frequency of VMPCLK. For timing see
Section 7.7, “MediaPlug Interface Timing” on page 123. VMPCLK is typically in the range
6-8MHz so MediaPlug Clock must be in the range of 12-16MHz.
Hardware Functional Specification
Issue Date: 01/02/06
S1D13506
X25B-A-001-10
Page 226
Epson Research and Development
Vancouver Design Center
20.3 Clocks vs. Functions
The S1D13506 has five clock signals. Not all clock signals must be active for certain chip
functions to be carried out. The following table shows which clocks are required for each
chip function.
Table 20-1: Clocks vs. Functions
Function
Required Clocks
BUSCLK
LCD PCLK
CRT/TV PCLK
MCLK
MediaPlug Clock
Register
read/write
Yes
No
No
No
No
LCD LUT
read/write
Yes
Yes
--
--
--
CRT/TV LUT
read/write
Yes
--
Yes
--
--
Memory
read/write
Yes
--
--
Yes
--
2D Operation
Yes
--
--
Yes
--
MediaPlug
Registers
read/write
Yes
--
--
--
Yes
Power Save
--
--
--
--
--
Note
The S1D13506 contains sophisticated power management that dynamically shuts down
clocks when not needed.
S1D13506
X25B-A-001-10
Hardware Functional Specification
Issue Date: 01/02/06
Epson Research and Development
Vancouver Design Center
Page 227
21 Mechanical Data
Unit: mm
128-pin QFP15 surface mount package
16.0 ± 0.4
14.0 ± 0.1
96
65
16.0 ± 0.4
64
14.0 ± 0.1
97
Index
128
33
32
0.4
0.16 ± 0.1
1.4 ± 0.1
0.125 ± 0.1
1
0.1
0~10°
0.5 ± 0.2
1.0
Figure 21-1: Mechanical Drawing QFP15
Hardware Functional Specification
Issue Date: 01/02/06
S1D13506
X25B-A-001-10
Page 228
Epson Research and Development
Vancouver Design Center
THIS PAGE LEFT BLANK
S1D13506
X25B-A-001-10
Hardware Functional Specification
Issue Date: 01/02/06
S1D13506 Color LCD/CRT/TV Controller
Programming Notes and Examples
Document Number: X25B-G-003-03
Copyright © 2001 Epson Research and Development, Inc. All Rights Reserved.
Information in this document is subject to change without notice.You may download and use this document, but only for your own use in
evaluating Seiko Epson/EPSON products. You may not modify the document. Epson Research and Development, Inc. disclaims any
representation that the contents of this document are accurate or current. The Programs/Technologies described in this document may contain
material protected under U.S. and/or International Patent laws.
EPSON is a registered trademark of Seiko Epson Corporation. All other trademarks are the property of their respective owners.
Page 2
Epson Research and Development
Vancouver Design Center
THIS PAGE LEFT BLANK
S1D13506
X25B-G-003-03
Programming Notes and Examples
Issue Date: 01/02/06
Epson Research and Development
Vancouver Design Center
Page 3
Table of Contents
1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2
Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3
Memory Models . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1 Display Buffer Location . . . . . . . . . . . . . . . . .
3.2 Memory Organization for 4 Bpp (16 Colors/16 Gray Shades) . . .
3.3 Memory Organization for 8 Bpp (256 Colors/16 Gray Shades) . .
3.4 Memory Organization for 15 Bpp (32768 Colors/32 Gray Shades) .
3.5 Memory Organization for 16 Bpp (65536 Colors/64 Gray Shades) .
4
Look-Up Table (LUT) . . . . . . . .
4.1 Registers . . . . . . . . . .
4.2 Look-Up Table Organization . .
4.2.1 Color Modes . . . . . . . . .
4.2.2 Gray Shade Modes . . . . .
.
.
.
.
.
. . .
. .
. .
. . .
. . .
. . . . . . .
. . . . . .
. . . . . .
. . . . . . . .
. . . . . . . .
.
.
.
.
.
. . . . . . . . . .
. . . . . . . .
. . . . . . . .
. . . . . . . . . . .
. . . . . . . . . . .
5
Virtual Displays . . . . .
5.1 Virtual Display . . .
5.1.1 Registers . . . .
5.1.2 Examples . . .
5.2 Panning and Scrolling
5.2.1 Registers . . . .
5.2.2 Examples . . .
. . . . . .
. . . . .
. . . . . . .
. . . . . . .
. . . . .
. . . . . . .
. . . . . . .
.
.
.
.
.
.
.
. . .
. .
. . .
. . .
. .
. . .
. . .
. . . . . . .
. . . . . .
. . . . . . . .
. . . . . . . .
. . . . . .
. . . . . . . .
. . . . . . . .
.
.
.
.
.
.
.
.
.
.
.
.
.
.
6
Power Save Mode . . . . . . . . . .
6.1 Overview . . . . . . . . . .
6.2 Registers . . . . . . . . . .
6.2.1 Enabling Power Save Mode .
6.2.2 Power Save Status Bits . . .
6.2.3 DRAM Refresh Selection . .
.
.
.
.
.
.
. . .
. .
. .
. . .
. . .
. . .
. . . . . . .
. . . . . .
. . . . . .
. . . . . . . .
. . . . . . . .
. . . . . . . .
.
.
.
.
.
.
7
LCD Power Sequencing . . . . . .
7.1 Automatic Sequencing . . . . .
7.2 Manual Sequencing . . . . . .
7.2.1 Registers . . . . . . . . . . .
7.2.2 Enabling the LCD Panel . . .
7.2.3 Disabling the LCD Panel . .
.
.
.
.
.
.
. . .
. .
. .
. . .
. . .
. . .
. . . . . . .
. . . . . .
. . . . . .
. . . . . . . .
. . . . . . . .
. . . . . . . .
8
Hardware Cursor/Ink Layer . . .
8.1 Introduction . . . . . . . .
8.2 Registers . . . . . . . . .
8.3 Initialization . . . . . . . .
.
.
.
.
. . .
. .
. .
. .
.
.
.
.
Programming Notes and Examples
Issue Date: 01/02/06
.
.
.
.
.
.
.
.
.
.
.
.
. . .
. .
. .
. .
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
. . . . . .
. . . . .
. . . . . . .
. . . . . . .
. . . . .
. . . . . . .
. . . . . . .
. . .
. .
. .
. .
. .
. .
.
.
.
.
.
.
.
.
.
.
.
.
16
16
16
17
17
18
. . . .
. . . .
. . . .
. . . . .
. . . . .
19
19
20
21
24
.
.
.
.
.
.
. . .
. . .
. . . .
. . . .
. . .
. . . .
. . . .
26
26
27
28
30
31
33
. . . . . . .
. . . . . .
. . . . . .
. . . . . . . .
. . . . . . . .
. . . . . . . .
. . . . . . .
. . . . . .
. . . . . .
. . . . . . . .
. . . . . . . .
. . . . . . . .
35
35
35
35
36
37
.
.
.
.
.
.
. . . . . . .
. . . . . .
. . . . . .
. . . . . . . .
. . . . . . . .
. . . . . . . .
. . . .
. . .
. . .
. . . .
. . . .
. . . .
. . .
. . .
. . .
. . . .
. . . .
. . . .
38
38
38
39
39
39
.
.
.
.
.
.
.
.
. . .
. .
. .
. .
.
.
.
.
. . .
. .
. .
. .
.
.
.
.
.
.
.
.
.
.
.
.
. . . .
. . .
. . . .
. . . .
. . .
. . . .
. . . .
.
.
.
.
.
.
.
.
.
.
.
.
.
.
. 40
. 40
. 41
. 47
S1D13506
X25B-G-003-03
Page 4
Epson Research and Development
Vancouver Design Center
8.3.1 Memory Considerations . . . . . . . . . . . . .
8.3.2 Examples . . . . . . . . . . . . . . . . . . . .
8.4 Writing Cursor/Ink Layer Images . . . . . . . .
8.4.1 Hardware Cursor/Ink Layer Data Format . . . .
8.4.2
Cursor Image . . . . . . . . . . . . . . . . . .
8.4.3 Ink Layer Image . . . . . . . . . . . . . . . . .
8.5 Cursor Movement . . . . . . . . . . . . . .
8.5.1 Move Cursor in Landscape Mode (no rotation) .
8.5.2 Move Cursor in SwivelView 90° Rotation . . .
8.5.3 Move Cursor in SwivelView 180° Rotation . . .
8.5.4 Move Cursor in SwivelView 270° Rotation . . .
.
.
.
.
.
.
.
.
.
.
.
. . .
. . .
. .
. . .
. . .
. . .
. .
. . .
. . .
. . .
. . .
.
.
.
.
.
.
.
.
.
.
.
. . .
. . .
. .
. . .
. . .
. . .
. .
. . .
. . .
. . .
. . .
SwivelView™ . . . . . . . . . . . . . .
9.1 S1D13506 SwivelView . . . . . .
9.2 Registers . . . . . . . . . . . .
9.3 Limitations . . . . . . . . . . .
9.4 Examples . . . . . . . . . . . .
9.5 Simultaneous Display Considerations .
. . . .
. . .
. . .
. . .
. . .
. . .
.
.
.
.
.
.
.
.
.
.
.
.
10 2D BitBLT Engine . . . . . . . . . . . . . . . . . . . . . . .
10.1 Registers . . . . . . . . . . . . . . . . . . . . .
10.2 BitBLT Descriptions . . . . . . . . . . . . . . . .
10.2.1 Write Blit with ROP . . . . . . . . . . . . . . . . . .
10.2.2 Color Expand BitBLT . . . . . . . . . . . . . . . . . .
10.2.3 Color Expand BitBLT With Transparency . . . . . . .
10.2.4 Solid Fill BitBLT . . . . . . . . . . . . . . . . . . . .
10.2.5 Move BitBLT in a Positive Direction with ROP . . . .
10.2.6 Move BitBLT in Negative Direction with ROP . . . . .
10.2.7 Transparent Write Blit . . . . . . . . . . . . . . . . . .
10.2.8 Transparent Move BitBLT in Positive Direction . . . .
10.2.9 Pattern Fill BitBLT with ROP . . . . . . . . . . . . . .
10.2.10 Pattern Fill BitBLT with Transparency . . . . . . . . .
10.2.11 Move BitBLT with Color Expansion . . . . . . . . . .
10.2.12 Transparent Move Blit with Color Expansion . . . . . .
10.2.13 Read Blit . . . . . . . . . . . . . . . . . . . . . . . . .
10.3 S1D13506 BitBLT Synchronization . . . . . . . . . .
10.4 S1D13506 BitBLT Known Limitations . . . . . . . . .
10.5 Sample Code . . . . . . . . . . . . . . . . . . .
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
. . . . . . . . . . .
. . . . . . . . .
. . . . . . . . .
. . . . . . . . . . . .
. . . . . . . . . . . .
. . . . . . . . . . . .
. . . . . . . . . . . .
. . . . . . . . . . . .
. . . . . . . . . . . .
. . . . . . . . . . . .
. . . . . . . . . . . .
. . . . . . . . . . . .
. . . . . . . . . . . .
. . . . . . . . . . . .
. . . . . . . . . . . .
. . . . . . . . . . . .
. . . . . . . . .
. . . . . . . . .
. . . . . . . . .
9
.
.
.
.
.
.
. . . .
. . .
. . .
. . .
. . .
. . .
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
. . . .
. . . .
. . .
. . . .
. . . .
. . . .
. . .
. . . .
. . . .
. . . .
. . . .
. . . .
. . .
. . .
. . .
. . .
. . .
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
. . .
. . .
. .
. . .
. . .
. . .
. .
. . .
. . .
. . .
. . .
.
.
.
.
.
.
.
.
.
.
.
. 47
. 48
.50
. 50
. 51
. 52
. 53
. 53
. 54
. 54
. 55
. . . .
. . .
. . .
. . .
. . .
. . .
.
.
.
.
.
.
. 56
.56
.56
.58
.59
. 60
. . 61
. .61
. .68
. . 69
. . 71
. . 76
. . 76
. . 77
. . 79
. . 81
. . 83
. . 85
. . 87
. . 88
. . 90
. . 90
. .92
. .94
. . 94
11 CRT/TV Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
11.1 CRT Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . .95
11.1.1 Generating CRT timings with 13506CFG . . . . . . . . . . . . . . . . . . . . . . . 95
S1D13506
X25B-G-003-03
Programming Notes and Examples
Issue Date: 01/02/06
Epson Research and Development
Vancouver Design Center
11.1.2 DAC Output Level Selection
11.1.3 Examples . . . . . . . . . .
11.2 TV Considerations . . . . . .
11.2.1 NTSC Timings . . . . . . .
11.2.2 PAL Timings . . . . . . . .
11.2.3 TV Filters . . . . . . . . . .
11.2.4 Examples . . . . . . . . . .
11.3 Simultaneous Display . . . . .
Page 5
.
.
.
.
.
.
.
.
. . .
. . .
. .
. . .
. . .
. . .
. . .
. .
.
.
.
.
.
.
.
.
. . .
. . .
. .
. . .
. . .
. . .
. . .
. .
.
.
.
.
.
.
.
.
. . .
. . .
. .
. . .
. . .
. . .
. . .
. .
.
.
.
.
.
.
.
.
. . .
. . .
. .
. . .
. . .
. . .
. . .
. .
.
.
.
.
.
.
.
.
. . . . . . . . . . . .
. . . . . . . . . . . .
. . . . . . . . .
. . . . . . . . . . . .
. . . . . . . . . . . .
. . . . . . . . . . . .
. . . . . . . . . . . .
. . . . . . . . .
95
96
96
96
96
97
97
98
12 MediaPlug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
12.1 Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
12.2 Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
13 Identifying the S1D13506 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
14 Hardware Abstraction Layer (HAL) . . . . . . . . . . . . . . . . . . .
14.1 API for 13506HAL . . . . . . . . . . . . . . . . . . . . . .
14.2 Initialization . . . . . . . . . . . . . . . . . . . . . . . . .
14.2.1 General HAL Support . . . . . . . . . . . . . . . . . . . . . . . . .
14.2.2 Advance HAL Functions . . . . . . . . . . . . . . . . . . . . . . .
14.2.3 Surface Support . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14.2.4 Register Access . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14.2.5 Memory Access . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14.2.6 Color Manipulation . . . . . . . . . . . . . . . . . . . . . . . . . .
14.2.7 Virtual Display . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14.2.8 Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14.2.9 Hardware Cursor . . . . . . . . . . . . . . . . . . . . . . . . . . .
14.2.10 Ink Layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14.2.11 PCI Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14.3 Porting LIBSE to a new target platform . . . . . . . . . . . . . .
14.3.1 Building the LIBSE library for SH3 target example . . . . . . . . .
14.3.2 Building a complete application for the target example . . . . . . .
. . .
. .
. .
. . .
. . .
. . .
. . .
. . .
. . .
. . .
. . .
. . .
. . .
. . .
. .
. . .
. . .
. . . . 102
. . . . 102
. . . . 107
. . . . .110
. . . . .115
. . . . .117
. . . . .120
. . . . .122
. . . . .124
. . . . .128
. . . . .130
. . . . .136
. . . . .143
. . . . .149
. . . . 150
. . . . . 151
. . . . . 151
15 Sample Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
Programming Notes and Examples
Issue Date: 01/02/06
S1D13506
X25B-G-003-03
Page 6
Epson Research and Development
Vancouver Design Center
THIS PAGE LEFT BLANK
S1D13506
X25B-G-003-03
Programming Notes and Examples
Issue Date: 01/02/06
Epson Research and Development
Vancouver Design Center
Page 7
List of Tables
Table 2-1: S1D13506 Initialization Sequence . . . . . . . . . . . . . . . . . .
Table 4-1: Look-Up Table Configurations . . . . . . . . . . . . . . . . . . . .
Table 4-2: Suggested LUT Values to Simulate VGA Default 16 Color Palette .
Table 4-3: Suggested LUT Values to Simulate VGA Default 256 Color Palette .
Table 4-4: Suggested LUT Values for 4 Bpp Gray Shade . . . . . . . . . . . .
Table 5-1: Number of Pixels Panned When Start Address Changed By 1 . . . .
Table 5-2: Active Pixel Pan Bits . . . . . . . . . . . . . . . . . . . . . . . . .
Table 6-1: Refresh Selection . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 8-1: Ink/Cursor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 8-2: Cursor/Ink Start Address Encoding . . . . . . . . . . . . . . . . . .
Table 8-3: LCD Hardware Cursor Initialization Sequence . . . . . . . . . . . .
Table 8-4: Ink Layer Start Address Encoding . . . . . . . . . . . . . . . . . . .
Table 8-5: LCD Ink Layer Initialization Sequence . . . . . . . . . . . . . . . .
Table 8-6: Ink/Cursor Color Select . . . . . . . . . . . . . . . . . . . . . . . .
Table 9-1: SwivelView Enable Bits . . . . . . . . . . . . . . . . . . . . . . . .
Table 9-2: LCD Memory Address Offset Values . . . . . . . . . . . . . . . . .
Table 9-3: LCD Display Start Address Values . . . . . . . . . . . . . . . . . .
Table 10-1: BitBLT ROP Code/Color Expansion Function Selection . . . . . . .
Table 10-2: BitBLT Operation Selection . . . . . . . . . . . . . . . . . . . . . .
Table 10-3: BitBLT Source Start Address Selection . . . . . . . . . . . . . . . .
Table 10-4: Possible Blit FIFO Writes . . . . . . . . . . . . . . . . . . . . . . .
Table 10-5: Possible Blit FIFO Writes . . . . . . . . . . . . . . . . . . . . . . .
Table 10-6: Possible Blit FIFO Writes . . . . . . . . . . . . . . . . . . . . . . .
Table 10-7: Possible Blit FIFO Reads . . . . . . . . . . . . . . . . . . . . . . .
Table 14-1: HAL Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Programming Notes and Examples
Issue Date: 01/02/06
. . . . . . . . . . 12
. . . . . . . . . . 20
. . . . . . . . . . 21
. . . . . . . . . . 22
. . . . . . . . . . 24
. . . . . . . . . . 31
. . . . . . . . . . 32
. . . . . . . . . . 37
. . . . . . . . . . 41
. . . . . . . . . . 41
. . . . . . . . . . 48
. . . . . . . . . . 49
. . . . . . . . . . 49
. . . . . . . . . . 50
. . . . . . . . . . 57
. . . . . . . . . . 57
. . . . . . . . . . 58
. . . . . . . . . . 63
. . . . . . . . . . 64
. . . . . . . . . . 65
. . . . . . . . . . 71
. . . . . . . . . . 75
. . . . . . . . . . 83
. . . . . . . . . . 92
. . . . . . . . . .102
S1D13506
X25B-G-003-03
Page 8
Epson Research and Development
Vancouver Design Center
THIS PAGE LEFT BLANK
S1D13506
X25B-G-003-03
Programming Notes and Examples
Issue Date: 01/02/06
Epson Research and Development
Vancouver Design Center
Page 9
List of Figures
Figure 3-1:
Figure 3-2:
Figure 3-3:
Figure 3-4:
Figure 5-1:
Figure 8-1:
Figure 10-1:
Figure 14-1:
Pixel Storage for 4 Bpp in One Byte of Display Buffer . . . . . . . . . .
Pixel Storage for 8 Bpp in One Byte of Display Buffer . . . . . . . . . .
Pixel Storage for 15 Bpp in Two Bytes of Display Buffer . . . . . . . .
Pixel Storage for 16 Bpp in Two Bytes of Display Buffer . . . . . . . .
Viewport Inside a Virtual Display . . . . . . . . . . . . . . . . . . . . .
Hardware Cursor/Ink Layer Data Format . . . . . . . . . . . . . . . . .
Move BitBLT Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Components needed to build 13506 HAL application . . . . . . . . . . .
Programming Notes and Examples
Issue Date: 01/02/06
. . . . . . . . 16
. . . . . . . . 17
. . . . . . . . 17
. . . . . . . . 18
. . . . . . . . 26
. . . . . . . . 50
. . . . . . . . 78
. . . . . . . 150
S1D13506
X25B-G-003-03
Page 10
Epson Research and Development
Vancouver Design Center
THIS PAGE LEFT BLANK
S1D13506
X25B-G-003-03
Programming Notes and Examples
Issue Date: 01/02/06
Epson Research and Development
Vancouver Design Center
Page 11
1 Introduction
This guide provides information on programming the S1D13506 Color LCD/CRT/TV
Controller. Included are algorithms which demonstrate how to program the S1D13506.
This guide discusses Power-on Initialization, Panning and Scrolling, LUT initialization,
LCD Power Sequencing, SwivelView™, etc. The example source code referenced in this
guide is available on the web at www.eea.epson.com.
This guide also introduces the Hardware Abstraction Layer (HAL), which is designed to
simplify the programming of the S1D13506. Most S1D1350x and S1D1370x products have
HAL support, thus allowing OEMs to do multiple designs with a common code base.
This document will be updated as appropriate. Please check the Epson Electronics America
Website at www.eea.epson.com for the latest revision of this document and source before
beginning any development.
We appreciate your comments on our documentation. Please contact us via email at
[email protected]
Programming Notes and Examples
Issue Date: 01/02/06
S1D13506
X25B-G-003-03
Page 12
Epson Research and Development
Vancouver Design Center
2 Initialization
This section describes how to initialize the S1D13506. Sample code for performing initialization of the S1D13506 is provided in the file init13506.c which is available on the
internet at www.eea.epson.com.
S1D13506 initialization can be broken into three steps.
• Enable the S1D13506 controller (if necessary identify the specific controller).
• Set all the registers to their initial values.
• Program the Look-Up Table (LUT) with color values. This section does not deal with
programming the LUT, for details see Section 4, “Look-Up Table (LUT)” .
The simplest way to generate initialization tables for the S1D13506 is to use the utility
program 13506CFG.EXE which to generates a header file that can be used by Windows CE
or the HAL. Otherwise modify the init13506.c file directly.
The following table represents the sequence and values written to the S1D13506 registers
to control a configuration with these specifications:
• 640x480 color format 1 dual passive LCD @ 78Hz.
• 16-bit data interface.
• 8 bit-per-pixel (bpp) color depth - 256 colors.
• 40 MHz input clock CLKI.
• CLKI used for BUSCLK (1:1); PCLK (2:1); MCLK (1:1).
• 50 ns EDO-DRAM, 2 CAS, 32 ms refresh.
Table 2-1: S1D13506 Initialization Sequenc e
Register
Value
[001h]
0000 0000
Enable the Memory/Register Select Bit.
Notes
See Also
[1FCh]
0000 0000
Disable the display outputs.
[004h]
0000 0000
[008h]
0000 0000
Setup GPIO as inputs; force low if outputs. The OEM may wish
GPIO for other purposes which our example does not
accommodate for.
Program the Clock Source selects.
[010h]
0000 0000
[014h]
0001 0000
[018h]
0000 0010
[01Ch]
0000 0010
[01Eh]
0000 0001
S1D13506
X25B-G-003-03
In this case we have a single input clock source attached to the
CLKI pin. This example uses this as BUSCLK, as MCLK and
divide by 2 for PCLK. The CRT clock and MediaPlug clocks are
set to CLKI2 reducing power consumption (there is no CLKI2 in
this example). If either the CRT or MediaPlug is to be used an
input clock must be enabled before accessing the control
registers or LUT.
Program CPU Wait States.
see REG[01Eh] for details
Programming Notes and Examples
Issue Date: 01/02/06
Epson Research and Development
Vancouver Design Center
Page 13
Table 2-1: S1D13506 Initialization Sequence (Continued)
Register
Value
[020h]
0000 0000
[021h]
0000 0110
[02Ah]
0000 0001
[02Bh]
0000 0001
[030h]
0010 0110
Program the LCD Panel type and Panel Timing Registers.
[031h]
0000 0000
[032h]
0100 1111
Panel width = 16-bit; Color Format = don’t care; Color Panel
selected; Dual Panel selected; Passive LCD selected.
[034h]
0001 1111
[035h]
0000 0000
[036h]
0000 0000
Horizontal and Vertical Non-display time has been adjusted to
provide 78Hz frame rate.
[038h]
1101 1111
TFT FPLINE registers = don’t care for passive panels.
[039h]
0000 0001
Display height = 480 therefore register = 1DFh
[03Ah]
0010 1100
TFT FPFRAME = don’t care for passive panels.
[03Bh]
0000 0000
[03Ch]
0000 0000
[040h]
0000 0003
[041h]
0000 0000
[042h]
0000 0000
[043h]
0000 0000
[044h]
0000 0000
[046h]
0100 0000
LCD Start Address should typically be from location 0 in the
frame buffer.
[047h]
0000 0001
Pixel Pan register is 0 for normal operation.
[048h]
0000 0000
[04Ah]
0000 0000
Memory offset register is set to ‘the panel width for normal
operation, therefore 640 ÷ 2 for words = 320 words= 140h
words
[04Bh]
0000 0000
Set FIFO values to 0 for “automatic” calculation.
[050h]
0000 0000
Program the CRT/TV Timing control registers.
[052h]
0000 0000
All values are = don’t care for this example.
[053h]
0000 0000
[054h]
0000 0000
[056h]
0000 0000
[057h]
0000 0000
[058h]
0000 0000
[059h]
0000 0000
[05Ah]
0000 0000
[05Bh]
0000 0000
Programming Notes and Examples
Issue Date: 01/02/06
Notes
See Also
Program the Frame Buffer Memory Configuration
Registers.
see REG[020h] REG[02Bh] for details
MOD rate = don’t care;
Display width = 640 pixels = 4Fh.
Program the Display Output Format and Start Locations for
the LCD output. This includes programming the FIFOs.
Select 8 bpp in REG[040h]
Ensure that the Dual Panel Buffer is enabled REG [41h] bit 0 =
0
S1D13506
X25B-G-003-03
Page 14
Epson Research and Development
Vancouver Design Center
Table 2-1: S1D13506 Initialization Sequence (Continued)
Register
Value
[060h]
0000 0000
[062h]
0000 0000
[063h]
0000 0000
[064h]
0000 0000
[066h]
0000 0000
[067h]
0000 0000
[068h]
0000 0000
[06Ah]
0000 0000
[06Bh]
0000 0000
[070h]
0000 0000
[071h]
0000 0000
[072h]
0000 0000
[073h]
0000 0000
[074h]
0000 0000
[075h]
0000 0000
[076h]
0000 0000
[077h]
0000 0000
[078h]
0000 0000
[07Ah]
0000 0000
[07Bh]
0000 0000
[07Ch]
0000 0000
[07Eh]
0000 0000
[080h]
0000 0000
[081h]
0000 0000
[082h]
0000 0000
[083h]
0000 0000
[084h]
0000 0000
[085h]
0000 0000
[086h]
0000 0000
[087h]
0000 0000
[088h]
0000 0000
[08Ah]
0000 0000
[08Bh]
0000 0000
[08Ch]
0000 0000
[08Eh]
0000 0000
S1D13506
X25B-G-003-03
Notes
See Also
Program the CRT/TV Display Output Format and
Configuration Registers including the FIFOs.
For this example, these values are = don’t care.
Program the LCD Ink Layer/Cursor Control, Position, Color
and FIFO registers.
For this example, since no Ink Layer or Cursor is used, these
registers are = don’t care.
Program the CRT/TV Ink Layer/Cursor Control, Position,
Color and FIFO registers.
For this example, since no Ink Layer or Cursor is used, these
registers are = don’t care.
Programming Notes and Examples
Issue Date: 01/02/06
Epson Research and Development
Vancouver Design Center
Page 15
Table 2-1: S1D13506 Initialization Sequence (Continued)
Register
Value
Notes
[100h]
0000 0000
[101h]
0000 0000
Program the 2D acceleration (BitBLT) registers to a known
state.
[102h]
0000 0000
[103h]
0000 0000
[104h]
0000 0000
[105h]
0000 0000
[106h]
0000 0000
[108h]
0000 0000
[109h]
0000 0000
[10Ah]
0000 0000
[10Ch]
0000 0000
[10Dh]
0000 0000
[110h]
0000 0000
[111h]
0000 0000
[112h]
0000 0000
[113h]
0000 0000
[114h]
0000 0000
[115h]
0000 0000
[116h]
0000 0000
[118h]
0000 0000
[119h]
0000 0000
[1E0]h
0000 0001
Program the Look-Up Table to a known state.
[1E2h]
0000 0000
[1E4h]
0000 0000
Selects LUT access to the LCD LUT only. Programming the
Look-Up Table is dealt with in a separate section of this
document. The init13506.c file shows the example.
[1F0h]]
0000 0000
Turn off Power Save Mode
[1F4h]
0000 0000
[1FCh]
0000 0001
Programming Notes and Examples
Issue Date: 01/02/06
Disable Watchdog Timer
Enable the Display
For this example, enable LCD only
See Also
see Section Section 4,
“Look-Up Table (LUT)” on
page 19.
‘
see REG[1FCh]
S1D13506
X25B-G-003-03
Page 16
Epson Research and Development
Vancouver Design Center
3 Memory Models
The S1D13506 is capable of several color depths. The memory model for each color depth
is packed pixel. The S1D13506 supports 4, 8, 15 and 16 bit-per-pixel (bpp) memory
models.
3.1 Display Buffer Location
The S1D13506 supports either a 512k byte or 2M byte display buffer. The display buffer is
memory mapped and is accessible directly by software. The memory block location
assigned to the S1D13506 display buffer varies with each individual hardware platform.
For further information on the display buffer, see the S1D13506 Hardware Functional
Specification, document number X25B-A-001-xx.
3.2 Memory Organization for 4 Bpp (16 Colors/16 Gray Shades)
Bit 7
Bit 6
Bit 5
Pixel 0
Bits 3-0
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pixel 1
Bits 3-0
Figure 3-1: Pixel Storage for 4 Bpp in One Byte of Display Buffer
In this memory format each byte of display buffer contains two adjacent pixels. Setting or
resetting any pixel will require reading the entire byte, masking out the upper or lower
nibble (4 bits) and setting the appropriate bits to 1.
Four bit pixels provide 16 gray shades/color possibilities. For monochrome panels the gray
shades are generated by indexing into the first 16 elements of the green component of the
Look-Up Table (LUT). For color panels the 16 colors are derived by indexing into the first
16 positions of the LUT.
S1D13506
X25B-G-003-03
Programming Notes and Examples
Issue Date: 01/02/06
Epson Research and Development
Vancouver Design Center
Page 17
3.3 Memory Organization for 8 Bpp (256 Colors/16 Gray Shades)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pixel 0
Bits 7-0
Figure 3-2: Pixel Storage for 8 Bpp in One Byte of Display Buffer
At a color depth of eight bpp each byte of display buffer represents one pixel on the display.
At this color depth the read-modify-write cycles of 4 bpp are eliminated making the update
of each pixel faster.
Each byte indexes into one of the 256 positions of the LUT. The S1D13506 LUT supports
four bits per primary color. This translates into 4096 possible colors when color mode is
selected. Therefore the displayed mode has 256 colors available out of a possible 4096.
When a monochrome panel is selected, the green component of the LUT is used to
determine the gray shade intensity. The green indices, with only four bits, can resolve 16
gray shades.
Note
When a monochrome panel (REG[030h] bit 2 = 0) is selected, a four bpp color depth
also provides 16 gray shades and uses less display buffer.
3.4 Memory Organization for 15 Bpp (32768 Colors/32 Gray Shades)
Bit 15
Bit 14
Bit 13
Bit 11
Bit 10
Bit 9
Red Component
Bits 4-0
Reserved
Bit 7
Bit 12
Bit 6
Bit 5
Green Component
Bits 2-0
Bit 4
Bit 8
Green Component
Bits 4-3
Bit 3
Bit 2
Bit 1
Bit 0
Blue Component
Bits 4-0
Figure 3-3: Pixel Storage for 15 Bpp in Two Bytes of Display Buffer
At a color depth of 15 bpp the S1D13506 is capable of displaying 32768 colors. The 32768
color pixel is divided into four parts: one reserved bit, five bits for red, five bits for green,
and five bits for blue. In this mode the LUT is bypassed and output goes directly into the
Frame Rate Modulator.
Programming Notes and Examples
Issue Date: 01/02/06
S1D13506
X25B-G-003-03
Page 18
Epson Research and Development
Vancouver Design Center
When dithering is enabled (REG[041h) bit 1) the full color range is available on all display
types. If dithering is disabled the full color range is only available on TFT/D-TFD or CRT
displays. Passive LCD displays are limited to using the four most significant bits from each
of the red, green and blue portions of each color resulting in 4096 (24 × 24 × 24) possible
colors.
Should a monochrome panel be used at this color depth, the output sends the five bits of the
green LUT component to the modulator for a total of 32 possible gray shades. If dithering
is disabled, the maximum number of gray shades is 16.
3.5 Memory Organization for 16 Bpp (65536 Colors/64 Gray Shades)
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Red Component
Bits 4-0
Bit 7
Bit 6
Bit 5
Green Component
Bits 2-0
Bit 9
Bit 8
Green Component
Bits 5-3
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Blue Component
Bits 4-0
Figure 3-4: Pixel Storage for 16 Bpp in Two Bytes of Display Buffer
At a color depth of 16 bpp the S1D13506 is capable of displaying 65536 colors. The 65536
color pixel is divided into three parts: five bits for red, six bits for green, and five bits for
blue. In this mode the LUT is bypassed and output goes directly into the Frame Rate
Modulator.
When dithering is enabled (REG[041h) bit 1) the full color range is available on all display
types. If dithering is disabled the full color range is only available on TFT/D-TFD or CRT
displays. Passive LCD displays are limited to using the four most significant bits from each
of the red, green and blue portions of each color resulting in 4096 (24 × 24 × 24) possible
colors.
Should monochrome mode be chosen at this color depth, the output sends the six bits of the
green LUT component to the modulator for a total of 64 possible gray shades. If dithering
is disabled, the maximum number of gray shades is 16.
S1D13506
X25B-G-003-03
Programming Notes and Examples
Issue Date: 01/02/06
Epson Research and Development
Vancouver Design Center
Page 19
4 Look-Up Table (LUT)
This section discusses programming the S1D13506 Look-Up Table (LUT). Included is a
summary of the LUT registers, recommendations for color/gray shade LUT values, and
additional programming considerations. For a discussion of the LUT architecture, refer to
the S1D13506 Hardware Functional Specification, document number X25B-A-001-xx.
The S1D13506 is designed with a separate LUT for both the LCD and CRT/TV. Each LUT
consists of 256 indexed red/green/blue entries. Each LUT entry is four bits wide. The color
depth determines how many indices are used to output the image to the display. 4 bpp uses
the first 16 indices, 8 bpp uses all 256 indices, and 15/16 bpp color depths bypass the LUT
entirely.
In color modes, the pixel values stored in the display buffer index directly to an RGB value
stored in the LUT. In monochrome modes, the pixel value indexes into the green
component of the LUT and the amount of green at that index controls the intensity.
Monochrome mode look-ups are done based on the Color/Mono Panel Select bit
(REG[030h] bit 2). The CRT interface receives the RGB values from the LUT even if
simultaneous display is used with a monochrome panel. Therefore, it is important to
program the R, G, and B components of the CRT LUT either with a unique set of values,
or with R, G, and B values all equivalent.
4.1 Registers
REG[1E0h] Look-Up Table Mode Register
n/a
n/a
n/a
n/a
n/a
n/a
LUT Mode
Bit 1
LUT Mode
Bit 0
The S1D13506 is designed with a separate LUT for both the LCD and CRT/TV. The LUT
Mode register selects which of the LUTs will be accessed by the CPU when reads/writes
are made to REG[1E2h] and REG[1E4h]. LUT mode selection allows the LUTs to be
individually written or have identical data written to both LUTs. Individual writes to these
registers are useful for Epson Independent Simultaneous Display (EISD) modes where
independent images are displayed on the LCD and the CRT/TV. For further information on
Epson Independent Simultaneous Display, see the S1D13506 Hardware Functional
Specification, document number X25B-A-001-xx.
For normal operation, this register should be set to 00h which will read the LCD LUT and
write both the LCD and CRT/TV LUTs with identical data. For selection of other LUT
modes, see REG[1E0h] in the S1D13506 Hardware Functional Specification, document
number X25B-A-001-xx.
REG[1E2h] Look-Up Table Address Register
LUT Address
Bit 7
LUT Address
Bit 6
Programming Notes and Examples
Issue Date: 01/02/06
LUT Address
Bit 5
LUT Address
Bit 4
LUT Address
Bit 3
LUT Address
Bit 2
LUT Address
Bit 1
LUT Address
Bit 0
S1D13506
X25B-G-003-03
Page 20
Epson Research and Development
Vancouver Design Center
The LUT address register selects which of the 256 LUT entries will be accessed. Writing
to this register will select the red bank. After three successive reads or writes to the data
register (REG[1E4h]) this register is automatically incremented by one.
REG[1E4h] Look-Up Table Data Register
LUT Data
Bit 3
LUT Data
Bit 2
LUT Data
Bit 1
LUT Data
Bit 0
n/a
n/a
n/a
n/a
This register is where the 4-bit red/green/blue data is written to/read from. With each
successive read or write the internal bank select is incremented. Three successive reads
from this register will result in reading the red, then the green, and finally the blue values
associated with the index set in the LUT address register.
After the third read the LUT address register is incremented and the internal bank select
points to the red bank again.
4.2 Look-Up Table Organization
• The Look-Up Table treats the value of a pixel as an index into an array of colors or gray
shades. For example, a pixel value of zero would point to the first LUT entry, whereas a
pixel value of seven would point to the eighth LUT entry.
• The value contained in each LUT entry represents the intensity of the given color or
gray shade. This intensity can range in value between 0 and 0Fh.
• The S1D13506 Look-Up Table is linear. This means increasing the LUT entry number
results in a lighter color or gray shade. For example, a LUT entry of 0Fh in the red bank
results in bright red output while a LUT entry of 05h results in dull red.
Table 4-1: Look-Up Table Configurations
Display Mode
4-Bit Wide Look-Up Table
RED
4 bpp gray
8 bpp gray
15 bpp gray
16 bpp gray
4 bpp color
8 bpp color
15 bpp color
16 bpp color
16
256
GREEN
16
16
BLUE
16
256
16
256
Effective Gray
Shades/Colors on an
Passive Panel With
Dithering Disabled
Effective Gray
Shades/Colors on a
Passive Panel With
Dithering Enabled
16 gray shades
16 gray shades
16 gray shades
16 gray shades
16 colors
256 colors
4096 colors
4096 colors
16 gray shades
16 gray shades
64 gray shades
64 gray shades
16 colors
256 colors
32768 colors
65536 colors
= Indicates the Look-Up Table is not used for that display mode
S1D13506
X25B-G-003-03
Programming Notes and Examples
Issue Date: 01/02/06
Epson Research and Development
Vancouver Design Center
Page 21
4.2.1 Color Modes
In color display modes, the number of LUT entries used is automatically selected
depending on the color depth.
4 bpp color
When the S1D13506 is configured for 4 bpp color mode the first 16 entries in the LUT are
used. Each byte in the display buffer contains two adjacent pixels. The upper and lower
nibbles of the byte are used as indices into the LUT.
The following table shows LUT values that will simulate those of a VGA operating in 16
color mode.
Table 4-2: Suggested LUT Values to Simulate VGA Default 16 Color Palette
Index
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
...
FF
Red
00
00
00
00
0A
0A
0A
0A
00
00
00
00
0F
0F
0F
0F
00
00
00
Green
00
00
0A
0A
00
00
0A
0A
00
00
0F
0F
00
00
0F
0F
00
00
00
Blue
00
0A
00
0A
00
0A
00
0A
00
0F
00
0F
00
0F
00
0F
00
00
00
= Indicates unused entries in the LUT
Programming Notes and Examples
Issue Date: 01/02/06
S1D13506
X25B-G-003-03
Page 22
Epson Research and Development
Vancouver Design Center
8 bpp color
When the S1D13506 is configured for 8 bpp color mode all 256 entries in the LUT are used.
Each byte in the display buffer corresponds to one pixel and is used as an index value into
the LUT.
The S1D13506 LUT has four bits (16 intensities) of intensity control per primary color
while a standard VGA RAMDAC has six bits (64 intensities). This four to one difference
must be considered when attempting to match colors between a VGA RAMDAC and the
S1D13506 LUT. (i.e. VGA levels 0 - 3 map to LUT level 0, VGA levels 4 - 7 map to LUT
level 1...). Additionally, the significant bits of the color tables are located at different offsets
within their respective bytes. After calculating the equivalent intensity value the result must
be shifted into the correct bit positions.
The following table shows LUT values that will approximate the VGA default color palette.
Table 4-3: Suggested LUT Values to Simulate VGA Default 256 Color Palette
Index
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
R
00
00
00
00
A0
A0
A0
A0
50
50
50
50
F0
F0
F0
F0
00
10
20
20
30
40
50
60
70
80
90
A0
B0
C0
E0
S1D13506
X25B-G-003-03
G
00
00
A0
A0
00
00
50
A0
50
50
F0
F0
50
50
F0
F0
00
10
20
20
30
40
50
60
70
80
90
A0
B0
C0
E0
B
00
A0
00
A0
00
A0
00
A0
50
F0
50
F0
50
F0
50
F0
00
10
20
20
30
40
50
60
70
80
90
A0
B0
C0
E0
Index
40
41
42
43
44
45
46
47
48
49
4A
4B
4C
4D
4E
4F
50
51
52
53
54
55
56
57
58
59
5A
5B
5C
5D
5E
R
F0
F0
F0
F0
F0
D0
B0
90
70
70
70
70
70
70
70
70
B0
C0
D0
E0
F0
F0
F0
F0
F0
F0
F0
F0
F0
E0
D0
G
70
90
B0
D0
F0
F0
F0
F0
F0
F0
F0
F0
F0
D0
B0
90
B0
B0
B0
B0
B0
B0
B0
B0
B0
C0
D0
E0
F0
F0
F0
B
70
70
70
70
70
70
70
70
70
90
B0
D0
F0
F0
F0
F0
F0
F0
F0
F0
F0
E0
D0
C0
B0
B0
B0
B0
B0
B0
B0
Index
80
81
82
83
84
85
86
87
88
89
8A
8B
8C
8D
8E
8F
90
91
92
93
94
95
96
97
98
99
9A
9B
9C
9D
9E
R
30
40
50
60
70
70
70
70
70
70
70
70
70
60
50
40
30
30
30
30
30
30
30
30
50
50
60
60
70
70
70
G
30
30
30
30
30
30
30
30
30
40
50
60
70
70
70
70
70
70
70
70
70
60
50
40
50
50
50
50
50
50
50
B
70
70
70
70
70
60
50
40
30
30
30
30
30
30
30
30
30
40
50
60
70
70
70
70
70
70
70
70
70
60
60
Index
C0
C1
C2
C3
C4
C5
C6
C7
C8
C9
CA
CB
CC
CD
CE
CF
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
DA
DB
DC
DD
DE
R
00
00
00
00
00
00
00
00
20
20
30
30
40
40
40
40
40
40
40
40
40
30
30
20
20
20
20
20
20
20
20
G
40
40
40
40
40
30
20
10
20
20
20
20
20
20
20
20
20
20
30
30
40
40
40
40
40
40
40
40
40
30
30
B
00
10
20
30
40
40
40
40
40
40
40
40
40
30
30
20
20
20
20
20
20
20
20
20
20
20
30
30
40
40
40
Programming Notes and Examples
Issue Date: 01/02/06
Epson Research and Development
Vancouver Design Center
Page 23
Table 4-3: Suggested LUT Values to Simulate VGA Default 256 Color Palette (Continued)
Index
1F
20
21
22
23
24
25
26
27
28
29
2A
2B
2C
2D
2E
2F
30
31
32
33
34
35
36
37
38
39
3A
3B
3C
3D
3E
3F
R
F0
00
40
70
B0
F0
F0
F0
F0
F0
F0
F0
F0
F0
B0
70
40
00
00
00
00
00
00
00
00
70
90
B0
D0
F0
F0
F0
F0
G
F0
00
00
00
00
00
00
00
00
00
40
70
B0
F0
F0
F0
F0
F0
F0
F0
F0
F0
B0
70
40
70
70
70
70
70
70
70
70
B
F0
F0
F0
F0
F0
F0
B0
70
40
00
00
00
00
00
00
00
00
00
40
70
B0
F0
F0
F0
F0
F0
F0
F0
F0
F0
D0
B0
90
Index
5F
60
61
62
63
64
65
66
67
68
69
6A
6B
6C
6D
6E
6F
70
71
72
73
74
75
76
77
78
79
7A
7B
7C
7D
7E
7F
R
C0
B0
B0
B0
B0
B0
B0
B0
B0
00
10
30
50
70
70
70
70
70
70
70
70
70
50
30
10
00
00
00
00
00
00
00
00
G
F0
F0
F0
F0
F0
F0
E0
D0
C0
00
00
00
00
00
00
00
00
00
10
30
50
70
70
70
70
70
70
70
70
70
50
30
10
B
B0
B0
C0
D0
E0
F0
F0
F0
F0
70
70
70
70
70
50
30
10
00
00
00
00
00
00
00
00
00
10
30
50
70
70
70
70
Index
9F
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
AA
AB
AC
AD
AE
AF
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
BA
BB
BC
BD
BE
BF
R
70
70
70
70
70
70
60
60
50
50
50
50
50
50
50
50
50
00
10
20
30
40
40
40
40
40
40
40
40
40
30
20
10
G
50
50
50
60
60
70
70
70
70
70
70
70
70
70
60
60
50
00
00
00
00
00
00
00
00
00
10
20
30
40
40
40
40
B
50
50
50
50
50
50
50
50
50
50
50
60
60
70
70
70
70
40
40
40
40
40
30
20
10
00
00
00
00
00
00
00
00
Index
DF
E0
E1
E2
E3
E4
E5
E6
E7
E8
E9
EA
EB
EC
ED
EE
EF
F0
F1
F2
F3
F4
F5
F6
F7
F8
F9
FA
FB
FC
FD
FE
FF
R
20
20
30
30
30
40
40
40
40
40
40
40
40
40
30
30
30
20
20
20
20
20
20
20
20
00
00
00
00
00
00
00
00
G
20
20
20
20
20
20
20
20
20
20
30
30
30
40
40
40
40
40
40
40
40
40
30
30
30
00
00
00
00
00
00
00
00
B
40
40
40
40
40
40
30
30
30
20
20
20
20
20
20
20
20
20
30
30
30
40
40
40
40
00
00
00
00
00
00
00
00
15 bpp color
The Look-Up Table is bypassed at this color depth, hence programming the LUT is not
required.
16 bpp color
The Look-Up Table is bypassed at this color depth, hence programming the LUT is not
required.
Programming Notes and Examples
Issue Date: 01/02/06
S1D13506
X25B-G-003-03
Page 24
Epson Research and Development
Vancouver Design Center
4.2.2 Gray Shade Modes
This discussion of gray shade (monochrome) modes only applies to the panel interface.
Monochrome mode is selected when REG[030h] bit 2 returns a 0. In this mode the value
output to the panel is derived solely from the green component of the LUT. The CRT/TV
image is formed from all three LUT components (RGB).
Note
In order to match the colors on a CRT/TV with the colors on a monochrome panel when
displaying identical images on the panel and CRT/TV, the red and blue components of
the LUT must be set to the same intensity as the green component.
4 bpp gray shade
The 4 bpp gray shade mode uses the green component of the first 16 LUT entries. The
remaining indices of the LUT are unused.
Table 4-4: Suggested LUT Values for 4 Bpp Gray Shade
Index
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
...
FF
Red
00
10
20
30
40
50
60
70
80
90
A0
B0
C0
D0
E0
F0
00
00
00
Green
00
10
20
30
40
50
60
70
80
90
A0
B0
C0
D0
E0
F0
00
00
00
Blue
00
10
20
30
40
50
60
70
80
90
A0
B0
C0
D0
E
F0
00
00
00
Required to match CRT to panel
Unused entries
S1D13506
X25B-G-003-03
Programming Notes and Examples
Issue Date: 01/02/06
Epson Research and Development
Vancouver Design Center
Page 25
8 bpp gray shade
The 8 bpp gray shade mode uses the green component of the first 16 LUT entries. The green
portion of the LUT provides 16 possible intensities. There is no increase in gray shades
when selecting 8 bpp mode over 4 bpp mode; however, Swivelview and the BitBLT engine
can be used in 8 bpp mode but not in 4 bpp mode.
15 bpp gray shade
The Look-Up Table is bypassed at this color depth, hence programming the LUT is not
required.
As with 8 bpp there are limitations to the colors which can be displayed. In this mode the
five bits of green are used to set the absolute intensity of the image. This results in 32 gray
shades when dithering is enabled and 16 gray shades when dithering is disabled.
16 bpp gray shade
The Look-Up Table is bypassed at this color depth, hence programming the LUT is not
required.
As with 8 bpp there are limitations to the colors which can be displayed. In this mode the
six bits of green are used to set the absolute intensity of the image. This results in 64 gray
shades when dithering is enabled and 16 gray shades when dithering is disabled.
Programming Notes and Examples
Issue Date: 01/02/06
S1D13506
X25B-G-003-03
Page 26
Epson Research and Development
Vancouver Design Center
5 Virtual Displays
This section discusses the concept of a virtual display and covers navigation within a virtual
display using panning and scrolling.
5.1 Virtual Display
Virtual display is where the image to be viewed is larger than the physical display. This can
be in the horizontal, vertical or both dimensions. To view the image, the display is used as
a window (or viewport) into the display buffer. At any given time only a portion of the
image is visible. Panning and scrolling are used to view the full image. For further information on panning and scrolling, see Section 5.2, “Panning and Scrolling” on page 30.
The Memory Address Offset registers determine the number of horizontal pixels in the
virtual image. The offset registers can be set for a maximum of 211 or 2048 words. At a
color depth of 4 bpp, 2048 words cover 8,192 pixels. At a color depth of 16 bpp, 2048 words
cover 2048 pixels.
The maximum number of lines of the virtual image is the size of the display buffer divided
by the number of bytes per horizontal line. The number of bytes per line equals the number
of words in the offset register multiplied by two. At the maximum horizontal size, the
greatest number of lines that can be displayed using 2M bytes of display memory is 512.
Reducing the horizontal size makes more display buffer available, thus increasing the
available virtual vertical size.
In addition to the calculated limit, the virtual vertical size is limited by the size and location
of the Dual Panel Buffer and the Ink Layer/Hardware Cursor (if present).
The maximum horizontal/vertical sizes are seldom used. Figure 5-1: “Viewport Inside a
Virtual Display,” shows a more typical use of a virtual display. With a display panel of
320x240 pixels, an image of 640x480 pixels can be viewed by navigating a 320x240 pixel
viewport around the image using panning and scrolling.
320x240
Viewport
640x480
“Virtual” Display
Figure 5-1: Viewport Inside a Virtual Display
S1D13506
X25B-G-003-03
Programming Notes and Examples
Issue Date: 01/02/06
Epson Research and Development
Vancouver Design Center
Page 27
5.1.1 Registers
REG[046h] LCD Memory Address Offset Register 0
LCD Memory
Address
Offset Bit 7
LCD Memory
Address
Offset Bit 6
LCD Memory
Address
Offset Bit 5
LCD Memory
Address
Offset Bit 4
LCD Memory
Address
Offset Bit 3
LCD Memory
Address
Offset Bit 2
LCD Memory
Address
Offset Bit 1
LCD Memory
Address
Offset Bit 0
n/a
LCD Memory
Address
Offset Bit 10
LCD Memory
Address
Offset Bit 9
LCD Memory
Address
Offset Bit 8
REG[047h] LCD Memory Address Offset Register 1
n/a
n/a
n/a
n/a
These registers form the 11-bit memory address offset for the LCD display. This offset
equals the number of words from the beginning of one line of the LCD display to the
beginning of the next line.
To maintain a constant virtual width as color depth changes, the memory address offset
must also change. At a color depth of 4 bpp each word contains 4 pixels, at 16 bpp each
word contains one pixel. The formula to determine the value for the memory address
registers is:
= PixelsPerVirtualLine ÷ PixelsPerWord
Offset
This value may not necessarily represent the number of words shown on the LCD display.
This is the virtual width of the display image and may be greater than or equal to the
physical display width. If PixelsPerVirtualLine equals the physical display width as set in
the LCD Horizontal Display Width register (REG[032h]), then the virtual display and
physical display are the same size.
REG[066h] CRT/TV Memory Address Offset Register 0
CRT/TV
Memory
Address
Offset Bit 7
CRT/TV
Memory
Address
Offset Bit 6
CRT/TV
Memory
Address
Offset Bit 5
CRT/TV
Memory
Address
Offset Bit 4
CRT/TV
Memory
Address
Offset Bit 3
CRT/TV
Memory
Address
Offset Bit 2
CRT/TV
Memory
Address
Offset Bit 1
CRT/TV
Memory
Address
Offset Bit 0
n/a
CRT/TV
Memory
Address
Offset Bit 10
CRT/TV
Memory
Address
Offset Bit 9
CRT/TV
Memory
Address
Offset Bit 8
REG[067h] CRT/TV Memory Address Offset Register 1
n/a
n/a
n/a
n/a
These registers form the 11-bit memory address offset for the CRT/TV display. This offset
equals the number of words form the beginning of one line of the CRT/TV display to the
beginning of the next line.
To maintain a constant virtual width as color depth changes, the memory address offset
must also change. At a color depth of 4 bpp each word contains 4 pixels, at 16 bpp each
word contains one pixel. The formula to determine the value for the memory address
registers is:
Programming Notes and Examples
Issue Date: 01/02/06
S1D13506
X25B-G-003-03
Page 28
Epson Research and Development
Vancouver Design Center
Offset
= PixelsPerVirtualLine ÷ PixelsPerWord
This value may not necessarily represent the number of words shown on the CRT/TV
display. This is the virtual width of the display image and may be greater than or equal to
the physical display width. If PixelsPerVirtualLine equals the physical display width as set
in the CRT/TV Horizontal Display Width register (REG[050h]), then the virtual display
and physical display are the same size.
5.1.2 Examples
Example 1: Determine the offset value required for a line of 800 pixels at a color
depth of 8 bpp.
At a color depth of 8 bpp each byte contains one pixel, therefore each word contains two
pixels.
PixelsPerWord
= 16 ÷ bpp
= 16 ÷ 8
=2
To calculate the offset value for this example, the following formula is used.
Offset
= PixelsPerVirtualLine ÷ PixelsPerWord
= 800 ÷ 2
= 400
= 190h words
For the LCD, REG[047h] is set to 01h and REG[046h] is set to 90h.
For the CRT/TV, REG[067h] is set to 01h and REG[066h] is set to 90h.
Example 2: Program the Memory Address Offset Registers to support a 16 color (4
bpp) 800x600 virtual display on a 640x480 LCD panel.
To create a virtual display the offset registers must be programmed to the horizontal size of
the larger “virtual” image. After determining the amount of memory used by each line (see
example 1), calculate whether there is enough memory to support the desired number of
lines.
1. Initialize the S1D13506 registers for a 640x480 panel. (See Section 2, “Initialization”
on page 12).
2. Calculate the number of pixels per word.
PixelsPerWord
= 16 ÷ bpp
= 16 ÷ 4
=4
3. Determine the offset register value.
S1D13506
X25B-G-003-03
Programming Notes and Examples
Issue Date: 01/02/06
Epson Research and Development
Vancouver Design Center
Page 29
Offset
= PixelsPerVirtualLine ÷ PixelsPerWord
= 800 ÷ 4
= 200 words
= 0C8h words
For the LCD, REG[047h] is set to 00h and REG[046h] is set to C8h.
For the CRT/TV, REG[067h] is set to 00h and REG[066h] is set to C8h.
4. To confirm whether there is enough memory for the required virtual height, the
following formula is used.
MemoryRequired
= WordsPerVirtualLine x 2 x NumberOfLines
= 200 x 2 x 600
= 240,000 bytes
This display configuration is supported on a system with the minimum supported
memory size of 512K bytes. It is safe to continue with these values.
Programming Notes and Examples
Issue Date: 01/02/06
S1D13506
X25B-G-003-03
Page 30
Epson Research and Development
Vancouver Design Center
5.2 Panning and Scrolling
The terms panning and scrolling refer to the actions used to move a viewport about a virtual
display. Although the entire image is stored in the display buffer, only a portion is visible
at any given time.
Panning describes the horizontal (side to side) motion of the viewport. When panning to the
right the image in the viewport appears to slide to the left. When panning to the left the
image to appears to slide to the right. Scrolling describes the vertical (up and down) motion
of the viewport. Scrolling down causes the image to appear to slide up and scrolling up
causes the image to appear to slide down.
Both panning and scrolling are performed by modifying the start address registers. The start
address refers to the word offset in the display buffer where the beginning of the image is
displayed from. At color depths less than 15 bpp, another register is required for smooth
movement. The pixel pan registers (REG[048h] for LCD, REG[068h] for CRT/TV) allow
panning in smaller increments than changing the start address alone.
Internally, the S1D13506 latches different signals at different times. Due to this internal
sequence, the start address and pixel pan registers should be accessed in a specific order
during panning and scrolling operations, in order to provide the smoothest scrolling. Setting
the registers in the wrong sequence, or at the wrong time, results in a “tearing” or jitter
effect on the display.
The start address is latched at the beginning of each frame, so the start address can be set
within the vertical non-display period (VNDP). The pixel pan register values are latched at
the beginning of each display line and must be set during the vertical non-display period.
The correct sequence for programing these registers is:
1. Wait for the beginning of the vertical non-display period - For the LCD, REG[03Ah]
bit 7 will return a 1 during VNDP; for the CRT/TV, REG[058h] bit 7 will return a 1
during VNDP. Wait for the transition of the appropriate bit to go from 0 to 1. This ensures the register updates are carried out at the beginning of VNDP.
2. Update the start address registers - For the LCD, REG[042h], REG[043h],
REG[044h]; for the CRT/TV, REG[062h], REG[063h], REG[064h].
3. Update the pixel panning register - For the LCD, REG[048h] bits 1-0; for the CRT/TV
REG[068h] bits 1-0.
Sample code for panning and scrolling is available in the file hal_virt.c which is included
in the HAL source code available on the internet at www.eea.epson.com.
S1D13506
X25B-G-003-03
Programming Notes and Examples
Issue Date: 01/02/06
Epson Research and Development
Vancouver Design Center
Page 31
5.2.1 Registers
REG[042h] LCD Display Start Address Register 0
LCD Display
Start Address
Bit 7
LCD Display
Start Address
Bit 6
LCD Display
Start Address
Bit 5
LCD Display
Start Address
Bit 4
LCD Display
Start Address
Bit 3
LCD Display
Start Address
Bit 2
LCD Display
Start Address
Bit 1
LCD Display
Start Address
Bit 0
LCD Display
Start Address
Bit 11
LCD Display
Start Address
Bit 10
LCD Display
Start Address
Bit 9
LCD Display
Start Address
Bit 8
LCD Display
Start Address
Bit 19
LCD Display
Start Address
Bit 18
LCD Display
Start Address
Bit 17
LCD Display
Start Address
Bit 16
CRT/TV
Display Start
Address
Bit 3
CRT/TV
Display Start
Address
Bit 2
CRT/TV
Display Start
Address
Bit 1
CRT/TV
Display Start
Address
Bit 0
CRT/TV
Display Start
Address
Bit 11
CRT/TV
Display Start
Address
Bit 10
CRT/TV
Display Start
Address
Bit 9
CRT/TV
Display Start
Address
Bit 8
CRT/TV
Display Start
Address
Bit 19
CRT/TV
Display Start
Address
Bit 18
CRT/TV
Display Start
Address
Bit 17
CRT/TV
Display Start
Address
Bit 16
REG[043h] LCD Display Start Address Register 1
LCD Display
Start Address
Bit 15
LCD Display
Start Address
Bit 14
LCD Display
Start Address
Bit 13
LCD Display
Start Address
Bit 12
REG[044h] LCD Display Start Address Register 2
n/a
n/a
n/a
n/a
REG[062h] CRT/TV Display Start Address Register 0
CRT/TV
Display Start
Address
Bit 7
CRT/TV
Display Start
Address
Bit 6
CRT/TV
Display Start
Address
Bit 5
CRT/TV
Display Start
Address
Bit 4
REG[063h] CRT/TV Display Start Address Register 1
CRT/TV
Display Start
Address
Bit 15
CRT/TV
Display Start
Address
Bit 14
CRT/TV
Display Start
Address
Bit 13
CRT/TV
Display Start
Address
Bit 12
REG[064h] CRT/TV Display Start Address Register 2
n/a
n/a
n/a
n/a
The Display Start Address registers form the word address to the display buffer where the
LCD or CRT/TV starts displaying from. An address of 0 points to the beginning of the
display buffer. Changing the start address registers by one pans from 1 to 4 pixels
depending on the current color depth. The following table lists the maximum number of
pixels affected by a change of one to these registers.
Table 5-1: Number of Pixels Panned When Start Address Changed By 1
Color Depth (bpp)
4
8
15
16
Programming Notes and Examples
Issue Date: 01/02/06
Pixels per Word
4
2
1
1
Number of Pixels Panned
4
2
1
1
S1D13506
X25B-G-003-03
Page 32
Epson Research and Development
Vancouver Design Center
REG[048h] LCD Pixel Panning Register
n/a
n/a
n/a
n/a
Reserved
Reserved
LCD Pixel
Panning Bit 1
LCD Pixel
Panning Bit 0
n/a
Reserved
Reserved
CRT/TV Pixel
Panning Bit 1
CRT/TV Pixel
Panning Bit 0
REG[068h] CRT/TV Pixel Panning Register
n/a
n/a
n/a
The pixel panning register offers finer control over panning than is available using the start
address registers. Using the pixel panning register, it is possible to pan the displayed image
one pixel at a time. The number of bits required to pan a single pixel at a time, change with
the color depth. The following table shows the bits of the pixel pan register which are used
for each color depth.
Table 5-2: Active Pixel Pan Bits
Color Depth (bpp)
4
8
15/16
Pixel Pan bits used
bits [1:0]
bit 0
none
Note
The pixel panning registers are not required for color depths of 15 or 16 bpp.
The pixel panning registers must be updated in conjunction with the start address registers.
The pixel panning registers can be thought of as the least significant bit(s) of the start
address registers.
When panning to the right on an LCD set for a color depth of 4 bpp, the registers would be
updated as follows.
1. Pan right by 1 pixel
- increment the pixel panning register by 1: REG[048h] = 01b.
2. Pan right by 1 pixel
- increment the pixel panning register by 1: REG[048h] = 10b.
3. Pan right by 1 pixel
- increment the pixel panning register by 1: REG[048h] = 11b.
4. Pan right by 1 pixel
- reset the pixel panning register to 0: REG[048h] = 00b.
- increment the start address register by 1: (REG[042h],
REG[043h], REG[044h]) + 1.
Note
The above example assumes the pixel panning register is initially set at 0.
S1D13506
X25B-G-003-03
Programming Notes and Examples
Issue Date: 01/02/06
Epson Research and Development
Vancouver Design Center
Page 33
When panning to the left on an LCD set for a color depth of 4 bpp, the registers would be
updated as follows.
1. Pan left by 1 pixel
- decrement the pixel panning register by 1: REG[048h] = 11b.
- decrement the start address register by 1: (REG[042h],
REG[043h], REG[044h]) - 1.
2. Pan left by 1 pixel
- decrement the pixel panning register by 1: REG[048h] = 10b.
3. Pan left by 1 pixel
- decrement the pixel panning register by 1: REG[048h] = 01b.
4. Pan left by 1 pixel
- decrement the pixel panning register by 1: REG[048h] = 00b.
Note
The above example assumes the pixel panning register is initially set at 0.
5.2.2 Examples
The following examples assume the display system has been configured to view a 800x600
pixel image in a 640x480 viewport. Refer to Section 2, “Initialization” on page 12 and
Section 5.1, “Virtual Display” on page 26 for assistance with these settings.
Example 3: Panning - Right and Left
To pan to the right, increment the value in the pixel panning register (REG[048h] for LCD,
REG[068h] for CRT/TV). When the pixel pan value reaches the maximum value for the
current color depth (i.e. 11b for 4 bpp, 1b for 8 bpp) then set the pixel pan value to zero and
increment the start address value. To pan to the left (assuming the pixel panning register is
zero), decrement the value in the pixel panning register and decrement the start address
register. When the pixel pan value reaches zero then decrement both the pixel panning
register and start address register again. If the pixel panning register contains a value other
than zero, decrement the value in the pixel panning register only and when the pixel pan
value reaches zero, decrement both the pixel panning register and start address register.
Note
Panning operations are easier to follow if a variable (e.g. PanValue) is used to track both
the pixel panning and start address registers. The least significant bits of PanValue will
represent the pixel panning register value and the more significant bits are the start address register value.
The following example pans to the right by one pixel when the color depth is 4 bpp.
1. Increment PanValue.
PanValue
= PanValue + 1
2. Mask off the values from PanValue for the pixel panning and start address register
portions. In this case, 4 bpp, the lower two bits are the pixel panning value and the
upper bits are the start address.
PixelPan
Programming Notes and Examples
Issue Date: 01/02/06
= PanValue AND 3
S1D13506
X25B-G-003-03
Page 34
Epson Research and Development
Vancouver Design Center
StartAddress
= PanValue SHR 2 (remove PixelPan bits)
3. Write the pixel panning and start address register values using the procedure outlined
in Section 5.2.1, “Registers” on page 31.
Example 4: Scrolling - Up and Down
To scroll down, increase the value in the Display Start Address Registers (REG[042h],
REG[043h], REG[044h] for LCD, REG[062h], REG[063h], REG[064h] for CRT/TV) by
the number of words in one virtual scan line. To scroll up, decrease the value in the Display
Start Address Registers by the number of words in one virtual scan line.
The following example scrolls down one line for a 16 color (4 bpp) 800x600 virtual image
using a 640x480 single panel LCD.
1. Determine the number of words in each line of the virtual image. For a color depth of
4 bpp each byte contains two pixels so each word contains 4 pixels.
OffsetWords
= PixelsPerVirtualLine ÷ PixelsPerWord
= 800 ÷ 4
= 200
= C8h
2. Increment the display start address by the number of words per virtual line.
StartAddress
= StartAddress + OffsetWords
= StartAddress + C8h
3. Separate the display start address value into three bytes. For the LCD, write the LSB
to REG[042h] and the MSB to REG[044h]. For the CRT/TV, write the LSB to
REG[062h] and the MSB to REG[064h].
For the LCD, REG[044h] is set to 00h, REG[043h] is set to 00h, and REG[042h] is set
to C8h.
For the CRT/TV, REG[064h] is set to 00h, REG[063h] is set to 00h, and REG[062h]
is set to C8h.
Note
The above example assumes the display start address was initially 0 (the beginning of
the display buffer).
S1D13506
X25B-G-003-03
Programming Notes and Examples
Issue Date: 01/02/06
Epson Research and Development
Vancouver Design Center
Page 35
6 Power Save Mode
The S1D13506 has been designed for very low-power applications. During normal
operation, the internal clocks are dynamically disabled when not required. The S1D13506
design also includes a Power Save Mode to further save power. When Power Save Mode is
initiated, automatic LCD power sequencing takes place to ensure the LCD bias power
supply is disabled properly. For further information on LCD power sequencing, see Section
7, “LCD Power Sequencing” on page 38.
For Power Save Mode AC Timing, see the S1D13506 Hardware Functional
Specification, document number X25B-A-001-xx.
6.1 Overview
The S1D13506 supports a software initiated Power Save Mode. Enabling/disabling Power
Save Mode is controlled using the Power Save Mode Enable bit (REG[1F0h] bit 0). The
type of DRAM refresh used during Power Save Mode can also be selected by software.
While Power Save Mode is enabled the following conditions apply.
• Display(s) are inactive.
• Registers are accessible.
• Memory is in-accessible.
• LUT is accessible.
6.2 Registers
6.2.1 Enabling Power Save Mode
REG[1F0h] Power Save Configuration Register
n/a
n/a
n/a
Reserved
n/a
n/a
n/a
Power Save
Mode Enable
The Power Save Mode Enable bit initiates Power Save Mode when set to 1. Setting the bit
back to 0 returns the S1D13506 back to normal mode.
Programming Notes and Examples
Issue Date: 01/02/06
S1D13506
X25B-G-003-03
Page 36
Epson Research and Development
Vancouver Design Center
6.2.2 Power Save Status Bits
REG[1F1h] Power Save Status Register
n/a
n/a
n/a
n/a
n/a
n/a
LCD Power
Save Status
Memory
Controller
Power Save
Status
The LCD Power Save Status bit is a read-only status bit which indicates the power save
state of the LCD panel. When this bit returns a 1, the panel is powered-off. When this bit
returns a 0, the LCD panel is powered up or in transition of powering up or down. This bit
will return a 1 after a chip reset.
Note
The LCD pixel clock source may be disabled when this bit returns a 1.
REG[1F1h] Power Save Status Register
n/a
n/a
n/a
n/a
n/a
n/a
LCD Power
Save Status
Memory
Controller
Power Save
Status
The Memory Controller Power Save Status bit is a read-only status bit which indicates the
power save state of the S1D13506 DRAM interface. When this bit returns a 1, the DRAM
interface is powered down (the DRAM is either in self-refresh mode or completely idle).
When this bit returns a 0, the DRAM interface is active. This bit will return a 0 after a chip
reset.
For this bit to return a 1, the DRAM Refresh Select bits must select either self-refresh or no
refresh. For information on the DRAM Refresh Select bits, see Section 6.2.3, “DRAM
Refresh Selection” on page 37.
Note
The memory clock source may be disabled when this bit returns a 1.
S1D13506
X25B-G-003-03
Programming Notes and Examples
Issue Date: 01/02/06
Epson Research and Development
Vancouver Design Center
Page 37
6.2.3 DRAM Refresh Selection
REG[021h] DRAM Refresh Rate Register
Refresh
Select Bit 1
Refresh
Select Bit 0
n/a
n/a
DRAM
Refresh Rate
Bit 2
n/a
DRAM
Refresh Rate
Bit 1
DRAM
Refresh Rate
Bit 0
The Refresh Select bits specify the type of DRAM refresh used while Power Save Mode is
enabled. DRAM refresh selection is as follows.
Table 6-1: Refresh Selection
Refresh Select Bits [1:0]
DRAM Refresh Type
00
CAS-before-RAS (CBR) refresh
01
Self-Refresh
1X
No Refresh
The Refresh Select bits must be set before Power Save Mode is enabled. While CBR refresh
is selected the memory controller cannot be powered down and the memory clock source
must remain active. If either self-refresh or no refresh is selected the memory controller
may be powered down and the memory clock source may be disabled. For further information, see Section 6.2.2, “Power Save Status Bits” on page 36.
Note
The Refresh Select bits must not be changed while in power save mode.
Programming Notes and Examples
Issue Date: 01/02/06
S1D13506
X25B-G-003-03
Page 38
Epson Research and Development
Vancouver Design Center
7 LCD Power Sequencing
The S1D13506 is designed with internal circuitry which automates LCD power sequencing
(the process of powering-on and powering-off the LCD panel). LCD power sequencing
allows the LCD bias voltage to discharge prior to shutting down the LCD signals,
preventing long term damage to the panel and avoiding unsightly “lines” at poweron/power-off.
Proper LCD power sequencing for power-off requires a delay from the time the LCD power
is disabled to the time the LCD signals are shut down. Power-on requires the LCD signals
to be active prior to applying power to the LCD. This time interval varies depending on the
LCD bias power supply design. For example, the LCD bias power supply on the S5U13506
Evaluation board requires 0.5 seconds to fully discharge. Other power supply designs may
vary.
For most applications automatic power sequencing is the appropriate choice, see Section
7.1, “Automatic Sequencing” . However, there may be situations where the internal time
delay is insufficient to discharge the LCD bias power supply before the LCD signals are
shut down. For the sequence used to manually power-off the LCD panel, see Section 7.2,
“Manual Sequencing” .
7.1 Automatic Sequencing
LCD power sequencing is automatically provided when the S1D13506 is powered-on or
powered-off using the built-in Power Save Mode. The Power Save Mode is enabled using
REG[1F0h] bit 0. For more information on Power Save Mode, see Section 6, “Power Save
Mode” .
For LCD power sequencing AC Timing, see the S1D13506 Hardware Functional
Specification, document number X25B-A-001-xx.
7.2 Manual Sequencing
In cases where automatic LCD power sequencing is not applicable, manual sequencing can
be done. This section assumes the LCD bias power is controlled through GPIO1. The
S1D13506 GPIO pins are multi-use pins and may not be available in all system designs.
For further information on the availability of GPIO pins, see the S1D13506 Hardware
Functional Specification, document number X25B-B-001-xx.
S1D13506
X25B-G-003-03
Programming Notes and Examples
Issue Date: 01/02/06
Epson Research and Development
Vancouver Design Center
Page 39
7.2.1 Registers
REG[040h] LCD Display Mode Register
LCD Display
Blank
n/a
n/a
SwivelView
Enable Bit 1
n/a
LCD
Bit-per-pixel
Select Bit 2
LCD
Bit-per-pixel
Select Bit 1
LCD
Bit-per-pixel
Select Bit 0
When set to 1, this bit disables the LCD display pipeline and forces all LCD data outputs
to zero. This effectively blanks the screen.
Note
If a dual panel is used, the Dual Panel Buffer must be disabled before blanking the LCD
display. This is done by setting REG[041h] bit 0 to 1b.
7.2.2 Enabling the LCD Panel
If the LCD bias power supply timing requirements are different than those timings built into
the S1D13506 automated LCD power sequencing, it may be necessary to manually enable
the LCD panel. In such a case, the following procedure applies.
1. Enable the LCD signals - Set REG[040h] = 0.
Note
If a dual panel is used, enable the Dual Panel Buffer by setting REG[041h] bit 0 = 0b.
2. Enable GPIO1 to activate the LCD bias power.
7.2.3 Disabling the LCD Panel
If the LCD bias power supply timing requirements are different than those timings built into
the S1D13506 automated LCD power sequencing, it may be necessary to manually disable
the LCD panel. In such a case, the following procedure applies.
1. Disable the LCD power using GPIO1.
2. Wait the required delay time for the LCD bias power supply to discharge.
3. Disable the LCD signals - Set REG[040h] = 1.
4. Disable the LCD pixel clock source if desired. (Optional)
Programming Notes and Examples
Issue Date: 01/02/06
S1D13506
X25B-G-003-03
Page 40
Epson Research and Development
Vancouver Design Center
8 Hardware Cursor/Ink Layer
8.1 Introduction
The S1D13506 supports either a Hardware Cursor or an Ink Layer for the LCD, and either
a Hardware Cursor or an Ink Layer for the CRT/TV. The LCD and CRT/TV are supported
independently, so it is possible to select combinations such as a Hardware Cursor on the
LCD and an Ink Layer on the CRT/TV.
A Hardware Cursor improves video throughput in graphical operating systems by offloading much of the work typically assigned to software. For example, consider the actions
which must be performed when the user moves the mouse. On a system without hardware
support, the operating system must restore the area under the current cursor position, save
the area under the new location, and finally draw the cursor shape. Contrast that with the
hardware assisted system where the operating system must simply update the cursor X and
cursor Y position registers.
An Ink Layer is designed to support stylus or pen input. Without an ink layer, the operating
system must save the area of the display buffer (possibly all) where pen input is to occur.
After the system recognizes the characters entered, the display would have to be restored
and the characters redrawn in a system font. When an Ink Layer is present, the stylus path
is drawn in the Ink Layer where it overlays the displayed image. After character recognition
finishes the display is updated with the new characters and the ink layer is simply cleared.
Saving and restoring the display data is not required providing faster throughput.
The S1D13506 Hardware Cursor/Ink Layer supports a 2 bpp (four color) overlay image.
Two of the available colors are transparent and invert. The remaining two colors are user
definable.
The Hardware Cursor uses many of the same registers as the Ink Layer. Additionally, the
cursor has positional registers for movement. The cursor resolution is 64x64 at a color
depth of 2 bpp. The Ink Layer resolution is the width of the display by the height of the
display at a color depth of 2 bpp. Both the Hardware Cursor and the Ink Layer use the same
pixel values to select colors. The Hardware Cursor requires 1024 bytes of display buffer
and the Ink Layer requires (display width x display height ÷ 4) bytes of display buffer.
S1D13506
X25B-G-003-03
Programming Notes and Examples
Issue Date: 01/02/06
Epson Research and Development
Vancouver Design Center
Page 41
8.2 Registers
REG[070h] LCD Ink/Cursor Control Register
n/a
n/a
n/a
n/a
n/a
n/a
LCD
Ink/Cursor
Mode Bit 1
LCD
Ink/Cursor
Mode Bit 0
n/a
n/a
CRT/TV
Ink/Cursor
Mode Bit 1
CRT/TV
Ink/Cursor
Mode Bit 0
REG[080h] CRT/TV Ink/Cursor Control Register
n/a
n/a
n/a
n/a
The Ink/Cursor mode bits determine which of the Hardware Cursor or Ink Layer is active
as shown in following table.
Table 8-1: Ink/Cursor Mode
bit 1
0
0
1
1
Ink/Cursor Control
bit 0
0
1
0
1
Operating Mode
Inactive
Cursor
Ink
Reserved
Note
When cursor mode is selected the cursor image is always 64x64 pixels. Selecting an ink
layer will result in an area which completely covers the display.
REG[071h] LCD Ink/Cursor Start Address Register
LCD
LCD
LCD
LCD
LCD
LCD
LCD
LCD
Ink/Cursor
Ink/Cursor
Ink/Cursor
Ink/Cursor
Ink/Cursor
Ink/Cursor
Ink/Cursor
Ink/Cursor
Start Address Start Address Start Address Start Address Start Address Start Address Start Address Start Address
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
REG[081h] CRT/TV Ink/Cursor Start Address Register
CRT/TV
CRT/TV
CRT/TV
CRT/TV
CRT/TV
CRT/TV
CRT/TV
CRT/TV
Ink/Cursor
Ink/Cursor
Ink/Cursor
Ink/Cursor
Ink/Cursor
Ink/Cursor
Ink/Cursor
Ink/Cursor
Start Address Start Address Start Address Start Address Start Address Start Address Start Address Start Address
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
REG[071h] and REG[081h] determine the display buffer location of the Hardware
Cursor/Ink Layer for the LCD and CRT/TV respectively. The Ink/Cursor Start Address
register does not contain an actual address, but a value based on the following table.
Table 8-2: Cursor/Ink Start Address Encoding
Ink/Cursor Start Address Bits [7:0]
0
1 - FFh
Programming Notes and Examples
Issue Date: 01/02/06
Start Address (Bytes)
Display Buffer Size - 1024
Display Buffer Size - (n ×
8192)
S1D13506
X25B-G-003-03
Page 42
Epson Research and Development
Vancouver Design Center
REG[072h] LCD Cursor X Position Register 0
LCD Cursor X LCD Cursor X LCD Cursor X LCD Cursor X LCD Cursor X LCD Cursor X LCD Cursor X LCD Cursor X
Position
Position
Position
Position
Position
Position
Position
Position
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
REG[073h] LCD Cursor X Position Register 1
LCD Cursor X
Sign
n/a
n/a
n/a
LCD Cursor X LCD Cursor X
Position
Position
Bit 9
Bit 8
n/a
n/a
CRT/TV
Cursor X
Position Bit 3
CRT/TV
Cursor X
Position Bit 2
CRT/TV
Cursor X
Position Bit 1
CRT/TV
Cursor X
Position Bit 0
n/a
n/a
CRT/TV
Cursor X
Position Bit 9
CRT/TV
Cursor X
Position Bit 8
REG[082h] CRT/TV Cursor X Position Register 0
CRT/TV
Cursor X
Position Bit 7
CRT/TV
Cursor X
Position Bit 6
CRT/TV
Cursor X
Position Bit 5
CRT/TV
Cursor X
Position Bit 4
REG[083h] CRT/TV Cursor X Position Register 1
CRT/TV
Cursor X Sign
n/a
n/a
n/a
REG[072h], REG[073h] and REG[082h], REG[083h] control the horizontal position of the
Hardware Cursor for the LCD and CRT/TV respectively. The value in these registers
specify the location of the left edge of the cursor. When ink mode is selected these registers
must be set to zero.
The Cursor X Position supports values of the range -63 to 1023. Negative values allow for
the Cursor to be clipped (partially off the screen). The following procedure sets the Cursor
X Position.
1. Write the absolute (non-negative) value of the position in bits 9-0.
2. If the position is negative, write a 1 in the Cursor X Sign bit; otherwise write a 0 to the
sign bit.
S1D13506
X25B-G-003-03
Programming Notes and Examples
Issue Date: 01/02/06
Epson Research and Development
Vancouver Design Center
Page 43
REG[074h] LCD Cursor Y Position Register 0
LCD Cursor Y LCD Cursor Y LCD Cursor Y LCD Cursor Y LCD Cursor Y LCD Cursor Y LCD Cursor Y LCD Cursor Y
Position
Position
Position
Position
Position
Position
Position
Position
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
REG[075h] LCD Cursor Y Position Register 1
LCD Cursor Y
Sign
n/a
n/a
n/a
LCD Cursor Y LCD Cursor Y
Position
Position
Bit 9
Bit 8
n/a
n/a
CRT/TV
Cursor Y
Position Bit 3
CRT/TV
Cursor Y
Position Bit 2
CRT/TV
Cursor Y
Position Bit 1
CRT/TV
Cursor Y
Position Bit 0
n/a
n/a
CRT/TV
Cursor Y
Position Bit 9
CRT/TV
Cursor Y
Position Bit 8
REG[084h] CRT/TV Cursor Y Position Register 0
CRT/TV
Cursor Y
Position Bit 7
CRT/TV
Cursor Y
Position Bit 6
CRT/TV
Cursor Y
Position Bit 5
CRT/TV
Cursor Y
Position Bit 4
REG[085h] CRT/TV Cursor Y Position Register 1
CRT/TV
Cursor Y Sign
n/a
n/a
n/a
REG[074h], REG[075h] and REG[084h], REG[085h] control the vertical position of the
Hardware Cursor for the LCD and CRT/TV respectively. The value in these registers
specify the location of the top edge of the cursor. When ink mode is selected these registers
must be set to zero.
The Cursor Y Position supports values of the range -63 to 1023. Negative values allow for
the Cursor to be clipped (partially off the screen). The following procedure sets the Cursor
X Position.
1. Write the absolute (non-negative) value of the position in bits 9-0.
2. If the position is negative, write a 1 in the Cursor Y Sign bit; otherwise write a 0 to the
sign bit.
Programming Notes and Examples
Issue Date: 01/02/06
S1D13506
X25B-G-003-03
Page 44
Epson Research and Development
Vancouver Design Center
REG[076h] LCD Ink/Cursor Blue Color 0 Register
n/a
n/a
n/a
LCD
Ink/Cursor
Blue Color 0
Bit 4
LCD
Ink/Cursor
Blue Color 0
Bit 3
LCD
Ink/Cursor
Blue Color 0
Bit 2
LCD
Ink/Cursor
Blue Color 0
Bit 1
LCD
Ink/Cursor
Blue Color 0
Bit 0
REG[077h] LCD Ink/Cursor Green Color 0 Register
n/a
n/a
LCD
LCD
LCD
LCD
LCD
LCD
Ink/Cursor
Ink/Cursor
Ink/Cursor
Ink/Cursor
Ink/Cursor
Ink/Cursor
Green Color 0 Green Color 0 Green Color 0 Green Color 0 Green Color 0 Green Color 0
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
REG[078h] LCD Ink/Cursor Red Color 0 Register
n/a
n/a
n/a
LCD
Ink/Cursor
Red Color 0
Bit 4
LCD
Ink/Cursor
Red Color 0
Bit 3
LCD
Ink/Cursor
Red Color 0
Bit 2
LCD
Ink/Cursor
Red Color 0
Bit 1
LCD
Ink/Cursor
Red Color 0
Bit 0
These registers form the 16 bpp (5-6-5) RGB values of user-defined color 0 for the LCD
Ink Layer/Hardware Cursor.
REG[07Ah] LCD Ink/Cursor Blue Color 1 Register
n/a
n/a
n/a
LCD
Ink/Cursor
Blue Color 1
Bit 4
LCD
Ink/Cursor
Blue Color 1
Bit 3
LCD
Ink/Cursor
Blue Color 1
Bit 2
LCD
Ink/Cursor
Blue Color 1
Bit 1
LCD
Ink/Cursor
Blue Color 1
Bit 0
REG[07Bh] LCD Ink/Cursor Green Color 1 Register
n/a
n/a
LCD
LCD
LCD
LCD
LCD
LCD
Ink/Cursor
Ink/Cursor
Ink/Cursor
Ink/Cursor
Ink/Cursor
Ink/Cursor
Green Color 1 Green Color 1 Green Color 1 Green Color 1 Green Color 1 Green Color 1
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
REG[07Ch] LCD Ink/Cursor Red Color 1 Register
n/a
n/a
n/a
LCD
Ink/Cursor
Red Color 1
Bit 4
LCD
Ink/Cursor
Red Color 1
Bit 3
LCD
Ink/Cursor
Red Color 1
Bit 2
LCD
Ink/Cursor
Red Color 1
Bit 1
LCD
Ink/Cursor
Red Color 1
Bit 0
These registers form the 16 bpp (5-6-5) RGB values of user-defined color 1 for the LCD
Ink Layer/Hardware Cursor.
S1D13506
X25B-G-003-03
Programming Notes and Examples
Issue Date: 01/02/06
Epson Research and Development
Vancouver Design Center
Page 45
REG[086h] CRT/TV Ink/Cursor Blue Color 0 Register
n/a
n/a
n/a
CRT/TV
Ink/Cursor
Blue Color 0
Bit 4
CRT/TV
Ink/Cursor
Blue Color 0
Bit 3
CRT/TV
Ink/Cursor
Blue Color 0
Bit 2
CRT/TV
Ink/Cursor
Blue Color 0
Bit 1
CRT/TV
Ink/Cursor
Blue Color 0
Bit 0
REG[087h] CRT/TV Ink/Cursor Green Color 0 Register
n/a
CRT/TV
CRT/TV
CRT/TV
CRT/TV
CRT/TV
CRT/TV
Ink/Cursor
Ink/Cursor
Ink/Cursor
Ink/Cursor
Ink/Cursor
Ink/Cursor
Green Color 0 Green Color 0 Green Color 0 Green Color 0 Green Color 0 Green Color 0
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
n/a
REG[088h] CRT/TV Ink/Cursor Red Color 0 Register
n/a
n/a
n/a
CRT/TV
Ink/Cursor
Red Color 0
Bit 4
CRT/TV
Ink/Cursor
Red Color 0
Bit 3
CRT/TV
Ink/Cursor
Red Color 0
Bit 2
CRT/TV
Ink/Cursor
Red Color 0
Bit 1
CRT/TV
Ink/Cursor
Red Color 0
Bit 0
These registers form the 16 bpp (5-6-5) RGB values of user-defined color 0 for the CRT/TV
Ink Layer/Hardware Cursor.
REG[08Ah] CRT/TV Ink/Cursor Blue Color 1 Register
n/a
n/a
n/a
CRT/TV
Ink/Cursor
Blue Color 1
Bit 4
CRT/TV
Ink/Cursor
Blue Color 1
Bit 3
CRT/TV
Ink/Cursor
Blue Color 1
Bit 2
CRT/TV
Ink/Cursor
Blue Color 1
Bit 1
CRT/TV
Ink/Cursor
Blue Color 1
Bit 0
REG[08Bh] CRT/TV Ink/Cursor Green Color 1 Register
n/a
CRT/TV
CRT/TV
CRT/TV
CRT/TV
CRT/TV
CRT/TV
Ink/Cursor
Ink/Cursor
Ink/Cursor
Ink/Cursor
Ink/Cursor
Ink/Cursor
Green Color 1 Green Color 1 Green Color 1 Green Color 1 Green Color 1 Green Color 1
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
n/a
REG[08Ch] CRT/TV Ink/Cursor Red Color 1 Register
n/a
n/a
n/a
CRT/TV
Ink/Cursor
Red Color 1
Bit 4
CRT/TV
Ink/Cursor
Red Color 1
Bit 3
CRT/TV
Ink/Cursor
Red Color 1
Bit 2
CRT/TV
Ink/Cursor
Red Color 1
Bit 1
CRT/TV
Ink/Cursor
Red Color 1
Bit 0
These registers form the 16 bpp (5-6-5) RGB values of user-defined color 1 for the CRT/TV
Ink Layer/Hardware Cursor.
Programming Notes and Examples
Issue Date: 01/02/06
S1D13506
X25B-G-003-03
Page 46
Epson Research and Development
Vancouver Design Center
REG[07Eh] LCD Ink/Cursor FIFO High Threshold Register
n/a
n/a
n/a
n/a
LCD
Ink/Cursor
FIFO High
Threshold
Bit 3
LCD
Ink/Cursor
FIFO High
Threshold
Bit 2
LCD
Ink/Cursor
FIFO High
Threshold
Bit 1
LCD
Ink/Cursor
FIFO High
Threshold
Bit 0
CRT/TV
Ink/Cursor
FIFO High
Threshold
Bit 2
CRT/TV
Ink/Cursor
FIFO High
Threshold
Bit 1
CRT/TV
Ink/Cursor
FIFO High
Threshold
Bit 0
REG[08Eh] CRT/TV Ink/Cursor FIFO High Threshold Register
n/a
n/a
n/a
n/a
CRT/TV
Ink/Cursor
FIFO High
Threshold
Bit 3
These registers control the Ink Layer/Hardware Cursor FIFO depth in order to sustain
uninterrupted display fetches.
REG[07Eh] determines the FIFO high threshold for the LCD Hardware Cursor/Ink Layer.
REG[08Eh] determines the FIFO high threshold for the CRT/TV Hardware Cursor/Ink
Layer. When this register is set to 00h, the threshold is automatically set in hardware. For
further information, see the 13506 Hardware Functional Specification, document number
X25B-A-001-xx.
S1D13506
X25B-G-003-03
Programming Notes and Examples
Issue Date: 01/02/06
Epson Research and Development
Vancouver Design Center
Page 47
8.3 Initialization
This section describes the process of initializing the S1D13506 for a Hardware Cursor or
Ink Layer.
8.3.1 Memory Considerations
Both the Hardware Cursor and Ink Layer are positioned in the display buffer by the LCD
Ink/Cursor Start Address register (REG[071h]) and CRT/TV Ink/Cursor Start Address
register (REG[081h]). The Hardware Cursor and Ink Layer should be allocated the highest
possible available memory address. If a Dual Panel Buffer is required, or if another
Hardware Cursor or Ink Layer is required, additional memory must be allocated and
programmed in the appropriate Ink/Cursor Start Address register.
The size of the Dual Panel Buffer is determined by the following.
Dual Panel Buffer Size (in bytes) = (Panel Width x Panel Height) x factor ÷ 16
where:
factor
= 4 for color panel
= 1 for monochrome panel
Note
The dual panel buffer always starts at (Display Memory Size - Dual Panel Buffer Size).
The size of a hardware cursor is always 1024 bytes.
The size of the ink layer in bytes is (display width x display height ÷ 4).
Programming Notes and Examples
Issue Date: 01/02/06
S1D13506
X25B-G-003-03
Page 48
Epson Research and Development
Vancouver Design Center
8.3.2 Examples
Example 5: Initializing the Hardware Cursor
The following example places an LCD Hardware Cursor at the end of a 2M byte display
buffer. SwivelView™ modes require software rotation of the Ink Layer. This can only
occur when a Dual Panel Buffer is not required. Color 0 is set to black, and color 1 is set to
white.
Note
The Hardware Cursor always requires 1024 (400h) bytes.
Table 8-3: LCD Hardware Cursor Initialization Sequence
Register
[070h]
[071h]
[072h]
[073h]
[074h]
[075h]
[076h]
[077h]
[078h]
[07Ah]
[07Bh]
[07Ch]
[07Eh]
S1D13506
X25B-G-003-03
Value
0000 0001
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0001 1111
0011 1111
0001 1111
0000 0000
Notes
Enable LCD hardware cursor
Set cursor start address to Memory Size - 1024
Set LCD Cursor X Position to 0
Set LCD Cursor Y Position to 0
Set Color 0 to black
Set Color 1 to white
Set FIFO High Threshold to default
Programming Notes and Examples
Issue Date: 01/02/06
Epson Research and Development
Vancouver Design Center
Page 49
Example 6: Initializing the Ink Layer
The following example places an Ink Layer at the end of a 2M byte display buffer.
SwivelView™ modes require software rotation of the Ink Layer. Color 0 is set to black, and
color 1 is set to white.
For a system with a 640x480 LCD display, the ink layer size is calculated as follows.
InkLayerSize
= (PanelWidth x PanelHeight) ÷ 4
= (640 x 480) ÷ 4
= 76,800 bytes
The Ink Layer must be allocated in 8K byte blocks. The value of the LCD Ink/Cursor Start
Address register is determined from the following table and calculation.
Table 8-4: Ink Layer Start Address Encoding
Ink/Cursor Start Address Bits [7:0]
Start Address (Bytes)
0
Display Buffer Size - 1024
1 - FFh
Display Buffer Size - (n x 8192)
n
= InkLayerSize ÷ RequiredBlockSize
= 76,800 ÷ 8192
= 9.375
Fractional values cannot be programmed, therefore round up to an address of 10 (0Ah).
This reserves 10 x 8192 = 81,920 bytes for the Ink Layer from the end of display buffer.
Note
Always round up the Ink/Cursor Start Address when calculating, otherwise insufficient
memory will be allocated for the Ink Layer.
Table 8-5: LCD Ink Layer Initialization Sequence
Register
[070h]
[071h]
[076h]
[077h]
[078h]
[07Ah]
[07Bh]
[07Ch]
[07Eh]
Programming Notes and Examples
Issue Date: 01/02/06
Value
0000 0010
0000 1010
0000 0000
0000 0000
0000 0000
0001 1111
0011 1111
0001 1111
0000 0000
Notes
Enable LCD ink layer
Set cursor start address to 0Ah (Memory Size - (8192 x 10))
Set Color 0 to black
Set Color 1 to white
Set FIFO High Threshold to default
S1D13506
X25B-G-003-03
Page 50
Epson Research and Development
Vancouver Design Center
8.4 Writing Cursor/Ink Layer Images
This section describes how to write images to the Hardware Cursor and Ink Layer. The
Hardware Cursor is a 64x64 image at a color depth of 2 bpp. The Ink Layer is the same size
as the virtual display (width x height) at a color depth of 2 bpp. The Ink Layer may be
described as a non-moveable cursor with the same resolution as the display device.
8.4.1 Hardware Cursor/Ink Layer Data Format
The Hardware Cursor/Ink Layer image is fixed at a color depth of 2 bpp. The following
diagram shows the Hardware Cursor/Ink Layer data format for a little endian system.
2 bpp:
bit 7
bit 0
Byte 0
A0
B0
A1
B1
A2
B2
A3
B3
Byte 1
A4
B4
A5
B5
A6
B6
A7
B7
P0 P1 P2 P3 P4 P5 P6 P7
Pn = (An, Bn)
Panel Display
Host Address
Hardware Cursor/Ink Layer Buffer
Figure 8-1: Hardware Cursor/Ink Layer Data Format
The image data for pixel n, (An,Bn), selects the color for pixel n as follows:
Table 8-6: Ink/Cursor Color Select
(An,Bn)
Color
00
Color 0
Ink/Cursor Color 0 Register:
For LCD, REG[076h], REG[077h], REG[078h].
For CRT/TV, REG[086h], REG[087h], REG[088h].
01
Color 1
Ink/Cursor Color 1 Register:
For LCD, REG[07Ah], REG[07Bh],REG[07Ch].
For CRT/TV, REG[08Ah], REG[08Bh], REG[08Ch].
10
Background
11
Inverted Background
S1D13506
X25B-G-003-03
Comments
Ink/Cursor is transparent – show background
Ink/Cursor is transparent – show inverted background
Programming Notes and Examples
Issue Date: 01/02/06
Epson Research and Development
Vancouver Design Center
8.4.2
Page 51
Cursor Image
The following procedures demonstrate how to write an image to the Hardware Cursor
buffer.
Landscape Mode (no rotation)
1. For the LCD cursor, calculate the start address based on the value in REG[071h].
For the CRT/TV cursor, calculate the start address based on the value in REG[081h].
Refer to the REG[071h] and REG[081h] register descriptions for more information.
2. Write the cursor image to the display buffer. The image must be exactly 1024 bytes.
SwivelView Modes
1. Save the current state of REG[1FCh] bit 6.
2. Set REG[1FCh] bit 6 to 0.
3. For the LCD cursor, calculate the start address based on the value in REG[071h].
For the CRT/TV cursor, calculate the start address based on the value in REG[081h].
Refer to the REG[071h] and REG[081h] register descriptions for more information.
4. Perform a software rotate of the cursor image.
5. Write the rotated cursor image to the display buffer. The image must be exactly 1024
bytes.
6. Restore the original state of REG[1FCh] bit 6.
Note
It is possible to use the same cursor image for both LCD and CRT/TV displays. Program
the LCD and CRT/TV Ink/Cursor Start Address registers (REG[071h] and REG[081h])
to the same location. This saves some display buffer which would otherwise be used by
a second cursor image. Note this saves 8192 bytes of display buffer, not 1024 bytes,
because the start address moves in steps of 8192 bytes.
Programming Notes and Examples
Issue Date: 01/02/06
S1D13506
X25B-G-003-03
Page 52
Epson Research and Development
Vancouver Design Center
8.4.3 Ink Layer Image
The following procedures demonstrate how to write an image to the Ink Layer buffer.
Landscape Mode (no rotation)
1. For the LCD, calculate the start address based on the value in REG[071h].
For the CRT/TV, calculate the start address based on the value in REG[081h].
Refer to the REG[071h] and REG[081h] register descriptions for more information.
2. Write the Ink Layer image to the display buffer. The image must be exactly (display
width x display height ÷ 4) bytes.
SwivelView Modes
1. Save the current state of REG[1FCh] bit 6.
2. Set REG[1FCh] bit 6 to 0.
3. For the LCD, calculate the start address based on the value in REG[071h].
For the CRT/TV, calculate the start address based on the value in REG[081h].
Refer to the REG[071h] and REG[081h] register descriptions for more information.
4. Perform a software rotate of the Ink Layer image.
5. Write the rotated Ink Layer image to the display buffer. The image must be exactly
(display width x display height ÷ 4) bytes.
6. Restore the original state of REG[1FCh] bit 6.
Note
It is possible to use the same Ink Layer image for both LCD and CRT/TV displays. Program the LCD and CRT/TV Ink/Cursor Start Address registers (REG[071h] and
REG[081h]) to the same location. This save some display buffer which would otherwise
be used by a second Ink Layer.
S1D13506
X25B-G-003-03
Programming Notes and Examples
Issue Date: 01/02/06
Epson Research and Development
Vancouver Design Center
Page 53
8.5 Cursor Movement
The following section discusses cursor movement in landscape, SwivelView 90°,
SwivelView 180°, and SwivelView 270° modes.
It is possible to move the top left corner of the cursor to a negative position (-63, -63). This
allows the cursor to be clipped (only a portion is visible on-screen).
Cursor positions don’t take effect until the most significant byte of the Y position register
is written. Therefore, the following register write order is recommended.
1. Set X Position Register 0
2. Set X Position Register 1
3. Set Y Position Register 0
4. Set Y Position Register 1.
8.5.1 Move Cursor in Landscape Mode (no rotation)
In the following example, (x, y) represents the desired cursor position.
1. Calculate abs(x), the absolute (non-negative) value of x.
2. Write the least significant byte of abs(x) to X Position Register 0.
3. If x is negative, take the value of the most significant byte of abs(x) and logically OR
with 80h. Write the result to X Position Register 1.
If x is positive, write the most significant byte of abs(x) to X Position Register 1.
4. Calculate abs(y), the absolute (non-negative) value of y.
5. Write the least significant byte of abs(y) to Y Position Register 0.
6. If y is negative, take the value of the most significant byte of abs(y) and logically OR
with 80h. Write the result to Y Position Register 1.
If y is positive, take the value of the most significant byte of abs(y) and write to Y Position Register 1.
Programming Notes and Examples
Issue Date: 01/02/06
S1D13506
X25B-G-003-03
Page 54
Epson Research and Development
Vancouver Design Center
8.5.2 Move Cursor in SwivelView 90° Rotation
In the following example, (x, y) represent the desired cursor position.
1. Calculate abs(x), the absolute (non-negative) value of x.
2. Write the least significant byte of abs(x) to Y Position Register 0.
3. If x is negative, take the value of the most significant byte of abs(x) and logically OR
with 80h. Write the result to Y Position Register 1.
If x is positive, write the most significant byte of abs(x) to Y Position Register 1.
4. Calculate a value for y2,
where y2 = display width - y - 64.
5. Calculate abs(y2), the absolute (non-negative) value of y2.
6. Write the least significant byte of abs(y2) to X Position Register 0.
7. If y2 is negative, take the value of the most significant byte of abs(y2) and logically
OR with 80h. Write the result to X Position Register 1.
If y2 is positive, write the most significant byte of abs(y2) to X Position Register 1.
8.5.3 Move Cursor in SwivelView 180° Rotation
In the following example, (x, y) represent the desired cursor position.
1. Calculate the value of x2,
where x2 = display width - x - 64
2. Calculate abs(x2), the absolute (non-negative) value of x2.
3. Write the least significant byte of abs(x2) to X Position Register0.
4. If x2 is negative, take the value of the most significant byte of abs(x2) and logically
OR with 80h. Write the result to X Position Register 1.
If x2 is positive, write the most significant byte of abs(x2) to X Position Register 1.
5. Calculate the value of y2,
where y2 = display height - y - 64
6. Calculate abs(y2), the absolute (non-negative) value of y2.
7. Write the least significant byte of abs(y2) to Y Position Register 0.
8. If y2 is negative, take the value of the most significant byte of abs(y2) and logically
OR with 80h. Write the result to Y Position Register 1.
If y2 is positive, write the most significant byte of abs(y2) to Y Position Register 1.
S1D13506
X25B-G-003-03
Programming Notes and Examples
Issue Date: 01/02/06
Epson Research and Development
Vancouver Design Center
Page 55
8.5.4 Move Cursor in SwivelView 270° Rotation
In the following example, (x, y) represent the desired cursor position.
1. Calculate the value of x2,
where x2 = display width - x - 64
2. Calculate abs(x2), the absolute (non-negative) value of x2.
3. Write the least significant byte of abs(x2) to Y Position Register 0.
4. If x2 is negative, take the value of the most significant byte of abs(x2) and logically
OR with 80h. Write the result to Y Position Register 1.
If x2 is positive, write the most significant byte of abs(x2) to Y Position Register 1.
5. Calculate abs(y), the absolute (non-negative) value of y.
6. Write the least significant byte of abs(y) to X Position Register 0.
7. If y is negative, take the value of the most significant byte of abs(y) and logically OR
with 80h. Write the result to X Position Register 1.
If y is positive, write the most significant byte of abs(y) to X Position Register 1.
Programming Notes and Examples
Issue Date: 01/02/06
S1D13506
X25B-G-003-03
Page 56
Epson Research and Development
Vancouver Design Center
9 SwivelView™
Most computer displays operate in landscape mode. In landscape mode the display is wider
than it is high. For example, a standard display size of 640x480 is 640 pixels wide and 480
pixels wide.
SwivelView rotates the display image clockwise in ninety degree increments, possibly
resulting in a display that is higher than it is wide. Rotating the image on a 640x480 display
by 90 or 270 degrees yields a display that is now 480 pixels wide and 640 pixels high.
SwivelView also works with panels that are designed with a "portrait" orientation. In this
case, when SwivelView 0° is selected, the panel will be in a “portrait” orientation. A
selection of SwivelView 90° or SwivelView 270° rotates to a landscape orientation.
9.1 S1D13506 SwivelView
The S1D13506 provides hardware support for SwivelView in 8, 15 and 16 bpp color depths
on LCD panels. SwivelView is not supported on CRT or TV displays.
Certain conditions must be considered when SwivelView is enabled.
• The virtual display offset (scan line) must be set to 1024 pixels (1024 bytes in 8 bpp,
2048 bytes in 15/16 bpp) when SwivelView Enable Bit 0 is set to 1.
• The display start address is calculated differently when SwivelView is enabled.
• Calculations that would result in panning in landscape mode, may result in scrolling
when SwivelView is enabled and vice-versa.
9.2 Registers
REG[01FCh] Display Mode Register
n/a
SwivelView
Enable Bit 0
n/a
n/a
n/a
Display Mode Display Mode Display Mode
Select Bit 2
Select Bit 1
Select Bit 0
SwivelView
Enable Bit 1
n/a
Bit-Per-Pixel
Select Bit 2
REG[040h] LCD Display Mode Register
LCD Display
Blank
n/a
n/a
Bit-Per-Pixel
Select Bit 1
Bit-Per-Pixel
Select Bit 0
The SwivelView modes are enabled using a combination of 2 enable bits - SwivelView
Enable Bit 0 (REG[1FCh]) and SwivelView Enable Bit 1 (REG[040h]). The combinations
of these bits provide the following rotations.
S1D13506
X25B-G-003-03
Programming Notes and Examples
Issue Date: 01/02/06
Epson Research and Development
Vancouver Design Center
Page 57
Table 9-1: SwivelView Enable Bits
SwivelView Enable SwivelView Enable
Bit 1
Bit 0
0
0
0
1
1
0
1
1
Display Rotated
(degrees)
0
90
180
270
REG[046h] LCD Memory Address Offset Register 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
n/a
Bit 10
Bit 9
Bit 8
REG[047h] LCD Memory Address Offset Register 1
n/a
n/a
n/a
n/a
The LCD Memory Address Offset Registers must be adjusted according to the desired
SwivelView rotation and color depth. Set the LCD Memory Address Offset Registers based
on the values provided for each color depth in the following table. Panel Width (PW) is the
horizontal panel size in pixels (i.e. for a 640x480 panel, PW is 640 regardless of the display
rotation).
Table 9-2: LCD Memory Address Offset Values
SwivelView Enable
Bit 1
Bit 0
0
0
0
1
1
0
1
1
Programming Notes and Examples
Issue Date: 01/02/06
Display Rotated
0 degrees
90 degrees
180 degrees
270 degrees
Memory Address Offset Value
15/16 bpp
8 bpp
PW
PW ÷ 2
1024
512
PW
PW ÷ 2
1024
512
S1D13506
X25B-G-003-03
Page 58
Epson Research and Development
Vancouver Design Center
REG[042h] LCD Display Start Address Register 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 11
Bit 10
Bit 9
Bit 8
Bit 19
Bit 18
Bit 17
Bit 16
REG[043h] LCD Display Start Address Register 1
Bit 15
Bit 14
Bit 13
Bit 12
REG[044h] LCD Display Start Address Register 2
n/a
n/a
n/a
n/a
The LCD Display Start Address Registers must be adjusted according to the desired
SwivelView rotation and color depth. Set the LCD Display Start Address Registers based
on the values provided for each color depth in the following table. Panel Width (PW) is the
horizontal panel size in pixels. Panel Height (PH) is the vertical panel size in lines (i.e. for
a 640x480 panel, PW is 640 and PH is 480 regardless of display rotation). Stride is the
based on the previously calculated memory offset in bytes (Stride = MemoryOffset × 2).
Table 9-3: LCD Display Start Address Values
SwivelView Enable
Bit 1
Bit 0
0
0
0
1
1
0
1
1
Display Rotated
0 degrees
90 degrees
180 degrees
270 degrees
(Stride ×
LCD Display Start Address Value
15/16 Bpp mode
8 Bpp mode
0
0
(1024 - PW)
(1024 - PW) ÷ 2
PH - (Stride - 2 × PW)) ÷ 2 - 1 (Stride × PH - (Stride - PW)) ÷ 2 - 1
(Stride × PH) ÷ 2 - 1
(Stride × PH) ÷ 2 - 1
9.3 Limitations
The following limitations apply when SwivelView bit 0 is set to 1 (rotation by 90° or 270°):
• Only 8/15/16 bpp modes can be rotated 90 or 270 degrees.
• Hardware Cursor and Ink Layer images are not rotated - software rotation must be used.
SwivelView must be turned off when the programmer is accessing the Hardware Cursor
or the Ink Layer. The blit engine ignores the SwivelView bits also.
• Pixel panning works vertically.
• It is not possible to rotate an already displayed image. The image must be redrawn.
Note
Drawing into the Hardware Cursor/Ink Layer with SwivelView enabled requires disabling SwivelView, drawing in the Hardware Cursor/Ink Layer buffer, then re-enabling
SwivelView.
S1D13506
X25B-G-003-03
Programming Notes and Examples
Issue Date: 01/02/06
Epson Research and Development
Vancouver Design Center
Page 59
9.4 Examples
Source code demonstrating various SwivelView rotations is provided in the file
13506swivel.c available on the internet at www.eea.epson.com.
Example 7: Rotate Image 90° for a 640x480 display at a color depth of 8 bpp.
Before enabling SwivelView, the display buffer should be cleared. This makes the
transition smoother as existing display images cannot be rotated by hardware - a repaint is
necessary.
1. Set the line offset to 1024 pixels. The Memory Offset register is the offset in words.
Write 02h to REG[047h] and write 00h to REG[046h].
2. Set the LCD Display Start Address. The Display Start Address registers form a pointer to a word, therefore the value to set the start.
Write C0h (192 or (1024 - 480)÷2) to REG[042h], REG[043h] and REG[044h]. That
is write C0h) to REG[042h], 00h to REG[043h] and 00h to REG[044h].
3. Enable SwivelView Bit 0 and clear SwivelView Bit 1. Set REG[1FCh] to 1 and
REG[040h] to 0.
4. The display is now configured for SwivelView 90° mode. Offset zero into the display
buffer corresponds to the upper left corner of the display. The only difference seen by
the programmer is the display offset is now 1024 pixels regardless of the physical
dimensions of the display.
5. Draw the desired image.
Example 8: Rotate Image 180 degrees for a 640x480 display at a color depth of 16
bpp.
Assuming the existing image is unrotated, the display buffer does not have to be cleared.
Existing display images are simply be rotated by hardware. In this case a repaint is not
necessary.
1. The Memory Offset register does not need to be modified.
2. Set the LCD Display Start Address. The Display Start Address registers form a pointer to a word, therefore the value to set the start. Calculate the value based on the following formula.
StartAddress = (ScanBytes × PanelHeight - (ScanBytes - 2 × PanelWidth)) ÷ 2 - 1
= (1280 × 480 - (1280 -2 × 640)) ÷ 2 - 1
= (1280 × 480) ÷ 2 - 1
= 307199
= 4AFFFh
Programming Notes and Examples
Issue Date: 01/02/06
S1D13506
X25B-G-003-03
Page 60
Epson Research and Development
Vancouver Design Center
Program the LCD Display Start Address Registers. REG[044h] is set to 04h,
REG[043h] is set to AFh, and REG[042h] is set to FFh.
3. Set SwivelView Bit 1 by setting bit 4 of REG[040h]
4. The display will now show the previous image rotated by 180 degrees. Offset zero
into display memory will correspond to the lower right corner of the display.
5. Draw any new desired image. The drawing software can be completely unaware of the
display being rotated.
9.5 Simultaneous Display Considerations
Although only the LCD panel image can be rotated, it is possible to simultaneously display
an independent image on the CRT or TV display. In this case, the programmer should be
aware of the following:
• As the LCD display buffer must start at offset 0 when a rotated display is required, the
CRT display buffer must be located after the LCD display buffer.
• When modifying the CRT display buffer, SwivelView Enable Bit 0 must be cleared and
then restored when finished. The following demonstrates this principle.
1. Save SwivelView Bit 0
2. Clear SwivelView Bit 0
3. Draw the CRT/TV image
4. Restore the saved SwivelView Bit 0.
S1D13506
X25B-G-003-03
Programming Notes and Examples
Issue Date: 01/02/06
Epson Research and Development
Vancouver Design Center
Page 61
10 2D BitBLT Engine
The term BitBLT is an acronym for Bit Block Transfer. During a BitBLT operation data is
transferred from one memory location (source) to another memory location (destination).
With current graphical user interfaces (GUIs) this term generally refers to the transfer of
bitmap images to or from video memory (display buffer).
The resulting bitmap image may be derived from up to three items or operands:
• the source data.
• an optional pattern.
• the current destination data.
The operands are combined using logical AND, OR, XOR and NOT operations. The
combining process is called a Raster Operation (ROP). The S1D13506 2D Accelerator
supports all possible 16 ROPs between source data and destination data. The destination is
always the display buffer and the source is either data in the display buffer, a pattern in the
display buffer, or data provided by the host CPU.
The 2D BitBLT Engine in the S1D13506 is designed to increase the speed of the most
common GUI operations by off-loading work from the CPU, thus reducing traffic on the
system bus and improving the efficiency of the display buffer interface. The 2D BitBLT
Engine is designed to work at color depths of 8 bpp, 15 bpp, and 16 bpp.
10.1 Registers
The BitBLT control registers on the S1D13506 are located at registers 100h through 119h.
The following is a description of all BitBLT registers.
REG[100h] BitBLT Control Register 0
BitBLT Active
Status
BitBLT FIFO
Not Empty
Status (RO)
BitBLT FIFO
Half Full
Status (RO)
BitBLT FIFO
Full Status
(RO)
n/a
n/a
BitBLT
BitBLT
Destination Source Linear
Linear Select
Select
The BitBLT Active Status bit has two data paths, one for write and one for read.
Write Data Path
When this bit is set to 1, the BitBLT as selected in the BitBLT Operation Register
(REG[103h]) is started.
Read Data Path
When this bit is read, it returns the status of the blit engine. When a read from this bit returns
0, the blit engine is idle and is ready for the next operation. When a read from this bit returns
a 1, the blit engine is busy.
Programming Notes and Examples
Issue Date: 01/02/06
S1D13506
X25B-G-003-03
Page 62
Epson Research and Development
Vancouver Design Center
REG[100h] BitBLT Control Register 0
BitBLT Active
Status
BitBLT FIFO
Not Empty
Status (RO)
BitBLT FIFO
Half Full
Status (RO)
BitBLT FIFO
Full Status
(RO)
n/a
n/a
BitBLT
BitBLT
Destination Source Linear
Linear Select
Select
The BitBLT FIFO Not Empty Status bit is a read-only status bit. When this bit returns a 0,
the BitBLT FIFO is empty. When this bit returns a 1, the BitBLT FIFO contains at least one
data.
REG[100h] BitBLT Control Register 0
BitBLT Active
Status
BitBLT FIFO
Not Empty
Status (RO)
BitBLT FIFO
Half Full
Status (RO)
BitBLT FIFO
Full Status
(RO)
n/a
n/a
BitBLT
BitBLT
Destination Source Linear
Linear Select
Select
The BitBLT FIFO Half Full Status bit is a read-only status bit. When this bit returns a 0,
the BitBLT FIFO is less than half full (contains 7 or less data). When this bit returns a 1,
the BitBLT FIFO is half full or greater than half full (contains 8 or more data).
REG[100h] BitBLT Control Register 0
BitBLT Active
Status
BitBLT FIFO
Not Empty
Status (RO)
BitBLT FIFO
Half Full
Status (RO)
BitBLT FIFO
Full Status
(RO)
n/a
n/a
BitBLT
BitBLT
Destination Source Linear
Linear Select
Select
The BitBLT FIFO Full Status bit is a read-only status bit. When this bit returns a 0, the
BitBLT FIFO is not full (contains less than 16 data). When this bit returns a 1, the BitBLT
FIFO is full (contains 16 data).
REG[100h] BitBLT Control Register 0
BitBLT Active
Status
BitBLT FIFO
Not Empty
Status (RO)
BitBLT FIFO
Half Full
Status (RO)
BitBLT FIFO
Full Status
(RO)
n/a
n/a
BitBLT
BitBLT
Destination Source Linear
Linear Select
Select
The BitBLT Destination Linear Select bit specifies the storage method of the destination
blit. If this bit = 0, the destination blit is stored as a rectangular region of memory. If this
bit = 1, the destination blit is stored as a contiguous linear block of memory.
REG[100h] BitBLT Control Register 0
BitBLT Active
Status
BitBLT FIFO
Not Empty
Status (RO)
BitBLT FIFO
Half Full
Status (RO)
BitBLT FIFO
Full Status
(RO)
n/a
n/a
BitBLT
BitBLT
Destination Source Linear
Select
Linear Select
The BitBLT Source Linear Select bit specifies the storage method of the source blit. If this
bit = 0, the source blit is stored as a rectangular region of memory. If this bit = 1, the source
blit is stored as a contiguous linear block of memory.
S1D13506
X25B-G-003-03
Programming Notes and Examples
Issue Date: 01/02/06
Epson Research and Development
Vancouver Design Center
Page 63
REG[101h] BitBLT Control Register 1
n/a
n/a
n/a
Reserved
n/a
n/a
n/a
BitBLT Color
Format Select
n/a
n/a
BitBLT Color
Format Select
This bit is reserved and must be set to 0.
REG[101h] BitBLT Control Register 1
n/a
n/a
n/a
Reserved
n/a
The BitBLT Color Format Select bit selects the color format that the BitBLT operation is
applied to. When this bit = 0, 8 bpp (256 color) format is selected. When this bit = 1, 16 bpp
(64K color) format is selected.
REG[102h] BitBLT ROP Code/Color Expansion Register
n/a
n/a
n/a
n/a
BitBLT ROP
Code
Bit 3
BitBLT ROP
Code
Bit 2
BitBLT ROP
Code
Bit 1
BitBLT ROP
Code
Bit 0
The BitBLT ROP Code/Color Expansion Register selects the Raster Operation (ROP) used
for the Write blit, Move blit, and Pattern fill. It is also used to specify the start bit position
for BitBLTs with color expansion. The following table summarizes the functionality of this
register.
Table 10-1: BitBLT ROP Code/Color Expansion Function Selection
BitBLT ROP Code
Bits [3:0]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Boolean Function for Write
Blit and Move Blit
0 (Blackness)
~S . ~D or ~(S + D)
~S . D
~S
S . ~D
~D
S^D
~S + ~D or ~(S . D)
S.D
~(S ^ D)
D
~S + D
S
S + ~D
S+D
1 (Whiteness)
Boolean Function for
Pattern Fill
0 (Blackness)
~P . ~D or ~(P + D)
~P . D
~P
P . ~D
~D
P^D
~P + ~D or ~(P . D)
P.D
~(P ^ D)
D
~P + D
P
P + ~D
P+D
1 (Whiteness)
Start Bit Position for Color
Expansion
bit 0
bit 1
bit 2
bit 3
bit 4
bit 5
bit 6
bit 7
bit 0
bit 1
bit 2
bit 3
bit 4
bit 5
bit 6
bit 7
S = Source, D = Destination, P = Pattern
Operators: ~ = NOT, . = Logical AND, + = Logical OR, ^ = Logical XOR
Programming Notes and Examples
Issue Date: 01/02/06
S1D13506
X25B-G-003-03
Page 64
Epson Research and Development
Vancouver Design Center
REG[103h] BitBLT Operation Register
n/a
n/a
n/a
BitBLT
Operation
Bit 3
n/a
BitBLT
Operation
Bit 2
BitBLT
Operation
Bit 1
BitBLT
Operation
Bit 0
The BitBLT Operation Register selects the BitBLT operation to be carried out based on the
following table:
Table 10-2: BitBLT Operation Selection
BitBLT Operation Bits [3:0]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
Other combinations
Blit Operation
Write Blit with ROP
Read Blit
Move Blit in positive direction with ROP
Move Blit in negative direction with ROP
Transparent Write Blit
Transparent Move Blit in positive direction
Pattern Fill with ROP
Pattern Fill with transparency
Color Expansion
Color Expansion with transparency
Move Blit with Color Expansion
Move Blit with Color Expansion and transparency
Solid Fill
Reserved
REG[104h] BitBLT Source Start Address Register 0
BitBLT
Source Start
Address
Bit 7
BitBLT
Source Start
Address
Bit 6
BitBLT
Source Start
Address
Bit 5
BitBLT
Source Start
Address
Bit 4
BitBLT
Source Start
Address
Bit 3
BitBLT
Source Start
Address
Bit 2
BitBLT
Source Start
Address
Bit 1
BitBLT
Source Start
Address
Bit 0
BitBLT
Source Start
Address
Bit 11
BitBLT
Source Start
Address
Bit 10
BitBLT
Source Start
Address
Bit 9
BitBLT
Source Start
Address
Bit 8
BitBLT
Source Start
Address
Bit 19
BitBLT
Source Start
Bit 18
BitBLT
Source Start
Address Bit
17
BitBLT
Source Start
Address
Bit 16
REG[105h] BitBLT Source Start Address Register 1
BitBLT
Source Start
Address
Bit 15
BitBLT
Source Start
Address
Bit 14
BitBLT
Source Start
Address
Bit 13
BitBLT
Source Start
Address
Bit 12
REG[106h] BitBLT Source Start Address Register 2
n/a
n/a
n/a
BitBLT
Source Start
Address
Bit 20
The BitBLT Source Start Address Registers form a 21-bit register that specifies the source
start address for the BitBLT operation selected by the BitBLT Operation Register
(REG[103h]).
S1D13506
X25B-G-003-03
Programming Notes and Examples
Issue Date: 01/02/06
Epson Research and Development
Vancouver Design Center
Page 65
If data is sourced from the CPU, then bit 0 is used for byte alignment within a 16-bit word
and the other address bits are ignored. In pattern fill operation, the BitBLT Source Start
Address is defined by the following equation:
Source Start Address Register = Pattern Base Address + Pattern Line Offset + Pixel Offset.
The following table shows how Source Start Address Register is defined for 8 and 16 bpp
color depths:
Table 10-3: BitBLT Source Start Address Selection
Color Format
8 bpp
16 bpp
Pattern Base Address[20:0]
BitBLT Source Start Address[20:6],
6’b0
BitBLT Source Start Address[20:7],
7’b0
Pattern Line Offset[2:0]
BitBLT Source Start
Address[5:3]
BitBLT Source Start
Address[6:4]
Pixel Offset[3:0]
1’b0, BitBLT Source Start
Address[2:0]
BitBLT Source Start
Address[3:0]
REG[108h] BitBLT Destination Start Address Register 0
BitBLT
BitBLT
BitBLT
BitBLT
BitBLT
BitBLT
BitBLT
BitBLT
Destination
Destination
Destination
Destination
Destination
Destination
Destination
Destination
Start Address Start Address Start Address Start Address Start Address Start Address Start Address Start Address
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
REG[109h] BitBLT Destination Start Address Register 1
BitBLT
BitBLT
BitBLT
BitBLT
BitBLT
BitBLT
BitBLT
BitBLT
Destination
Destination
Destination
Destination
Destination
Destination
Destination
Destination
Start Address Start Address Start Address Start Address Start Address Start Address Start Address Start Address
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
REG[10Ah] BitBLT Destination Start Address Register 2
n/a
n/a
n/a
BitBLT
BitBLT
BitBLT
BitBLT
BitBLT
Destination
Destination
Destination
Destination
Destination
Start Address Start Address Start Address Start Address Start Address
Bit 20
Bit 19
Bit 18
Bit 17
Bit 16
The BitBLT Destination Start Address Registers form a 21-bit register that specifies the
destination start address for the BitBLT operation selected by the BitBLT Operation
Register (REG[103h]). The destination address represents the upper left corner of the
BitBLT rectangle (lower right corner of the BitBLT rectangle for Move Blit in Negative
Direction).
Programming Notes and Examples
Issue Date: 01/02/06
S1D13506
X25B-G-003-03
Page 66
Epson Research and Development
Vancouver Design Center
REG[10Ch] BitBLT Memory Address Offset Register 0
BitBLT
Memory
Address
Offset Bit 7
BitBLT
Memory
Address
Offset Bit 6
BitBLT
Memory
Address
Offset Bit 5
BitBLT
Memory
Address
Offset Bit 4
BitBLT
Memory
Address
Offset Bit 3
BitBLT
Memory
Address
Offset Bit 2
BitBLT
Memory
Address
Offset Bit 1
BitBLT
Memory
Address
Offset Bit 0
n/a
BitBLT
Memory
Address
Offset Bit 10
BitBLT
Memory
Address
Offset Bit 9
BitBLT
Memory
Address
Offset Bit 8
REG[10Dh] BitBLT Memory Address Offset Register 1
n/a
n/a
n/a
n/a
The BitBLT Memory Address Offset Registers form the BitBLTs 11-bit address offset
from the starting word of line “n” to the starting word of line “n + 1”. They are used for
address calculation only when the BitBLT is configured as a rectangular region of memory
using the BitBLT Destination/Source Linear Select bits (REG[100h] bits 1-0). They are not
used for the displays.
REG[110h] BitBLT Width Register 0
BitBLT Width
Bit 7
BitBLT Width
Bit 6
BitBLT Width
Bit 5
BitBLT Width
Bit 4
BitBLT Width
Bit 3
BitBLT Width
Bit 2
BitBLT Width
Bit 1
BitBLT Width
Bit 0
n/a
n/a
n/a
BitBLT Width
Bit 9
BitBLT Width
Bit 8
REG[111h] BitBLT Width Register 1
n/a
n/a
n/a
The BitBLT Width Registers form a 10-bit register that specifies the BitBLT width in
pixels less 1.
Note
The BitBLT operations Pattern Fill with ROP and Pattern Fill with transparency require
a BitBLT Width ≥ 2.
REG[112h] BitBLT Height Register 0
BitBLT Height BitBLT Height BitBLT Height BitBLT Height BitBLT Height BitBLT Height BitBLT Height BitBLT Height
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
REG[113h] BitBLT Height Register 1
n/a
n/a
n/a
n/a
n/a
n/a
BitBLT Height BitBLT Height
Bit 9
Bit 8
The BitBLT Height Registers form a 10-bit register that specifies the BitBLT height in
pixels less 1.
S1D13506
X25B-G-003-03
Programming Notes and Examples
Issue Date: 01/02/06
Epson Research and Development
Vancouver Design Center
Page 67
REG[114h] BitBLT Background Color Register 0
BitBLT
Background
Color
Bit 7
BitBLT
Background
Color
Bit 6
BitBLT
Background
Color
Bit 5
BitBLT
Background
Color
Bit 4
BitBLT
Background
Color
Bit 3
BitBLT
Background
Color
Bit 2
BitBLT
Background
Color
Bit 1
BitBLT
Background
Color
Bit 0
BitBLT
Background
Color
Bit 11
BitBLT
Background
Color
Bit 10
BitBLT
Background
Color
Bit 9
BitBLT
Background
Color
Bit 8
REG[115h] BitBLT Background Color Register 1
BitBLT
Background
Color
Bit 15
BitBLT
Background
Color
Bit 14
BitBLT
Background
Color
Bit 13
BitBLT
Background
Color
Bit 12
The BitBLT Background Color Registers form a 16-bit register that specifies the BitBLT
background color for Color Expansion or the key color for transparent blits. For 16 bpp
color depth (REG[101h] bit 0 = 1), all 16 bits are used. For 8 bpp color depth (REG[101h]
bit 0 = 0), only bits 7-0 are used.
REG[118h] BitBLT Foreground Color Register 0
BitBLT
Foreground
Color
Bit 7
BitBLT
Foreground
Color
Bit 6
BitBLT
Foreground
Color
Bit 5
BitBLT
Foreground
Color
Bit 4
BitBLT
Foreground
Color
Bit 3
BitBLT
Foreground
Color
Bit 2
BitBLT
Foreground
Color
Bit 1
BitBLT
Foreground
Color
Bit 0
BitBLT
Foreground
Color
Bit 11
BitBLT
Foreground
Color
Bit 10
BitBLT
Foreground
Color
Bit 9
BitBLT
Foreground
Color
Bit 8
REG[119h] BitBLT Foreground Color Register 1
BitBLT
Foreground
Color
Bit 15
BitBLT
Foreground
Color
Bit 14
BitBLT
Foreground
Color
Bit 13
BitBLT
Foreground
Color
Bit 12
The BitBLT Foreground Color Registers form a 16-bit register that specifies the BitBLT
foreground color for Color Expansion or the Solid Fill BitBLT. For 16 bpp color depth
(REG[101h] bit 0 = 1), all 16 bits are used. For 8 bpp color depth (REG[101h] bit 0 = 0),
only bits 7-0 are used.
Programming Notes and Examples
Issue Date: 01/02/06
S1D13506
X25B-G-003-03
Page 68
Epson Research and Development
Vancouver Design Center
10.2 BitBLT Descriptions
The S1D13506 supports 13 fundamental BitBLT operations:
• Write Blit with ROP.
• Read Blit.
• Move Blit in positive direction with ROP.
• Move Blit in negative direction with ROP.
• Transparent Write Blit.
• Transparent Move Blit in positive direction.
• Pattern Fill with ROP.
• Pattern Fill with Transparency.
• Color Expansion.
• Color Expansion with Transparency.
• Move Blit with Color Expansion.
• Move Blit with Color Expansion and Transparency.
• Solid Fill.
Most of the 13 operations are self completing. This means once they begin they complete
on their own, not requiring data transfers with the CPU. The remaining five BitBLT operations (Write Blit with ROP, Transparent Write Blit, Color Expansion, Color Expansion
with Transparency, Read Blit) require data to be written/read to/from the display buffer.
This data must be transferred one word (16-bits) at a time. This does not imply only 16-bit
CPU instructions are acceptable. If a system is able to separate one DWORD write into two
WORD writes, then 32-bit CPU instructions are acceptable. Otherwise, two back to back
16-bit CPU instructions are required.
The data is not directly written/read to/from the display buffer. It is written/read to/from the
BitBLT FIFO through the 1M blit aperture specified at the address of REG[100000h]. The
16 word FIFO can be written to only when not full and can be read from only when not
empty. Failing to monitor the FIFO status can result in a BitBLT FIFO overflow or
underflow.
While the FIFO is being written to by the CPU, it is also being emptied by the S1D13506.
If the S1D13506 empties the FIFO faster than the CPU can fill it, it may not be possible to
cause an overflow/underflow. In these cases, performance can be improved by not
monitoring the FIFO status. However, this is very much platform dependent and must be
determined for each system.
Note
When TV with flicker filter is enabled or simultaneous display is active, always test the
FIFO status before reading from/writing to the FIFO.
S1D13506
X25B-G-003-03
Programming Notes and Examples
Issue Date: 01/02/06
Epson Research and Development
Vancouver Design Center
Page 69
10.2.1 Write Blit with ROP
The Write Blit increases the speed of transferring data from system memory to the display
buffer.
The Write Blit with ROP fills a specified area of the display buffer with data supplied by
the CPU. This blit is typically used to copy a bitmap image from system memory to the
display buffer. The Write Blit supports all 16 ROPs, although the most frequent ROP is
ROP 0Ch (Copy Source into Destination). It also supports both Destination Linear and
Destination Rectangular modes.
The Write Blit requires the CPU to provide data. The blit engine expects to receive a certain
number of WORDS. For 15/16 bpp color depths, the number of WORDS is the same as the
number of pixels due to the fact that each pixel is one WORD wide. The number of WORD
writes the blit engine expects is calculated using the following formula.
nWORDS
= nPixels
= BlitWidth × BlitHeight
For 8 bpp color depths, the formula must take into consideration that the blit engine accepts
only WORD accesses and each pixel is one BYTE. The blit engine needs to know whether
the first pixel of a line is stored in the low byte or high byte. This is determined by bit 0 of
the Source Start Address Register 0 (REG[104h]). If the Source Phase is 1 (bit 0 of the
Source Start Address Register 0 is set), the first pixel of each line is in the high byte of the
WORD and the contents of the low byte are ignored. If the Source Phase is 0, the first pixel
is in the low byte and the second pixel is in the high byte. Depending on the Source Phase
and the Blit Width, the last WORD may contain only one pixel. In this case it is always in
the low byte. The number of WORD writes the blit engine expects for 8 bpp color depths
is shown in the following formula.
nWORDS
= ((BlitWidth + 1 + SourcePhase) ÷ 2) × BlitHeight
Note
The blit engine counts WORD writes in the blit address space. This does not imply only
16-bit CPU instructions are acceptable. If a system is able to separate one DWORD
write into two WORD writes, then 32-bit CPU instructions are acceptable. Otherwise,
two back to back 16-bit CPU instructions are required.
Programming Notes and Examples
Issue Date: 01/02/06
S1D13506
X25B-G-003-03
Page 70
Epson Research and Development
Vancouver Design Center
Example 9: Write a 100 x 20 rectangle at the screen coordinates x = 25, y = 38 using
a 640x480 display at a color depth of 8 bpp.
1. Calculate the destination address (upper left corner of the screen blit rectangle) using
the following formula.
DestinationAddress = (y × ScreenStride) + (x × BytesPerPixel)
= (38 × 640) + (25 × 1)
= 24345
= 5F19h
where:
BytesPerPixel = 1 for 8 bpp
BytesPerPixel = 2 for 15/16 bpp
ScreenStride = DisplayWidthInPixels × BytesPerPixel = 640 for 8 bpp
Program the BitBLT Destination Start Address Registers. REG[10Ah] is set to 00h,
REG[109h] is set to 5Fh, and REG[108h] is set to 19h.
2. Program the BitBLT Width Registers to 100 - 1. REG[111h] is set to 00h and
REG[110h] is set to 63h (99 decimal).
3. Program the BitBLT Height Registers to 20 - 1. REG[113h] is set to 00h and
REG[112h] is set to 13h (19 decimal).
4. Program the Source Phase in the BitBLT Source Start Address Register. In this example the data is WORD aligned, so the source phase is 0. REG[104h] is set to 00h.
5. Program the BitBLT Operation Register to select the Write Blit with ROP.
REG[103h] is set to 00h.
6. Program the BitBLT ROP Code Register to select Destination = Source. REG[102h]
is set to 0Ch.
7. Program the BitBLT Color Format Select bit for 8 bpp operations. REG[101h] is set
to 00h.
8. Program the BitBLT Memory Offset Registers to the ScreenStride in WORDS:
BltMemoryOffset
= DisplayWidthInPixels ÷ BytesPerPixel
= 640 ÷ 2
= 140h
REG[10Dh] is set to 01h and REG[10Ch] is set to 40h.
9. Calculate the number of WORDS the blit engine expects to receive.
nWORDS
S1D13506
X25B-G-003-03
= ((BlitWidth + 1 + SourcePhase) ÷ 2) × BlitHeight
= (100 + 1) ÷ 2 × 20
= 1000
= 3E8h
Programming Notes and Examples
Issue Date: 01/02/06
Epson Research and Development
Vancouver Design Center
Page 71
10. Program the BitBLT Destination/Source Linear Select bits for a rectangular blit (BitBLT Destination Linear Select = 0, BitBLT Source Linear Select = 0).
Start the blit operation and wait for the blit engine to start. REG[100h] is set to 80h,
then wait until REG[100h] bit 7 returns a 1.
11. Prior to writing all nWORDS to the Blit FIFO, confirm the Blit FIFO is not full
(REG[100h] bit 4 returns a 0). If the BitBLT FIFO Not Empty Status returns a 0 (the
FIFO is empty), write up to 16 WORDS. If the BitBLT FIFO Not Empty Status returns a 1 and the BitBLT FIFO Half Full Status returns a 0 then you can write up to 8
WORDS. If the BitBLT FIFO Full Status returns a 1, do not write to the BitBLT FIFO
until it returns a 0.
The following table summarizes how many words can be written to the Blit FIFO.
Table 10-4: Possible Blit FIFO Writes
BitBLT Control Register 0 (REG[100h])
FIFO Not Empty Status
FIFO Half Full Status
FIFO Full Status
0
0
0
1
0
0
1
1
0
1
1
1
Word Writes
Available
16
8
up to 8
0 (do not write)
Note
The order of register initialization is irrelevant as long as all relevant registers are programmed before the BitBLT is started.
10.2.2 Color Expand BitBLT
This Color Expand BitBLT is similar to the Write BitBLT. It differs in that a bit set to 1 in
the source data becomes a pixel of foreground color. A source bit set to 0 is converted to a
pixel of background color. This function increases the speed of writing text while in
graphical modes.
This BitBLT operation includes several options which enhance its text handling capabilities. As with the Write BitBLT, all data sent to the blit engine must be word (16-bit) writes.
The blit engine expands the low byte, then the high byte starting at bit 7 of each byte.
The start byte of the first WORD to be expanded and the start bit position within this byte
must be specified. The start byte position is selected by setting source address bit 0 to 0 to
start expanding the low byte or 1 to start expanding the high byte.
Programming Notes and Examples
Issue Date: 01/02/06
S1D13506
X25B-G-003-03
Page 72
Epson Research and Development
Vancouver Design Center
Partially “masked” color expand BitBLT can be used when drawing a portion of a pattern
(i.e. a portion of a character) on the screen. The following examples illustrate how one
WORD is expanded using the Color Expand BitBLT.
1. To expand bits 0-1 of the word:
Source Address = 0
Start Bit Position = 1
Blit Width = 2
The following bits are expanded.
15
Word Sent To BitBLT Engine
8 7
7
0
7
High Byte
0
0
Low Byte
2. To expand bits 0-15 of the word (entire word)
Source Address = 0
Start Bit Position = 7 (bit seven of the low byte)
Blit Width = 16
The following bits are expanded.
15
Word Sent To BitBLT Engine
8 7
7
0
7
High Byte
0
0
Low Byte
3. To expand bits 8-9 of the word
Source Address = 1
Start Bit Position = 1
Blit Width = 2
The following bits are expanded.
15
Word Sent To BitBLT Engine
8 7
7
0
High Byte
7
0
0
Low Byte
4. To expand bits 0,15-14 of the word
S1D13506
X25B-G-003-03
Programming Notes and Examples
Issue Date: 01/02/06
Epson Research and Development
Vancouver Design Center
Page 73
Source Address = 0
Start Bit Position = 0
Blit Width = 3
The following bits are expanded.
Word Sent To BitBLT Engine
8 7
15
7
0
7
0
0
High Byte
Low Byte
All subsequent WORDS in one blit line are then serially expanded starting at bit 7 of the
low byte until the end of the blit line. All unused bits in the last WORD are discarded. It is
extremely important that the exact number of WORDS is provided to the blit engine. The
number of WORDS is calculated from the following formula. This formula is valid for all
color depths (8/15/16 bpp).
nWords = ((Sx MOD 16 + BltWidth + 15) ÷ 16) × BltHeight
where:
Sx is the X coordinate of the starting pixel in a word aligned monochrome bitmap.
Monochrome Bitmap
Byte 1
Sx =
0
1
2
3
Byte 2
4
5
6
7
8
9 10 11 12 13 14 15
Example 10: Color expand a rectangle of 12 x 18 starting at the coordinates Sx =
125, Sy = 17 using a 640x480 display at a color depth of 8 bpp.
This example assumes a monochrome, WORD aligned bitmap of dimensions 300 x 600
with the origin at an address A. The color expanded rectangle will be displayed at the screen
coordinates X = 20, Y = 30. The foreground color corresponds to the LUT entry at index
134, the background color to index 124.
1. First we need to calculate the address of the WORD within the monochrome bitmap
containing the pixel x = 125,y = 17.
SourceAddress
Programming Notes and Examples
Issue Date: 01/02/06
= BitmapOrigin + (y × SourceStride) + (x ÷ 8)
= A + (Sy × SourceStride) + (Sx ÷ 8)
= A + (17 × 38) + (125 ÷ 8)
= A + 646 + 15
= A + 661
S1D13506
X25B-G-003-03
Page 74
Epson Research and Development
Vancouver Design Center
where:
SourceStride
= (BitmapWidth + 15) ÷ 16
= (300 + 15) ÷ 16
= 19 WORDS per line
= 38 BYTES per line
2. Calculate the destination address (upper left corner of the screen blit rectangle) using
the following formula.
DestinationAddress = (Y × ScreenStride) + (X × BytesPerPixel)
= (30 × 640) + (20 × 1)
= 19220
= 4B14h
where:
BytesPerPixel = 1 for 8 bpp
BytesPerPixel = 2 for 15/16 bpp
ScreenStride = DisplayWidthInPixels × BytesPerPixel = 640 for 8 bpp
Program the BitBLT Destination Start Address Registers. REG[10Ah] is set to 00h,
REG[109h] is set to 4Bh, and REG[108h] is set to 14h.
3. Program the BitBLT Width Registers to 12 - 1. REG[111h] is set to 00h, REG[110h]
is set to 0Bh (11 decimal).
4. Program the BitBLT Height Registers to 18 - 1. REG[113h] is set to 00h, REG[112h]
is set to 11h (17 decimal).
5. Program the Source Phase in the BitBLT Source Start Address Register. In this example the source address equals A + 661 (odd), so REG[104h] is set to 1.
Since only bit 0 flags the source phase, more efficient code would simply write the
low byte of the SourceAddress into REG[104h] directly -- not needing to test for an
odd/even address. Note that in 15/16 bpp color depths the Source address is guaranteed to be even.
6. Program the BitBLT Operation Register to select the Color Expand Blit. REG[103h]
is set to 08h.
7. Program the Color Expansion Register. The formula for this example is as follows.
Reg[102h]
= 7 - (Sx MOD 8)
= 7 - (125 MOD 8)
=7-5
=2
REG[102h] is set to 02h.
8. Program the Background Color Registers to the background color. REG[115h] is set
to 00h and REG[114h] is set to 7Ch (124 decimal).
Note that for 15/16 bpp color depths, REG[115h] and REG[114h] are both required
and programmed directly with the value of the background color.
S1D13506
X25B-G-003-03
Programming Notes and Examples
Issue Date: 01/02/06
Epson Research and Development
Vancouver Design Center
Page 75
9. Program the Foreground Color Registers to the foreground color. REG[119h] is set to
00h and REG[118h] is set to 86h (134 decimal).
Note that for 15/16 bpp color depths REG[119h] and Reg[118h] are both required and
programmed directly with the value of the foreground color.
10. Program the BitBLT Color Format Register for 8 bpp operation. REG[101h] is set to
00h.
11. Program the BitBLT Memory Offset Registers to the ScreenStride in WORDS.
BltMemoryOffset
= ScreenStride ÷ 2
= 640 ÷ 2
= 140h
REG[10Dh] is set to 01h and REG[10Ch] is set to 40h.
12. Calculate the number of WORDS the blit engine expects to receive.
First, the number of WORDS in one blit line must be calculated as follows.
nWordsOneLine
= ((125 MOD 16) + 12 + 15) ÷ 16
= (13 + 12 + 15) ÷ 16
= 40 ÷ 16
=2
Therefore, the total WORDS the blit engine expects to receive is calculated as follows.
nWords
= nWordsOneLine × 18
= 2 × 18
= 36
13. Program the BitBLT Destination/Source Linear Select bits for a rectangular blit (BitBLT Destination Linear Select = 0, BitBLT Source Linear Select = 0).
Start the blit operation and wait for the Blit Engine to start. REG[100h] is set to 80h,
then wait until REG[100h] bit 7 returns a 1.
14. Prior to writing all nWORDS to the Blit FIFO, confirm the Blit FIFO is not full
(REG[100h] bit 4 returns a 0). One WORD expands into 16 pixels which fills all 16
FIFO words in 15/16 bpp or 8 FIFO words in 8 bpp.
The following table summarizes how many words can be written to the Blit FIFO.
Table 10-5: Possible Blit FIFO Writes
BitBLT Control Register 0 (REG[100h])
FIFO Not Empty Status
FIFO Half Full Status
FIFO Full Status
0
0
0
1
0
0
1
1
0
1
1
1
Programming Notes and Examples
Issue Date: 01/02/06
8 bpp Word
Writes Available
16 bpp Word
Writes Available
2
1
1
0 (do not write)
0 (do not write)
S1D13506
X25B-G-003-03
Page 76
Epson Research and Development
Vancouver Design Center
Note
The order of register initialization is irrelevant as long as all relevant registers are programmed before the BitBLT is initiated.
10.2.3 Color Expand BitBLT With Transparency
This BitBLT operation is virtually identical to the Color Expand BitBLT, except the
background color is completely ignored. All bits set to 1 in the source monochrome bitmap
are color expanded to the foreground color. All bits set to 0 that would be expanded to the
background color in the Color Expand BitBLT are not expanded at all.
Program REG[103h] to 09h instead of 08h. Programming the background color is not
required.
10.2.4 Solid Fill BitBLT
The Solid Fill BitBLT fills a rectangular area of the display buffer with a solid color. This
operation is used to paint large screen areas or to set areas of the display buffer to a given
value.
Example 11: Fill a red 9 x 321 rectangle at the screen coordinates x = 100, y = 10 using a 640x480 display at a color depth of 16 bpp.
1. Calculate the destination address (upper left corner of the destination rectangle) using
the following formula.
DestinationAddress = (y × ScreenStride) + (x × BytesPerPixel)
= (10 × (640 × 2)) + (100 × 2)
= 13000
= 32C8h
where:
BytesPerPixel = 1 for 8 bpp
BytesPerPixel = 2 for 15/16 bpp
ScreenStride = DisplayWidthInPixels × BytesPerPixel = 1280 for 16 bpp.
Program the BitBLT Destination Start Address Registers. REG[10Ah] is set to 00h,
REG[109h] is set to 32h, and REG[108h] is set to C8h.
2. Program the BitBLT Width Registers to 9 - 1. REG[111h] is set to 00h and
REG[110h] is set to 08h.
3. Program the BitBLT Height Registers to 321 - 1. REG[113h] is set to 01h and
REG[112h] is set to 40h (320 decimal).
4. Program the BitBLT Foreground Color Registers. REG[119h] is set to F8h and
REG[118h] is set to 00h (Full intensity red in 16 bpp is F800h).
5. Program the BitBLT Operation Register to select Solid Fill. REG[103h] is set to 0Ch.
S1D13506
X25B-G-003-03
Programming Notes and Examples
Issue Date: 01/02/06
Epson Research and Development
Vancouver Design Center
Page 77
6. Program the BitBLT Color Format Register for 16 bpp operations. REG[101h] is set
to 01h.
7. Program the BitBLT Memory Offset Registers to the ScreenStride in WORDS.
BltMemoryOffset
= ScreenStride ÷ 2
= 640
= 280h
REG[10Dh] is set to 02h and REG[10Ch] is set to 80h.
8. Program the BitBLT Destination/Source Linear Select bits for a rectangular blit (BitBLT Destination Linear Select = 0, BitBLT Source Linear Select = 0).
Start the blit operation. REG[100h] is set to 80h.
Note
The order of register initialization is irrelevant as long as all relevant registers are programmed before the BitBLT is initiated.
10.2.5 Move BitBLT in a Positive Direction with ROP
The Move BitBLT moves an area of the display buffer to a different area of the display
buffer. This operation has two intended purposes:
• Copying unattended display buffer to display buffer.
• Saving a visible bitmap to off-screen display buffer.
The Move BitBLT may move data from one rectangular area to another, or it may be
specified as linear. This allows the temporary saving of a portion of the visible display
buffer to an area off-screen. The linear configuration may be applied to the source or destination. Defining the Move BitBLT as linear allows each line of the Move BitBLT area to
be placed directly after the previous line, rather than requiring a complete row of address
space for each line.
Note
When the destination area overlaps the original source area and the destination address
is greater then the source address, use the Move BitBLT in Negative Direction with
ROP.
Programming Notes and Examples
Issue Date: 01/02/06
S1D13506
X25B-G-003-03
Page 78
Epson Research and Development
Vancouver Design Center
S
D
D
S
Destination Address less than Source Address
Destination Address greater than Source Address
Use Move BitBLT in Positive Direction
Use Move BitBLT in Negative Direction
Figure 10-1: Move BitBLT Usage
Example 12: Copy a 9 x 321 rectangle at the screen coordinates x = 100, y = 10 to
screen coordinates x = 200, y = 20 using a 640x480 display at a color
depth of 16 bpp.
1. Calculate the source and destination addresses (upper left corners of the source and
destination rectangles), using the following formula.
SourceAddress
= (y × ScreenStride) + (x × BytesPerPixel)
= (10 × (640 × 2)) + (100 × 2)
= 13000
= 32C8h
DestinationAddress = (y × ScreenStride) + (x × BytesPerPixel)
= (20 × (640 × 2)) + (200 × 2)
= 26000
= 6590h
where:
BytesPerPixel = 1 for 8 bpp
BytesPerPixel = 2 for 15/16 bpp
ScreenStride = DisplayWidthInPixels × BytesPerPixel = 1280 for 16 bpp
Program the BitBLT Source Start Address Registers. REG[106h] is set to 00h,
REG[105h] is set to 32h, and REG[104h] is set to C8h.
Program the BitBLT Destination Start Address Registers. REG[10Ah] is set to 00h,
REG[109h] is set to 65h, and REG[108h] is set to 90h.
2. Program the BitBLT Width Registers to 9 - 1. REG[111h] is set to 00h and
REG[110h] is set to 08h.
3. Program the BitBLT Height Registers to 321 - 1. REG[113h] is set to 01h and
REG[112h] is set to 40h (320 decimal).
4. Program the BitBLT Operation Register to select the Move BitBLT in Positive Direction with ROP. REG[103h] is set to 02h.
S1D13506
X25B-G-003-03
Programming Notes and Examples
Issue Date: 01/02/06
Epson Research and Development
Vancouver Design Center
Page 79
5. Program the BitBLT ROP Code Register to select Destination = Source. REG[102h]
is set to 0Ch.
6. Program the BitBLT Color Format Select bit for 16 bpp operations. REG[101h] is set
to 01h.
7. Program the BitBLT Memory Offset Registers to the ScreenStride in WORDS.
BltMemoryOffset
= ScreenStride ÷ 2
= 640
= 280h
REG[10Dh] is set to 02h and REG[10Ch] is set to 80h.
8. Program the BitBLT Destination/Source Linear Select bits for a rectangular blit (BitBLT Destination Linear Select = 0, BitBLT Source Linear Select = 0).
Start the blit operation. REG[100h] is set to 80h.
Note
The order of register initialization is irrelevant as long as all relevant registers are programmed before the BitBLT is initiated.
10.2.6 Move BitBLT in Negative Direction with ROP
The Move BitBLT in Negative Direction with ROP is very similar to the Move BitBLT in
Positive direction and must be used when the source and destination blit areas overlap and
the destination address is greater then the source address.
Note
For the Move BitBLT in Negative Direction it is necessary to calculate the addresses of
the last pixel as opposed to the first pixel. This means calculating the addresses of the
lower right corners as opposed to the upper left corners.
Example 13: Copy a 9 x 321 rectangle at the screen coordinates x = 100, y = 10 to
screen coordinates X = 105, Y = 20 using a 640x480 display at a color
depth of 16 bpp.
In the following example, the coordinates of the source and destination rectangles intentionally overlap.
1. Calculate the source and destination addresses (lower right corners of the source and
destination rectangles) using the following formula.
SourceAddress
= ((y + Height - 1) × ScreenStride) + ((x + Width - 1) × BytesPerPixel)
= ((10 + 321 - 1) × (640 × 2)) + ((100 + 9 - 1) × 2)
= 422616
= 672D8h
Programming Notes and Examples
Issue Date: 01/02/06
S1D13506
X25B-G-003-03
Page 80
Epson Research and Development
Vancouver Design Center
DestinationAddress
= ((Y + Height - 1) × ScreenStride) + ((X + Width - 1) × BytesPerPixel)
= ((20 + 321 - 1) × (640 × 2)) + ((105 + 9 - 1) × 2)
= 435426
= 6A4E2h
where:
BytesPerPixel = 1 for 8 bpp
BytesPerPixel = 2 for 15/16 bpp
ScreenStride = DisplayWidthInPixels × BytesPerPixel = 1280 for 16 bpp
Program the BitBLT Source Start Address Registers. REG[106h] is set to 06h,
REG[105h] is set to 72h, and REG[104h] is set to D8h.
Program the BitBLT Destination Start Address Registers. REG[10Ah] is set to 06h,
REG[109h] is set to A4h, and REG[108h] is set to E2h.
2. Program the BitBLT Width Registers to 9 - 1. REG[111h] is set to 00h and
REG[110h] is set to 08h.
3. Program the BitBLT Height Registers to 321 - 1. REG[113h] is set to 01h and
REG[112h] is set to 40h (320 decimal).
4. Program the BitBLT Operation Register to select the Move Blit in Negative Direction
with ROP. REG[103] is set to 03h.
5. Program the BitBLT ROP Code Register to select Destination = Source. REG[102h]
is set to 0Ch.
6. Program the BitBLT Color Format Select bit for 16 bpp operations. REG[101h] is set
to 01h.
7. Program the BitBLT Memory Offset Registers to the ScreenStride in WORDS.
BltMemoryOffset
= ScreenStride ÷ 2
= 640
= 280h
REG[10Dh] is set to 02h and REG[10Ch] is set to 80h.
8. Program the BitBLT Destination/Source Linear Select bits for a rectangular blit (BitBLT Destination Linear Select = 0, BitBLT Source Linear Select = 0).
Start the blit operation. REG[100h] is set to 80h.
Note
The order of register initialization is irrelevant as long as all relevant registers are programmed before the BitBLT is initiated.
S1D13506
X25B-G-003-03
Programming Notes and Examples
Issue Date: 01/02/06
Epson Research and Development
Vancouver Design Center
Page 81
10.2.7 Transparent Write Blit
The Transparent Write Blit increases the speed of transferring data from system memory to
the display buffer. Once the Transparent Write Blit begins, the blit engine remains active
until all pixels have been written.
The Transparent Write Blit updates a specified area of the display buffer with data supplied
by the CPU. This blit is typically used to copy a bitmap image from system memory to the
display buffer with one color marked as transparent. Any pixel of the transparent color is
not transferred. This allows fast display of non-rectangular images. For example, consider
a source bitmap having a red circle on a blue background. By selecting the blue color as the
transparent color and using the Transparent Write Blit on the whole rectangle, the effect is
a blit of the red circle only. The Transparent Write Blit supports both Destination Linear
and Destination Rectangular modes.
This Transparent Write Blit requires the CPU to provide data. The blit engine expects to
receive a certain number of WORDS. For 15/16 bpp color depths, the number of WORDS
is the same as the number of pixels due to the fact that each pixel is one WORD wide. The
number of WORD writes the blit engine expects is calculated using the following formula.
nWORDS
= nPixels
= Blit Width × Blit Height
For 8 bpp color depths, the formula must take into consideration that the blit engine accepts
only WORD accesses and each pixel is one BYTE. The blit engine needs to know whether
the first pixel of a line is stored in the low byte or high byte. This is determined by bit 0 of
the Source Start Address Register 0 (REG[104h]). If the Source Phase is 1 (bit 0 of the
Source Start Address Register 0 is set), the first pixel of each line is in the high byte of the
WORD and the contents of the low byte are ignored. If the Source Phase is 0, the first pixel
is in the low byte and the second pixel is in the high byte. Depending on the Source Phase
and the Blit Width, the last WORD in each line may contain only one pixel. It is always in
the low byte if more than one WORD per line is required. The number of WORD reads the
blit engine expects for 8 bpp color depths is shown in the following formula.
nWORDS
= ((BlitWidth + 1 + SourcePhase) ÷ 2) × BlitHeight
Note
The blit engine counts WORD writes in the blit address space. This does not imply only
16-bit CPU instructions are acceptable. If a system is able to separate one DWORD
write into two WORD writes, then 32-bit CPU instructions are acceptable. Otherwise,
two back to back 16-bit CPU instructions are required.
Example 14: Write 100 x 20 pixels at the screen coordinates x = 25, y = 38 using a
640x480 display at a color depth of 8 bpp. Transparent color is high intensity blue (assumes LUT Index 124).
1. Calculate the destination address (upper left corner of the screen blit rectangle), using
the formula:
Programming Notes and Examples
Issue Date: 01/02/06
S1D13506
X25B-G-003-03
Page 82
Epson Research and Development
Vancouver Design Center
DestinationAddress = (y × ScreenStride) + (x × BytesPerPixel)
= (38 × 640) + (25 × 1)
= 24345
= 5F19h
where:
BytesPerPixel = 1 for 8 bpp
BytesPerPixel = 2 for 15/16 bpp
ScreenStride = DisplayWidthInPixels × BytesPerPixel = 640 for 8 bpp
Program the BitBLT Destination Start Address Registers. REG[10Ah] is set to 00h,
REG[109h] is set to 5Fh, and REG[108h] is set to 19h.
2. Program the BitBLT Width Registers to 100 - 1. REG[111h] is set to 00h and
REG[110h] is set to 63h (99 decimal).
3. Program the BitBLT Height Registers to 20 - 1. REG[113h] is set to 00h and
REG[112h] is set to 13h (19 decimal).
4. Program the Source Phase in the BitBLT Source Start Address Register. In this example, the data is WORD aligned, so the source phase is 0. REG[104h] is set to 00h.
5. Program the BitBLT Operation Register to select Transparent Write Blit. REG[103h]
is set to 04h.
6. Program the BitBLT Background Color Registers to select transparent color.
REG[114h] is set to 7Ch (124 decimal).
Note that for 15/16 bpp color depths, REG[115h] and REG[114h] are both required
and programmed directly with the value of the transparent background color.
7. Program the BitBLT Color Format Select bit for 8 bpp operations. REG[101h] is set
to 00h.
8. Program the BitBLT Memory Offset Registers to the ScreenStride in WORDS.
BltMemoryOffset
= ScreenStride ÷ 2
= 640 ÷ 2
= 320
= 140h
REG[10Dh] is set to 01h and REG[10Ch] is set to 40h.
9. Calculate the number of WORDS the blit engine expects to receive.
nWORDS
S1D13506
X25B-G-003-03
= ((BlitWidth + 1 + SourcePhase) ÷ 2) × BlitHeight
= (100 + 1 + 0) ÷ 2 × 20
= 1000
= 3E8h
Programming Notes and Examples
Issue Date: 01/02/06
Epson Research and Development
Vancouver Design Center
Page 83
10. Program the BitBLT Destination/Source Linear Select bits for a rectangular blit (BitBLT Destination Linear Select = 0, BitBLT Source Linear Select = 0).
Start the blit operation and wait for the blit engine to start. REG[100h] is set to 80h,
then wait until REG[100h] bit 7 returns a 1.
11. Prior to writing all nWORDS to the Blit FIFO, confirm the Blit FIFO is not full
(REG[100h] bit 4 returns a 0). If the BitBLT FIFO Not Empty Status returns a 0 (the
FIFO is empty), write up to 16 WORDS. If the BitBLT FIFO Not Empty Status returns a 0 and the BitBLT FIFO Half Full Status returns a 0 then you can write up to 8
WORDS. If the BitBLT FIFO Full Status returns a 1, do not write to the BitBLT FIFO
until it returns a 0.
The following table summarizes how many words can be written to the Blit FIFO.
Table 10-6: Possible Blit FIFO Writes
BitBLT Control Register 0 (REG[100h])
FIFO Not Empty Status
FIFO Half Full Status
FIFO Full Status
0
0
0
1
0
0
1
1
0
1
1
1
Word Writes
Available
16
8
less than 8
0 (do not write)
Note
The order of register initialization is irrelevant as long as all relevant registers are programmed before the BitBLT is initiated.
10.2.8 Transparent Move BitBLT in Positive Direction
The Transparent Move BitBLT in Positive Direction moves an area of the display buffer to
a different area of the display buffer. It allows for selection of a transparent color which is
not copied during the blit. This allows fast display of non-rectangular images. For example,
consider a source bitmap having a red circle on a blue background. By selecting the blue
color as the transparent color and using the Transparent Move Blit on the whole rectangle,
the effect is a blit of the red circle only.
The Transparent Move BitBLT may move data from one rectangular area to another, or it
may be specified as linear. The linear configuration may be applied to the source or destination. Defining the Move BitBLT as linear allows each line of the Move BitBLT area to
be placed directly after the previous line, rather than requiring a complete row of address
space for each line.
Note
The Transparent Move BitBLT is supported only in a positive direction.
Programming Notes and Examples
Issue Date: 01/02/06
S1D13506
X25B-G-003-03
Page 84
Epson Research and Development
Vancouver Design Center
Example 15: Copy a 9 x 321 rectangle at the screen coordinates x = 100, y = 10 to
screen coordinates X = 200, Y = 20 using a 640x480 display at a color
depth of 16 bpp. Transparent color is blue.
1. Calculate the source and destination addresses (upper left corners of the source and
destination rectangles), using the formula:
SourceAddress
= (y × ScreenStride) + (x × BytesPerPixel)
= (10 × (640 × 2)) + (100 × 2)
= 13000
= 32C8h
DestinationAddress = (Y × ScreenStride) + (X × BytesPerPixel)
= (20 × (640 × 2)) + (200 × 2)
= 26000
= 6590h
where:
BytesPerPixel = 1 for 8 bpp
BytesPerPixel = 2 for 15/16 bpp
ScreenStride = DisplayWidthInPixels × BytesPerPixel = 1280 for 16 bpp
Program the BitBLT Source Start Address Registers. REG[106h] is set to 00h,
REG[105h] is set to 32h, and REG[104h] is set to C8h.
Program the BitBLT Destination Start Address Registers. REG[10Ah] is set to 00h,
REG[109h] is set to 65h, and REG[108h] is set to 90h.
2. Program the BitBLT Width Registers to 9 - 1. REG[111h] is set to 00h and
REG[110h] is set to 08h.
3. Program the BitBLT Height Registers to 321 - 1. REG[113h] is set to 01h and
REG[112h] is set to 40h (320 decimal).
4. Program the BitBLT Operation Register to select the Transparent Move Blit in Positive Direction. REG[103h] is set to 05h.
5. Program the BitBLT Background Color Registers to select blue as the transparent color. REG[115h] is set to 00h and REG[114h] is set to 1Fh (Full intensity blue in 16 bpp
is 001Fh).
6. Program the BitBLT Color Format Register to select 16 bpp operations. REG[101h] is
set to 01h.
7. Program the BitBLT Memory Offset Registers to the ScreenStride in WORDS.
BltMemoryOffset
= ScreenStride ÷ 2
= 640
= 280h
REG[10Dh] is set to 02h and REG[10Ch] is set to 80h.
S1D13506
X25B-G-003-03
Programming Notes and Examples
Issue Date: 01/02/06
Epson Research and Development
Vancouver Design Center
Page 85
8. Program the BitBLT Destination/Source Linear Select bits for a rectangular blit (BitBLT Destination Linear Select = 0, BitBLT Source Linear Select = 0).
Start the blit operation. REG[100h] is set to 80h.
Note
The order of register initialization is irrelevant as long as all relevant registers are programmed before the BitBLT is initiated.
10.2.9 Pattern Fill BitBLT with ROP
The Pattern Fill BitBLT with ROP fills a specified rectangular area of the display buffer
with a pattern. The fill pattern is an array of pixels stored in off-screen display buffer. The
fill pattern is limited to an eight by eight pixel array and must be loaded to off-screen
memory prior to the BitBLT starting. The pattern can be logically combined with the destination using all 16 ROP codes, but typically the copy pattern ROP is used (ROP code 0Ch).
The pattern itself must be stored in a consecutive array of pixels. As a pattern is defined to
be eight pixels square, this results in 64 consecutive bytes for 8 bpp color depths and 128
bytes for 15/16 bpp color depths. For 8 bpp color depths the pattern must begin on a 64 byte
boundary, for 15/16 bpp color depths the pattern must begin on a 128 byte boundary.
To fill an area using the pattern BitBLT, the blit engine requires the location of the pattern,
the destination rectangle position and size, and the ROP code. The blit engine also needs to
know which pixel from the pattern is the first pixel in the destination rectangle (the pattern
start phase). This allows seamless redrawing of any part of the screen using the pattern fill.
Example 16: Fill a 100 x 250 rectangle at the screen coordinates x = 10, y = 20 with
the pattern in off-screen memory at offset 10 0000h using a 640x480 display at a color depth of 8 bpp. The first pixel (upper left corner) of the
rectangle is the pattern pixel at x = 3, y = 4.
1. Calculate the destination address (upper left corner of the destination rectangle), using
the formula:
DestinationAddress = (y × ScreenStride) + (x × BytesPerPixel)
= (20 × 640) + (10 × 1)
= 12810
= 320Ah
where:
BytesPerPixel = 1 for 8 bpp
BytesPerPixel = 2 for 15/16 bpp
ScreenStride = DisplayWidthInPixels × BytesPerPixels = 640 for 8 bpp
Program the BitBLT Destination Start Address Registers. REG[10Ah] is set to 00h,
REG[109h] is set to 32h, and REG[108h] is set to 0Ah.
2. Calculate the source address. This is the address of the pixel in the pattern that is the
origin of the destination fill area. The pattern begins at offset 1M, but the first pattern
pixel is at x = 3, y = 4. Therefore, an offset within the pattern itself must be calculated.
Programming Notes and Examples
Issue Date: 01/02/06
S1D13506
X25B-G-003-03
Page 86
Epson Research and Development
Vancouver Design Center
SourceAddress
= PatternOffset + StartPatternY × 8 × BytesPerPixel + StartPatternX × BytesPerPixel
= 1M + (4 × 8 × 1) + (3 × 1)
= 1M + 35
= 1048611
= 100023h
where:
BytesPerPixel = 1 for 8 bpp
BytesPerPixel = 2 for 15/16 bpp
Program the BitBLT Source Start Address Registers. REG[106h] is set to 10h,
REG[105h] is set to 00h, and REG[104h] is set 23h.
3. Program the BitBLT Width Registers to 100 - 1. REG[111h] is set to 00h, REG[110h]
is set to 63h (99 decimal).
4. Program the BitBLT Height Registers to 250-1. REG[113h] is set to 00h, and
REG[112h] is set to F9h (249 decimal).
5. Program the BitBLT Operation Register to select the Pattern Fill with ROP.
REG[103h] is set to 06h.
6. Program the BitBLT ROP Code Register to select Destination = Source. REG[102h]
is set to 0Ch.
7. Program the BitBLT Color Format Select bit for 8 bpp operations. REG[101h] is set
to 00h.
8. Program the BitBLT Memory Offset Registers to the ScreenStride in WORDS.
BltMemoryOffset
= ScreenStride ÷ 2
= 640 ÷ 2
= 320
= 140h
REG[10Dh] is set to 01h and REG[10Ch] is set to 40h.
9. Program the BitBLT Destination/Source Linear Select bits for a rectangular blit (BitBLT Destination Linear Select = 0, BitBLT Source Linear Select = 0).
Start the blit operation. REG[100h] is set to 80h.
Note
The order of register initialization is irrelevant as long as all relevant registers are programmed before the BitBLT is initiated.
S1D13506
X25B-G-003-03
Programming Notes and Examples
Issue Date: 01/02/06
Epson Research and Development
Vancouver Design Center
Page 87
10.2.10 Pattern Fill BitBLT with Transparency
The Pattern Fill BitBLT with Transparency fills a specified rectangular area of the display
buffer with a pattern. When a transparent color is selected, pattern pixels of the transparent
color will not get copied, allowing creation of hatched patterns. The fill pattern is an eight
by eight array of pixels stored in off-screen display buffer. The fill pattern must be loaded
to off-screen display buffer prior to the BitBLT starting.
The pattern itself must be stored in a consecutive array of pixels. As a pattern is defined to
be eight pixels square, this results in 64 consecutive bytes for 8 bpp color depths and 128
bytes for 15/16 bpp color depths. For 8 bpp color depths the pattern must begin on a 64 byte
boundary, for 15/16 bpp color depths the pattern must begin on a 128 byte boundary.
To fill an area using the Pattern Fill BitBLT with Transparency, the blit engine requires the
location of the pattern, the destination rectangle position and size, and the transparency
color. The blit engine also needs to know which pixel from the pattern is the first pixel in
the destination rectangle (the pattern start phase). This allows seamless redrawing of any
part of the screen using the pattern fill.
Example 17: Fill a 100 x 250 rectangle at the screen coordinates x = 10, y = 20 with
the pattern in off-screen memory at offset 10000h using a 640x480 display at a color depth of 8 bpp. The first pixel (upper left corner) of the
rectangle is the pattern pixel at x = 3, y = 4. Transparent color is blue (assumes LUT index 1).
1. Calculate the destination address (upper left corner of destination rectangle), using the
formula:
DestinationAddress = (y × ScreenStride) + (x × BytesPerPixel)
= (20 × 640) + (10 × 1)
= 12810
= 320Ah
where:
BytesPerPixel = 1 for 8 bpp
BytesPerPixel = 2 for 15/16 bpp
ScreenStride = DisplayWidthInPixels × BytesPerPixels = 640 for 8 bpp
Program the BitBLT Destination Start Address Registers. REG[10Ah] is set to 00h,
REG[109h] is set to 32h, and REG[108h] is set to 0Ah.
2. Calculate the source address. This is the address of the pixel in the pattern that is the
origin of the destination fill area. The pattern begins at offset 1M, but the first pattern
pixel is at x = 3, y = 4. Therefore, an offset within the pattern itself must be calculated.
SourceAddress
= PatternOffset + StartPatternY × 8 × BytesPerPixel + StartPatternX × BytesPerPixel
= 1M + (4 × 8 × 1) + (3 × 1)
= 1M + 35
= 1048611
= 100023h
Programming Notes and Examples
Issue Date: 01/02/06
S1D13506
X25B-G-003-03
Page 88
Epson Research and Development
Vancouver Design Center
where:
BytesPerPixel = 1 for 8 bpp
BytesPerPixel = 2 for 15/16 bpp
Program the BitBLT Source Start Address Registers. REG[106h] is set to 10h,
REG[105h] is set to 00h, and REG[104h] is set 23h.
3. Program the BitBLT Width Registers to 100 - 1. REG[111h] is set to 00h and
REG[110h] is set to 63h (99 decimal).
4. Program the BitBLT Height Registers to 250-1. REG[113h] is set to 00h, and
REG[112h] is set to F9h (249 decimal).
5. Program the BitBLT Operation Register to select the Pattern Fill BitBLT with Transparency. REG[103h] is set to 07h.
6. Program the BitBLT Background Color Registers to select transparent color. This example uses blue (LUT index 1) as the transparent color. REG[114h] is set to 01h.
Note that for 15/16 bpp color depths, REG[115h] and REG[114h] are both required
and programmed directly with the value of the transparent background color. For example, for full intensity green to be the transparent color in 16 bpp, REG[115h] is set
to 07h and REG[114h] is set to E0h.
7. Program the BitBLT Color Format Select bit for 8 bpp operations. REG[101h] is set
to 00h.
8. Program the BitBLT Memory Offset Registers to the ScreenStride in WORDS.
BltMemoryOffset
= ScreenStride ÷ 2
= 640 ÷ 2
= 320
= 140h
REG[10Dh] is set to 01h and REG[10Ch] is set to 40h.
9. Program the BitBLT Destination/Source Linear Select bits for a rectangular blit (BitBLT Destination Linear Select = 0, BitBLT Source Linear Select = 0).
Start the blit operation. REG[100h] is set to 80h.
Note
The order of register initialization is irrelevant as long as all relevant registers are programmed before the BitBLT is initiated.
10.2.11 Move BitBLT with Color Expansion
The Move BitBLT with Color Expansion takes a monochrome bitmap as the source and
color expands it into the destination. Color expansion moves all bits in the monochrome
source to pixels in the destination. All bits in the source set to one are expanded into destination pixels of the selected foreground color. All bits in the source set to zero are expanded
into pixels of the selected background color.
S1D13506
X25B-G-003-03
Programming Notes and Examples
Issue Date: 01/02/06
Epson Research and Development
Vancouver Design Center
Page 89
The Move BitBLT with Color Expansion is used to accelerate text drawing on the screen.
A monochrome bitmap of a font in off-screen memory occupies very little space and takes
advantage of the hardware acceleration. Since the foreground and background colors are
programmable, text of any color can be created.
The Move BitBLT with Color Expansion may move data from one rectangular area to
another, or it may be specified as linear. The linear configuration may be applied to the
source or destination. Defining the Move BitBLT as linear allows each line of the Move
BitBLT area to be placed directly after the previous line, rather than requiring a complete
row of address space for each line.
Note
The BitBLT ROP Code/Color Expansion Register must be programmed to value 07h
because in the first word in a line color expansion is started with the most significant bit
of the low byte.
Example 18: Color expand a 9 x 16 rectangle using the pattern in off-screen memory
at 10 0000h and move it to the screen coordinates x = 200, y = 20. Assume a 640x480 display at a color depth of 16 bpp, Foreground color of
black, and background color of white.
1. Calculate the destination and source addresses (upper left corner of the destination and
source rectangles), using the formula.
DestinationAddress = (y × ScreenStride) + (x × BytesPerPixel)
= (20 × (640 × 2)) + (200 × 2)
= 26000
= 6590h
where:
BytesPerPixel = 1 for 8 bpp
BytesPerPixel = 2 for 15/16 bpp
ScreenStride = DisplayWidthInPixels × BytesPerPixels = 1280 for 16 bpp
SourceAddress
= 1M
= 100000h
Program the BitBLT Destination Start Address Registers. REG[10Ah] is set to 00h,
REG[109h] is set to 65h, and REG[108h] is set to 90h.
Program the BitBLT Source Start Address Registers. REG[106h] is set to 10h,
REG[105h] is set to 00h, and REG[104h] is set to 00h.
2. Program the BitBLT Width Registers to 9 - 1. REG[111h] is set to 00h and
REG[110h] is set to 08h.
3. Program the BitBLT Height Registers to 16 - 1. REG[113h] is set to 00h and
REG[112h] is set to 0Fh.
4. Program the BitBLT ROP Code/Color Expansion Register. REG[102h] is set to
07h.
Programming Notes and Examples
Issue Date: 01/02/06
S1D13506
X25B-G-003-03
Page 90
Epson Research and Development
Vancouver Design Center
5. Program the BitBLT Operation Register to select the Move Blit with Color Expansion. REG[103h] is set to 0Bh.
6. Program the BitBLT Foreground Color Register to select black (in 16 bpp black =
0000h). REG[119h] is set to 00h and REG[118h] is set to 00h.
7. Program the BitBLT Background Color Register to select white (in 16 bpp white =
FFFFh). REG[115h] is set to FFh and REG[114h] is set to FFh.
8. Program the BitBLT Color Format Select bit for 16 bpp operations. REG[101h] is set
to 01h.
9. Program the BitBLT Memory Offset Registers to the ScreenStride in WORDS.
BltMemoryOffset
= ScreenStride ÷ 2
= 640
= 280h
REG[10Dh] is set to 02h and REG[10Ch] is set to 80h.
10. Program the BitBLT Destination/Source Linear Select bits for a rectangular blit (BitBLT Destination Linear Select = 0, BitBLT Source Linear Select = 0).
Start the blit operation. REG[100h] is set to 80h.
Note
The order of register initialization is irrelevant as long as all relevant registers are programmed before the BitBLT is initiated.
10.2.12 Transparent Move Blit with Color Expansion
The Transparent Move Blit with Color Expansion is virtually identical to the Move Blit
with Color Expansion. The background color is ignored and bits in the monochrome source
bitmap set to 0 are not color expanded.
10.2.13 Read Blit
This Read Blit increases the speed of transferring data from the display buffer to system
memory. This blit complements the Write Blit and is typically used to save a part of the
display buffer to the system memory. Once the Read Blit begins, the blit engine remains
active until all the pixels have been read.
The blit engine requires the address to copy from and the size of the area to copy (width x
height). The blit engine expects to read a certain number of words. For 15/16 bpp color
depths, the number of words is the same as the number of pixels due to the fact that each
pixel is one WORD wide. The number of WORD reads the blit engine expects is calculated
using the following formula.
nWORDS
S1D13506
X25B-G-003-03
= nPixels
= Blit Width × Blit Height
Programming Notes and Examples
Issue Date: 01/02/06
Epson Research and Development
Vancouver Design Center
Page 91
For 8 bpp color depths, the formula must take into consideration that the blit engine accepts
only WORD accesses and each pixel is one BYTE. The blit engine needs to know whether
the first pixel of each line is stored in the low byte or high byte. This is determined by bit 0
of the Destination Start Address Register 0 (REG[108h]). If the Destination Phase is 1 (bit
0 of the Destination Start Address Register 0 is set), the first pixel of each line is placed in
the high byte of the WORD and the contents of the low byte is undefined. If the Destination
Phase is 0, the first pixel is placed in the low byte and the second pixel is placed in the high
byte. Depending on the Destination Phase and the Blit Width, the last WORD in each line
may contain only one pixel. It is always in the low byte if more than one WORD per line is
required. The number of WORD reads the blit engine expects for 8 bpp color depths is
shown in the following formula.
nWORDS
= ((BlitWidth + 1 + DestinationPhase) ÷ 2) × BlitHeight
Example 19: Read 100 x 20 pixels at the screen coordinates x = 25, y = 38 and save
to system memory. Assume a display of 640x480 at a color depth of 8
bpp.
1. Calculate the source address (upper left corner of the screen blit rectangle), using the
formula.
SourceAddress
= (y × ScreenStride) + (x × BytesPerPixel)
= (38 × 640) + (25 × 1)
= 24345
= 5F19h
where:
BytesPerPixel = 1 for 8 bpp
BytesPerPixel = 2 for 15/16 bpp
ScreenStride = DisplayWidthInPixels × BytesPerPixels = 640 for 8 bpp
Program the BitBLT Source Start Address Registers. REG[106h] is set to 00h,
REG[105h] is set to 5Fh, and REG[104h] is set to 19h.
2. Program the BitBLT Width Registers to 100 - 1. REG[111h] is set to 00h and
REG[110h] is set to 63h (99 decimal).
3. Program the BitBLT Height Registers to 20 - 1. REG[113h] is set to 00h and
REG[112h] is set to 13h (19 decimal).
4. Program the Destination Phase in the BitBLT Destination Start Address Register. In
this example, the data is WORD aligned, so the destination phase is 0. REG[108h] is
set to 0.
5. Program the BitBLT Operation to select the Read Blit. REG[103h] is set to 01h.
6. Program the BitBLT Color Format Select bit for 8 bpp operations. REG[101h] is set
to 00h.
7. Program the BitBLT Memory Offset Registers to the ScreenStride in WORDS.
Programming Notes and Examples
Issue Date: 01/02/06
S1D13506
X25B-G-003-03
Page 92
Epson Research and Development
Vancouver Design Center
BltMemoryOffset = ScreenStride ÷ 2
= 640 ÷ 2
= 320
= 140h
REG[10Dh] is set to 01h and REG[10Ch] is set to 40h.
8. Calculate the number of WORDS the blit engine expects to receive.
nWORDS
= ((BlitWidth + 1 + DestinationPhase) ÷ 2) × BlitHeight
= (100 + 1 + 0) ÷ 2 × 20
= 1000
= 3E8h
9. Program the BitBLT Destination/Source Linear Select bits for a rectangular blit (BitBLT Destination Linear Select = 0, BitBLT Source Linear Select = 0).
Start the blit operation and wait for the blit engine to start. REG[100h] is set to 80h,
then wait until REG[100h] bit 7 returns a 1.
10. Prior to reading all nWORDS from the Blit FIFO, confirm the Blit FIFO is not empty
(REG[100h] bit 4 returns a 1). If the BitBLT FIFO Not Empty Status returns a 1 and
the BitBLT FIFO Half Full Status returns a 0 then you can read up to 8 WORDS. If
the BitBLT FIFO Full Status returns a 1, read up to 16 WORDS. If the BitBLT FIFO
Not Empty Status returns a 0 (the FIFO is empty), do not read from the BitBLT FIFO
until it returns a 1.
The following table summarizes how many words can be read from the Blit FIFO.
Table 10-7: Possible Blit FIFO Reads
BitBLT Control Register 0 (REG[100h])
FIFO Not Empty Status
FIFO Half Full Status
FIFO Full Status
0
0
0
1
0
0
1
1
0
1
1
1
Word Reads
Available
0 (do not read)
up to 8
8
16
Note
The order of register initialization is irrelevant as long as all relevant registers are programmed before the BitBLT is initiated.
10.3 S1D13506 BitBLT Synchronization
A BitBLT operation can only be started if the blit engine is not busy servicing another blit.
Before a new BitBLT operation is started, software must confirm the BitBLT Active Status
bit (REG[100h] bit 7) returns a 0. Software can either test this bit after each BitBLT
operation, or before each BitBLT operation.
Testing the BitBLT Status After
S1D13506
X25B-G-003-03
Programming Notes and Examples
Issue Date: 01/02/06
Epson Research and Development
Vancouver Design Center
Page 93
Testing the BitBLT Active Status after starting a new BitBLT is simpler and less prone to
errors.
To test after each BitBLT operation, perform the following.
1. Program and start the blit engine.
2. Wait for the current BitBLT operation to finish -- Poll the BitBLT Active Status bit
(REG[100h] bit) until it returns a 0.
3. Continue the program.
Programming Notes and Examples
Issue Date: 01/02/06
S1D13506
X25B-G-003-03
Page 94
Epson Research and Development
Vancouver Design Center
Testing the BitBLT Status Before
Testing the BitBLT Active Status before starting a new BitBLT results in better performance, as both CPU and blit engine can be running at the same time. This is most useful
for BitBLTs that are self completing (once started they don’t require any CPU assistance).
While the blit engine is busy, the CPU can do other tasks. To test before each BitBLT
operation, perform the following.
1. Wait for the current BitBLT operation to finish -- Poll the BitBLT Active Status bit
(REG[100h] bit 7) until it returns a 0.
2. Program and start the new BitBLT operation.
3. Continue the program (CPU and blit engine work independently).
However, this approach can pose problems if the CPU writes a pixel while the blit engine
is running a blit. If the CPU writes the pixel before the BitBLT finishes, the pixel may be
overwritten by the blit. To avoid this scenario, always assure no BitBLT is in progress
before accessing the display buffer with the CPU, or don’t use the CPU to access display
buffer at all.
10.4 S1D13506 BitBLT Known Limitations
The S1D13506 blit engine has the following limitations.
• BitBLT Width must be greater than 0.
• BitBLT Height must be greater than 0.
• The blit engine is not SwivelView aware. If BitBLTs are used when SwivelView is
enabled, the coordinates and verticies are swapped. It may be possible to recalculate
these coordinates and vertices allowing use of some of the BitBLT functions. However
the coordinate transformations required may nullify the benefits of the BitBLT.
• The Pattern Fill with ROP (0Ch or 03h) and Transparent Pattern Fill are designed such
that the BitBLT Width must be > 1 for 15/16 bpp color depths and > 2 for 8 bpp.
10.5 Sample Code
Sample code demonstrating how to program the S1D13506 BitBLT engine is provided in
the file 13506BLT.ZIP. This file is available on the internet at www.eea.epson.com.
S1D13506
X25B-G-003-03
Programming Notes and Examples
Issue Date: 01/02/06
Epson Research and Development
Vancouver Design Center
Page 95
11 CRT/TV Considerations
The S1D13506 is capable of driving an LCD panel, CRT display, or a TV monitor.
However, only an LCD panel and CRT or an LCD panel and TV can be driven simultaneously. It is not possible to drive both a CRT and TV at the same time.
The horizontal and vertical timing requirements of LCD panels allows for a wide timing
variance. In comparison, a CRT display has very strict timing requirements with even a
very small timing variance degrading the displayed image. TV monitors require timings
based on the NTSC or PAL specifications.
The utility 13506CFG.EXE can be used to generate a header file containing the register
values required for CRT/TV or LCD panel timings. For further information on
13506CFG.EXE, see the 13506CFG Users Manual, document number X25B-B-001-xx.
11.1 CRT Considerations
CRT timings are based on the VESA Monitor Timing Specifications. The VESA specification details all the parameters of the display and non-display times, as well as the input
clock required to meet the times. Failing to use correct timings can result in an unsynchronized image on a particular monitor, which can permanently damage the
monitor. Virtually all VGA monitors sync if VESA timings are used.
For more information on VESA timings, contact the Video Electronics Standards Association on the internet at www.vesa.org.
11.1.1 Generating CRT timings with 13506CFG
13506CFG.EXE will generate correct VESA timings for 640x480 and 800x600 if provided
the correct VESA input clock. The following timings can be generated:
• 640x480 @ 60Hz (Input Clock = 25.175 MHz)
• 640x480 @ 72Hz (Input Clock = 31.500 MHz)
• 640x480 @ 75Hz (Input Clock = 31.500 MHz)
• 640x480 @ 85 Hz (Input Clock = 36.000 MHz)
• 800x600 @ 56 Hz (Input Clock = 36.000 MHz)
• 800x600 @ 60 Hz (Input Clock = 40.000 MHz)
11.1.2 DAC Output Level Selection
When the CRT is active, the DAC Output Level Select bit (REG[05Bh] bit 3) can be used
to double values outpu to the DAC. This would normally result in very bright colors on the
display, but if IREF is reduced at the same time the display will remain at its intended
brightness and power consumption is reduced.
Programming Notes and Examples
Issue Date: 01/02/06
S1D13506
X25B-G-003-03
Page 96
Epson Research and Development
Vancouver Design Center
11.1.3 Examples
Example 20: Enable the CRT display. Assume the CRT timing registers are already
programmed.
1. Confirm the TV PAL/NTSC Output Select bit is clear. REG[05Bh] bit 0 is set to 0.
2. Confirm the CRT and TV displays are disabled. REG[1FCh] bits 2-1 are set to 0.
3. Enable the CRT. REG[1FCh] is set to 1.
Sample code demonstrating how to enable the CRT display is provided in the file
56_CRT.c. This file is available on the internet at www.eea.epson.com.
11.2 TV Considerations
TV timings are based on either the NTSC or PAL specifications. The TV display can be
output in either composite video or S-video format.
11.2.1 NTSC Timings
NTSC timings require a 14.318 MHz input clock. With the correct input clock the
following resolutions are supported.
• 640x480
• 696x436
• 752x484
11.2.2 PAL Timings
PAL timings require a 17.734 MHz input clock. With the correct input clock the following
resolutions are supported.
• 640x480
• 800x572
• 856x518
• 920x572
S1D13506
X25B-G-003-03
Programming Notes and Examples
Issue Date: 01/02/06
Epson Research and Development
Vancouver Design Center
Page 97
11.2.3 TV Filters
The S1D13506 is designed with three filters which improve TV picture quality.
• Flicker Filter.
• Chrominance Filter.
• Luminance Filter.
Each filter is independent and can be enabled/disabled separately. The TV picture quality
varies depending on the actual picture displayed (static image, moving image, number of
colors etc.) and may be improved using the filters.
Flicker Filter
The Flicker Filter is controlled by the Display Mode Select bits (REG[1FCh] bits 2-0). It
reduces the “flickering” effect seen on interlaced displays caused by sharp vertical image
transitions that occur over one line (e.g. one pixel high lines, edges of window boxes, etc.).
The Flicker Filter may be used to for both composite video and S-video formats.
Note
The CRT/TV PCLK 2X Enable bit (REG[018h] bit 7) must be set to 1 when the Flicker
Filter is enabled.
Chrominance Filter
The Chrominance Filter is controlled by the TV Chrominance Filter Enable bit
(REG[05Bh] bit 5). It adjusts the color of the TV, reducing the “ragged edges” seen a the
boundaries between sharp color transitions. The Chrominance Filter may improve the TV
picture quality when in composite video format.
Luminance Filter
The Luminance Filter is controlled by the TV Luminance Filter Enable bit (REG[05Bh] bit
4). It adjusts the brightness of the TV, reducing the “rainbow-like” colors at the boundaries
between sharp brightness transitions. The Luminance Filter may improve the TV picture
quality when in composite video format.
For further information on the TV filters, see the S1D13506 Hardware Functional Specification, document number X25B-A-001-xx.
11.2.4 Examples
Example 21: Enable the TV display and set the Flicker Filter. Assume the TV timing
registers are already programmed.
1. Enable the TV with Flicker Filter enabled. REG[1FCh] is set to 06h.
2. Enable the CRT/TV PCLK 2X bit (REG[018h] bit 7). REG[018h] bit 7 is set to 1b.
Programming Notes and Examples
Issue Date: 01/02/06
S1D13506
X25B-G-003-03
Page 98
Epson Research and Development
Vancouver Design Center
Sample code demonstrating how to enable the TV display is provided in the file 156_TV.c.
This file is available on the internet at www.eea.epson.com.
11.3 Simultaneous Display
The S1D13506 supports simultaneous display of an LCD panel and CRT or an LCD panel
and TV. Both display images are completely independent. Each display can show separate
areas of the display buffer and display different color depths. There are separate Look-Up
Tables and Hardware Cursors/Ink Layers for both the LCD and CRT/TV. If desired, the
LUTs for the LCD and CRT/TV may be written to simultaneously (REG[1E0h] bit 0 = 0).
Note
Not all combinations of panel and CRT/TV display resolutions are possible. For further
information, see the S1D13506 Hardware Functional Specification, document number
X25B-A-001-xx.
S1D13506
X25B-G-003-03
Programming Notes and Examples
Issue Date: 01/02/06
Epson Research and Development
Vancouver Design Center
Page 99
12 MediaPlug
The S1D13506 is designed with support for MediaPlug. MediaPlug is a digital interface
supporting the Winnov Videum camera. The Videum camera supports simultaneous video
and audio capture of streaming (real-time) and still images. It also supports streaming live
video at speeds near 30 frames per second on fast host systems (i.e. Pentium-2 300MHz or
faster).
12.1 Programming
MediaPlug and the Winnov Videum camera are a proprietary design of Winnov. Due to the
complexity of the digital interface, all software and drivers for the camera are provided by
Winnov. Customers intending to use the MediaPlug interface in their design should contact
Epson Electronics America to obtain the latest S1D13506 MediaPlug drivers for testing
purposes.
The MediaPlug interface on the S1D13506 must be enabled to function correctly. To enable
the MediaPlug interface, MD13 and MD14 must be high (1) on the rising edge of RESET#.
When the MediaPlug interface is enabled, GPIO2 is controlled by the MediaPlug LCMD
register, and the GPIO2 bits in both REG[004h] and REG[008h] have no effect. Also
when the MediaPlug interface is enabled, the camera power (VMPEPWR) is controlled by
MA11/GPIO2 pin.
The MediaPlug LCMD 16-bit register REG[1000h] contains status bits which can be read
by software. For further information on these status bits, see the S1D13506 Hardware
Functional Specification, document number X25B-A-001-xx.
The MediaPlug IC Revision bits (REG[1000h] bits 11-8) contain the revision of the
interface. The 16-bit value read from REG[1000h] should be masked with 0F00h and
compared with 0300h (the current revision of the interface).
The MediaPlug Cable Detected Status bit (REG[1000h] bit 7) determines if a camera is
connected to the MediaPlug interface. When this bit returns a 0, a camera is connected.
When this bit returns a 1, a camera is not connected.
The MediaPlug Power Enable to Remote bit (REG[1000h], bit 1) controls the power to the
remote camera. GPIO2 is controlled by this bit when the MediaPlug interface is enabled.
Therefore, this bit must be used instead of the GPIO2 control bits in REG[004h] and
REG[008h] when programming the external ICD2061A clock chip used on the
S5U13506B00x evaluation boards. Writing this bit is necessary only when software needs
to control the MA11/GPIO2 pin.
Programming Notes and Examples
Issue Date: 01/02/06
S1D13506
X25B-G-003-03
Page 100
Epson Research and Development
Vancouver Design Center
12.2 Considerations
Software can determine if the MediaPlug interface is enabled or disabled by reading the
MD Configuration Readback Register (REG[00Dh]) and masking the data with 60h. If the
masked result equals 60h, the MediaPlug Interface is enabled.
When the MediaPlug interface is enabled, FPDAT[15:8] are used exclusively for the
MediaPlug interface. Therefore, when the MediaPlug interface is enabled, Color 16-bit
panels cannot be used without an external multiplexing circuit. For further information on
the external circuit required, see the S1D13506 Hardware Functional Specification,
document number X25B-A-001-xx.
The MediaPlug interface requires a source clock between 8MHz and 19MHz to operate
(optimal is 14.318MHz). By default, the MediaPlug software assumes a 14.318MHz
frequency is available on CLKI2. If the frequency of CLKI2 is changed, software should
reprogram the MediaPlug Clock Register (REG[01Ch]) to select a clock source that is
suitable, or program the clock divide bits to obtain a frequency within the correct range.
If the S5U13506B00x evaluation board is used, the clock chip should be programmed to
support a valid clock for the MediaPlug interface. The ICD2061A clock chip selects
frequencies based on the states of GPIO1 and GPIO2. Since the MediaPlug interface uses
the GPIO2 pin for camera power, it is important to program the clock chip for the correct
MediaPlug interface frequency when the camera is both on or off (GPIO2 low or high). A
HAL function is available which programs the clock chip for the MediaPlug interface.
S1D13506
X25B-G-003-03
Programming Notes and Examples
Issue Date: 01/02/06
Epson Research and Development
Vancouver Design Center
Page 101
13 Identifying the S1D13506
The S1D13506 can only be identified once the Memory/Register Select bit is set to 0. The
steps to identify the S1D13506 are:
1. Set the Memory/Register Select bit to 0 by writing 00h to REG[001h].
2. Read REG[000h].
3. The production version of the S1D13506 will return a value of 11h (00010001b).
4. The product code is 4 (000100b based on bits 7-2).
5. The revision code is 1 (01b based on bits 1-0).
Programming Notes and Examples
Issue Date: 01/02/06
S1D13506
X25B-G-003-03
Page 102
Epson Research and Development
Vancouver Design Center
14 Hardware Abstraction Layer (HAL)
The HAL is a processor independent programming library designed to help port applications and utilities from one S1D13x0x product to another. Epson has provided this library
as a result of developing test utilities for the S1D13x0x LCD controller products.
The HAL contains functions which are designed to be consistent between S1D13x0x
products, but as the semiconductor products evolve, so must the HAL; consequently there
are some differences between HAL functions for different S1D13x0x products.
Note
As the S1D13x0x line of products changes, the HAL may change significantly or cease
to be a useful tool. Seiko Epson reserves the right to change the functionality of the
HAL or discontinue its use if no longer required.
14.1 API for 13506HAL
This section is a description of the HAL library Application Programmers Interface (API).
Updates and revisions to the HAL may include new functions not included in the following
documentation.
Table 14-1: HAL Functions
Function
Description
Initialization
seRegisterDevice
Registers the S1D13506 parameters with the HAL.
seRegisterDevice MUST be the first HAL function called by an application.
seInitReg
Initializes the registers, LUT, and allocates memory for and assigns.
seGetHalVersion
Returns HAL library version information
seGetId
Identifies the controller by interpreting the revision code register.
seGetLibseVersion
Return version information on the LIBSE libraries (for non-x86 platforms)
General HAL Support:
seGetInstalledMemorySize
Returns the total size of the display buffer memory.
seGetAvailableMemorySize
Determines the last byte of display memory, before the Dual Panel buffer, available to an
application
seGetResolution
seGetLcdResolution
seGetCrtResolution
seGetTvResolution
Retrieve the width and height of the physical display device.
seGetBytesPerScanline
seGetLcdBytesPerScanline
seGetCrtBytesPerScanline
seGetTvBytesPerScanline
Returns the number of bytes in each scanline of the display including non-display size.
seSetSoftwareSuspend
Sets/resets software suspend mode.
seGetSoftwareSuspend
Returns the current software suspend state.
seCheckEndian
Retrieves the “endian-ness” of the host CPU platform.
seGetLcdOrientation
Returns the SwivelView orientation of the LCD panel.
seDelay
Delays the given number of seconds before returning.
S1D13506
X25B-G-003-03
Programming Notes and Examples
Issue Date: 01/02/06
Epson Research and Development
Vancouver Design Center
Page 103
Table 14-1: HAL Functions (Continued)
Function
Description
seDisplayBlank
seDisplayLcdBlank
seDisplayCrtBlank
seDisplayTvBlank
Blank/unblank the display by disabling the FIFO.
seDisplayEnable
seLcdDisplayEnable
seCrtDisplayEnable
seTvDisplayEnable
Enable/disable the display.
seBeginHighPriority
Increase thread priority for time critical routines.
seEndHighPriority
Return thread priority to normal.
seSetClock
Set the programmable clock.
seGetSurfaceDisplayMode
Returns the display surface associated with the active surface.
seGetSurfaceSize
Returns the number of bytes allocated to the active surface.
seGetSurfaceLinearAddress
Returns the linear address of the start of display memory for the active surface.
seGetSurfaceOffsetAddress
Returns the offset from the start of display memory to the start of surface memory.
seAllocLcdSurface
seAllocCrtSurface>
seAllocTvSurface
Use to manually allocate display buffer memory for a surface.
seFreeSurface
Free any allocated surface memory.
seSetLcdAsActiveSurface
seSetCrtAsActiveSurface
seSetTvAsActiveSurface
Call one of these function to change the active surface.
seReadRegByte
Reads one register using a byte access.
seReadRegWord
Reads two registers using a word access.
seReadRegDword
Reads four registers using a dword access.
seWriteRegByte
Writes one register using a byte access.
Advanced HAL Functions:
Surface Support
Register Access:
seWriteRegByte
Writes two registers using a word access.
seWriteRegByte
Writes four registers using a dword access.
Memory Access
seReadDisplayByte
Reads one byte from display memory.
seReadDisplayWord
Reads one word from display memory.
seReadDisplayDword
Reads one dword from display memory.
seWriteDisplayBytes
Writes one or more bytes to display memory.
seWriteDisplayWords
Writes one or more words to display memory.
seWriteDisplayDwords
Writes one or more dwords to display memory.
Color Manipulation:
seWriteLutEntry
seWriteLcdLutEntry
seWriteCrtLutEntry
seWriteTvLutEntry
Programming Notes and Examples
Issue Date: 01/02/06
Writes one RGB element to the lookup table.
S1D13506
X25B-G-003-03
Page 104
Epson Research and Development
Vancouver Design Center
Table 14-1: HAL Functions (Continued)
Function
Description
seReadLutEntry
seReadLcdLutEntry
seReadCrtLutEntry
seReadTvLutEntry
Reads one RGB element from the lookup table.
seWriteLut
seWriteLcdLut
seWriteCrtLut
seWriteTvLut
Write the entire lookup table.
seReadLut
seReadLcdLut
seReadCrtLut
seReadTvLut
Read the entire lookup table.
seSetBitsPerPixel
seSetLcdBitsPerPixel
seSetCrtBitsPerPixel
seSetTvBitsPerPixel
seSetLcdCrtBitsPerPixel
seSetLcdTvBitsPerPixel
Sets the color depth. In addition to setting the control bits to set the color depth this action
sets a default lookup table for the selected color depth.
Virtual Display
seVirtInit
seLcdVirtInit
seCrtVirtInit
seTvVirtInit
seLcdCrtVirtInit
seLcdTvVirtInit
Initialize a surface to hold an image larger than the physical display size.
seVirtPanScroll
seVirtPanScroll
seVirtPanScroll
seVirtPanScroll
seVirtPanScroll
seVirtPanScroll
Pan (right/left) and Scroll (up/down) the display device over the indicated virtual surface.
Drawing
seSetPixel
seSetLcdPixel
seSetCrtPixel
seSetTvPixel
Set one pixel at the specified x,y co-ordinate and color.
seGetPixel
seGetLcdPixel
seGetCrtPixel
seGetTvPixel
Returns the color of the pixel at the specified x,y co-ordinate.
seDrawLine
seDrawLcdLine
seDrawCrtLine
seDrawTvLine
Draws a line between two endpoints in the specified color
seDrawRect
seDrawLcdRect
seDrawCrtRect
seDrawTvRect
Draws a rectangle. The rectangle can be outlined or filled.
S1D13506
X25B-G-003-03
Programming Notes and Examples
Issue Date: 01/02/06
Epson Research and Development
Vancouver Design Center
Page 105
Table 14-1: HAL Functions (Continued)
Function
Description
seDrawCircle
seDrawLcdCircle
seDrawCrtCircle
seDrawTvCircle
Draws a circle of given radius and color at the specified center point.
seDrawEllipse
seDrawLcdEllipse
seDrawCrtEllipse
seDrawTvEllipse
Draws an ellipse centered on a given point with the specified horizontal and vertical
radius.
Hardware Cursor
seInitCursor
seInitLcdCursor
seInitCrtCursor
seInitTvCursor
Prepares the hardware cursor for use.
seFreeCursor
seFreeLcdCursor
seFreeCrtCursor
seFreeTvCursor
Releases the memory allocated to the hardware cursor by the cursor init function.
seEnableCursor
seEnableLcdCursor
seEnableCrtCursor
seEnableTvCursor
Enable (show) or disable (hide) the hardware cursor.
seGetCursorLinearAddress
seGetLcdCursorLinearAddress
seGetCrtCursorLinearAddress
seGetTvCursorLinearAddress
Returns the linear address of the start of the cursor.
seGetCursorOffsetAddress
seGetLcdCursorOffsetAddress
seGetCrtCursorOffsetAddress
seGetTvCursorOffsetAddress
Returns the offset from the start of display memory to the start of the cursor memory.
seMoveCursor
seMoveLcdCursor
seMoveCrtCursor
seMoveTvCursor
Moves the top-left corner of the hardware cursor to the specified x,y co-ordinates.
seSetCursorColor
seSetLcdCursorColor
seSetCrtCursorColor
seSetTvCursorColor
Allows the application to set the color values for either of the two changeable elements of
the hardware cursor.
seSetCursorPixel
seSetLcdCursorPixel
seSetCrtCursorPixel
seSetTvCursorPixel
Set one pixel at the specified x,y co-ordinate within the hardware cursor.
seDrawCursorLine
seDrawLcdCursorLine
seDrawCrtCursorLine
seDrawTvCursorLine
Draws a line between two endpoints within the hardware cursor, in the specified color.
seDrawCursorRect
seDrawLcdCursorRect
seDrawCrtCursorRect
seDrawTvCursorRect
Draws a hollow or filled rectangle within the hardware cursor.
Ink Layer
Programming Notes and Examples
Issue Date: 01/02/06
S1D13506
X25B-G-003-03
Page 106
Epson Research and Development
Vancouver Design Center
Table 14-1: HAL Functions (Continued)
Function
Description
seInitInk
seInitLcdInk
seInitCrtInk
seInitTvInk
Prepares the hardware ink layer for use.
seFreeInk
seFreeLcdInk
seFreeCrtInk
seFreeTvInk
Frees memory allocated to the hardware ink layer.
seEnableInk
seEnableLcdInk
seEnableCrtInk
seEnableTvInk
Enable (show) or disable (hide) the hardware ink layer.
seGetInkLinearAddress
seGetLcdInkLinearAddress
seGetCrtInkLinearAddress
seGetTvInkLinearAddress
Returns the linear address of the start of the hardware ink layer.
seGetInkOffsetAddress
seGetLcdInkOffsetAddress
seGetCrtInkOffsetAddress
seGetTvInkOffsetAddress
Returns the offset from the start of display memory to the start of ink layer memory.
seSetInkColor
seSetLcdInkColor
seSetCrtInkColor
seSetTvInkColor
Allows the application to set the color values for either of the two changeable elements of
the ink layer.
seSetInkPixel
seSetLcdInkPixel
seSetCrtInkPixel
seSetTvInkPixel
Set one pixel at the x,y co-ordinate within the ink layer.
seDrawInkLine
seDrawLcdInkLine
seDrawCrtInkLine
seDrawTvInkLine
Draws a line between two endpoints within the hardware ink layer.
seDrawInkRect
seDrawLcdInkRect
seDrawCrtInkRect
seDrawTvInkRect
Draws an outlined or solid rectangle within the hardware ink layer.
S1D13506
X25B-G-003-03
Programming Notes and Examples
Issue Date: 01/02/06
Epson Research and Development
Vancouver Design Center
Page 107
14.2 Initialization
Initialization functions are normally the first functions in the HAL library that an application calls. These routine allow the application to learn a little about the controller and to
prepare the HAL library for use.
int seRegisterDevice(const LPHAL_STRUC lpHalInfo)
Description:
This function registers the S1D13506 device parameters with the HAL library. The device
parameters include such item as address range, register values, desired frame rate, and
more which are stored in the HAL_STRUCT structure pointed to by lpHalInfo. Additionally this routine allocates system memory as address space for accessing registers and the
display buffer.
Parameters:
lpHalInfo
A pointer to a HAL_STRUCT structure. This structure
must be filled with appropriate values prior to calling
seRegisterDevice.
Return Value:
ERR_OK
operation completed with no problems
ERR_UNKNOWN_DEVICE The HAL was unable to locate the S1D13506.
ERR_FAILED
The HAL was unable to map S1D13506 display memory
to the host platform.
In addition, on Win32 platforms, the following two error values may be returned:
ERR_PCI_DRIVER_NOT_FOUND
The HAL was unable to locate file S1D13X0X.VXD
ERR_PCI_BRIDGE_ADAPTER_NOT_FOUND
The driver file S1D13X0X.VXD was unable to locate the
S1D13506.
Note
seRegisterDevice() MUST be called before any other HAL functions.
Programming Notes and Examples
Issue Date: 01/02/06
S1D13506
X25B-G-003-03
Page 108
Epson Research and Development
Vancouver Design Center
int seInitReg(unsigned DisplayMode, unsigned Flags)
Description:
This function initializes the S1D13506 registers, the LUT, assigns default surfaces and
allocates memory accordingly.
Parameters:
DisplayMode
Set this parameter according to the type of initialization desired.
Valid values for DisplayMode are:
0
LCD
CRT
TV
LCD | CRT
LCD | TV
Flags
Use the values configured by 13506CFG.EXE
Initialize for use with an LCD panel.
Initialize for use with a monitor.
Initialize for use with a TV
Initialize for both LCD panel and monitor.
Initialize for both LCD panel and TV.
Provides additional information about how to perform the initialization.
Valid values for Flags are:
CLEAR_MEMZero display memory as part of the initialization
DISP_BLANKBlank the display, for aesthetics, during initialization.
Return Value:
ERR_OK
ERR_FAILED
The initialization completed with no problems.
seInitReg failed to initialize the system correctly.
void seGetHalVersion(const char ** pVersion, const char ** pStatus, const char
**pStatusRevision)
Description:
Retrieves the HAL library version information. By retrieving and displaying the HAL version information along with application version information it is possible to determine at a
glance whether the latest version of the software is being run.
Parameters:
pVersion
A pointer to the array to receive the HAL version code.
pStatus
A pointer to the array to receive the HAL status code
A “B” designates a beta version of the HAL, a NULL indicates the
release version
pStatusRevision A pointer to the array to receive the HAL revision status.
Return Value:
S1D13506
X25B-G-003-03
The version information is returned as the contents of the pointer arguments. A typical
return might be:
*pVersion == “1.01” (HAL version 1.01)
*pStatus == “B” (BETA release)
*pStatusRevision == “5” (fifth update of the beta)
Programming Notes and Examples
Issue Date: 01/02/06
Epson Research and Development
Vancouver Design Center
Page 109
int seGetId(int * pId)
Description:
Reads the S1D13506 revision code register to determine the controller product and revision.
Parameters:
pId
A pointer to an integer to receive the controller ID. The value returned
is an interpreted version of the controller identification.
For the S1D13506 the return values are:
ID_S1D13506_REV0
ID_S1D13506_REV1
ID_UNKNOWN
Return Value:
ERR_OK
ERR_UNKNOWN_DEVICE
S1D13506 Test Sample version.
S1D13506 Production version
The HAL was unable to identify the controller.
The operation completed with no problems
Return value when pID is ID_UNKNOWN.
Note
seGetId() will disable hardware suspend on x86 platforms, and enables the Memory/Register Select bit (REG[001h] bit 7) on all platforms.
Programming Notes and Examples
Issue Date: 01/02/06
S1D13506
X25B-G-003-03
Page 110
Epson Research and Development
Vancouver Design Center
14.2.1 General HAL Support
This category of HAL functions provide several essential services which do not readily
group with other functions.
DWORD seGetInstalledMemorySize(void)
Description:
This function returns the size of display buffer memory in bytes.
Memory size is determined during the call to seRegisterDevice() by reading the status of
MD6 and MD7. seGetInstalledMemorySize() returns the memory size determined during
the HAL initialization.
Parameters:
None
Return Value:
The return value is the size of the video memory buffer in bytes and will be either 80000h
(512kb) or 200000h (2 MB).
DWORD seGetAvailableMemorySize(void)
Description:
This function returns an offset to the last byte memory, before the Dual Panel buffer,
accessible to an application.
An application can directly access memory from offset zero to the offset returned by this
function. On most systems the return value will be the last byte of physical display memory. On systems configured for a dual STN panel the return value will account for the presence of the Dual Panel buffer.
Parameters:
None.
Return Value:
The return value is an offset to the last byte memory directly accessible to an application.
S1D13506
X25B-G-003-03
Programming Notes and Examples
Issue Date: 01/02/06
Epson Research and Development
Vancouver Design Center
Page 111
int seGetResolution(unsigned *Width, unsigned *Height)
void seGetLcdResolution(unsigned *Width, unsigned *Height)
void seGetCrtResolution(unsigned *Width, unsigned *Height)
void seGetTvResolution(unsigned *Width, unsigned *Height)
Description:
These functions return the width and height of the physical display device. Virtual dimensions are not accounted for in the return value.
seGetResolution() returns the width and height of the active surface. If there is more than
one display associated with the surface then precedence is given to the LCD.
seGetLcdResolution() returns the width and height of the LCD panel. The width and
height are adjusted for SwivelView orientation.
seGetCrtResolution() and seGetTvResolution() return the width and height of the display
indicated by the function name.
Parameters:
Return Value:
Width
A pointer to an unsigned integer which will receive the width, in pixels,
for the indicated surface.
Height
A pointer to an unsigned integer which will receive the height, in pixels,
for the indicated surface.
seGetResolution() returns one of the following:
ERR_OK
ERR_FAILED
Function completed successfully
Returned when there is not an active display surface.
seGetLcdResolution(), seGetCrtResolution(), and seGetTvResolution() do not return any
value.
unsigned seGetBytesPerScanline(void)
unsigned seGetLcdBytesPerScanline(void)
unsigned seGetTvBytesPerScanline(void)
unsigned seGetCrtBytesPerScanline(void)
Description:
These functions return the number of bytes per scanline, including both displayed and
non-displayed for the current video mode.
seGetBytesPerScanline() returns the number of bytes per scanline for the current active
surface.
seGetLcdBytesPerScanline(), seGetTvBytesPerScanline(), and seGetCrtBytesPerScanline() return the number of bytes per scanline for the surface indicated in the function
name.
To work correctly the S1D13505 registers have been initialized prior to calling any of
these routines.
Parameters:
None.
Return Value:
The return value is the “stride” or number of bytes from the first byte of one scanline to the
first byte of the next scanline. This value includes both the displayed and the non-displayed bytes on each logical scanline.
For rotated display modes the return value will be either 1024 (8 bpp) or 2048 (15/16 bpp)
to reflect the 1024 x 1024 virtual area of the rotated memory.
Programming Notes and Examples
Issue Date: 01/02/06
S1D13506
X25B-G-003-03
Page 112
Epson Research and Development
Vancouver Design Center
void seSetSoftwareSuspend(BOOL Enable)
Description:
This function enables or disables software power suspend.
When software suspend is enabled the S1D13506 reduces power consumption by making
the displays inactive and ignoring memory accesses. Disabling software suspend reenables the video system to full functionality.
Parameters:
Enable
Return Value:
None.
Call with Enable set to TRUE to set software power suspend
Call with Enable set to FALSE to disable software power suspend.
BOOL seGetSoftwareSuspend(void)
Description:
seGetSoftwareSuspend() returns the current state of software power suspend.
Parameters:
None.
Return Value:
The return value is TRUE if software suspend is enabled. The return FALSE if software
suspend is not enabled.
int seCheckEndian(BOOL *ReverseBytes)
Description:
This function returns the “endian-ness” of the CPU the application is running on.
Parameters:
ReverseBytes
Return Value:
The return value is always ERR_OK.
A pointer to boolean value to receive the endian-ness of the system. On
return from this function ReverseBytes is FALSE if the CPU is little
endian (i.e. Intel). ReverseBytes will be TRUE if the CPU is
big-endian (i.e. Motorola)
unsigned seGetLcdOrientation(void)
Description:
This function retrieves the SwivelView orientation of the LCD display.
The SwivelView status is read directly from the S1D13506 registers. Calling this function
when the LCD display is not enabled will result in an erroneous return a value.
Note
Only the LCD interface supports SwivelView. A CRT/TV is always assumed to be in
LANDSCAPE mode.
Parameters:
None.
Return Value:
LANDSCAPE
ROTATE90
ROTATE180
ROTATE270
S1D13506
X25B-G-003-03
Not rotated.
Display is rotated 90 degrees clockwise.
Display is rotated 180 degrees clockwise.
Display is rotated 270 degrees.
Programming Notes and Examples
Issue Date: 01/02/06
Epson Research and Development
Vancouver Design Center
Page 113
int seDelay(DWORD Seconds)
Description:
This function, intended for non-Intel platforms, delays for the specified number of seconds
then returns to the calling routine. On several evaluation platforms it was not readily
apparent where to obtain an accurate source of time delays. seDelay() was the result of the
need to delay a specified amount of time on these platforms.
seDelay works by calculating and counting the number of vertical non-display periods in
the requested delay time. This implies two conditions for proper operation:
a) The S1D13506 control registers must be configured to correct values.
b) Either the CRT or LCD display interface must be enabled.
On Intel and other supported platforms seDelay() calls the C library time functions to
delay the desired amount of time.
Parameters:
Seconds
The number of seconds to delay for.
Return Value:
ERR_OK
ERR_FAILED
Returned by all platforms at the completion of a successful delay.
Returned by platforms which do not have time functions in their
standard C library and either of the operating conditions is violated.
void seDisplayBlank(BOOL Blank)
void seDisplayLcdBlank(BOOL Blank)
void seDisplayCrtBlank(BOOL Blank)
void seDisplayTvBlank(BOOL Blank)
Description:
These functions blank the display by disabling the FIFO for the specified surface. Blanking the display is a fast convenient means of temporarily shutting down a display device
For instance updating the entire display in one write may produce a flashing or tearing
effect. If the display is blanked prior to performing the update then the operation is perceived to be smoother and cleaner.
seDisplayBlank() will blank the display associated with the current active surface.
seDisplayLcdBlank(), seDisplayCrtBlank(), and seDisplayTvBlank() blank the display for
the surface indicated in the function name.
Parameters:
Blank
Return Value:
None.
Programming Notes and Examples
Issue Date: 01/02/06
Call with Blank set to TRUE to blank the display. Call with Blank set to
FALSE to un-blank the display.
S1D13506
X25B-G-003-03
Page 114
Epson Research and Development
Vancouver Design Center
void seDisplayEnable(BOOL Enable)
void seLcdDisplayEnable(BOOL Enable)
void seCrtDisplayEnable(BOOL Enable)
void seTvDisplayEnable(BOOL Enable)
Description:
These functions enable or disable the selected display device.
seDisplayEnable() enables or disables the display for the active surface.
seLcdDisplayEnable() enables or disables the LCD display.
seCrtDisplayEnable() enables or disables the CRT display. seCrtDisplayEnable() will disable CRT/TV PCLK 2X clock and as a side effect will disable TV, if the TV was enabled.
seTvDisplayEnable() enables or disables the TV display. If the CRT is enabled then seTvDisplayEnable() disables it. When seTvDisplayEnable is called the TV flicker filter is
enabled or disabled based on the values saved by the configuration program.
Parameters:
Enable
Return Value:
None.
S1D13506
X25B-G-003-03
Call with Enable set to TRUE to enable the display device. Call with
Enable set to FALSE to disable the device.
Programming Notes and Examples
Issue Date: 01/02/06
Epson Research and Development
Vancouver Design Center
Page 115
14.2.2 Advance HAL Functions
The advanced HAL functions include a level of access that most applications don’t will
never need to access.
int seBeginHighPriority(void)
Description:
Writing and debugging software under the Windows operating system greatly simplifies
the developing process for the S1D13506 evaluation system. One issue which impedes
application programming is that of latency. Time critical operations, performance measurement for instance, are not guaranteed any set amount of processor time.
This function raises the priority of the thread and virtually eliminates the question of
latency for programs running on a Windows platform.
Note
The application should not leave it’s thread running in a high priority state for long periods of time. As soon as a time critical operation is complete the application should call
seEndHighPriorty().
Parameters:
None.
Return Value:
ERR_OK
If the function completes successfully.
int seEndHighPriority(void)
Description:
The function returns the thread priority of the calling application to normal.
After performing some time critical operation the application should call seEndHighPriority() to return the thread priority to a normal level.
Parameters:
None.
Return Value:
None.
Programming Notes and Examples
Issue Date: 01/02/06
S1D13506
X25B-G-003-03
Page 116
Epson Research and Development
Vancouver Design Center
int seSetClock(CLOCKSELECT ClockSelect, FREQINDEX FreqIndex)
Description:
Call seSetClock() to set the clock rate of the programmable clock.
Parameters:
ClockSelect
The ICD2061A programmable clock chip supports two output clock
signals. ClockSelect chooses which of the two output clocks to adjust.
Valid ClockSelect values are defined by the HAL contents CLKI or
CLKI2
FreqIndex
FreqIndex is an enumerated constant and determines what the output
frequency should be.
Valid values for FreqIndex are:
FREQ_6000
FREQ_10000
FREQ_14318
FREQ_17734
FREQ_20000
FREQ_24000
FREQ_25000
FREQ_25175
FREQ_28318
FREQ_30000
FREQ_31500
FREQ_32000
FREQ_33000
FREQ_33333
FREQ_34000
FREQ_35000
FREQ_36000
FREQ_40000
FREQ_49500
FREQ_50000
FREQ_56250
FREQ_65000
FREQ_80000
Return Value:
ERR_OK
ERR_FAILED
6.000 MHz
10.000 MHz
14.318 MHz
17.734 MHz
20.000 MHz
24.000 MHz
25.000 MHz
25.175 MHz
28.318 MHz
30.000 MHz
31.500 MHz
32.000 MHz
33.000 MHz
33.333 MHz
34.000 MHz
35.000 MHz
36.000 MHz
40.000 MHz
49.500 MHz
50.000 MHz
56.250 MHz
65.000 MHz
80.000 MHz
The function completed with no problems.
seSetClock failed the cause may be an invalid ClockSelect or an
invalid frequency index
Note
If seSetClock is called with a ClockSelect of CLKI2 and FreqIndex of FREQ_17734
then the HAL will bypass the programmable clock and select the Feature Clock as the
input clock source. This is done with the assumption that the application is setting up for
TV output and the Feature Clock oscillator will provide a more stable clock for use with
TV. (The feature oscillator must be 17.734 MHz)
S1D13506
X25B-G-003-03
Programming Notes and Examples
Issue Date: 01/02/06
Epson Research and Development
Vancouver Design Center
Page 117
14.2.3 Surface Support
The S1D13506 HAL library depends heavily on the concept of surfaces. Through surfaces
the HAL tracks memory requirements of the attached display devices, hardware cursor and
ink layers, and the Dual Panel buffer.
Surfaces allow the HAL to permit or fail function calls which change the geometry of the
S1D13506 display memory. Most HAL functions either allocate surface memory or manipulate a surface that has been allocated.
The functions in this sections allow the application programmer a little greater control over
surfaces.
int seGetSurfaceDisplayMode(void)
Description:
This function determines the type of display associated with the current active surface.
Parameters:
None.
Return Value:
The return value indicates the active surface display type. Return values will be one of:
LCD
CRT
TV
The LCD panel is the active surface.
The CRT display is the active surface.
The TV is the active display.
DWORD seGetSurfaceSize(void)
Description:
This function returns the number of display memory bytes allocated to the current active
surface. The return value does not account for the size for the hardware cursor or ink layer
which may be associated with the surface.
Parameters:
None.
Return Value:
The return value is the number of bytes allocated to the current active surface.
The return value can be 0 if this function is called before initializing and making active a
surface.
DWORD seGetSurfaceLinearAddress(void)
Description:
This function returns the linear address of the start of memory for the active surface.
Parameters:
None.
Return Value:
The return value is the linear address to the start of memory for the active surface. A linear
address is a 32-bit offset, in CPU address space.
The return value will be NULL if this function is called before a surface has been initialized and made active.
Note
On 16-bit Intel platforms, this function will always return NULL. The PCI memory may
be located beyond the addressing range of 16-bit programs so all S1D13505 controller
accesses must be made through the HAL.
Programming Notes and Examples
Issue Date: 01/02/06
S1D13506
X25B-G-003-03
Page 118
Epson Research and Development
Vancouver Design Center
DWORD seGetSurfaceOffsetAddress(void)
Description:
This function returns the offset, from the first byte of display memory to the first byte of
memory associated with the active display surface.
Parameters:
None.
Return Value:
The return value is the offset, in bytes, from the start of display memory to the start of the
active surface. An address of 0 indicates the surface starts in the first byte of display buffer
memory.
Note
This function also returns 0 if there is no memory allocated to an active surface. You
must ensure that memory is allocated before calling seGetSurfaceOffsetAddress().
DWORD seAllocLcdSurface(DWORD Size)
DWORD seAllocCrtSurface(DWORD Size)
DWORD seAllocTvSurface(DWORD Size)
Description:
These functions allocate display buffer memory for a surface. If the surface previously had
memory allocated then that memory is first released. Newly allocated memory is not
cleared.
Call seAllocLcdSurface(), seAllocCrtSurface(), and seAllocTvSurface() to allocate the
requested amount of display memory for the indicated surface.
These functions allow an application to bypass the automatic surface allocation which
occurs when functions such as seInitReg() or seSetBitsPerPixel() are called.
Parameters:
Size
The size in bytes of the requested memory block.
Return Value:
If the memory allocation succeeds then the return value is the linear address of the allocated memory. If the allocation fails then the return value is 0. A linear address is a 32-bit
offset, in CPU address space.
int seFreeSurface(DWORD LinearAddress)
Description:
This function can be called to free any previously allocated display buffer memory.
This function is intended to complement seAllocLcdSurface(), seAllocCrtSurface(), and
seAllocTvSurface(). seFreeSurface can be used to free memory allocated for the hardware
cursor and ink layer however it is recommended that seFreeCursor() or seFreeInk() be
called for these surfaces.
After calling one of these functions the application must switch the active surface to one
which has memory allocated before calling any drawing functions.
Parameters:
LinearAddress
A valid linear address. The linear address is a dword returned to the
application by any surface allocation call.
Return Value:
ERR_OK
ERR_FAILED
Function completed successfully.
Function failed.
S1D13506
X25B-G-003-03
Programming Notes and Examples
Issue Date: 01/02/06
Epson Research and Development
Vancouver Design Center
Page 119
void seSetLcdAsActiveSurface(void)
void seSetCrtAsActiveSurface(void)
void seSetTvAsActiveSurface(void)
Description:
These functions set the active surface to the display indicated in the function name.
Before calling one of these surface selection routines, that surface must have been allocated using any of the surface allocation methods.
Parameters:
None.
Return Value:
None.
Programming Notes and Examples
Issue Date: 01/02/06
S1D13506
X25B-G-003-03
Page 120
Epson Research and Development
Vancouver Design Center
14.2.4 Register Access
The Register Access functions provide convenient method of accessing the control
registers of the S1D13506 controller using byte, word or dword widths.
To reduce the overhead of the function call as much as possible, two steps were taken:
• To gain maximum efficiency on all compilers and platforms, byte and word size arguments are passed between the application and the HAL as unsigned integers. This typically allows a compiler to produce more efficient code for the platform.
• Index alignment for word and dword accesses is not tested. On non-Intel platforms
attempting to access a word or dword on a non-aligned boundary may result in a
processor trap. It is the responsibility of the caller to ensure that the requested index
offset is correctly aligned for the target platform.
unsigned seReadRegByte(DWORD Index)
Description:
This routine reads the register specified by Index and returns the value.
Parameters:
Index
Return Value:
The return value is the byte read from the register.
Offset, in bytes, to the register to read.
unsigned seReadRegWord(DWORD Index)
Description:
This routine read two consecutive registers as a word and returns the value.
Parameters:
Index
Return Value:
The return value is the word read from the S1D13506 registers.
Offset to the first register to read.
DWORD seReadRegDword(DWORD Index)
Description:
This routine reads four consecutive registers as a dword and returns the value.
Parameters:
Index
Return Value:
The return value is the dword read from the S1D13506 registers.
Offset to the first of the four registers to read.
int seWriteRegByte(DWORD Index, unsigned Value)
Description:
This routine writes Value to the register specified by Index.
Parameters:
Index
Offset to the register to be written
Value
The value, in the least significant byte, to write to the register
Return Value:
S1D13506
X25B-G-003-03
None
Programming Notes and Examples
Issue Date: 01/02/06
Epson Research and Development
Vancouver Design Center
Page 121
void seWriteRegWord(DWORD Index, unsigned Value)
Description:
This routine writes the word contained in Value to the specified index.
Parameters:
Index
Offset to the register pair to be written.
Value
The value, in the least significant word, to write to the registers.
Return Value:
None.
void seWriteRegDword(DWORD Index, DWORD Value)
Description:
This routine writes the value specified to four registers starting at Index.
Parameters:
Index
Offset to the register to be written to.
Value
The dword value to be written to the registers.
Return Value:
None.
Programming Notes and Examples
Issue Date: 01/02/06
S1D13506
X25B-G-003-03
Page 122
Epson Research and Development
Vancouver Design Center
14.2.5 Memory Access
The Memory Access functions provide convenient method of accessing the display
memory on an S1D13506 controller using byte, word or dword widths.
To reduce the overhead of these function calls as much as possible, two steps were taken:
• To gain maximum efficiency on all compilers and platforms, byte and word size arguments are passed between the application and the HAL as unsigned integers. This typically allows a compiler to produce more efficient code for the platform.
• Offset alignment for word and dword accesses is not tested. On non-Intel platforms
attempting to access a word or dword on a non-aligned boundary may result in a
processor trap. It is the responsibility of the caller to ensure that the requested offset is
correctly aligned for the target platform.
unsigned seReadDisplayByte(DWORD Offset)
Description:
Reads a byte from the display buffer memory at the specified offset and returns the value.
Parameters:
Offset
Return Value:
The return value, in the least significant byte, is the byte read from display memory.
Offset, in bytes, from start of the display buffer to the byte to read.
unsigned seReadDisplayWord(DWORD Offset)
Description:
Reads one word from display buffer memory at the specified offset and returns the value.
Parameters:
Offset
Return Value:
The return value, in the least significant word, is the word read from display memory.
Offset, in bytes, from start of the display buffer to the word to read.
DWORD seReadDisplayDword(DWORD Offset)
Description:
Reads one dword from display buffer memory at the specified offset and returns the value.
Parameters:
Offset
Return Value:
The DWORD read from display memory.
Offset, in bytes, from start of the display buffer to the dword to read.
void seWriteDisplayBytes(DWORD Offset, unsigned Value, DWORD Count)
Description:
This routine writes one or more bytes to the display buffer at the offset specified by Offset.
Parameters:
Offset
Offset, in bytes, from start of display memory to the first byte to be
written.
Value
An unsigned integer containing the byte to be written in the least
significant byte.
Count
Number of bytes to write. All bytes will have the same value.
Return Value:
S1D13506
X25B-G-003-03
None.
Programming Notes and Examples
Issue Date: 01/02/06
Epson Research and Development
Vancouver Design Center
Page 123
Note
If ((Offset + Count) > memory size) then this function limits the writes to the end of display memory.
void seWriteDisplayWords(DWORD Offset, unsigned Value, DWORD Count)
Description:
This routine writes one or more words to display memory starting at the specified offset.
Parameters:
Offset
Offset, in bytes, from the start of display memory to the first word to
write.
Value
An unsigned integer containing the word to written in the least
significant word
Count
Number of words to write. All words will have the same value.
Return Value:
None.
Note
If ((Offset + (Count * 2)) > memory size) then this function limits the writes to the end
of display memory.
void seWriteDisplayDwords(DWORD Offset, DWORD Value, DWORD Count)
Description:
This routine writes one or more dwords to display memory starting at the specified offset.
Parameters:
Offset
Return Value:
Value
Offset, in bytes, from the start of display memory to the first dword to
write.
The value to be written to display memory.
Count
Number of dwords to write. All dwords will have the same value.
None.
Note
If ((Offset + (Count * 4)) > memory size) then this function limits the writes to the end
of display memory.
Programming Notes and Examples
Issue Date: 01/02/06
S1D13506
X25B-G-003-03
Page 124
Epson Research and Development
Vancouver Design Center
14.2.6 Color Manipulation
The functions in the Color Manipulation section deal with altering the color values in the
Look-Up Table directly through the accessor functions and indirectly through the color
depth setting functions.
Keep in mind that all lookup table data is contained in the upper nibble of each byte.
void seWriteLutEntry(int Index, BYTE *pRGB)
void seWriteLcdLutEntry(int Index, BYTE *pRGB)
void seWriteCrtLutEntry(int Index, BYTE *pRGB)
void seWriteTvLutEntry(int Index, BYTE *pRGB)
¦Description:
These routines write one lookup table entry to the specified index of the lookup table.
seWriteLutEntry() writes to the specified index of the current active surface. See seSetLcdAsActiveSurface(), seSetCrtAsActiveSurface() and seSetTvAsActiveSurface() for
information about changing the active surface.
seWriteLcdLutEntry(), seWriteCrtLutEntry() and seWriteTvLutEntry() modify one entry
of the lookup table of the surface indicated in by the function name.
Parameter:
Return Value:
S1D13506
X25B-G-003-03
Index
Offset to the lookup table entry to be modified. (i.e. a 0 will write the
first entry and a 255 will write the last lookup table entry)
pRGB
A pointer to byte array of data to write to the lookup table. The array
must consist of three bytes; the first byte contains the red value the
second byte contains the green value and the third byte contains the
blue value.
None
Programming Notes and Examples
Issue Date: 01/02/06
Epson Research and Development
Vancouver Design Center
Page 125
void seReadLutEntry(int Index, BYTE *pRGB)
void seReadLcdLutEntry(int Index, BYTE *pRGB)
void seReadCrtLutEntry(int Index, BYTE *pRGB)
void seReadTvLutEntry(int Index, BYTE *pRGB)
¦Description:
These routines read one lookup table entry and return the results in the byte array pointed
to by pRGB.
seReadLutEntry() reads the specified index from the lookup table of the current active surface. See seSetLcdAsActiveSurface(), seSetCrtAsActiveSurface() and seSetTvAsActiveSurface() for information about changing the active surface.
seReadLcdLutEntry(), seReadCrtLutEntry(), and seReadTvLutEntry() read one entry
form the lookup table for the surface indicated by the function name.
Parameter:
Return Value:
Index
Offset to the lookup table entry to be read. (i.e. setting index to 2 will
return a the value of the third element of the lookup table)
pRGB
A pointer to an array to receive the lookup table data. The array must be
at least three bytes long. On return from this function the first byte of
the array will contain the red data, the second byte will contain the
green data and the third byte will contain the blue data.
None.
void seWriteLut(BYTE *pRGB, int Count)
void seWriteLcdLut(BYTE *pRGB, int Count)
void seWriteCrtLut(BYTE *pRGB, int Count)
void seWriteTvLut(BYTE *pRGB, int Count)
¦Description:
These routines write one or more lookup table entries starting at offset zero.
seWriteLut() modifies Count entries in the current active surface. See seSetLcdAsActiveSurface(), seSetCrtAsActiveSurface() and seSetTvAsActiveSurface() for information
about changing the active surface.
seWriteLcdLut(), seWriteCrtLut(), and seWriteTvLut() modifies the lookup table for the
surface indicated in the function name.
This routine is intended to allow setting as many lookup table entries as the current color
depth allows in call.
Parameter:
Return Value:
pRGB
A pointer to an array of lookup table entry values to write to the LUT.
Each lookup table entry must consist of three bytes. The first byte must
contain the red value, the second byte must contain the green value and
the third byte must contain the blue value to modify the lookup table
with.
Count
The number of lookup table entries to modify.
None.
Programming Notes and Examples
Issue Date: 01/02/06
S1D13506
X25B-G-003-03
Page 126
Epson Research and Development
Vancouver Design Center
void seReadLut(BYTE *pRGB, int Count)
void seReadLcdLut(BYTE *pRGB, int Count)
void seReadCrtLut(BYTE *pRGB, int Count)
void seReadTvLut(BYTE *pRGB, int Count)
¦Description:
This routine reads one or more lookup table entries and returns the result in the array
pointed to by pRGB. The read always begins at the first lookup table entry.
seReadLut() reads the first Count lookup table entries from the current active surface. See
seSetLcdAsActiveSurface(), seSetCrtAsActiveSurface() and seSetTvAsActiveSurface()
for information about changing the active surface.
seReadLcdLut(), seReadCrtLut(), and seReadTvLut() read the first Count entries from the
surface indicated by the function name.
This routine allows reading all the lookup table elements used by the current color depth in
one library call.
Parameters:
Return Value:
pRGB
A pointer to an array of bytes large enough to hold the requested
number of lookup table entries. Each lookup table entry consists of
three bytes; the first byte will contain the red data, the second the green
data and the third the blue data.
Count
The number of lookup table entries to read.
None.
DWORD seSetBitsPerPixel(unsigned BitsPerPixel)
DWORD seSetLcdBitsPerPixel(unsigned BitsPerPixel)
DWORD seSetCrtBitsPerPixel(unsigned BitsPerPixel)
DWORD seSetTvBitsPerPixel(unsigned BitsPerPixel)
DWORD seSetLcdCrtBitsPerPixel(unsigned BitsPerPixel)
DWORD seSetLcdTvBitsPerPixel(unsigned BitsPerPixel)
Description:
These functions change the color depth of the display and update the appropriate LUT.
Display memory is automatically released and then reallocated as necessary for the display size.
seSetBitsPerPixel() changes the bits-per-pixel mode for the active surface. Memory is
reassigned according to the descriptions for each of the following mode sets.
seSetLcdBitsPerPixel() changes the bits-per-pixel mode for the panel display. This function uses the current register settings for SwivelView to determine the amount of memory
to allocate, and what starting register addresses are required.
Note
seSetLcdBitsPerPixel() frees CRT/TV memory in order to guarantee the LCD image
starts at the beginning of display buffer memory.
seSetCrtBitsPerPixel() and seSetTvBitsPerPixel() change the bits-per-pixel mode for the
indicated display device. These functions ignore the rotate90 and rotate180 register bits.
Memory is allocated only for the landscape mode.
S1D13506
X25B-G-003-03
Programming Notes and Examples
Issue Date: 01/02/06
Epson Research and Development
Vancouver Design Center
Page 127
seSetLcdCrtBitsPerPixel() and seSetLcdTvBitsPerPixel() change the color depth for a surface which combines LCD and CRT/TV. Portrait (SwivelView 90) is disabled. If the display resolution is not the same for the two displays then memory is allocated based on the
larger of the two.
IMPORTANT
When the LCD color depth is changed, memory allocated for the display buffer and ink
layer/hardware cursors is freed and the display buffer memory is reassigned. The application must redraw the display and re-initialize the cursor/ink and redraw after calling seSetBitsPerPixel().
seSetLcdCrtBitsPerPixel(), and seSetLcdTvBitsPerPixel() will free all allocated memory
for all displays and all ink layers/hardware cursors, then allocate memory only for the display(s) mentioned in the function name. The cursor/ink must be re-initialized and restored
after making one of these calls.
If the active surface is the panel then seSetBitsPerPixel() will free all allocated memory
for all displays and all ink layers/hardware cursors, then allocate memory ONLY for the
active surface (LCD). If the active surface is the CRT or TV, seSetBitsPerPixel() will free
memory only for the active surface (CRT or TV), and then reallocate memory for this surface as required.
Parameters:
BitsPerPixel
The new color depth. BitsPerPixel can be one of the following:
4, 8, 15, 16.
Return Value:
The return value is the thirty-two bit offset to the start of the surface display memory. If
there is an error the return value is 0. A linear address is the 32-bit offset, in CPU address
space, where the application can directly read or write display memory.
The thirty-two bit address must be converted to a segment:offset for use with a 16-bit Intel
platform.
unsigned seGetBitsPerPixel(void)
unsigned seGetLcdBitsPerPixel(void)
unsigned seGetCrtBitsPerPixel(void)
unsigned seGetTvBitsPerPixel(void);
Description:
These functions returns the current color depth for a the associated display surface.
seGetBitsPerPixel() returns the color depth for the current active surface.
seGetLcdBitsPerPixel(), seGetCrtBitsPerPixel(), and seGetTvBitsPerPixel() return the
color depth for the surface indicated in the function name.
Parameters:
None.
Return Value:
The color depth of the surface. This value will be 4, 8, 15 or 16.
Programming Notes and Examples
Issue Date: 01/02/06
S1D13506
X25B-G-003-03
Page 128
Epson Research and Development
Vancouver Design Center
14.2.7 Virtual Display
int seVirtInit(DWORD Width, DWORD Height)
int seLcdVirtInit(DWORD Width, DWORD Height)
int seCrtVirtInit(DWORD Width, DWORD Height)
int seTvVirtInit(DWORD Width, DWORD Height)
int seLcdCrtVirtInit(DWORD Width, DWORD Height)
int seLcdTvVirtInit(DWORD Width, DWORD Height)
Description:
These functions prepare the S1D13506 for displaying a virtual image.
“Virtual Image” describes the condition where the image contained in display memory is
larger than the physical display. In this situation the display surface is used as a window
into the larger display memory area. Panning (right/left) and scrolling (up/down) are used
move the display surface in order to view the entire image a portion at a time.
seVirtInit() prepares the current active surface for virtual image display. Memory is allocated based on width, height and the current color depth.
seLcdVirtInit initializes and allocates memory for the LCD based on width and height and
color depth. If the panel surface is rotated 90 or 270 degrees then the height is limited to a
maximum 1024 lines.
seCrtVirtInit and seTvVirtInit initialize and allocate memory for the given display based
on current width and height and color depth.
seLcdCrtVirtInit and seLcdTvVirtInit initialize and allocate memory for a surface which
combines both LCD and CRT/TV. Memory is allocated based on the requirements of the
larger of the two surfaces (if different). If the panel surface is rotated 90 or 270 degrees
then the height is limited to a maximum of 1024 lines.
Memory previously allocated for this surface is released then reallocated to the larger size.
Parameters:
Width
The desired virtual width of the display in pixels.
Width must be a multiple of the number of pixels contained in one word
of display memory. At 15/16 bit per pixel Width may be any value. At 8
bit per pixel Width must be a multiple of two and at 4 bit per pixel
Width must be a multiple of four.
Height
The desired virtual height of the display in pixels.
The HAL performs internal memory management to ensure that all
display surfaces and cursor/ink layer have sufficient memory for
operation. The Height parameter is required so the HAL can determine
the amount of memory the application requires for the virtual image.
Return Value:
ERR_OK
The function completed successfully.
ERR_HAL_BAD_ARG
The requested virtual dimensions are smaller than
the physical display size.
ERR_NOT_ENOUGH_MEMORY There is insufficient free display memory to set the
requested virtual display size.
S1D13506
X25B-G-003-03
Programming Notes and Examples
Issue Date: 01/02/06
Epson Research and Development
Vancouver Design Center
Page 129
void seVirtPanScroll(DWORD x, DWORD y)
void seLcdVirtPanScroll(DWORD x, DWORD y)
void seCrtVirtPanScroll(DWORD x, DWORD y)
void seTvVirtPanScroll(DWORD x, DWORD y)
void seLcdCrtVirtPanScroll(DWORD x, DWORD y)
void seLcdTvVirtPanScroll(DWORD x, DWORD y)
Description:
When displaying a virtual image the display surface is smaller than the virtual image contained in display memory. In order to view the entire image the display is treated as a window into the virtual image.
These functions allow an application to pan (right and left) and scroll (up and down) the
display over the virtual image.
seVirtPanScroll() will pan and scroll the current active surface.
seLcdVirtPanScroll(), seCrtVirtPanScroll(), seTvVirtPanScroll(), seLcdCrtVirtPanScroll(), and seLcdTvVirtPanScroll() will pan and scroll the surface indicated in the function name.
Parameters:
Return Value:
x
The new x offset, in pixels, of the upper left corner of the display.
y
The new y offset, in pixels, of the upper left corner of the display.
None.
Programming Notes and Examples
Issue Date: 01/02/06
S1D13506
X25B-G-003-03
Page 130
Epson Research and Development
Vancouver Design Center
14.2.8 Drawing
Functions in this category perform primitive drawing on the specified display surface.
Supported drawing primitive include pixels, lines, rectangles, ellipses and circles.
void seSetPixel(long x, long y, DWORD Color)
void seSetLcdPixel(long x, long y, DWORD Color)
void seSetCrtPixel(long x, long y, DWORD Color)
void seSetTvPixel(long x, long y, DWORD Color)
Description:
These routines set a pixel at the location x,y with the specified color.
Use seSetPixel() to set one pixel on the current active surface. See seSetLcdAsActiveSurface(), seSetCrtAsActiveSurface() and seSetTvAsActiveSurface() for information about
changing the active surface.
Use seSetLcdPixel(), seSetCrtPixel(), and seSetTvPixel() to set one pixel on the surface
indicated in the function name.
Parameters:
x
The X co-ordinate, in pixels, of the pixel to set.
y
The Y co-ordinate, in pixels, of the pixel to set.
Color
Specifies the color to draw the pixel with. Color is interpreted
differently at different color depths.
At 4 and 8 bit per pixel display colors are derived from the lookup table
values. The least significant byte of Color forms an index into the
lookup table.
At 15 and 16 bit per pixel the lookup table is bypassed and each word of
display memory forms the color to display. At 15 bit per pixel the least
significant word directly represents the color to draw the pixel with as a
5-5-5 RGB value with the most significant bit of the word discarded. In
16 bit per pixel display mode the least significant word describes the
color to draw the pixel with in 5-6-5 RGB format.
Return Value:
S1D13506
X25B-G-003-03
None.
Programming Notes and Examples
Issue Date: 01/02/06
Epson Research and Development
Vancouver Design Center
Page 131
DWORD seGetPixel(long x, long y)
DWORD seGetLcdPixel(long x, long y)
DWORD seGetCrtPixel(long x, long y)
DWORD seGetTvPixel(long x, long y)
Description:
Returns the pixel color at the specified display location
Use seGetPixel() to read the pixel color at the specified x,y co-ordinates on the current
active surface. See seSetLcdAsActiveSurface(), seSetCrtAsActiveSurface() and
seSetTvAsActiveSurface() for information about changing the active surface.
Use seGetLcdPixel(), seGetCrtPixel(), and seGetTvPixel() to read the pixel color at the
specified x,y co-ordinate on the display surface referenced in the function name.
Parameters:
Return Value:
x
The X co-ordinate, in pixels, of the pixel to read
y
The Y co-ordinate, in pixels, of the pixel to read
The return value is a dword describing the color read at the x,y co-ordinate. Color is interpreted differently at different color depths.
At 4 and 8 bit per pixel, display colors are derived from the lookup table values. The return
value is an index into the lookup table. The red, green and blue components of the color
can be determined by reading the lookup table values at the returned index.
At 15 and 16 bit per pixel the lookup table is bypassed and each word of display memory
form the color to display. At 15 bit per pixel the least significant word of the return value
directly represents the color of the pixel as a 5-5-5 RGB value with the most significant bit
of the word discarded. In 16 bit per pixel display mode the least significant word of the
return value describes the color as a 5-6-5 RGB value.
Programming Notes and Examples
Issue Date: 01/02/06
S1D13506
X25B-G-003-03
Page 132
Epson Research and Development
Vancouver Design Center
void seDrawLine(long x1, long y1, long x2, long y2, DWORD Color)
void seDrawLcdLine(long x1, long y1, long x2, long y2, DWORD Color)
void seDrawCrtLine(long x1, long y1, long x2, long y2, DWORD Color)
void seDrawTvLine(long x1, long y1, long x2, long y2, DWORD Color)
Description:
These functions draw a line between two points in the specified color.
Use seDrawLine() to draw a line on the current active surface. See seSetLcdAsActiveSurface(), seSetCrtAsActiveSurface() and seSetTvAsActiveSurface() for information about
changing the active surface.
Use seDrawLcdLine(), seDrawCrtLine(), and seDrawTvLine() to draw a line on the surface referenced by the function name
Parameters:
x1
The X co-ordinate, in pixels, of the first endpoint of the line to be
drawn.
y1
The Y co-ordinate, in pixels, or the first endpoint of the line to be
drawn.
x2
The X co-ordinate, in pixels, of the second endpoint of the line to be
drawn.
y2
The Y co-ordinate, in pixels, of the second endpoint of the line to be
drawn.
Color
Specifies the color to draw the line with. Color is interpreted differently
at different color depths.
At 4 and 8 bit per pixel display colors are derived from the lookup table
values. The least significant byte of Color is an index into the lookup
table.
At 15 and 16 bit per pixel the lookup table is bypassed and each word of
display memory forms the color to display. At 15 bit per pixel the least
significant word directly represents the color to draw the line with as a
5-5-5 RGB value with the most significant bit of the word discarded. In
16 bit per pixel display mode the least significant word describes the
color to draw the line with in 5-6-5 RGB format.
Return Value:
S1D13506
X25B-G-003-03
None.
Programming Notes and Examples
Issue Date: 01/02/06
Epson Research and Development
Vancouver Design Center
Page 133
void seDrawRect(long x1, long y1, long x2, long y2, DWORD Color, BOOL SolidFill)
void seDrawLcdRect(long x1, long y1, long x2, long y2, DWORD Color, BOOL SolidFill)
void seDrawCrtRect(long x1, long y1, long x2, long y2, DWORD Color, BOOL SolidFill)
void seDrawTvRect(long x1, long y1, long x2, long y2, DWORD Color, BOOL SolidFill)
Description:
These routines draw a rectangle on the screen in the specified color. The rectangle is
bounded on the upper left by the co-ordinate x1,y1 and on the lower right by the co-ordinate x2,y2. The SolidFill parameter allows the programmer to select whether to fill the
interior or the rectangle or to only draw the border.
Use seDrawRect() to draw a rectangle on the current active display surface.See seSetLcdAsActiveSurface(), seSetCrtAsActiveSurface() and seSetTvAsActiveSurface() for
information about changing the active surface.
Use seDrawLcdRect(), seDrawCrtRect(), and seDrawTvRect() to draw a rectangle on the
display surface indicated by the function name.
Parameters:
x1
The X co-ordinate, in pixels, of the upper left corner of the rectangle.
y1
The Y co-ordinate, in pixels, of the upper left corner of the rectangle.
x2
The X co-ordinate, in pixels, of the lower right corner of the rectangle.
y2
The Y co-ordinate, in pixels, of the lower right corner of the rectangle.
Color
Specifies the color to draw the line with. Color is interpreted differently
at different color depths.
At 4 and 8 bit per pixel display colors are derived from the lookup table
values. The least significant byte of Color is an index into the lookup
table.
At 15 and 16 bit per pixel the lookup table is bypassed and each word of
display memory forms the color to display. At 15 bit per pixel the least
significant word directly represents the color to draw the line with as a
5-5-5 RGB value with the most significant bit of the word discarded. In
16 bit per pixel display mode the least significant word describes the
color to draw the line with in 5-6-5 RGB format.
SolidFill
A boolean value specifying whether to fill the interior of the rectangle.
Set to FALSE “0” to draw only the rectangle border. Set to TRUE
“non-zero” to instruct this routine to fill the interior of the rectangle.
Return Value:
None
Programming Notes and Examples
Issue Date: 01/02/06
S1D13506
X25B-G-003-03
Page 134
Epson Research and Development
Vancouver Design Center
void seDrawCircle(long xCenter, long yCenter, long Radius, DWORD Color)
void seDrawLcdCircle(long xCenter, long yCenter, long Radius, DWORD Color)
void seDrawCrtCircle(long xCenter, long yCenter, long Radius, DWORD Color)
void seDrawTvCircle(long xCenter, long yCenter, long Radius, DWORD Color)
Description:
These routines draw a circle on the screen in the specified color. The circle is centered at
the co-ordinate x,y and is drawn with the specified radius and Color. Circles cannot be
solid filled.
Use seDrawCircle() to draw the circle on the current active display surface. See seSetLcdAsActiveSurface(), seSetCrtAsActiveSurface() and seSetTvAsActiveSurface() for
information about changing the active surface.
Use seDrawLcdCircle(), seDrawCrtCircle(), seDrawTvCircle() draw the circle on the display surface indicated by the function name
Parameters:
x
The X co-ordinate, in pixels, of the center of the circle.
y
The Y co-ordinate, in pixels, or the center of the circle.
Radius
Specifies the radius of the circle in pixels.
Color
Specifying the color to draw the circle. Color is interpreted
differently at different color depths.
At 4 and 8 bit per pixel display colors are derived from the lookup table
values. The least significant byte of Color is an index into the lookup
table.
At 15 and 16 bit per pixel the lookup table is bypassed and each word of
display memory forms the color to display. At 15 bit per pixel the least
significant word directly represents the color to draw the circle with as a
5-5-5 RGB value with the most significant bit of the word discarded. In
16 bit per pixel display mode the least significant word describes the
color to draw the circle with in 5-6-5 RGB format.
Return Value:
S1D13506
X25B-G-003-03
None.
Programming Notes and Examples
Issue Date: 01/02/06
Epson Research and Development
Vancouver Design Center
Page 135
void seDrawEllipse(long xc, long yc, long xr, long yr, DWORD Color)
void seDrawLcdEllipse(long xc, long yc, long xr, long yr, DWORD Color)
void seDrawCrtEllipse(long xc, long yc, long xr, long yr, DWORD Color)
void seDrawTvEllipse(long xc, long yc, long xr, long yr, DWORD Color)
Description:
These routines draw an ellipse on the screen in the specified color. The circle is centered at
the co-ordinate x,y and is drawn in the specified color with the indicated radius for the x
and y axis. Ellipses cannot be solid filled.
Use seDrawEllipse() to draw the circle on the current active display surface. See seSetLcdAsActiveSurface(), seSetCrtAsActiveSurface() and seSetTvAsActiveSurface() for
information about changing the active surface.
Use seDrawLcdEllipse(), seDrawCrtEllipse(), seDrawTvEllipse() draw the ellipse on the
display surface indicated by the function name
Parameters:
xc
The X co-ordinate, in pixels, of the center of the ellipse.
yc
The Y co-ordinate, in pixels, of the center of the ellipse.
xr
A long integer specifying the X radius of the ellipse, in pixels.
yr
A long integer specifying the Y radius of the ellipse, in pixels.
Color
A dword specifying the color to draw the ellipse. Color is interpreted
differently at different color depths.
At 4 and 8 bit per pixel display colors are derived from the lookup table
values. The least significant byte of Color is an index into the lookup
table.
At 15 and 16 bit per pixel the lookup table is bypassed and each word of
display memory forms the color to display. At 15 bit per pixel the least
significant word directly represents the color to draw the ellipse with as
a 5-5-5 RGB value with the most significant bit of the word discarded.
In 16 bit per pixel display mode the least significant word describes the
color to draw the circle with in 5-6-5 RGB format.
Return Value:
None.
Programming Notes and Examples
Issue Date: 01/02/06
S1D13506
X25B-G-003-03
Page 136
Epson Research and Development
Vancouver Design Center
14.2.9 Hardware Cursor
The routines in this section support hardware cursor. Most of the calls look similar to
normal drawing calls (i.e. seDrawCursorLine()); however, these calls remove the
programmer from having to know the particulars of the cursor memory location, layout and
whether portrait mode is enabled.
The same S1D13506 uses the same hardware for both hardware cursor and ink layer which
means that only the cursor or the ink layer can be active at any given time.The difference
between the hardware cursor and the ink layer is that in cursor mode the image is a
maximum of 64x64 pixels and can be moved around the display while in ink layer mode
the image is as large as the physical size of the display and is fixed in position. Both the ink
layer and hardware cursor have the same number of colors and handle these colors identically.
DWORD seInitCursor(void)
DWORD seInitLcdCursor(void)
DWORD seInitCrtCursor(void)
DWORD seInitTvCursor(void)
Description:
These functions allocate cursor memory, fills the cursor image with a transparent block,
and enable the cursor. If memory was previously allocated for the cursor, this memory is
first released.
The S1D13506 supports two independent hardware cursors, one on a panel surface and
one on the CRT/TV surface.
Use seInitCursor() to initialize the cursor for the active surface.
Use seInitLcdCursor(), seInitCrtCursor(), and seInitTvCursor() initialize the cursor on the
display surface indicated in the function name.
Parameters:
None.
Return Value:
The return value is the thirty-two bit offset to the start of the hardware cursor memory. If
there is an error the return value is 0.
Note
On a 16-bit DOS the return value must be converted into a segment:offset before use.
S1D13506
X25B-G-003-03
Programming Notes and Examples
Issue Date: 01/02/06
Epson Research and Development
Vancouver Design Center
Page 137
void seFreeCursor(void)
void seFreeLcdCursor(void)
void seFreeCrtCursor(void)
void seFreeTvCursor(void)
Description:
These functions release memory allocated to the hardware cursor by seInitCursor() functions.
Use seFreeCursor() to free the hardware cursor memory for the current active surface.
Use seFreeLcdCursor(), seFreeCrtCursor(), and seFreeTvCursor() to free the resources
associated with the surface indicated by the function name.
Parameters:
None.
Return Value:
None.
void seEnableCursor(int Enable)
void seEnableLcdCursor(int Enable)
void seEnableCrtCursor(int Enable)
void seEnableTvCursor(int Enable)
Description:
These functions enable or disable the hardware cursor. When enabled the cursor will be
visible on the display surface. When disabled the cursor will not be displayed.
Call seEnableCursor() to enable/disable the hardware cursor of the active surface.
Call seEnableLcdCursor(), seEnableCrtCursor(), and seEnableTvCursor() to enable/disable the hardware cursor for the surface indicated by the function name.
Recall that the CRT and TV share the same cursor. Enabling/disabling the cursor for one
device will affect the other display as well.
Parameters:
Enable
A flag indicating whether to enable or disable the hardware cursor.
Call with Enable set to FALSE “0” to disable the hardware cursor for
the surface. Call with Enable set to TRUE “non-0” to enable the
hardware cursor for the device.
Return Value:
None.
Programming Notes and Examples
Issue Date: 01/02/06
S1D13506
X25B-G-003-03
Page 138
Epson Research and Development
Vancouver Design Center
DWORD seGetCursorLinearAddress(void)
DWORD seGetLcdCursorLinearAddress(void)
DWORD seGetCrtCursorLinearAddress(void)
DWORD seGetTvCursorLinearAddress(void)
Description:
These routines return address for the hardware cursor through which the application can
directly access the cursor memory.
Call seGetCursorLinearAddress() to retrieve the address of the hardware cursor associated
with the current active surface.
Call seGetLcdCursorLinearAddress(), seGetCrtCursorLinearAddress(), or seGetTvCursorLinearAddress() to retrieve the address of the hardware cursor associated with the display surface indicated by the function name.
Parameters:
None.
Return Value:
The return value is the linear address of the hardware cursor. A linear address is the 32 bit
offset in CPU address space where the application can directly read or write the hardware
cursor.
DWORD seGetCursorOffsetAddress(void)
DWORD seGetLcdCursorOffsetAddress(void)
DWORD seGetCrtCursorOffsetAddress(void)
DWORD seGetTvCursorOffsetAddress(void)
Description:
These routines return the offset in display memory of the hardware cursor. Using this offset the application can use HAL API calls such as seSetWriteDisplayBytes() to access the
hardware cursor image.
Call seGetCursorOffsetAddress() to get the offset to the hardware cursor associated with
the current active surface.
Call seGetLcdCursorOffsetAddress(), seGetCrtCursorOffsetAddress(), and seGetTvCursorOffsetAddress() to retrieve the offset to the hardware cursor for the surface indicated in
the function name.
Parameters:
None.
Return Value:
The return value is the offset, in bytes, from the start of display memory to the start of the
hardware cursor.
S1D13506
X25B-G-003-03
Programming Notes and Examples
Issue Date: 01/02/06
Epson Research and Development
Vancouver Design Center
Page 139
void seMoveCursor(long x, long y)
void seMoveLcdCursor(long x, long y)
void seMoveCrtCursor(long x, long y)
void seMoveTvCursor(long x, long y)
Description:
These routines are move where the hardware cursor is shown on the display surface.
Call seMoveCursor() to move the hardware cursor on the current active surface.
Call seMoveLcdCursor(), seMoveCrtCursor(), and seMoveTvCursor() to move the hardware cursor associated with the surface indicated in the function name.
Parameter:
Return Value:
x
The desired display surface X co-ordinate, in pixels, of the upper left
corner of the cursor.
y
The desired display surface Y co-ordinate, in pixels, of the upper left
corner of the cursor.
None.
void seSetCursorColor(int Index, DWORD Color)
void seSetLcdCursorColor(int Index, DWORD Color)
void seSetCrtCursorColor(int Index, DWORD Color)
void seSetTvCursorColor(int Index, DWORD Color)
Description:
These routines allow the user to set the either of the two user definable colors.
The hardware cursor can be thought of as a four color image. Two of the colors cannot be
changed. Displaying these two colors in a cursor image will always result in transparent
and inverse video being displayed.
The remaining two colors can be changed.
Call seSetCursorColor() to change the cursor colors for the current active surface.
Call seSetLcdCursorColor(), seSetCrtCursorColor(), or seSetTvCursorColor() to change
the color for the surface associated with the function name.
Parameters:
Index
Specifies which of the two application changeable colors this operation
is to affect.
Legal values for Index are 0 and 1.
Color
The new color to set as the hardware cursor color.
The color values in the dword are arranged as follows:
xxxx xxxx xxxR RRRR xxGG GGGG xxxB BBB
Where x is don’t care (set to 0), R is five bits of red intensity, G is six
bits of green intensity and B is five bits of blue intensity.
Return Value:
None.
Programming Notes and Examples
Issue Date: 01/02/06
S1D13506
X25B-G-003-03
Page 140
Epson Research and Development
Vancouver Design Center
void seSetCursorPixel(long x, long y, DWORD Color)
void seSetLcdCursorPixel(long x, long y, DWORD Color)
void seSetCrtCursorPixel(long x, long y, DWORD Color)
void seSetTvCursorPixel(long x, long y, DWORD Color)
Description:
These functions are intended for drawing in the hardware cursor area a pixel at a time.
Call seSetCursorPixel() to set a pixel in the cursor associated with the current active surface.
Call seSetLcdCursorPixel(), seSetCrtCursorPixel(), and seSetTvCursorPixel() to set pixels
in the cursor associated with the display surface indicated in the function name.
Parameters:
x
The X co-ordinate of the cursor, in pixels, at which to set the pixel color.
Valid values for x range from 0 to 63.
y
The Y co-ordinate of the cursor, in pixels, a which to set the pixel color.
Valid values for y range from 0 to 63.
Color
Specifies which of the four cursor colors set the pixel to. Valid values
for Color are:
0 - to set the pixel to the solid color 0
1 - to set the pixel to the solid color 1
2 - to set the pixel to the transparent color
3 - to set the pixel to the inverted color.
Return Value:
S1D13506
X25B-G-003-03
None.
Programming Notes and Examples
Issue Date: 01/02/06
Epson Research and Development
Vancouver Design Center
Page 141
void seDrawCursorLine(long x1, long y1, long x2, long y2, DWORD Color)
void seDrawLcdCursorLine(long x1, long y1, long x2, long y2, DWORD Color)
void seDrawCrtCursorLine(long x1, long y1, long x2, long y2, DWORD Color)
void seDrawTvCursorLine(long x1, long y1, long x2, long y2, DWORD Color)
Description:
These routines assist in defining the cursor shape by drawing a line in the hardware cursor
between the specified points.
Call seDrawCursorLine() to draw a line in the hardware cursor image associated with the
current active surface.
Call seDrawLcdCursorLine(), seDrawCrtCursorLine(), or seDrawTvCursorLine() to draw
a line in the hardware cursor image associated with the display surface indicated in the
function name.
Parameter:
x1
Specifies the X co-ordinate of the first endpoint of the line measured in
pixels from the left edge of the cursor image.
y1
Specifies the Y co-ordinate of the first endpoint of the line measured in
pixels from the top edge of the cursor image.
x2
Specifies the X co-ordinate of the second endpoint of the line measured
in pixels from the left edge of the cursor image.
y2
Specifies the Y co-ordinate of the second endpoint of the line measured
in pixels from the top edge of the cursor image.
Color
Specifies which of the four cursor colors to draw the line with. Valid
values for Color are:
0 - to draw the line in solid color 0
1 - to draw the line in solid color 1
2 - to draw the line in the transparent color
3 - to draw the line in the inverted color.
Return Value:
None.
Programming Notes and Examples
Issue Date: 01/02/06
S1D13506
X25B-G-003-03
Page 142
Epson Research and Development
Vancouver Design Center
void seDrawCursorRect(long x1, long y1, long x2, long y2, DWORD color, BOOL SolidFIll)
void seDrawLcdCursorRect(long x1, long y1, long x2, long y2, DWORD color, BOOL SolidFill)
void seDrawCrtCursorRect(long x1, long y1, long x2, long y2, DWORD color, BOOL SolidFill)
void seDrawTvCursorRect(long x1, long y1, long x2, long y2, DWORD color, BOOL SolidFill)
Description:
These routines draw rectangles on the hardware cursor surface. The rectangle may be
drawn as just a border or as a solid filled area.
Call seDrawCursorRect() to draw a rectangle in the hardware cursor image associated
with the current active surface.
Call seDrawLcdCursorRect(), seDrawCrtCursorRect(), or seDrawTvCursorRect() to draw
a rectangle in the hardware cursor image associated with the display surface indicated by
the function name.
Parameter:
x1
The X co-ordinate for the top left corner of the rectangle measured in
pixels from the left edge of the cursor image.
y1
The Y co-ordinate for the top left corner of the rectangle measured in
pixels from the top of the cursor image.
x2
The X co-ordinate for the bottom right corner of the rectangle measured
in pixels from the left edge of the cursor image.
y2
The Y co-ordinate for the bottom right corner of the rectangle measured
in pixels from the top edge of the cursor image.
Color
Specifies which of the four cursor colors to draw the line with. Valid
values for Color are:
0 - to draw the rectangle in solid color 0
1 - to draw the rectangle in solid color 1
2 - to draw the rectangle to the transparent color
3 - to draw the rectangle in the inverted color.
SolidFill
Flags whether to fill the rectangle as or to only draw the border.
Set SolidFill to FALSE (“0”) to draw only the outline of the rectangle.
Set SolidFill to TRUE (“1”) to fill the interior of the rectangle.
Return Value:
S1D13506
X25B-G-003-03
None.
Programming Notes and Examples
Issue Date: 01/02/06
Epson Research and Development
Vancouver Design Center
Page 143
14.2.10 Ink Layer
The functions in this section support the hardware ink layer. These functions are nearly
identical to the routines to control the hardware cursor.
The same S1D13506 uses the same hardware for both hardware cursor and ink layer which
means that only the cursor or the ink layer can be active at any given time.The difference
between the hardware cursor and the ink layer is that in cursor mode the image is a
maximum of 64x64 pixels and can be moved around the display while in ink layer mode
the image is as large as the physical size of the display and is fixed in position. Both the ink
layer and hardware cursor have the same number of colors and handle these colors identically.
DWORD seInitInk(void)
DWORD seInitLcdInk(void)
DWORD seInitCrtInk(void)
DWORD seInitTvInk(void)
Description:
These functions initialize the ink layer for use. The initialization includes: allocating ink
layer memory, filling the ink layer image with a transparent color, and enabling the ink
layer.
If memory was previously allocated for the ink layer or a hardware cursor on the surface
then this memory is first released.
Call seInitInk() to initialize the ink layer for the current active surface.
Call seInitLcdInk(), seInitCrtInk(), and seInitTvInk() to initialize the ink layer for the surface indicated in the display name.
Parameters:
None.
Return Value:
The return value is the thirty-two bit offset in CPU address space to the start of the ink
layer memory. If there is an error the return value is 0.
Note
On 16-bit DOS systems the return value must be converted into a segment:offset before
use.
Programming Notes and Examples
Issue Date: 01/02/06
S1D13506
X25B-G-003-03
Page 144
Epson Research and Development
Vancouver Design Center
void seFreeInk(void)
void seFreeLcdInk(void)
void seFreeCrtInk(void)
void seFreeTvInk(void)
Description:
These functions release the memory allocations made by the call to the seInitInk() calls.
Prior to calling the seFreeInk() functions the application must make a call to seEnableInk() to hide the ink layer.
Call seFreeInk() to Free the ink layer memory associated with the current active surface.
Call seFreeLcdInk(), seFreeCrtInk(), or seFreeTvInk() to free the ink layer memory associated with the surface indicated in the function name.
Parameters:
None.
Return Value:
None.
void seEnableInk(int Enable)
void seEnableLcdInk(int Enable)
void seEnableCrtInk(int Enable)
void seEnableTvInk(int Enable)
Description:
These functions enable or disable the hardware ink layer. When enabled the ink layer will
be visible and when disabled the ink layer will be hidden.
Call seEnableInk() to enable/disable the ink layer associated with the current active surface.
Call seEnableLcdInk(), seEnableCrtInk(), and seEnableTvInk() to enable/disable the hardware ink layer for the surface indicated by the function name.
Recall that the CRT and TV share the same ink layer. Enabling/disabling the ink layer for
one device will affect the other display as well.
Parameters:
Enable
A flag indicating whether to enable or disable the ink layer.
Set Enable to FALSE (0) to disable the ink layer or set Enable to TRUE (non-0) to enable
the ink layer.
Return Value:
S1D13506
X25B-G-003-03
None.
Programming Notes and Examples
Issue Date: 01/02/06
Epson Research and Development
Vancouver Design Center
Page 145
DWORD seGetInkLinearAddress(void)
DWORD seGetLcdInkLinearAddress(void)
DWORD seGetCrtInkLinearAddress(void)
DWORD seGetTvInkLinearAddress(void)
Description:
These routines return address for the hardware ink layer through which the application can
directly access the ink layer memory.
Call seGetInkLinearAddress() to retrieve the address of the ink layer associated with the
current active surface.
Call seGetLcdInkLinearAddress(), seGetCrtInkLinearAddress(), or seGetTvInkLinearAddress() to retrieve the address of the ink layer associated with the display surface indicated
in the function name.
Parameters:
None.
Return Value:
The return value is the linear address of the hardware cursor. A linear address is the 32 bit
offset in CPU address space where the application can directly read or write the hardware
ink layer memory
DWORD seGetInkOffsetAddress(void)
DWORD seGetLcdInkOffsetAddress(void)
DWORD seGetCrtInkOffsetAddress(void)
DWORD seGetTvInkOffsetAddress(void)
Description:
These routines return the offset in display memory of the hardware ink layer. Using this
offset an application can use HAL API calls such as seSetWriteDisplayBytes() to access
the ink layer memory.
Call seGetInkOffsetAddress() to get the offset to the ink layer associated with the current
active surface.
Call seGetLcdInkOffsetAddress(), seGetCrtInkOffsetAddress(), and seGetTvInkOffsetAddress() to retrieve the offset to the ink layer for the surface indicated in the function
name.
Parameters:
None.
Return Value:
The return value is the offset, in bytes, from the start of display memory to the start of ink
layer memory.
Programming Notes and Examples
Issue Date: 01/02/06
S1D13506
X25B-G-003-03
Page 146
Epson Research and Development
Vancouver Design Center
void seSetInkColor(int index, DWORD color)
void seSetLcdInkColor(int index, DWORD color)
void seSetCrtInkColor(int index, DWORD color)
void seSetTvInkColor(int index, DWORD color)
Description:
These routines allow the user to set the either of the two user definable hardware ink layer
colors.
The hardware ink layer can be thought of as a four color image of which only two colors
can be changed. The non-changeable colors will displays as transparent and inverted colors.
Call seSetInkColor() to change the in colors for the current active surface.
Call seSetLcdInkColor(), seSetCrtInkColor(), or seSetTvInkColor() to change the color
for the surface indicated by the function name.
Parameters:
Index
Index to specifies which of the two changeable colors to access. Valid
values for Index are 0 and 1.
Color
The new color to set as the ink layer color.
The color values in the dword are arranged as follows:
xxxx xxxx xxxR RRRR xxGG GGGG xxxB BBB
Where x is don’t care (set to 0), R is five bits of red intensity, G is six
bits of green intensity and B is five bits of blue intensity.
Return Value:
None.
void seSetInkPixel(long x, long y, DWORD color)
void seSetLcdInkPixel(long x, long y, DWORD color)
void seSetCrtInkPixel(long x, long y, DWORD color)
void seSetTvInkPixel(long x, long y, DWORD color)
Description:
These functions are intended for drawing on the hardware ink layer a pixel at a time.
Call seSetInkPixel() to set a pixel in the ink layer associated with the current active surface.
Call seSetLcdInkPixel(), seSetCrtInkPixel(), and seSetTvInkPixel() to set pixels in the ink
layer associated with the display surface indicated in the function name.
Parameters:
x
The X co-ordinate of the ink layer, in pixels, at which to set the pixel
color. Valid values for x range from 0 to display width - 1.
y
The Y co-ordinate of the ink layer, in pixels, a which to set the pixel
color. Valid values for y range from 0 to display height - 1.
Color
Specifies which of the four cursor colors set the pixel to. Valid values
for Color are:
0 - to set the pixel to the solid color 0
1 - to set the pixel to the solid color 1
2 - to set the pixel to the transparent color
3 - to set the pixel to the inverted color.
Return Value:
S1D13506
X25B-G-003-03
None.
Programming Notes and Examples
Issue Date: 01/02/06
Epson Research and Development
Vancouver Design Center
Page 147
void seDrawInkLine(long x1, long y1, long x2, long y2, DWORD color)
void seDrawLcdInkLine(long x1, long y1, long x2, long y2, DWORD color)
void seDrawCrtInkLine(long x1, long y1, long x2, long y2, DWORD color)
void seDrawTvInkLine(long x1, long y1, long x2, long y2, DWORD color)
Description:
These routines draw lines on the hardware ink layer between two points in the specified
color.
Call seDrawInkLine() to draw a line in the hardware ink layer associated with the current
active surface.
Call seDrawLcdInkLine(), seDrawCrtInkLine(), or seDrawTvInkLine() to draw a line in
the hardware ink layer image associated with the display surface indicated in the function
name.
Parameter:
x1
Specifies the X co-ordinate of the first endpoint of the line measured in
pixels from the left edge of the display.
y1
Specifies the Y co-ordinate of the first endpoint of the line measured in
pixels from the top edge of the display.
x2
Specifies the X co-ordinate of the second endpoint of the line measured
in pixels from the left edge of the display.
y2
Specifies the Y co-ordinate of the second endpoint of the line measured
in pixels from the top edge of the display.
Color
Specifies which of the four ink layer colors to draw the line with. Valid
values for Color are:
0 - to draw the line in solid color 0
1 - to draw the line in solid color 1
2 - to draw the line in the transparent color
3 - to draw the line in the inverted color.
Return Value:
None.
Programming Notes and Examples
Issue Date: 01/02/06
S1D13506
X25B-G-003-03
Page 148
Epson Research and Development
Vancouver Design Center
void seDrawInkRect(long x1, long y1, long x2, long y2, DWORD color, BOOL SolidFill)
void seDrawLcdInkRect(long x1, long y1, long x2, long y2, DWORD color, BOOL SolidFill)
void seDrawCrtInkRect(long x1, long y1, long x2, long y2, DWORD color, BOOL SolidFill)
void seDrawTvInkRect(long x1, long y1, long x2, long y2, DWORD color, BOOL SolidFIll)
Description:
These routines draw rectangles on the hardware ink layer surface. The rectangle may be
drawn as just a border or as a solid filled area.
Call seDrawInkRect() to draw a rectangle in the hardware ink layer cursor image associated with the current active surface.
Call seDrawLcdInkRect(), seDrawCrtInkRect(), or seDrawTvInkRect() to draw a rectangle in the hardware ink layer associated with the display surface indicated by the function
name.
Parameter:
x1
The X co-ordinate for the top left corner of the rectangle measured in
pixels from the left edge of the display surface.
y1
The Y co-ordinate for the top left corner of the rectangle measured in
pixels from the top edge of the display surface.
x2
The X co-ordinate for the bottom right corner of the rectangle measured
in pixels from the left edge of the display surface.
y2
The Y co-ordinate for the bottom right corner of the rectangle measured
in pixels from the top edge of the display surface.
Color
Specifies which of the four ink layer colors to draw the line with. Valid
values for Color are:
0 - to draw the rectangle in solid color 0
1 - to draw the rectangle in solid color 1
2 - to draw the rectangle to the transparent color
3 - to draw the rectangle in the inverted color.
SolidFill
Flags whether to fill the rectangle as or to only draw the border.
Set SolidFill to FALSE (“0”) to draw only the outline of the rectangle.
Set SolidFill to TRUE (“1”) to fill the interior of the rectangle.
Return Value:
S1D13506
X25B-G-003-03
None.
Programming Notes and Examples
Issue Date: 01/02/06
Epson Research and Development
Vancouver Design Center
Page 149
14.2.11 PCI Support
The S1D13506 utilizes up to two megabytes of display memory. Addressing that much
memory on Intel ISA based evaluation platforms is difficult and prone to introducing
conflicts. To overcome these obstacles the standard PCI evaluation boar is PCI based.
By placing the S1D13506 evaluation board on a PCI bus the issue of address space is eliminated. In addition 32 bit software can be written and debugged in a Microsoft Windows
environment before being ported to an embedded platform.
In order for an application to access the S1D13506 memory and register the following two
functions are provided.
DWORD seGetLinearDisplayAddress(void)
Description:
This function returns the linear address for the start of physical display memory on a PCI
system
Parameters:
None.
Return Value:
The return value is the linear address of the start of display memory. A linear address is a
32-bit offset, in CPU address space.
DWORD seGetLinearRegAddress(void)
Description:
This function returns the linear address of the start of S1D13506 control registers.
Parameters:
None.
Return Value:
The return value is the linear address of the start of S1D13506 control registers. A linear
address is a 32-bit offset, in CPU address space.
Programming Notes and Examples
Issue Date: 01/02/06
S1D13506
X25B-G-003-03
Page 150
Epson Research and Development
Vancouver Design Center
14.3 Porting LIBSE to a new target platform
Building Epson applications like a simple HelloApp for a new target platform requires 3
things, the HelloApp code, the 13506HAL library, and a some standard C functions
(portable ones are encapsulated in our mini C library LIBSE).
HelloApp Source code
HelloApp
C Library Functions (LIBSE for embedded platforms)
13506HAL Library
Figure 14-1: Components needed to build 13506 HAL application
For example, when building HELLOAPP.EXE for the x86 16-bit platform, you need the
HELLOAPP source files, the 13506HAL library and its include files, and some Standard C
library functions (which in this case would be supplied by the compiler as part of its runtime library). As this is a DOS .EXE application, you do not need to supply start-up code
that sets up the chip selects or interrupts, etc... What if you wanted to build the application
for an SH-3 target, one not running DOS?
Before you can build that application to load onto the target, you need to build a C library
for the target that contains enough of the Standard C functions (like sprintf and strcpy) to
let you build the application. Epson supplies the LIBSE for this purpose, but your compiler
may come with one included. You also need to build the 13506HAL library for the target.
This library is the graphics chip dependent portion of the code. Finally, you need to build
the final application, linked together with the libraries described earlier. The following
examples assume that you have a copy of the complete source code for the S1D13506
utilities, including the nmake makefiles, as well as a copy of the GNU Compiler v2.7-96q3a
for Hitachi SH3. These are available on the Epson Electronics America Website at
http://www.eea.epson.com.
S1D13506
X25B-G-003-03
Programming Notes and Examples
Issue Date: 01/02/06
Epson Research and Development
Vancouver Design Center
Page 151
14.3.1 Building the LIBSE library for SH3 target example
In the LIBSE files, there are three main types of files:
• C files that contain the library functions.
• assembler files that contain the target specific code.
• makefiles that describe the build process to construct the library.
The C files are generic to all platforms, although there are some customizations for targets
in the form of #ifdef LCEVBSH3 code (the ifdef used for the example SH3 target Low Cost
Eval Board SH3). The majority of this code remains constant whichever target you build
for.
The assembler files contain some platform setup code (stacks, chip selects) and jumps into
the main entry point of the C code that is contained in the C file entry.c. For our example,
the assembler file is STARTSH3.S and it performs only some stack setup and a jump into
the code at _mainEntry (entry.c).
In the embedded targets, printf (in file rprintf.c), putchar (putchar.c) and getch (kb.c)
resolve to serial character input/output. For SH3, much of the detail of handling serial IO
is hidden in the monitor of the evaluation board, but in general the primitives are fairly
straight forward, providing the ability to get characters to/from the serial port.
For our target example, the nmake makefile is makesh3.mk. This makefile calls the Gnu
compiler at a specific location (TOOLDIR), enumerates the list of files that go into the
target and builds a .a library file as the output of the build process.
With nmake.exe in your path run:
nmake -fmakesh3.mk
14.3.2 Building a complete application for the target example
Source code for this example is available in the file 56_sh3_target.c. This file is available
on the internet at www.eea.epson.com.
Programming Notes and Examples
Issue Date: 01/02/06
S1D13506
X25B-G-003-03
Page 152
Epson Research and Development
Vancouver Design Center
15 Sample Code
Example source code demonstrating programming the S1D13506 using the HAL library is
availble on the internet at www.eea.epson.com. Also included are three header files that
may make some of the structures used clearer.
S1D13506
X25B-G-003-03
Programming Notes and Examples
Issue Date: 01/02/06
S1D13506 Register Summary
X25B-R-001-02
REG[000h] REVISION CODE REGISTER 2 (For S1D13506: Product Code=000100b, Revision Code=01b)RO
Product Code
Bit 5
Bit 4
Bit 3
Revision Code
Bit 2
Bit 1
Bit 0
Bit 1
Reserved
Reserved
RW
REG[032h] LCD HORIZONTAL DISPLAY WIDTH REGISTER
n/a
Bit 0
LCD Horizontal Display Width
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RW
REG[034h] LCD HORIZONTAL NON-DISPLAY PERIOD REGISTER
1/0
REG[001h] MISCELLANEOUS REGISTER
Register/
Memory
Select
n/a
n/a
n/a
n/a
RW
Reserved
n/a
n/a
LCD Horizontal Non-Display Period
n/a
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RW
REG[035h] TFT FPLINE START POSITION REGISTER
REG[004h] GENERAL I/O P INS CONFIGURATION REGISTER 3
Reserved
Reserved
Reserved
Reserved
1/0
RW
n/a
GPIO3 Pin
I/O Config
GPIO2 Pin
I/O Config
GPIO1 Pin
I/O Config
GPIO3 Pin
I/O Status
GPIO2 Pin
I/O Status
GPIO1 Pin
I/O Status
Reserved
Reserved
Reserved
Reserved
MD[2]
Status
MD[1]
Status
MD[0]
Status
RW
RW
REG[00Ch] MD CONFIGURATION READBACK REGISTER 0
MD[7]
Status
MD[6]
Status
MD[5]
Status
MD[4]
Status
MD[3]
Status
RW
REG[00Dh] MD CONFIGURATION READBACK REGISTER 1
MD[15]
Status
MD[14]
Status
MD[13]
Status
MD[12]
Status
MD[11]
Status
MD[10]
Status
MD[9]
Status
MD[8]
Status
n/a
n/a
MCLK
Divide Slct
n/a
LCD PCLK Divide Select
Bit 1
Bit 0
n/a
n/a
n/a
MCLK
Source Slct
RW
n/a
n/a
Bit 1
Bit 0
RW
CRT/TV PCLK Divide Slct
n/a
Bit 1
Bit 0
n/a
n/a
Bit 1
n/a
n/a
Bit 1
Bit 0
n/a
RW
n/a
Bit 0
MediaPlug Clock Source
Select
Bit 1
Bit 0
REG[01Eh] CPU TO MEMORY WAIT STATE S ELECT REGISTER 11
n/a
n/a
n/a
n/a
n/a
n/a
CPU to Memory Wait State
Select
Bit 0
REG[020h] MEMORY CONFIGURATION REGISTER 12
n/a
n/a
n/a
LCD
FPLINE
Polarity Slct
Bit 0
n/a
n/a
n/a
n/a
Bit 7
Bit 4
n/a
n/a
n/a
Bit 2
Bit 1
Page 1
n/a
n/a
n/a
Bit 3
Bit 2
Bit 1
n/a
RW
n/a
n/a
n/a
n/a
Bit 2
Bit 1
Bit 0
RW
LCD Display FIFO Low Threshold
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RW
CRT/TV Horizontal Display Width
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RW
REG[052h] CRT/TV HORIZONTAL NON-D ISPLAY PERIOD REGISTER
n/a
CRT/TV Horizontal Non-Display Period
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
REG[053h] CRT/TV HRTC START POSITION REGISTER
n/a
Bit 0
LCD Vertical Display
Height
Bit 3
REG[050h] CRT/TV HORIZONTAL DISPLAY WIDTH REGISTER
n/a
Bit 9
RW
CRT/TV HRTC Start Position
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
REG[054h] CRT HRTC PULSE WIDTH REGISTER
CRT HRTC
Polarity Slct
n/a
n/a
n/a
RW
CRT HRTC Pulse Width
Bit 3
Bit 2
Bit 1
Bit 0
Bit 8
REG[056h] CRT/TV VERTICAL DISPLAY HEIGHT REGISTER 0
RW
REG[03Ah] LCD VERTICAL NON-D ISPLAY PERIOD REGISTER
LCD VNDP
Status(RO)
n/a
LCD Vertical Non-Display Period
Bit 5
Bit 4
Bit 3
Bit 2
RW
CRT/TV Vertical Display Height
Bit 7
Bit 1
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 0
REG[057h] CRT/TV VERTICAL DISPLAY HEIGHT REGISTER 1
REG[03Bh] TFT FPFRAME S TART POSITION REGISTER
n/a
n/a
RW
RW
n/a
TFT FPFRAME Start Position
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
n/a
n/a
n/a
n/a
CRT/TV Vertical Display
Height
n/a
Bit 9
Bit 0
REG[03Ch] TFT FPFRAME P ULSE WIDTH REGISTER 18
LCD
FPFRAME
Polarity Slct
RW
TFT FPFRAME Pulse Width
n/a
n/a
n/a
n/a
Bit 2
Bit 1
Bit 0
REG[040h] LCD DISPLAY MODE REGISTER 19
LCD Display
Blank
n/a
n/a
RW
SwivelView
Enable Bit 1
LCD Bit-per-pixel Select
n/a
Bit 8
REG[058h] CRT/TV VERTICAL NON-DISPLAY PERIOD REGISTER
CRT/TV
VNDP
Status (RO)
Bit 1
Bit 0
n/a
Dithering
Disable
Dual Panel
Buffer
Disable
RW
CRT/TV Vertical Non-Display Period
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
REG[059h] CRT/TV VRTC START P OSITION REGISTER
n/a
Bit 2
REG[041h] LCD MISCELLANEOUS REGISTER
n/a
n/a
n/a
RW
n/a
n/a
RW
LCD Display Start Address
Bit 6
Bit 5
RW
CRT/TV VRTC Start Position
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 4
Bit 14
Bit 13
Bit 3
Bit 2
Bit 1
Bit 11
Bit 10
Bit 9
n/a
Bit 8
n/a
RW
n/a
CRT VRTC Pulse Width
n/a
Bit 2
Bit 1
Bit 0
n/a
TV S-Video/
Composite
Output Slct
TV PAL/
NTSC
Output Slct
REG[05Bh] CRT/TV OUTPUT CONTROL REGISTER
RW
TV
DAC Output
Luminance
Level Select
Filter Enable Filter Enable
TV
n/a
Bit 0
RW
Bit 12
REG[05Ah] CRT/TV VRTC PULSE WIDTH REGISTER
CRT VRTC
Polarity Slct
n/a
LCD Display Start Address
Bit 0
Bit 3
REG[044h] LCD DISPLAY START ADDRESS REGISTER 2
Bit 2
Bit 1
Bit 0
Chrominance
REG[060h] CRT/TV DISPLAY M ODE REGISTER 21
CRT/TV
Display
Blank
RW
CRT/TV Bit-per-pixel Select
n/a
n/a
n/a
n/a
Bit 2
Bit 1
Bit 0
n/a
n/a
n/a
RW
REG[062h] CRT/TV DISPLAY S TART ADDRESS REGISTER 0
LCD Display Start Address
n/a
Bit 19
Bit 18
Bit 17
RW
CRT/TV Display Start Address
Bit 16
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RW
n/a
n/a
DRAM Timing Control
Bit 9
REG[046h] LCD MEMORY ADDRESS OFFSET REGISTER 0
RW
REG[063h] CRT/TV DISPLAY S TART ADDRESS REGISTER 1
LCD Memory Address Offset
Bit 8
Bit 0
Panel Data
Color/Mono Dual/Single TFT/Passive
Format
Panel Select Panel Select Panel Select
Select
Bit 6
Bit 5
Bit 4
Bit 3
RW
CRT/TV Display Start Address
Bit 2
Bit 1
Bit 0
REG[047h] LCD MEMORY ADDRESS OFFSET REGISTER 1
n/a
n/a
n/a
RW
REG[048h] LCD PIXEL PANNING REGISTER
MOD Rate
Bit 5
Bit 4
Bit 4
RW
REG[031h] MOD RATE REGISTER
n/a
RW
Bit 5
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
RW
Panel Data Width
Bit 1
Bit 5
n/a
Bit 0
REG[039h] LCD VERTICAL DISPLAY HEIGHT REGISTER 1
Bit 7
n/a
Bit 1
REG[043h] LCD DISPLAY START ADDRESS REGISTER 1
DRAM Refresh Rate
n/a
REG[030h] PANEL TYPE REGISTER 16
EL Panel
Mode
Enable
Bit 2
RW
REG[02Bh] DRAM TIMING CONTROL REGISTER 1 15
n/a
Bit 6
Bit 0
DRAM Timing Control
Bit 5
Bit 3
LCD Display FIFO High Threshold
REG[04Bh] LCD DISPLAY FIFO LOW THRESHOLD CONTROL REGISTER
n/a
LCD Vertical Display Height
Bit 15
Bit 6
n/a
REG[042h] LCD DISPLAY START ADDRESS REGISTER 0
Memory Type
Bit 1
REG[02Ah] DRAM TIMING CONTROL REGISTER 0 15
Bit 7
n/a
REG[038h] LCD VERTICAL DISPLAY HEIGHT REGISTER 0
Bit 7
Refresh Select
RW
TFT FPLINE Pulse Width
n/a
RW
REG[021h] DRAM REFRESH RATE REGISTER 13,14
Bit 1
Bit 0
n/a
RW
Bit 1
n/a
Bit 1
n/a
CRT/TV PCLK Source Slct
REG[01Ch] MEDIAPLUG CLOCK CONFIGURATION REGISTER 9,10
MediaPlug Clock Divide
Select
Bit 2
LCD PCLK Source Select
REG[018h] CRT/TV PIXEL CLOCK CONFIGURATION REGISTER 7,8
CRT/TV
PCLK 2X
Enable
Bit 3
RW
REG[014h] LCD PIXEL CLOCK CONFIGURATION REGISTER 5,6
n/a
Bit 4
REG[036h] TFT FPLINE PULSE WIDTH REGISTER 17
n/a
REG[010h] MEMORY CLOCK CONFIGURATION REGISTER 4
n/a
TFT FPLINE Start Position
n/a
Reserved
REG[008h] GENERAL I/O P INS CONTROL REGISTER
Reserved
n/a
RW
REG[04Ah] LCD DISPLAY FIFO HIGH THRESHOLD CONTROL REGISTER
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
n/a
n/a
n/a
n/a
RW
n/a
LCD Memory Address Offset
Bit 10
Bit 9
20
n/a
Bit 8
RW
Reserved
Reserved
REG[064h] CRT/TV DISPLAY S TART ADDRESS REGISTER 2
n/a
n/a
n/a
Bit 0
RW
CRT/TV Display Start Address
Bit 19
Bit 18
Bit 17
Bit 16
REG[066h] CRT/TV MEMORY ADDRESS OFFSET REGISTER 0
LCD Pixel Panning
Bit 1
n/a
RW
CRT/TV Memory Address Offset
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
01/02/08
S1D13506 Register Summary
X25B-R-001-02
REG[067h] CRT/TV MEMORY ADDRESS OFFSET REGISTER 1
n/a
n/a
n/a
n/a
REG[068h] CRT/TV PIXEL PANNING REGISTER
n/a
n/a
n/a
RW
CRT/TV Memory Address Offset
n/a
Bit 10
Bit 9
22
RW
n/a
Reserved
Reserved
n/a
Bit 1
n/a
n/a
REG[071h] LCD
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RW
CRT/TV Display FIFO Low Threshold
Bit 5
Bit 4
n/a
Bit 3
Bit 2
n/a
n/a
Bit 1
23
n/a
Bit 0
RW
Bit 1
Bit 0
RW
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
REG[072h] LCD CURSOR X P OSITION REGISTER 0
Bit 0
RW
LCD Cursor X Position
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
n/a
n/a
Bit 1
REG[073h] LCD CURXOR X P OSITION REGISTER 1
LCD Cursor
X Sign
n/a
n/a
Bit 0
RW
n/a
LCD Cursor X Position
Bit 9
REG[074h] LCD CURSOR Y P OSITION REGISTER 0
Bit 8
RW
LCD Cursor Y Position
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
n/a
n/a
Bit 1
REG[075h] LCD CURSOR Y P OSITION REGISTER 1
LCD Cursor
Y Sign
n/a
n/a
LCD Cursor Y Position
Bit 9
REG[076h] LCD INK/C URSOR BLUE COLOR 0 R EGISTER
n/a
n/a
n/a
n/a
LCD Ink/Cursor Blue Color 0
Bit 4
Bit 3
Bit 2
Bit 1
n/a
RW
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
n/a
n/a
n/a
RW
Bit 4
Bit 3
Bit 2
Bit 1
n/a
RW
Bit 4
Bit 3
Bit 2
Bit 1
n/a
Bit 4
n/a
Page 2
n/a
n/a
n/a
Bit 1
Bit 0
26
Bit 3
Bit 2
Bit 1
Bit 0
RW
Bit 3
Bit 2
Bit 1
Bit 0
RW
RW
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 7
Bit 6
Bit 5
Bit 4
Bit 2
Bit 1
Bit 0
RW
Bit 3
Bit 2
n/a
n/a
Bit 1
Bit 0
REG[083h] CRT/TV CURSOR X P OSITION REGISTER 1
CRT/TV
Cursor X
Sign
Bit 2
Bit 1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
REG[105h] BITBLT SOURCE START ADDRESS REGISTER 1
n/a
RW
n/a
Bit 9
Bit 8
REG[084h] CRT/TV CURSOR Y P OSITION REGISTER 0
Bit 15
Bit 14
Bit 13
n/a
n/a
RW
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
n/a
n/a
Bit 1
Bit 0
RW
CRT/TV Cursor Y Position
n/a
n/a
n/a
Bit 9
n/a
RW
CRT/TV Ink/Cursor Blue Color 0
n/a
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
REG[087h] CRT/TV INK/CURSOR GREEN COLOR 0 R EGISTER
n/a
n/a
RW
CRT/TV Ink/Cursor Green Color 0
Bit 5
Bit 4
Bit 3
n/a
Bit 2
Bit 1
Bit 4
RW
Bit 3
Bit 2
Bit 1
Bit 0
REG[08Ah] CRT/TV INK/CURSOR BLUE COLOR 1 REGISTER
n/a
n/a
RW
CRT/TV Ink/Cursor Blue Color 1
n/a
Bit 4
Bit 3
n/a
Bit 2
Bit 1
Bit 4
RW
Bit 3
Bit 2
Bit 1
Bit 0
RW
REG[08Ch] CRT/TV INK/CURSOR RED COLOR 1 REGISTER
n/a
n/a
CRT/TV Ink/Cursor Red Color 1
n/a
Bit 4
Bit 3
Bit 7
n/a
n/a
n/a
Bit 2
Bit 1
RW
Bit 2
Bit 1
Bit 0
n/a
BitBlt
Destination
Linear Slct
BitBlt
Source
Linear Slct
REG[100h] BITBLT CONTROL REGISTER 0 27
RW
BitBlt FIFO BitBlt FIFO BitBlt FIFO
BitBlt Active
Not Empty
Half Full
Full
Status
Status (RO) Status (RO) Status (RO)
n/a
Bit 8
RW
Bit 20
Bit 19
Bit 18
Bit 17
Bit 16
RW
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RW
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
REG[10Ah] BITBLT DESTINATION START ADDRESS REGISTER 2
n/a
n/a
RW
BitBlt Destination Start Address
n/a
Bit 20
Bit 19
Bit 18
Bit 17
Bit 16
REG[10Ch] BITBLT MEMORY ADDRESS OFFSET REGISTER 0
RW
BitBlt Memory Address Offset
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
REG[10Dh] BITBLT MEMORY ADDRESS OFFSET REGISTER 1
n/a
n/a
n/a
n/a
RW
BitBlt Memory Address Offset
Bit 10
Bit 9
Bit 8
REG[110h] BITBLT WIDTH REGISTER 0
RW
BitBlt Width
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
n/a
n/a
n/a
Bit 1
Bit 0
REG[111h] BITBLT WIDTH REGISTER 1
n/a
n/a
RW
BitBlt Width
Bit 9
Bit 8
REG[112h] BITBLT HEIGHT REGISTER 0
RW
BitBlt Height
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
n/a
n/a
n/a
Bit 1
Bit 0
REG[113h] BITBLT HEIGHT REGISTER 1
n/a
n/a
RW
Bit 0
CRT/TV Ink/Cursor FIFO Threshold
Bit 3
Bit 9
REG[109h] BITBLT DESTINATION START ADDRESS REGISTER 1
n/a
REG[08Eh] CRT/TV INK/CURSOR FIFO THRESHOLD REGISTER
n/a
Bit 10
Bit 0
CRT/TV Ink/Cursor Green Color 1
Bit 5
Bit 11
BitBlt Destination Start Address
n/a
REG[08Bh] CRT/TV INK/CURSOR GREEN COLOR 1 R EGISTER
n/a
RW
Bit 0
CRT/TV Ink/Cursor Red Color 0
n/a
Bit 0
REG[108h] BITBLT DESTINATION START ADDRESS REGISTER 0
n/a
REG[088h] CRT/TV INK/CURSOR RED COLOR 0 REGISTER
n/a
Bit 1
BitBlt Source Start Address
Bit 8
REG[086h] CRT/TV INK/CURSOR BLUE COLOR 0 REGISTER
n/a
Bit 2
BitBlt Destination Start Address
REG[085h] CRT/TV CURSOR Y P OSITION REGISTER 1
CRT/TV
Cursor Y
Sign
Bit 12
n/a
CRT/TV Cursor Y Position
Bit 7
Bit 3
30
REG[106h] BITBLT SOURCE START ADDRESS REGISTER 2 30
CRT/TV Cursor X Position
n/a
RW
BitBlt Source Start Address
BitBlt Source Start Address
REG[082h] CRT/TV CURSOR X P OSITION REGISTER 0
BitBlt Height
Bit 9
Bit 8
REG[114h] BITBLT BACKGROUD COLOR REGISTER 0
RW
BitBlt Background Color
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
REG[115h] BITBLT BACKGROUND COLOR REGISTER 1
RW
BitBlt Background Color
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
REG[118h] BITBLT FOREGROUND COLOR REGISTER 0
n/a
n/a
n/a
RW
BitBlt FIFO
Depth
n/a
n/a
n/a
REG[102h] BITBLT ROP CODE/C OLOR EXPANSION REGISTER 28
n/a
n/a
n/a
n/a
RW
Bit 3
Bit 2
Bit 1
REG[103h] BITBLT OPERATION REGISTER 29
n/a
n/a
n/a
BitBlt Color
Format Slct
Bit 7
Bit 6
Bit 5
Bit 0
BitBlt Operation
Bit 3
Bit 2
Bit 1
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
REG[119h] BITBLT FOREGROUND COLOR REGISTER 1
RW
BitBlt Foreground Color
RW
n/a
RW
BitBlt Foreground Color
BitBlt ROP Code
LCD Ink/Cursor FIFO Threshold
Bit 3
REG[104h] BITBLT SOURCE START ADDRESS REGISTER 0 30
CRT/TV Ink/Cursor Start Address
LCD Ink/Cursor Red Color 1
Bit 4
n/a
REG[101h] BITBLT CONTROL REGISTER 1
REG[07Eh] LCD INK/CURSOR FIFO T HRSHOLD REGISTER
n/a
Bit 0
LCD Ink/Cursor Green Color 1
Bit 5
n/a
RW
REG[07Ch] LCD INK/CURSOR RED COLOR 1 REGISTER
n/a
Bit 0
LCD Ink/Cursor Blue Color 1
REG[07Bh] LCD INK/CURSOR GREEN COLOR 1 REGISTER
n/.a
Bit 0
LCD Ink/Cursor Red Color 0
REG[07Ah] LCD INK/CURSOR BLUE COLOR 1 R EGISTER
n/a
Bit 0
LCD Ink/Cursor Green Color 0
REG[078h] LCD INK/C URSOR RED COLOR 0 REGISTER
n/a
Bit 8
RW
REG[077h] LCD INK/C URSOR GREEN COLOR 0 REGISTER
n/a
Bit 0
RW
n/a
n/a
REG[081h] CRT/TV INK/CURSOR S TART ADDRESS REGISTER
LCD Ink/Cursor Mode
INK/C URSOR START ADDRESS REGISTER 24
Bit 6
n/a
RW
CRT/TV Ink/Cursor Mode
CRT/TV Cursor X Position
LCD Ink/Cursor Start Address
Bit 7
n/a
CRT/TV Display FIFO High Threshold
REG[070h] LCD INK/C URSOR CONTROL REGISTER
n/a
Bit 1
RW
REG[06Bh] CRT/TV DISPLAY FIFO LOW THRESHOLD CONTROL REGISTER
n/a
n/a
CRT/TV Pixel Panning
REG[06Ah] CRT/TV DISPLAY FIFO H IGH THRESHOLD CONTROL REGISTER
n/a
Bit 8
REG[080h] CRT/TV INK/CURSOR CONTROL REGISTER 25
Bit 15
REG[1E0h]
n/a
Bit 0
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
n/a
n/a
Bit 9
Bit 8
LOOK-UP TABLE MODE REGISTER 31
n/a
n/a
n/a
RW
LUT Mode
Bit 1
Bit 0
01/02/08
S1D13506 Register Summary
X25B-R-001-02
RW
REG[1E2h] LOOK-UP TABLE ADDRESS REGISTER
LUT Address
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RW
REG[1E4h] LOOK-UP TABLE DATA REGISTER
LUT Data
Bit 3
Bit 2
Bit 1
Bit 0
n/a
n/a
n/a
11 REG[01Eh] Minimum Memory Timing Selection
Pin
MD14 on
Reset
MD[7:6] on
Reset
MA9/GPIO3
MA10/GPIO1
MA11/GPIO2
1
00
GPIO3
GPIO1
VMPEPWR
1
01
MA9
GPIO1
VMPEPWR
1
10
MA9
GPIO1
VMPEPWR
1
11
MA9
MA10
MA11
Wait State Bits [1:0]
Condition
00
no restrictions
01
2 * period (MCLK) - 4ns > period(BCLK)
10
period(MCLK) - 4ns > period(BCLK)
11
Reserved
n/a
4 REG[010h] MCLK Source Select
n/a
n/a
Reserved
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
Bit 5
RW
Bit 4
Bit 3
Bit 2
Bit 1
REG[1FCh] DISPLAY MODE REGISTER 32
n/a
SwivelView
Enable Bit 0
0
CLKI
1
BUSCLK
Memory Type Bits [1:0]
Memory Type
00
EDO-DRAM with 2-CAS#
01
FPM-DRAM with 2-CAS#
10
EDO-DRAM with 2-WE#
11
FPM-DRAM with 2-WE#
5 REG[014h] LCD PCLK Divide Select
CPU-to-Memory Access Watchdog Timer
n/a
MCLK Source
RO
Memory
LCD Power Controller
Save Status Power Save
Status
REG[1F4h] CPU-TO-MEMORY ACCESS WATCHDOG TIMER REGISTER
n/a
MCLK Source Select
Power Save
Mode Enbl
REG[1F1h] POWER SAVE STATUS REGISTER
n/a
12 REG[020h] Memory Type Select
RW
REG[1F0h] POWER SAVE CONFIGURATION REGISTER
Bit 0
LCD PCLK Divide Select Bits [1:0]
LCD PCLK Source to LPCLK Frequency Ratio
00
1:1
01
2:1
10
3:1
11
4:1
13 REG[021h] DRAM Refresh Select
DRAM Refresh Select Bits [1:0]
DRAM Refresh Type
00
CBR Refresh
01
Self-Refresh
1X
No Refresh
RW
n/a
n/a
Display Mode Select
n/a
Bit 2
Bit 1
Bit 0
6 REG[014h] LCD PCLK Source Select
RW
REG[1000h] MEDIAPLUG LCMD REGISTER
MediaPlug LCMD
LCD PCLK Source Select Bits [1:0]
LCD PCLK Source
00
CLKI
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
01
BUSCLK
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
10
CLKI2
11
MCLK
RW
REG[1002h] MEDIAPLUG RESERVED LCMD REGISTER
MediaPlug Reserved LCMD
Bit 23
Bit 22
Bit 21
Bit 20
Bit 19
Bit 18
Bit 17
Bit 16
Bit 31
Bit 30
Bit 29
Bit 28
Bit 27
Bit 26
Bit 25
Bit 24
REG[1004h] MEDIAPLUG CMD REGISTER
7 REG[018h] CRT/TV PCLK Divide Select
RW
MediaPlug CMD
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
REG[1006h] MEDIAPLUG RESERVED CMD REGISTER
RW
14 REG[021h] DRAM Refresh Rate
DRAM Refresh
Rate Bits [2:0]
MCLK Source Divide
Amount
Refresh Rate for 40MHz
MCLK Source
DRAM Refresh
Time/256 cycles
000
64
625 kHz
0.4 ms
001
128
312 kHz
0.8 ms
010
256
156 kHz
1.6 ms
011
512
78 kHz
3.3 ms
100
1024
39 kHz
6.6 ms
CRT/TV PCLK Divide Select Bits [1:0]
CRT/TV PCLK Source to DPCLK Frequency Ratio
101
2048
20 kHz
13.1 ms
00
1:1
110
4096
10 kHz
26.2 ms
01
2:1
111
8192
5 kHz
52.4 ms
10
3:1
11
4:1
8 REG[018h] CRT/TV PCLK Source Select
MediaPlug Reserved CMD
Bit 23
Bit 22
Bit 21
Bit 20
Bit 19
Bit 18
Bit 17
Bit 16
Bit 31
Bit 30
Bit 29
Bit 28
Bit 27
Bit 26
Bit 25
Bit 24
REG[1008h] TO REG[1FFEh], even address MEDIAPLUG DATA REGISTERS
CRT/TV PCLK Source Select Bits [1:0]
RW
MediaPlug Data
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
CRT/TV PCLK Source
00
CLKI
01
BUSCLK
10
CLKI2
11
MCLK
9 REG[01Ch] MediaPlug Clock Divide Select
A20-A0 = 100000h-1FFFFEh, even address BITBLT DATA REGISTER 0
RW
BitBlt Data
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
MediaPlug Clock Divide Select
Bits [1:0]
MediaPlug Clock Source to CRT/TV Pixel Clock
Frequency Ratio
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
00
1:1
01
2:1
10
3:1
11
4:1
1 N/A bits should be written 0.
Reserved bits must be written 0.
2 REG[000h] These bits are used to identify the S1D13506. For the S1D13506 the product code should be 4; the
revision code should be 1. The host interface must be enabled before reading this register (set REG[001] b7=0).
3 REG[004h] MA[11:9]/GPIO[1:3] Pin Functionality
Page 3
10 REG[01Ch] MediaPlug Clock Source Select
Pin
MD14 on
Reset
MD[7:6] on
Reset
MA9/GPIO3
MA10/GPIO1
MA11/GPIO2
0
00
GPIO3
GPIO1
GPIO2
0
01
MA9
GPIO1
GPIO2
0
10
MA9
GPIO1
GPIO2
0
11
MA9
MA10
MA11
MediaPlug Clock Source Select Bits [1:0]
MediaPlug Clock Source
00
CLKI
01
BUSCLK
10
CLKI2
11
MCLK
01/02/08
S1D13506 Register Summary
X25B-R-001-02
15 REG[02Ah], REG[02Bh] DRAM Timing Control Registers
DRAM Type
21 REG[060h] CRT/TV Bit-per-pixel Select
DRAM
Speed (ns)
MCLK Frequency
(MHz)
DRAM Timing
Control Reg 0
DRAM Timing
Control Reg 1
Bit-per-pixel Select Bits 1:0
Bit-per-pixel (bpp)
000-001
Reserved
50
40
01h
01h
010
4 bpp
01h
01h
011
8 bpp
50
33
60
50
60
EDO
30
~D
~D
bit 5
0110
S^D
P^D
bit 6
0111
~S + ~D or ~(S . D)
~P + ~D or ~(P . D)
bit 7
01h
100
15 bpp
1000
S.D
P.D
bit 0
02h
101
16 bpp
1001
~(S ^ D)
~(P ^ D)
bit 1
110-111
Reserved
1010
D
D
bit 2
1011
~S + D
~P + D
bit 3
1100
S
P
bit 4
1101
S + ~D
P + ~D
bit 5
1110
S+D
P+D
bit 6
1111
1 (Whiteness)
1 (Whiteness)
bit 7
01h
00h
00h
50
12h
02h
60
12h
02h
01h
01h
22 REG[068h] CRT/TV Pixel Planning
Color Depth
Screen 2 Pixel Panning Bits Used
4 bpp
Bits [1:0]
8 bpp
Bit 0
15/16 bpp
---
80
00h
01h
50
12h
02h
12h
02h
12h
02h
01h
01h
12h
02h
01h
01h
12h
02h
LCD Ink/Cursor Bits [1:0]
Mode
0001
Read Blit.
12h
02h
00
Inactive
0010
Move Blit in positive direction with ROP.
11h
02h
01
Cursor
0011
Move Blit in negative direction with ROP.
01h
01h
10
Ink
0100
Transparent Write Blit.
11
Reserved
0101
Transparent Move Blit in positive direction.
60
20
70
80
50
25
60
50
FPM
0101
Start Bit Positon for
Color Expansion
01h
01h
25
Boolean Function for
Pattern Fill
12h
70
70
Boolean Function for
Write Blit and Move
Blit
BitBlt ROP Code
Bits [3:0]
60
20
70
80
29 REG[103h] BitBlt Operation Selection
BitBlt Operation Bits [3:0]
23 REG[070h] LCD Ink/Cursor Selection
0000
16 REG[030h] Panel Data Width
24 REG[071h] LCD Ink/Cursor Start Address Encoding
Panel Data Width Bits [1:0]
Passive LCD Panel Data Width
TFT/D-TFD Panel Data Width
00
4-bit
9-bit
LCD Ink/Cursor Start Address Bits [7:0]
Start Address
01
8-bit
12-bit
0
Memory Size - 1024
10
16-bit
18-bit (64K color)
n = 255...1
Memory Size - n * 8192
11
Reserved
Reserved
Blit Operation
Write Blit with ROP.
0110
Pattern Fill with ROP.
0111
Pattern Fill with transparency.
1000
Color Expansion.
1001
Color Expansion with transparency.
1010
Move Blit with Color Expansion.
1011
Move Blit with Color Expansion and transparency.
1100
Solid Fill.
Other combinations
Reserved
25 REG[080h] CRT/TV Ink/Cursor Selection
17 REG[036h] LCD FPLINE Polarity Select
30 REG[104h],[105h],[106h] BitBlt Source Start Address Selection
CRT/TV Ink/Cursor Bits [1:0]
Mode
TFT FPLINE Polarity
00
Inactive
active high
active low
01
Cursor
active low
active high
10
Ink
11
Reserved
LCD FPLINE Polarity Select
Passive LCD FPLINE Polarity
0
1
18 REG[03Ch] LCD FPFRAME Polarity Select
Color
Format
Pattern Base Address[20:0]
Pattern Line
Offset[2:0]
Pixel Offset[3:0]
8 bpp
BitBlt Source Start
Address[20:6], 6’b0
BitBlt Source Start
Address[5:3]
1’b0, BitBlt Source Start
Address[2:0]
16 bpp
BitBlt Source Start
Address[20:7], 7’b0
BitBlt Source Start
Address[6:4]
BitBlt Source Start
Address[3:0]
26 REG[081h] CRT/TV Ink/Cursor Start Address Encoding
LCD FPFRAME Polarity Select
Passive LCD FPFRAME Polarity
0
active high
TFT FPFRAME Polarity
active low
CRT/TV Ink/Cursor Start Address Bits [7:0]
Start Address
1
active low
active high
0
Memory Size - 1024
n = 255...1
Memory Size - n * 8192
31 REG[1E0h] LUT Mode Selection
19 REG[040h] LCD Bit-per-pixel Select
27 REG[100h] BitBlt Active Status
Bit-per-pixel Select Bits [1:0]
Color Depth (bpp)
000-001
Reserved
4 bpp
Write
Read
011
8 bpp
0
0
Idle
100
15 bpp
0
1
Reserved
101
16 bpp
1
0
Initiatiating operation
110-111
Reserved
1
1
Operation in progress
Screen 2 Pixel Panning Bits Used
4 bpp
Bits [1:0]
8 bpp
Bit 0
15/16 bpp
---
BitBlt ROP Code
Bits [3:0]
0000
Write
LCD LUT
LCD and CRT/TV LUT’s
01
LCD LUT
LCD LUT
10
CRT/TV LUT
CRT/TV LUT
11
Reserved
Reserved
32 REG[1FCh] Display Mode Select
28 REG[102h] BitBlt ROP Code/Color Expansion Function Selection
Color Depth
Read
00
State
010
20 REG[048h] LCD Pixel Planning
Page 4
BitBlt Active Status
LUT Mode Bits [1:0]
Boolean Function for
Write Blit and Move
Blit
Boolean Function for
Pattern Fill
0 (Blackness)
0 (Blackness)
Start Bit Positon for
Color Expansion
bit 0
0001
~S . ~D or ~(S + D)
~P . ~D or ~(P + D)
bit 1
0010
~S . D
~P . D
bit 2
0011
~S
~P
bit 3
0100
S . ~D
P . ~D
bit 4
Display Mode Select Bits [2:0]
Display Mode Enabled
000
no display
001
LCD only
010
CRT only
011
Double CRT and LCD
100
TV with flicker filter off
101
Double Display TV with flicker filter off and LCD
110
TV with flicker filter on
111
Double Display TV with flicker filter on and LCD
01/02/08
S1D13506 Color LCD/CRT/TV Controller
13506CFG Configuration Program
Document Number: X25B-B-001-02
Copyright © 2000, 2001 Epson Research and Development, Inc. All Rights Reserved.
Information in this document is subject to change without notice.You may download and use this document, but only for your own use in
evaluating Seiko Epson/EPSON products. You may not modify the document. Epson Research and Development, Inc. disclaims any
representation that the contents of this document are accurate or current. The Programs/Technologies described in this document may contain
material protected under U.S. and/or International Patent laws.
EPSON is a registered trademark of Seiko Epson Corporation. Microsoft and Windows are registered trademarks of Microsoft Corporation.
All other trademarks are the property of their respective owners.
Page 2
Epson Research and Development
Vancouver Design Center
THIS PAGE LEFT BLANK
S1D13506
X25B-B-001-02
13506CFG Configuration Program
Issue Date: 01/03/14
Epson Research and Development
Vancouver Design Center
Page 3
Table of Contents
13506CFG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
S1D13506 Supported Evaluation Platforms
Installation . . . . . . . . . . . . .
Usage . . . . . . . . . . . . . . .
13506CFG Configuration Tabs . . . . .
General Tab . . . . . . . . . . . . . .
Preferences Tab . . . . . . . . . . . .
Memory Tab . . . . . . . . . . . . . .
Clocks Tab . . . . . . . . . . . . . . .
Panel Tab . . . . . . . . . . . . . . . .
CRT/TV Tab . . . . . . . . . . . . . .
Registers Tab . . . . . . . . . . . . . .
13506CFG Menus . . . . . . . . . .
Open... . . . . . . . . . . . . . . . . .
Save . . . . . . . . . . . . . . . . . .
Save As... . . . . . . . . . . . . . . . .
Configure Multiple . . . . . . . . . . .
Export . . . . . . . . . . . . . . . . .
Enable Tooltips . . . . . . . . . . . .
ERD on the Web . . . . . . . . . . . .
About 13506CFG . . . . . . . . . . .
Comments . . . . . . . . . . . . .
13506CFG Configuration Program
Issue Date: 01/03/14
. .
. .
. .
. .
. . .
. . .
. . .
. . .
. . .
. . .
. . .
. .
. . .
. . .
. . .
. . .
. . .
. . .
. . .
. . .
. .
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
. .
. .
. .
. .
. . .
. . .
. . .
. . .
. . .
. . .
. . .
. .
. . .
. . .
. . .
. . .
. . .
. . .
. . .
. . .
. .
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
. . . . . . . . . . . . . . .
. . . . . . . . . . . . . . .
. . . . . . . . . . . . . . .
. . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . ..
. . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . .. .
. . . . . . . . . . . . . . . .. . . .
. . . . . . . . . . . . . . . . . . ..
. . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . .. . .
. . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . .
.5
.6
.6
.7
.7
.9
10
12
16
20
22
23
23
24
24
25
26
27
27
27
27
S1D13506
X25B-B-001-02
Page 4
Epson Research and Development
Vancouver Design Center
THIS PAGE LEFT BLANK
S1D13506
X25B-B-001-02
13506CFG Configuration Program
Issue Date: 01/03/14
Epson Research and Development
Vancouver Design Center
Page 5
13506CFG
13506CFG is an interactive Windows® 9x/ME/NT/2000 program that calculates register
values for a user defined S1D13506 configuration. The configuration information can be
used to directly alter the operating characteristics of the S1D13506 utilities or any program
built with the Hardware Abstraction Layer (HAL) library. Alternatively, the configuration
information can be saved in a variety of text file formats for use in other applications.
S1D13506 Supported Evaluation Platforms
13506CFG runs on PC systems running Windows 9x/ME/NT/2000 and can modify the
executable files based on the S1D13506 HAL for the following evaluation platforms:
• PC system with an Intel 80x86 processor.
• M68EC000IDP (Integrated Development Platform) board, revision 3.0, with a Motorola
M68EC000 processor.
• MC68030IDP (Integrated Development Platform) board, revision 3.0, with a Motorola
MC68030 processor.
• SH3-LCEVB board, revision B, with an Hitachi SH-3 HD6417780 processor.
• MPC821ADS (Applications Development System) board, revision B, with a Motorola
MPC821 processor.
13506CFG Configuration Program
Issue Date: 01/03/14
S1D13506
X25B-B-001-02
Page 6
Epson Research and Development
Vancouver Design Center
Installation
Create a directory for 13506cfg.exe and the S1D13506 utilities. Copy the files
13506cfg.exe and panels.def to that directory. Panels.def contains configuration information for a number of panels and must reside in the same directory as 13506cfg.exe.
Usage
13506CFG can be started from the Windows desktop or from a Windows command
prompt.
To start 13506CFG from the Windows desktop, double click the program icon or the link
icon if one was created during installation.
To start 13506CFG from a Windows command prompt, change to the directory
13506cfg.exe was installed to and type the command 13506cfg.
The basic procedure for using 13506CFG is:
1. Start 13506CFG as described above.
2. Open an existing file to serve as a starting reference point (this step is optional).
3. Modify the configuration. For specific information on editing the configuration, see
“13506CFG Configuration Tabs” on page 7.
4. Save the new configuration. The configuration information can be saved in two ways;
as an ASCII text file or by modifying the executable image on disk.
Several ASCII text file formats are supported. Most are formatted C header files used
to build display drivers or standalone applications.
Utility files based on the Hardware Abstraction Layer (HAL) can be modified directly
by 13506CFG.
S1D13506
X25B-B-001-02
13506CFG Configuration Program
Issue Date: 01/03/14
Epson Research and Development
Vancouver Design Center
Page 7
13506CFG Configuration Tabs
13506CFG provides a series of tabs which can be selected at the top of the main window.
Each tab allows the configuration of a specific aspect of S1D13506 operation.
The tabs are labeled “General”, “Preference”, “Memory”, “Clocks”, “Panel”, “CRT/TV”,
and “Registers”. The following sections describe the purpose and use of each of the tabs.
General Tab
Decode Addresses
Register Address
Display Buffer Address
The General tab contains S1D13506 evaluation board specific information. The values
presented are used for configuring HAL based executable utilities. The settings on this tab
specify where in CPU address space the registers and display buffer are located.
Decode Addresses
13506CFG Configuration Program
Issue Date: 01/03/14
Selecting one of the listed evaluation platforms changes
the values for the “Register address” and “Display
buffer address” fields. The values used for each evaluation platform are examples of possible implementations as used by the Epson S1D13506 evaluation board.
If your hardware implementation differs from the
addresses used, select the User-Defined option and
enter the correct addresses for “Register address” and
“Display buffer address”.
S1D13506
X25B-B-001-02
Page 8
Epson Research and Development
Vancouver Design Center
Register Address
The physical address of the start of register decode
space (in hexadecimal).
This field is automatically set according to the Decode
Address unless the “User-Defined” decode address is
selected.
Display Buffer Address
The physical address of the start of display buffer
decode space (in hexadecimal).
This field is automatically set according to the Decode
Address unless the “User-Defined” decode address is
selected.
Note
When “Epson S5U13506B00B/B00C Evaluation Board” is selected, the register and
display buffer addresses are blanked because the evaluation board uses the PCI interface
and the decode addresses are determined by the system BIOS during boot-up.
If using the S1D13506 Evaluation Board on a PCI based platform, both Windows and
the S1D13XXX device driver must be installed. For further information on the
S1D13XXX device driver, see the S1D13XXX Windows 9x/NT/2000 Device Driver Installation Guide, document number X00A-E-003-xx.
S1D13506
X25B-B-001-02
13506CFG Configuration Program
Issue Date: 01/03/14
Epson Research and Development
Vancouver Design Center
Page 9
Preferences Tab
Initial Display
Panel SwivelView
Panel Color Depth
CRT/TV Color Depth
The Preference tab contains settings pertaining to the initial display state. During runtime
the display or color depth may be changed.
Initial Display
Sets which display device is used for the initial display.
Selections made on the CRT/TV tab may cause selections on this tab to be grayed out. The selections “None”
and “Panel” are always available.
Panel SwivelView
The S1D13506 SwivelView feature is capable of
rotating the image displayed on an LCD panel 90°,
180°, or 270° in a clockwise direction. This sets the
initial orientation of the panel.
This setting is greyed out when any display device other
than “Panel” is selected as the Initial Display.
Panel Color Depth
Sets the initial color depth on the LCD panel.
CRT/TV Color Depth
Sets the initial color depth on the CRT or TV display.
13506CFG Configuration Program
Issue Date: 01/03/14
S1D13506
X25B-B-001-02
Page 10
Epson Research and Development
Vancouver Design Center
Memory Tab
Access Time
Refresh Time
Memory Type
WE# Control
Suspend Mode
Installed Memory
The Memory tab contains settings that control the configuration of the DRAM used for the
S1D13506 display buffer.
Note
The DRAM memory type and access time determines the optimal memory clock
(MCLK). See “Clocks Tab” on page 12 for an explanation on how to determine the optimal memory clock.
Memory Configuration
Access Time
These four settings must be configured based on the
specification of the DRAM being used. For each of the
following settings refer to the DRAM manufacturer’s
specification, unless otherwise noted.
Selects the access time of the DRAM.
The S1D13506 evaluation boards use 50ns DRAM.
Memory Type
Selects the memory type, either Extended Data Out
(EDO) or Fast Page Mode (FPM).
The S1D13506 evaluation boards use EDO DRAM.
S1D13506
X25B-B-001-02
13506CFG Configuration Program
Issue Date: 01/03/14
Epson Research and Development
Vancouver Design Center
Page 11
WE# Control
Selects the WE# control used for the DRAM. DRAM
uses one of two methods of control when writing to
memory. These methods are referred to as 2-CAS# and
2-WE#.
The S5U13506 evaluation boards use DRAM requiring
the 2-CAS# method.
Refresh Time
Suspend Mode Refresh
Selects the number of ms required to refresh 256 rows
of DRAM.
Selects the DRAM refresh method used during power
save mode.
The S5U13506 evaluation boards use DRAM requiring
CAS before RAS. For all other implementations, refer
to the manufacturer’s specification for DRAM refresh
requirements.
CAS before RAS
This setting is selected for DRAM that requires timing
where the CAS signal occurs just before the RAS
signal.
Self refresh
This setting is selected for DRAM that requires no
signal from the S1D1306 to maintain memory refresh.
No refresh
This setting does not refresh the memory during power
save mode. If this option is selected, the memory
contents are lost during power save.
Installed Memory
Selects the amount of DRAM available for the display
buffer.
The S1D13506 evaluation board use 2M bytes of
DRAM.
13506CFG Configuration Program
Issue Date: 01/03/14
S1D13506
X25B-B-001-02
Page 12
Epson Research and Development
Vancouver Design Center
Clocks Tab
LCD PCLK
Source
LCD PCLK
Divide
CLKI
MediaPlugCLK
Source
MediaPlugCLK
Divide
CLKI2
CRT/TV PCLK
Source
CRT/TV PCLK
Divide
BUSCLK
BCLK=BUSCLK/2
MCLK Source
MCLK Divide
The Clocks tab is intended to simplify the selection of input clock frequencies and the
source of internal clocking signals. For further information regarding clocking and clock
sources, refer to the S1D13506 Hardware Functional Specification, document number
X25B-A-001-xx.
In automatic mode the values for CLKI and CLKI2 are calculated based on selections made
for LCD and CRT/TV timings from the “Panel” and “CRT/TV” tabs. In this mode, the
required frequencies for the input clocks are displayed in blue in the “Auto” section of each
group. It is the responsibility of the system designer to ensure that the correct CLKI
frequencies are supplied to the S1D13506.
Making a selection other than “Auto” indicates that the values for CLKI or CLKI2 are
known and are fixed by the system design. Options for LCD and CRT/TV frame rates are
limited to ranges determined by the clock values.
Note
Changing clock values may modify or invalidate Panel or CRT/TV settings. Confirm all
settings on these two tabs after changing any clock settings.
Note
If the same source clock is selected for use by both CRT/TV and LCD panels, the available LCD pixel clock selections are limited due to more stringent CRT/TV timings.
S1D13506
X25B-B-001-02
13506CFG Configuration Program
Issue Date: 01/03/14
Epson Research and Development
Vancouver Design Center
Page 13
The S1D13506 may use as many as three input clocks or as few as one. The more clocks
used the greater the flexibility of choice in display type and memory speed.
CLKI
This setting determines the frequency of CLKI. CLKI is
typically used for the panel and CRT/TV pixel clocks.
Select “Auto” to have the CLKI frequency determined
automatically based on settings made on other configuration tabs. After completing the other configurations,
the required CLKI frequency will be displayed in blue
in the Auto section.
If the CLKI frequency must be fixed to a particular rate,
set this value by selecting a preset frequency from the
drop down list or entering the desired frequency in
MHz.
CLKI2
This setting determines the frequency of CLKI2. If the
MediaPlug interface is required, CLKI2 is typically
used as the clock source.
Select “Auto” to have the CLKI2 frequency determined
automatically based on settings made on other configuration tabs. After completing the other configurations,
the required CLKI2 frequency will be displayed in blue
in the Auto section.
If the CLKI2 frequency must be fixed to a particular
rate, set this value by selecting a preset frequency from
the drop down list or entering the desired frequency in
MHz.
BUSCLK
This setting determines the frequency of the bus
interface clock (BUSCLK). This value is required for
calculating internal divisors which will yield the best
performance.
The BUSCLK frequency must be fixed to a particular
rate. Set this value by selecting a preset frequency from
the drop down list or entering the desired frequency in
MHz.
BCLK=BUSCLK/2
Indicates the BCLK to BUSCLK ratio. This ratio is set
at RESET# by the configuration pin CONF5.
Under normal circumstances BCLK = BUSCLK. This
option is only for configuring Toshiba/Philips interfaces when DCLKOUT is connected to the S1D13506
BUSCLK signal.
13506CFG Configuration Program
Issue Date: 01/03/14
S1D13506
X25B-B-001-02
Page 14
Epson Research and Development
Vancouver Design Center
LCD PCLK
These settings select the signal source and input clock
divisor for the panel pixel clock (LCD PCLK).
Source
Selects the LCD PCLK source. Possible sources include
CLKI, CLKI2, BUSCLK or MCLK. Typically the LCD
PCLK is derived from CLKI.
Divide
Specifies the divide ratio for the clock source signal.
Selecting “Auto” for the divisor allows the configuration program to calculate the best clock divisor.
Unless a very specific clocking is being specified, it is
best to leave this setting on “Auto”.
Timing
CRT/TV PCLK
This field shows the actual LCD PCLK used by the
configuration process.
These settings select the signal source and input clock
divisor for the CRT/TV pixel clock (CRT/TV PCLK).
Source
Selects the CRT/TV PCLK source. Possible sources
include CLKI, CLKI2, BUSCLK or MCLK. Typically
the CRT/TV PCLK is derived from CLKI.
Divide
Specifies the divide ratio for the clock source signal.
Selecting “Auto” for the divisor allows the configuration program to calculate the best clock divisor.
Unless a very specific clocking is required, it is best to
leave this setting on “Auto”.
Timing
S1D13506
X25B-B-001-02
This field shows the actual CRT/TV PCLK used by the
configuration process.
13506CFG Configuration Program
Issue Date: 01/03/14
Epson Research and Development
Vancouver Design Center
Page 15
MCLK
These settings select the signal source and input clock
divisor for the memory clock (MCLK). MCLK should
be set based on the type and speed of DRAM as follows.
Memory Type
EDO
FPM
Optimal Memory Clock (MCLK)
50ns
60ns
70ns
40MHz
33MHz
30MHz
—
25MHz
20MHz
Source
Selects the MCLK source. Possible sources include
CLKI or BUSCLK. Typically MCLK is derived from
BUSCLK.
Divide
Specifies the divide ratio for the clock source signal.
Unless the MCLK source frequency is very high,
resulting in more than a 50MHz MCLK, this ratio
should be set at 1:1.
Timing
MediaPlugCLK
13506CFG Configuration Program
Issue Date: 01/03/14
This field shows the actual MCLK frequency used by
the configuration process.
These settings select the signal source and input clock
divide for the MediaPlug clock (MediaPlugCLK).
Source
Selects the MediaPlug clock source.
Divide
Selects the divide ratio for the MediaPlug clock source.
Timing
This field shows the actual MediaPlugCLK frequency
used by the configuration process.
S1D13506
X25B-B-001-02
Page 16
Epson Research and Development
Vancouver Design Center
Panel Tab
Panel Data Width
Single/Dual
Dual Panel
Buffer Disable
Mono/Color
Format 2
Panel Type
FPLINE
Polarity
EL Support
FPFRAME
Polarity
Frame Rate
Panel Dimensions
Pixel Clock
Predefined
Panels
TFT/FPLINE
Non-Display
Period
TFT/FPFRAME
The S1D13506 supports many panel types. This tab allows configuration of most panel
settings such as panel dimensions, type and timings.
Panel Type
Selects between passive (STN) and active (TFT) panel
types. Select TFT for TFT compatible D-TFD panel
types.
Several options may change or become unavailable
when the STN/TFT setting is switched. Therefore,
confirm all settings on this tab after the Panel Type is
changed.
EL Support
S1D13506
X25B-B-001-02
Enable Electro-Luminescent panel support. This option
is only available when the selected panel type is STN.
13506CFG Configuration Program
Issue Date: 01/03/14
Epson Research and Development
Vancouver Design Center
Panel Data Width
Page 17
Selects the panel data width. Panel data width is the
number of bits of data transferred to the LCD panel on
each clock cycle and shouldn’t be confused with color
depth which determines the number of displayed colors.
When the panel type is STN, the available options are 4
bit, 8 bit, and 16 bit. When the panel type is TFT the
available options are 9 bit, 12 bit, and 18 bit.
Single / Dual
Selects between a single or dual panel.
When the panel type is TFT, “Single” is automatically
selected and the “Dual” option is grayed out.
Disable Dual Panel Buffer
The Dual Panel Buffer is used with dual STN panels to
improve image quality by buffering display data in a
format directly usable by the panel.
This option is primarily intended for testing purposes. It
is not recommended that the Dual Panel Buffer be
disabled as a reduction of display quality will result.
Mono / Color
Selects between a monochrome or color panel.
Format 2
Selects color STN panel format 2. This option is specifically for configuring 8-bit color STN panels.
See the S1D13506 Hardware Functional Specification,
document number X25B-A-001-xx, for description of
format 1 / format 2 data formats. Most new panels use
the format 2 data format.
FPLINE Polarity
Selects the polarity of the FPLINE pulse.
Refer to the panel specification for the correct polarity
of the FPLINE pulse.
FPFRAME Polarity
Selects the polarity of the FPFRAME pulse.
Refer to the panel specification for the correct polarity
of the FPFRAME pulse.
Panel Dimensions
These fields specify the panel width and height. A
number of common widths and heights are available in
the selection boxes. If the width/height of your panel is
not listed, enter the actual panel dimensions into the edit
field.
Manually entered panel widths must be a multiple of
13506CFG Configuration Program
Issue Date: 01/03/14
S1D13506
X25B-B-001-02
Page 18
Epson Research and Development
Vancouver Design Center
eight pixels. If a manually entered panel width is not a
multiple of eight pixels a notification box appears and
13506CFG rounds up the value to the next allowable
width.
Non-display period
It is recommended that these automatically generated
non-display values be used without adjustment.
However, manual adjustment may be useful in fine
tuning the non-display width and the non-display
height.
As a general rule passive LCD panels and some CRTs
are tolerant of a wide range of non-display times. Active
panels, TVs and some CRTs are far less tolerant of
changes to the non-display period.
Frame Rate
Select the desired frame rate (in Hz) from the dropdown list. The values in the list are the range of possible
frame rates using the currently selected pixel clock. To
change the range of frame rates, select a different Pixel
Clock rate (in MHz).
Panel dimensions are fixed therefore frame rate can
only be adjusted by changing either PCLK or nondisplay period values. Higher frame rates correspond to
smaller horizontal and vertical non-display values, or
higher frequencies.
Pixel Clock
Select the desired Pixel Clock (in MHz) from the dropdown list. The range of frequencies displayed is
dependent on settings selected on the Clocks tab.
For example:
If CLKI is chosen to be Auto and LCD PCLK is sourced
from CLKI on the Clocks tab, then the range for Pixel
Clock will range from 1.5 MHz to 80 MHz.
Selecting a fixed LCD PCLK on the Clocks tab, say
25.175 MHz, will result in only four selections: 6.293,
8.392, 12.587, and 25.175 MHz. (these frequencies
represent the four possible frequencies from a fixed
25.175 MHz input clock divided by the PCLK divider).
TFT/FPLINE (pixels)
S1D13506
X25B-B-001-02
These settings allow fine tuning of the TFT/D-TFT line
pulse parameters and are only available when the
selected panel type is TFT. Refer to S1D13506
Hardware Functional Specification, document number
X25B-A-001-xx for a complete description of the
FPLINE pulse settings.
13506CFG Configuration Program
Issue Date: 01/03/14
Epson Research and Development
Vancouver Design Center
Page 19
Start pos
Specifies the delay (in pixels) from the start of the
horizontal non-display period to the leading edge of the
FPLINE pulse.
Pulse Width
Specifies the delay (in pixels) from the start of the
horizontal non-display period to the leading edge of the
FPLINE pulse.
TFT/FPFRAME (lines)
These settings allow fine tuning of the TFT/D-TFT
frame pulse parameters and are only available when the
selected panel type is TFT. Refer to S1D13506
Hardware Functional Specification, document number
X25B-A-001-xx, for a complete description of the
FPFRAME pulse settings.
Start pos
Specify the delay (in lines) from the start of the vertical
non-display period to the leading edge of the
FPFRAME pulse.
Pulse width
Specifies the pulse width (in lines) of the FPFRAME
output signal.
Predefined Panels
13506CFG Configuration Program
Issue Date: 01/03/14
13506CFG uses a file (panels.def) which lists various
panel manufacturers recommended settings. If the file
panels.def is present in the same directory as
13506cfg.exe, the settings for a number of predefined
panels are available in the drop-down list. If a panel is
selected from the list, 13506CFG loads the predefined
settings contained in the file.
S1D13506
X25B-B-001-02
Page 20
Epson Research and Development
Vancouver Design Center
CRT/TV Tab
Display Dimensions
TV Filters
Display Selection
TV Output
CRT DAC
Output Level
The CRT/TV tab configures settings specific to CRT/TV display devices.
Display Selection
Select the type of alternate display from: CRT,
TV/NTSC, or TV/PAL.
Note that CRT and TV cannot be simultaneously
selected.
Display Dimensions
Selects the resolution and frame rate from the dropdown list. The available selections vary based on selections made in the Clocks tab and which Display
Selection is chosen on this tab (CRT, TV/NTSC,
TV/PAL).
If no selections are available, the CRT/TV pixel clock
settings on the Clocks tab must be changed.
S1D13506
X25B-B-001-02
13506CFG Configuration Program
Issue Date: 01/03/14
Epson Research and Development
Vancouver Design Center
Page 21
TV Filters
When displaying computer images on a TV, several
image distortions may arise. The S1D13506 incorporates three filters which reduce these distortions. Each
filter type is enabled by checking the associated box.
Luminance
The luminance filter adjusts the brightness of the TV
and reduces the “rainbow-like” colors at the boundaries
between sharp luminance transitions. This filter is most
useful for composite video output.
Chrominance
The chrominance filter adjusts the color of the TV and
reduces the “ragged edges” seen at the boundaries
between sharp color transitions. This filter is most
useful for composite video output.
Flicker
The “flickering” effect seen on interlaced displays is
caused by sharp vertical image transitions such as
window edges. Turning on the anti-flicker filter
averages adjacent lines on the TV display to reduce
flickering.
TV Output
Selects the TV output format: Composite or S-Video.
CRT DAC output level
When the CRT is active, the CRT DAC Output Level
can be used to double values output to the DAC. This
would normally result in very bright colors on the
display, but if IREF is reduced at the same time the
display will remain at its intended brightness and power
consumption is reduced.
For more information on setting the CRT DAC output
level, see the S1D13506 Hardware Functional Specification, document number X25B-A-001-xx.
Note
For CRT operations, 13506CFG supports VESA timings only. For TV operations,
13506CFG supports NTSC and PAL timings only. Overriding these register values on
the Registers page may cause the CRT or TV to display incorrectly.
13506CFG Configuration Program
Issue Date: 01/03/14
S1D13506
X25B-B-001-02
Page 22
Epson Research and Development
Vancouver Design Center
Registers Tab
The Registers tab allows viewing and direct editing the S1D13506 register values.
Scroll up and down the list of registers and view their configured value. Individual register
settings may be changed by double-clicking on the register in the listing. Manual changes
to the registers are not checked for errors, so caution is warranted when directly
editing these values. It is strongly recommended that the S1D13506 Hardware Functional
Specification, document number X25B-A-001-xx be referred to before making an manual
register settings.
Manually entered values may be changed by 13506CFG if further configuration changes
are made on the other tabs. In this case, the user is notified of the changes when they return
to the registers tab.
Note
Manual changes to the registers may have unpredictable results if incorrect values are
entered.
S1D13506
X25B-B-001-02
13506CFG Configuration Program
Issue Date: 01/03/14
Epson Research and Development
Vancouver Design Center
Page 23
13506CFG Menus
The following sections describe each of the options in the File and Help menus.
Open...
From the Menu Bar, select “File”, then “Open...” to display the Open File Dialog Box.
The Open option allows 13506CFG to open files containing HAL configuration information. When 13506CFG opens a file it scans the file for an identification string, and if
found, reads the configuration information. This may be used to quickly arrive at a starting
point for register configuration. The only requirement is that the file being opened must
contain a valid S1D13506 HAL library information block.
13506CFG supports a variety of executable file formats. Select the file type(s) 13506CFG
should display in the Files of Type drop-down list and then select the filename from the list
and click on the Open button.
Note
13506CFG is designed to work with utilities programmed using a given version of the
HAL. If the configuration structure contained in the executable file differs from the version 13506CFG expects the Open will fail and an error message is displayed. This may
happen if the version of 13506CFG is substantially older, or newer, than the file being
opened.
13506CFG Configuration Program
Issue Date: 01/03/14
S1D13506
X25B-B-001-02
Page 24
Epson Research and Development
Vancouver Design Center
Save
From the Menu Bar, select “File”, then “Save” to initiate the save action. The Save menu
option allows a fast save of the configuration information to a file that was opened with the
Open menu option.
Note
This option is only available once a file has been opened.
Note
13506cfg.exe can be configured by making a copy of the file 13506cfg.exe and configuring the copy. It is not possible to configure the original while it is running.
Save As...
From the Menu Bar, select “File”, then “Save As...” to display the Save As Dialog Box.
“Save as” is very similar to Save except a dialog box is displayed allowing the user to name
the file before saving.
Using this technique a tester can configure a number of files differing only in configuration
information and name (e.g. BMP60Hz.EXE, BMP72Hz.EXE, BMP75Hz.EXE where only
the frame rate changes in each of these files).
Note
When “Save As” is selected then an exact duplicate of the file as opened by the “Open”
option is created containing the new configuration information.
S1D13506
X25B-B-001-02
13506CFG Configuration Program
Issue Date: 01/03/14
Epson Research and Development
Vancouver Design Center
Page 25
Configure Multiple
After determining the desired configuration, “Configure Multiple” allows the information
to be saved into one or more executable files built with the HAL library.
From the Menu Bar, select “File”, then “Configure Multiple” to display the Configure
Multiple Dialog Box.This dialog box is also displayed when a file(s) is dragged onto the
13506CFG window.
The left pane lists files available for configuration; the right pane lists files that have been
selected for configuration. Files can be selected by clicking the “Add” or “Add All”
buttons, double clicking any file in the left pane, or by dragging the file(s) from Windows
Explorer.
Selecting “Show all files” displays all files in the selected directory, whereas selecting
“Show conf. files only” will display only files that can be configured using 13506CFG.
The configuration values can be saved to a specific EXE file for Intel platforms, or to a
specific S9 or ELF file for non-Intel platforms. The file must have been compiled using the
13506 HAL library.
Checking “Preserve Physical Addresses” instructs 13506CFG to use the register and
display buffer address values the files were previously configured with. Addresses
specified in the General Tab are discarded. This is useful when configuring several
programs for various hardware platforms at the same time. For example, if configuring PCI,
MPC and IDP based programs at the same time for a new panel type, the physical addresses
for each are retained. This feature is primarily intended for the test lab where multiple
hardware configurations exist and are being tested.
13506CFG Configuration Program
Issue Date: 01/03/14
S1D13506
X25B-B-001-02
Page 26
Epson Research and Development
Vancouver Design Center
Export
After determining the desired configuration, “Export” permits the user to save the register
information as a variety of ASCII text file formats. The following is a list and description
of the currently supported output formats:
• a C header file for use in writing HAL library based applications.
• a C header file which lists each register and the value it should be set to.
• a C header file for use in developing Window CE display drivers.
• a C header file for use in developing display drivers for other operating systems such as
Linux, QNX, and VxWorks UGL or WindML.
• a comma delimited text file containing an offset, a value, and a description for each
S1D13506 register.
After selecting the file format, click the “Export As..." button to display the file dialog box
which allows the user to enter a filename before saving. Before saving the configuration
file, clicking the “Preview” button starts Notepad with a copy of the configuration file about
to be saved.
When the C Header File for S1D13506 WinCE Drivers option is selected as the export
type, additional options are available and can be selected by clicking on the Options button.
The options dialog appears as:
Mode Number
selects the mode number for
use in the header file
CRT/TV=Primary Display
sets the CRT/TV as the primary
display in the header file
Cursor Support
selects the type of cursor support
enabled in the header file
(for primary device context)
HW Acceleration
enables hardware acceleration
(BitBLT engine) in the header file
(for primary device context)
S1D13506
X25B-B-001-02
Cursor Support
selects the type of cursor support
enabled in the header file
(for secondary device context)
HW Acceleration
enables hardware acceleration
(BitBLT engine) in the header file
(for secondary device context)
13506CFG Configuration Program
Issue Date: 01/03/14
Epson Research and Development
Vancouver Design Center
Page 27
Enable Tooltips
Tooltips provide useful information about many of the items on the configuration tabs.
Placing the mouse pointer over nearly any item on any tab generates a popup window
containing helpful advice and hints.
To enable/disable tooltips check/uncheck the “Tooltips” option form the “Help” menu.
Note
Tooltips are enabled by default.
ERD on the Web
This “Help” menu item is actually a hotlink to the Epson Research and Development
website. Selecting “Help” then “ERD on the Web” starts the default web browser and
points it to the ERD product web site.
The latest software, drivers, and documentation for the S1D13506 is available at this
website.
About 13506CFG
Selecting the “About 13506CFG” option from the “Help” menu displays the about dialog
box for 13506CFG. The about dialog box contains version information and the copyright
notice for 13506CFG.
Comments
• On any tab particular options may be grayed out if selecting them would violate the
operational specification of the S1D13506 (i.e. Selecting extremely low CLK frequencies on the Clocks tab may result in no possible CRT/TV options. Selecting TFT or STN
on the Panel tab enables/disables options specific to the panel type).
• The file panels.def is a text file containing operational specifications for several
supported, and tested, panels. This file can be edited with any text editor.
• 13506CFG allows manually altering register values. The manual changes may violate
memory and LCD timings as specified in the S1D13506 Hardware Functional Specification, document number X25B-A-001-xx. If this is done, unpredictable results may
occur. Epson Research and Development, Inc. does not assume liability for any damage
done to the display device as a result of configuration errors.
13506CFG Configuration Program
Issue Date: 01/03/14
S1D13506
X25B-B-001-02
Page 28
Epson Research and Development
Vancouver Design Center
THIS PAGE LEFT BLANK
S1D13506
X25B-B-001-02
13506CFG Configuration Program
Issue Date: 01/03/14
S1D13506 Color LCD/CRT/TV Controller
13506SHOW Demonstration Program
Document Number: X25B-B-002-03
Copyright © 2001 Epson Research and Development, Inc. All Rights Reserved.
Information in this document is subject to change without notice.You may download and use this document, but only for your own use in
evaluating Seiko Epson/EPSON products. You may not modify the document. Epson Research and Development, Inc. disclaims any
representation that the contents of this document are accurate or current. The Programs/Technologies described in this document may contain
material protected under U.S. and/or International Patent laws.
EPSON is a registered trademark of Seiko Epson Corporation. All other trademarks are the property of their respective owners.
Page 2
Epson Research and Development
Vancouver Design Center
THIS PAGE LEFT BLANK
S1D13506
X25B-B-002-03
13506SHOW Demonstration Program
Issue Date: 01/02/06
Epson Research and Development
Vancouver Design Center
Page 3
13506SHOW
13506SHOW is designed to demonstrate and test some of the S1D13506 display capabilities. The program can cycle through all color depths and display a pattern showing all
available colors or shades of gray. Alternately, the user can specify a color depth and
display configuration. 13506SHOW supports SwivelView™ (90°, 180°, and 270°
hardware rotation of the display image).
The 13506SHOW demonstration program must be configured and/or compiled to work
with your hardware platform. The program 13506CFG.EXE can be used to configure
13506SHOW. Consult the 13506CFG users guide, document number X25B-B-001-xx, for
more information on configuring S1D13506 utilities.
This software is designed to work in both embedded and personal computer (PC) environments. For the embedded environment, it is assumed that the system has a means of
downloading software from the PC to the target platform. Typically this is done by serial
communications, where the PC uses a terminal program to send control commands and
information to the target processor. Alternatively, the PC can program an EPROM, which
is then placed in the target platform. Some target platforms can also communicate with the
PC via a parallel port connection, or an Ethernet connection.
S1D13506 Supported Evaluation Platforms
13506SHOW supports the following S1D13506 evaluation platforms:
• PC system with an Intel 80x86 processor.
• M68EC000IDP (Integrated Development Platform) board, revision 3.0, with a Motorola
M68EC000 processor.
• MC68030IDP (Integrated Development Platform) board, revision 3.0, with a Motorola
MC68030 processor.
• SH3-LCEVB board, revision B, with an Hitachi SH-3 HD6417780 processor.
• MPC821ADS (Applications Development System) board, revision B, with a Motorola
MPC821 processor.
Installation
PC platform:
Copy the file 13506show.exe to a directory specified in the path (e.g. PATH=C:\13506.
Embedded platform:
Download the program 13506show to the system.
13506SHOW Demonstration Program
Issue Date: 01/02/06
S1D13506
X25B-B-002-03
Page 4
Epson Research and Development
Vancouver Design Center
Usage
PC Platform
At the prompt, type:
13506SHOW [/a] [bl=n] [bc=n] [ds=n | ds=?] [/g] [/noinit] [/r90 | /r180 | /r270] [/read]
[/s] [/write] [/?]
Embedded platform
Execute 13506show and type the command line argument at the prompt.
Where:
S1D13506
X25B-B-002-03
/a
cycles through all video modes automatically.
bl=n
shows the LCD display at a user specified color depth (bpp)
where n = (4, 8, 15, 16).
bc=n
shows the CRT/TV display at a user specified color depth
(bpp) where n = (4, 8, 15, 16).
ds=n
selects display surfaces (see Section , “Display Surfaces”
on page 5).
ds=?
shows the available display surfaces (see Section , “Display
Surfaces” on page 5).
/g
shows a grid on the image.
/noinit
skips full register initialization. Only registers used for
changing the color depth (bpp), selecting the
memory/registers and programming the clock synthesizer are updated. Additionally, some registers are read
to determine information such as display size and type
(LCD, CRT, TV).
/r90
SwivelView™ 90°, clockwise hardware rotation of LCD
image by 90 degrees
/r180
SwivelView™ 180°, clockwise hardware rotation of LCD
image by 180 degrees
/r270
SwivelView™ 270°, clockwise hardware rotation of LCD
image by 270 degrees
13506SHOW Demonstration Program
Issue Date: 01/02/06
Epson Research and Development
Vancouver Design Center
Page 5
/read
after drawing the image, continually reads from the screen
(for testing purposes).
/s
displays a vertical stripe pattern.
/write
continually writes to one word of offscreen memory (for
testing purposes only).
/?
displays the help screen.
Note
Pressing the Esc key will exit the program.
Display Surfaces
A surface is a block of memory assigned to one or more physical display devices.
13506SHOW provides 7 display surfaces (0-6) which cover the possible combinations of
display types. Table 1:, “Display Surfaces” lists the predefined display surfaces that may
be selected.
Table 1: Display Surfaces
Display Surfaces
(ds=)
Display
Display
Device(s) using Device(s) using
Memory Block 0 Memory Block 1
0
LCD
1
CRT
2
TV
3
LCD & CRT
4
LCD & TV
5
LCD
CRT
6
LCD
TV
Display surfaces 0 through 2 each display data from a single memory block to an individual
display device (LCD, CRT, or TV).
Display surfaces 3 and 4 output to two separate display devices, but generate the output
from the same memory block. This may be useful when the same image is to be displayed
on both display devices. It also reduces the total amount of display memory required.
Display surfaces 5 and 6 output to two separate devices from different memory blocks. This
allows two completely different images to be displayed at the same time. When using
display surfaces 5 or 6, some combinations of display modes with a high resolution and/or
high color depth may not be supported within a 2MB display buffer.
13506SHOW Demonstration Program
Issue Date: 01/02/06
S1D13506
X25B-B-002-03
Page 6
Epson Research and Development
Vancouver Design Center
13506SHOW Examples
13506SHOW is designed to both demonstrate and test some of the features of the
S1D13506. The following examples show how to use the program in both instances.
Using 13506SHOW For Demonstration
1. To show color patterns which must be manually stepped through, type the following:
13506SHOW
The program displays the default color depth and display surface as selected in
13506CFG. Press any key to go to the next screen. Once all screens are shown the program exits. To exit the program immediately press the Esc key.
2. To show color patterns which automatically step through all color depths beginning
with the default color depth (as selected in 13506CFG), type the following:
13506SHOW /a
The program will display the default color depth. Each screen is shown for
approximately 1 second before the next screen is automatically shown. The program
exits after the last screen is shown. To exit the program immediately press
CTRL+BREAK.
3. To show a color pattern for a specific color depth on the LCD, type the following:
13506SHOW bl=[mode]
where mode = 4, 8, 15, or 16.
The program displays the requested screen and then exits.
Note
If a monochrome LCD panel is used, the image is formed using only the green
component of the Look-Up Table.
4. To show a color pattern for a specific color depth on the CRT, type the following:
13506SHOW bc=[mode]
where mode = 4, 8, 15, or 16.
The program display the requested screen and then exits.
S1D13506
X25B-B-002-03
13506SHOW Demonstration Program
Issue Date: 01/02/06
Epson Research and Development
Vancouver Design Center
Page 7
5. To show the color patterns in SwivelView™ 90° mode, type the following:
13506SHOW /r90
The program will display the default color depth (as selected in 13506CFG). Press any
key to go to the next screen. Since SwivelView™ 90° is limited to color depths of 8,
15 and 16 bpp the program exits. To exit the program immediately press the Esc key.
The “/r90”, “/r180”, and “/r270” switches can be used in combination with other command line switches.
6. To show solid vertical stripes, type the following:
13506SHOW /s
The program will display the default color depth (as selected in 13506CFG). Press any
key to go to the next screen. Once all screens are shown the program exits. To exit the
program immediately press the Esc key.
The “/s” switch can be used in combination with other command line switches.
Using 13506SHOW For Testing
1. To show a test grid over the 8 bpp color pattern on an LCD, type the following:
13506SHOW bl=8 /g
The program will display the 8 bpp color pattern overlaid with a white grid 20 pixels
wide and then exit. The grid makes it obvious if the image is shifted or if pixels are
missing. Note the grid is not aligned with the color pattern, therefore the color
boxes will not match the grid boxes.
The “/g” switch can be used in combination with other command line switches.
2. To test background memory reads to the CRT, type the following:
13506SHOW bc=16 /read
The program will test screen reads. If there is a problem with memory access, the
displayed pattern will appear different than when the “/read” switch is not used. If
there is a problem, check the configuration parameters of 13506SHOW using the utility 13506CFG. See the 13506CFG user guide, document number X25B-B-001-xx, for
more information.
The “/read” switch should be used in combination with the “b=” setting, otherwise the
test will always start with the default color depth (as selected in 13506CFG). To exit
the program after using “/read”, press the Esc key and wait for a couple of seconds
(the keystroke is checked after reading a full screen).
13506SHOW Demonstration Program
Issue Date: 01/02/06
S1D13506
X25B-B-002-03
Page 8
Epson Research and Development
Vancouver Design Center
Comments
• If 13506SHOW is started without defining the color depth, the program automatically
cycles through the available color depths from highest to lowest. The first color depth
shown is the default color depth value saved to 13506SHOW using 13506CFG. This
approach avoids showing color depths not supported by a given hardware configuration.
• 13506SHOW checks if the display(s) selected from the DS= option have been previously configured by 13506CFG. If these display(s) have not been configured,
13506SHOW displays an error message. For example, if the system is configured for the
CRT, an error is displayed if the user selects the TV with the DS= option.
• If the DS= option is used to combine two displays of different resolutions into the same
surface, the program will display an error message.
• 13506SHOW cannot show a greater color depth than the display allows.
• SwivelView™ (/r90, /r270) is available only for color depths of 8, 15, and 16 bpp.
• SwivelView™ (/r180) is available for color depths of 4, 8, 15, and 16 bpp.
• If the “bl=” or “bc=” options are not used, 13506SHOW will cycle through all available
color depths.
S1D13506
X25B-B-002-03
13506SHOW Demonstration Program
Issue Date: 01/02/06
Epson Research and Development
Vancouver Design Center
Page 9
Program Messages
ERROR: Could not detect S1D13506.
The ID register did not indicate the presence of the 13506.
ERROR: Could not map memory from evaluation board to host platform.
This message should only be shown for DOS platforms. In this case the DOS extender could not be
initialized, or was unable to get the linear address of the display memory.
ERROR: In the given display surface configuration, the user must select the same BPP for
both LCD and CRT/TV.
When two displays are using an image from the same display memory block, both displays must be
configured for the same color depth (bpp).
ERROR: Invalid display surface number.
The "ds=" command line option included an invalid value. The parameter "ds=?" lists the valid
numbers.
ERROR: LCD and CRT resolutions must be identical.
LCD: (width, height)
CRT: (width, height)
When the LCD and CRT are using an image from the same display memory block, both displays
must be the same resolution.
ERROR: LCD and TV resolutions must be identical.
LCD: (width, height)
TV: (width, height)
When the LCD and TV are using an image from the same display memory block, both displays must
be the same resolution.
ERROR: LCD must be in landscape mode.
The LCD panel must be configured for SwivelView 0° mode (landscape) if both the LCD display
and CRT/TV are active.
ERROR: Not enough display buffer memory.
There was insufficient display buffer memory for the given configuration. Memory requirements
depend on:
• the display resolution(s).
• the bit-per-pixel depth(s).
• whether a half-frame buffer is required.
• the number of displays active (LCD or LCD and CRT/TV).
13506SHOW Demonstration Program
Issue Date: 01/02/06
S1D13506
X25B-B-002-03
Page 10
Epson Research and Development
Vancouver Design Center
ERROR: Not enough memory for LCD/CRT/TV in 4/8/16 bits-per-pixel.
13506SHOW is unable to change the color depth due to insufficient display buffer memory.
Memory requirements depend on:
• the display resolution(s).
• the bit-per-pixel depth(s).
• whether a half-frame buffer is required.
• the number of displays active (LCD or LCD and CRT/TV).
ERROR: PCI bridge adapter not found.
The Windows PCI driver did not find the PCI Bridge Adapter.
ERROR: PCI driver not found.
The Windows PCI driver is not loaded.
ERROR: Program not configured for LCD/CRT/TV. Run 13506CFG and configure for
LCD/CRT/TV.
The program was configured by 13506CFG for a display device that is not available. This typically
occurs if the wrong command line was entered for the current configuration.
WARNING: CLKI frequency not in HAL table. Program assumes that external oscillator is
used.
WARNING: CLKI2 frequency not in HAL table. Program assumes that external oscillator is
used.
The correct frequency was not found in the HAL table used to program the clock synthesizer. An
external oscillator may be in use. This warning message will not stop the program.
WARNING: CRT/TV only available in LANDSCAPE mode.
SwivelView™ is only available on LCD only configurations.
ERROR: b= option cannot be used with /noinit.
The command line options b= and /noinit are contradictory, since b= instructs the program to change
the color depth and /noinit indicates that no register changes are to be made.
ERROR: Continual screen read will not work with the /a switch.
ERROR: Continual screen write will not work with the /a switch.
The /a switch automatically cycles through the different color depths, whereas the continual screen
read/write goes into an infinite loop to read/write memory.
ERROR: Do not select 4 BPP LCD in SwivelView ™ 90 or SwivelView™ 270 degrees.
SwivelView™ 90 and SwivelView™ 270 are available only in 8 and 16 bits-per-pixel modes.
S1D13506
X25B-B-002-03
13506SHOW Demonstration Program
Issue Date: 01/02/06
S1D13506 Color LCD/CRT/TV Controller
13506PLAY Diagnostic Utility
Document Number: X25B-B-003-02
Copyright © 2001 Epson Research and Development, Inc. All Rights Reserved.
Information in this document is subject to change without notice.You may download and use this document, but only for your own use in
evaluating Seiko Epson/EPSON products. You may not modify the document. Epson Research and Development, Inc. disclaims any
representation that the contents of this document are accurate or current. The Programs/Technologies described in this document may contain
material protected under U.S. and/or International Patent laws.
EPSON is a registered trademark of Seiko Epson Corporation. All other trademarks are the property of their respective owners.
Page 2
Epson Research and Development
Vancouver Design Center
THIS PAGE LEFT BLANK
S1D13506
X25B-B-003-02
13506PLAY Diagnostic Utility
Issue Date: 01/02/06
Epson Research and Development
Vancouver Design Center
Page 3
13506PLAY
13506PLAY is a diagnostic utility which allows the user to read/write to all the S1D13506
Registers, Look-Up Tables and Display Buffer. 13506PLAY is similar to the DOS DEBUG
program; commands are received from the standard input device, and output is sent to the
standard output device (console for Intel, terminal for embedded platforms). This utility
requires the target platform to support standard IO (stdio).
13506PLAY commands can be entered interactively by a user, or be executed from a script
file. Scripting is a powerful feature which allows command sequences to be used repeatedly
without re-entry.
The 13506PLAY diagnostic utility must be configured and/or compiled to work with your
hardware platform. The program 13506CFG.EXE can be used to configure 13506PLAY.
Consult the 13506CFG users guide, document number X25B-B-001-xx, for more information on configuring S1D13506 utilities.
This software is designed to work in both embedded and personal computer (PC) environments. For the embedded environment, it is assumed that the system has a means of
downloading software from the PC to the target platform. Typically this is done by serial
communications, where the PC uses a terminal program to send control commands and
information to the target processor. Alternatively, the PC can program an EPROM, which
is then placed in the target platform. Some target platforms can also communicate with the
PC via a parallel port connection, or an Ethernet connection.
S1D13506 Supported Evaluation Platforms
13506PLAY supports the following S1D13506 evaluation platforms:
• PC with an Intel 80x86 processor running Windows ‘95/’98/NT.
• M68EC000IDP (Integrated Development Platform) board, revision 3.0, with a Motorola
M68EC000 processor.
• MC68030IDP (Integrated Development Platform) board, revision 3.0, with a Motorola
MC68030 processor.
• SH3-LCEVB board, revision B, with an Hitachi SH-3 HD6417780 processor.
• MPC821ADS (Applications Development System) board, revision B, with a Motorola
MPC821 processor.
13506PLAY Diagnostic Utility
Issue Date: 01/02/06
S1D13506
X25B-B-003-02
Page 4
Epson Research and Development
Vancouver Design Center
Installation
PC platform
Copy the file 13506play.exe to a directory in the path (e.g. PATH=C:\S1D13506).
Embedded platform
Download the program 13506play to the system.
Usage
PC platform
At the prompt, type:
13506play [/?]
Where:
/?
displays program version information.
Embedded platform
Execute 13506play and at the prompt, type the command line argument.
Where:
/?
S1D13506
X25B-B-003-02
displays program version information.
13506PLAY Diagnostic Utility
Issue Date: 01/02/06
Epson Research and Development
Vancouver Design Center
Page 5
Commands
The following commands are designed to be used from within the 13506PLAY program.
However, simple commands can also be executed from the command line. If a command
with multiple arguments is executed from the command line, it must be enclosed in double
quotes (e.g. 13506play “f 0 1FFFFF AB” q).
CLKI [?] iFreq
Selects a preset clock frequency (MHz) for CLKI. If the “?” option is used, the current
CLKI frequency is displayed.
Where:
?
Displays a list of available frequencies for CLKI (MHz).
iFreq
Sets CLKI to a preset frequency (MHz) specified by iFreq.
CLKI2 [?] iFreq
Selects a preset clock frequency (MHz) for CLKI2. If the “?” option is used, the current
CLKI2 frequency is displayed.
Where:
?
Displays a list of available frequencies for CLKI2 (MHz).
iFreq
Sets CLKI2 to a preset frequency (MHz) specified by iFreq.
CW word
Sends a 24-bit hexadecimal value to the programmable clock. Note that the programmable
clock documentation uses the term “word” to describe the 24-bit value. The use of “word”
does not imply a 16-bit value in this case.
F addr addr data...
Fills a specified address range with 8-bit data (bytes).
Where:
addr
Address range to be filled (hex).
data
Data to be written (hex). Data can be a list of bytes that will
be repeated for the duration of the fill. To use decimal
values, attach a “t” suffix to the value. (e.g. 100t is 100
decimal)
FD addr addr data...
Fills a specified address range with 32-bit data (dwords).
Where:
addr
Address range to be filled (hex).
data
Data to be written (hex). Data can be a list of dwords that
will be repeated for the duration of the fill. To use decimal
values, attach a “t” suffix to the value. (e.g. 100t is 100
decimal)
13506PLAY Diagnostic Utility
Issue Date: 01/02/06
S1D13506
X25B-B-003-02
Page 6
Epson Research and Development
Vancouver Design Center
FW addr addr data...
Fills a specified address range with 16-bit data (words).
Where:
addr
Address range to be filled (hex).
data
Data to be written (hex). Data can be a list of words that will
be repeated for the duration of the fill. To use decimal
values, attach a “t” suffix to the value. (e.g. 100t is 100
decimal).
H [lines]
Sets the number of lines of data that will be displayed at a time. The display will be halted
after the specified number of lines. Setting the number of lines to 0 will disable the halt
function and allow the data to continue displaying until all data has been shown.
Where:
lines
Number of lines that will be shown before halting the
displayed data (decimal value).
I [?] {LCD|CRT|TV} [d=iCrtTv] [COMP | SVIDEO] [FLICKER=ON | OFF]
Initializes the S1D13506 registers for a given display type.
Where:
?
Displays a help message.
LCD
Initializes the LCD registers.
CRT
Initializes the CRT registers.
TV
Initializes the TV registers.
d = iCrtTv
Initializes the CRT/TV for a display configuration based on
the following table.
Table 1: iCrtTv Selection
COMP
SVIDEO
FLICKER=ON
FLICKER=OFF
S1D13506
X25B-B-003-02
iCrtTv
Resolution
Display Type
0
640x480
CRT
1
800x600
CRT
2
752x484
TV (NTSC)
3
696x436
TV (NTSC)
4
640x480
TV (NTSC)
5
920x572
TV (PAL)
6
856x518
TV (PAL)
7
800x572
TV (PAL)
8
640x480
TV (PAL)
Initializes for Composite video output (TV only).
Initializes for SVideo output (TV only).
Initializes for Flicker Filter enabled (TV only).
Initializes for Flicker Filter disabled (TV only).
13506PLAY Diagnostic Utility
Issue Date: 01/02/06
Epson Research and Development
Vancouver Design Center
Page 7
IC {LCD|CRT|TV}
Initializes the Hardware Cursor for a given display type.
Where:
LCD
Initializes for the LCD display.
CRT
Initializes for the CRT display.
TV
Initializes for the TV display.
II {LCD|CRT|TV}
Initializes the Ink Layer for a given display type.
Where:
LCD
Initializes for the LCD display.
CRT
Initializes for the CRT display.
TV
Initializes for the TV display.
L {LCD|CRT|TV} index [red green blue]
Writes red, green, and blue Look-Up Table (LUT) components for a given display type. If
the red, green, and blue components are not specified, reads the components at the given
index.
Where:
LCD
LUT used by the LCD display.
CRT
LUT used by the CRT display.
TV
LUT used by the TV display.
index
Index into the LUT (hex).
red
Red component of the LUT (hex).
green
Green component of the LUT (hex).
blue
Blue component of the LUT (hex).
Note
Only bits 7-4 of each color are used in the LUT. For example, 10h is the first color intensity after 00h. Valid LUT colors follow the pattern 00h, 10h, 20h, 30h,...E0h, F0h.
LA {LCD|CRT|TV}
Reads all LUT values for a given display.
Where:
LCD
Reads LUT values for LCD display.
CRT
Reads LUT values for CRT display.
TV
Reads LUT values for TV display.
Note
Only bits 7-4 of each color are used in the LUT. For example, 10h is the first color intensity after 00h. Valid LUT colors follow the pattern 00h, 10h, 20h, 30h,...E0h, F0h.
13506PLAY Diagnostic Utility
Issue Date: 01/02/06
S1D13506
X25B-B-003-02
Page 8
Epson Research and Development
Vancouver Design Center
M [?] {LCD|CRT|TV} [bpp]
Sets the color depth (bpp) for the specified display type. If no color depth is provided, information about the current setting on the specified display are listed.
Where:
?
Displays basic information on the current mode for a given
display.
LCD
Sets the color depth of the LCD display.
CRT
Sets the color depth of the CRT display.
TV
Sets the color depth of the TV display.
bpp
Color depth to be set (4/8/16 bpp).
MC [?] {LCD|CRT|TV} [bpp]
Gets extended information and sets the color depth (bpp).
Where:
?
Displays further information on the current mode for a given
display.
LCD
Sets the color depth of the LCD display.
CRT
Sets the color depth of the CRT display.
TV
Sets the color depth of the TV display.
bpp
Color depth to be set (4/8/16 bpp).
Q
Quits the program.
R addr [count]
Reads a certain number of bytes from the specified address. If no value is provided for
count, it defaults to 10h.
Where:
addr
Address from which byte(s) will be read (hex).
count
Number of bytes to be read (hex).
RD addr [count]
Reads a certain number of dwords from the specified address. If no value is provided for
count, it defaults to 10h.
Where:
addr
Address from which dword(s) will be read (hex).
count
Number of dwords to be read (hex).
RW addr [count]
Reads a certain number of words from the specified address. If no value is provided for
count, it defaults to 10h.
Where:
addr
Address from which word(s) will be read (hex).
count
Number of words to be read (hex).
S1D13506
X25B-B-003-02
13506PLAY Diagnostic Utility
Issue Date: 01/02/06
Epson Research and Development
Vancouver Design Center
Page 9
S {CLKI | CLKI2 | BUSCLK} freq
Sets PCLK source frequency (in kHz).
Where:
CLKI
Sets PCLK source to CLKI.
CLKI2
Sets PCLK source to CLKI2.
BUSCLK
Sets PCLK source to BUSCLK.
freq
Sets the frequency of the PCLK source (decimal value).
V
Calculates the current frame rate for all enabled display devices. The frame rate is calculated from the VNDP count.
W addr data ...
Writes byte(s) of data to specified memory address.
Where:
addr
Address data is written to
data
Data to be written (hex). Data can be a list of bytes that will
be repeated for the duration of the write. To use decimal
values, attach a “t” suffix to the value. (e.g. 100t is 100
decimal).
WD addr data ...
Writes dword(s) of data to specified memory address.
Where:
addr
Address data is written to
data
Data to be written (hex). Data can be a list of dwords that
will be repeated for the duration of the write. To use decimal
values, attach a “t” suffix to the value. (e.g. 100t is 100
decimal).
WW addr data ...
Writes word(s) of data to specified memory address.
Where:
addr
Address data is written to
data
Data to be written (hex). Data can be a list of words that will
be repeated for the duration of the write. To use decimal
values, attach a “t” suffix to the value. (e.g. 100t is 100
decimal).
X index [data]
Writes byte data to the register at index. If no data is specified, reads the 8-bit (byte) data
from the register at index.
Where:
index
Index into the registers (hex).
data
Data to be written to/read from register (hex). Data can be a
list of bytes that will be repeated for the duration of the
write. To use decimal values, attach a “t” suffix to the value.
(e.g. 100t is 100 decimal).
13506PLAY Diagnostic Utility
Issue Date: 01/02/06
S1D13506
X25B-B-003-02
Page 10
Epson Research and Development
Vancouver Design Center
XA
Reads all the S1D13506 registers.
XD index [data]
Writes dword data to the register at index. If no data is specified, reads the 32-bit (dword)
data from the register at index.
Where:
index
Index into the registers (hex).
data
Data to be written to/read from register (hex). Data can be a
list of dwords that will be repeated for the duration of the
write. To use decimal values, attach a “t” suffix to the value.
(e.g. 100t is 100 decimal).
XW index [data]
Writes word data to the register at index. If no data is specified, reads the 16-bit (word) data
from the register at index.
Where:
index
Index into the registers (hex).
data
Data to be written to/read from register (hex). Data can be a
list of words that will be repeated for the duration of the
write. To use decimal values, attach a “t” suffix to the value.
(e.g. 100t is 100 decimal).
?
Displays the help screen.
S1D13506
X25B-B-003-02
13506PLAY Diagnostic Utility
Issue Date: 01/02/06
Epson Research and Development
Vancouver Design Center
Page 11
13506PLAY Example
1. Type 13506PLAY to start the program.
2. Type ? for help.
3. Type i LCD to initialize the registers.
4. Type xa to display the contents of the registers.
5. Type x 34 to read register 34h.
6. Type x 34 10 to write 10h to register 34h.
7. Type f 0 ffff aa to fill the first FFFFh bytes of the display buffer with AAh.
8. Type f 0 1fffff aa to fill 2M bytes of the display buffer with AAh.
9. Type r 0 100 to read the first 100h bytes of the display buffer.
10. Type q to exit the program.
13506PLAY Diagnostic Utility
Issue Date: 01/02/06
S1D13506
X25B-B-003-02
Page 12
Epson Research and Development
Vancouver Design Center
Scripting
13506PLAY can be driven by a script file. This is useful when:
• there is no display output and a current register status is required.
• various registers must be quickly changed to view results.
A script file is an ASCII text file with one 13506PLAY command per line. All scripts must
end with a “q” (quit) command.
On a PC platform, a typical script command line might be:
“13506PLAY < dumpregs.scr > results.”
This causes the file “dumpregs.scr” to be interpreted as commands by 13506PLAY and the
results to be sent to the file “results.”
Example: Create an ASCII text file that contains the commands i, xa, and q.
; This file initializes the S1D13506 and reads the registers.
; Note: after a semicolon (;), all characters on a line are ignored.
; Note: all script files must end with the “q” command.
i
xa
q
Comments
• All displayed numeric values are considered to be hexadecimal unless identified otherwise. For example, 10 = 10h = 16 decimal; 10t = 10 decimal; 010b = 2 decimal.
• Redirecting commands from a script file (PC platform) allows those commands to be
executed as though they were typed.
S1D13506
X25B-B-003-02
13506PLAY Diagnostic Utility
Issue Date: 01/02/06
Epson Research and Development
Vancouver Design Center
Page 13
Program Messages
ERROR: Could not map memory from evaluation board to host platform.
This message should only be shown for DOS platforms. In this case the DOS extender could not be
initialized, or was unable to get the linear address of the display memory.
ERROR: Not enough display buffer memory.
There was insufficient display buffer memory for the given configuration. Memory requirements
depend on:
• the display resolution(s).
• the bit-per-pixel depth(s).
• whether a half-frame buffer is required.
• the number of displays active (LCD or LCD and CRT/TV).
ERROR: Not enough memory for LCD/CRT/TV in 4/8/16 bits-per-pixel.
13506BMP is unable to change the color depth due to insufficient display buffer memory. Memory
requirements depend on:
• the display resolution(s).
• the bit-per-pixel depth(s).
• whether a half-frame buffer is required.
• the number of displays active (LCD or LCD and CRT/TV).
ERROR: PCI bridge adapter not found.
The Windows PCI driver did not find the PCI Bridge Adapter.
ERROR: PCI driver not found.
The Windows PCI driver is not loaded.
ERROR: Program not configured for LCD/CRT/TV. Run 13506CFG and configure for
LCD/CRT/TV.
The program was configured by 13506CFG for a display device that is not available. This typically
occurs if the wrong command line was entered for the current configuration.
WARNING: CLKI frequency not in HAL table. Program assumes that external oscillator is
used.
WARNING: CLKI2 frequency not in HAL table. Program assumes that external oscillator is
used.
The correct frequency was not found in the HAL table used to program the clock synthesizer. An
external oscillator may be in use. This warning message will not stop the program.
ERROR: At least one of the displays must be enabled.
This message is shown when 13506PLAY received the V command, but no display is enabled. At
least one display must be enabled for the V command to function (5 seconds of VNDP pulses are
counted to calculate the frame rate).
ERROR: Invalid iFreq value.
The CLKI and/or CLKI2 commands were used with an invalid iFreq value. To display a list of iFreq
values, type "CLKI ?" or "CLKI2 ?".
13506PLAY Diagnostic Utility
Issue Date: 01/02/06
S1D13506
X25B-B-003-02
Page 14
Epson Research and Development
Vancouver Design Center
ERROR: Not enough display buffer memory for LCD/CRT/TV cursor/ink layer.
There was insufficient display buffer memory for the given Hardware Cursor/Ink Layer configuration. Memory requirements depend on:
• the display resolution(s).
• the bit-per-pixel depth(s).
• whether a half-frame buffer is required.
• the number of displays active (LCD or LCD and CRT/TV).
WARNING: FEATCLK cannot be multiplexed to CLKI. Clock synthesizer programmed
instead.
In 13506PLAY, the CLKI command was used to select the FEATCLK frequency. Since the
FEATCLK can only be multiplexed to CLKI2, the clock synthesizer is programmed instead.
S1D13506
X25B-B-003-02
13506PLAY Diagnostic Utility
Issue Date: 01/02/06
S1D13506 Color LCD/CRT/TV Controller
13506BMP Demonstration Program
Document Number: X25B-B-004-02
Copyright © 2001 Epson Research and Development, Inc. All Rights Reserved.
Information in this document is subject to change without notice.You may download and use this document, but only for your own use in
evaluating Seiko Epson/EPSON products. You may not modify the document. Epson Research and Development, Inc. disclaims any
representation that the contents of this document are accurate or current. The Programs/Technologies described in this document may contain
material protected under U.S. and/or International Patent laws.
EPSON is a registered trademark of Seiko Epson Corporation. All other trademarks are the property of their respective owners.
Page 2
Epson Research and Development
Vancouver Design Center
THIS PAGE LEFT BLANK
S1D13506
X25B-B-004-02
13506BMP Demonstration Program
Issue Date: 01/02/06
Epson Research and Development
Vancouver Design Center
Page 3
13506BMP
13506BMP is a demonstration utility used to show the S1D13506 display capabilities by
rendering bitmap images on the display device(s). The program will display any bitmap
stored in Windows BMP file format and then exit. 13506BMP supports SviwelView™
(90°, 180°, and 270° hardware rotation of the display image).
13506BMP is designed to operate on a personal computer (PC) within a 32-bit environment
only (Windows ‘95/’98/NT). Other embedded platforms are not supported due to the
possible lack of system memory or structured file system.
The 13506BMP demonstration utility must be configured and/or compiled to work with
your hardware configuration. The program 13506CFG.EXE can be used to configure
13506BMP. Consult the 13506CFG users guide, document number X25B-B-001-xx, for
more
information on configuring S1D13506 utilities.
S1D13506 Supported Evaluation Platforms
13506BMP supports the following S1D13506 evaluation platforms:
• PC with an Intel 80x86 processor running Windows ‘95/’98/NT.
Note
The 13506BMP source code may be modified by the OEM to support other evaluation
platforms.
Installation
Copy the file 13506bmp.exe to a directory in the path (e.g. PATH=C:\S1D13506).
13506BMP Demonstration Program
Issue Date: 01/02/06
S1D13506
X25B-B-004-02
Page 4
Epson Research and Development
Vancouver Design Center
Usage
At the prompt, type:
13506bmp bmpfile [ds=n | ds=?] [/noinit] [/r90 | /r180 | /r270] [/v] [/?]
Where:
bmpfile
specifies filename of a windows format bmp image
ds=n
selects display surfaces (see Section , “Display Surfaces”
on page 5)
ds=?
shows available display surfaces (see Section , “Display
Surfaces” on page 5)
/noinit
skips full register initialization. Only registers used for
changing the color depth (bpp), selecting the
memory/registers and programming the clock synthesizer are updated. Additionally, some registers are read
to determine information such as display size and type
(LCD, CRT, TV).
/r90
SwivelView™ 90°, clockwise hardware rotation of LCD
image by 90 degrees
/r180
SwivelView™ 180°, clockwise hardware rotation of LCD
image by 180 degrees
/r270
SwivelView™ 270°, clockwise hardware rotation of LCD
image by 270 degrees
/v
verbose mode (provides information about the displayed
image)
/?
displays the help message
Note
13506BMP will automatically finish execution and return to the prompt.
S1D13506
X25B-B-004-02
13506BMP Demonstration Program
Issue Date: 01/02/06
Epson Research and Development
Vancouver Design Center
Page 5
Display Surfaces
A surface is a block of memory assigned to one or more physical display devices.
13506BMP provides 7 display surfaces (0-6) which cover the possible combinations of
display types. Table 1:, “Display Surfaces” lists the predefined display surfaces that may
be selected.
Table 1: Display Surfaces
Display Surfaces
(ds=)
Display
Display
Device(s) using Device(s) using
Memory Block 0 Memory Block 1
0
LCD
1
CRT
2
TV
3
LCD & CRT
4
LCD & TV
5
LCD
CRT
6
LCD
TV
Display surfaces 0 through 2 each display data from a single memory block to an individual
display device (LCD, CRT, or TV).
Display surfaces 3 and 4 output to two seperate display devices, but generate the output
from the same memory block. This may be useful when the same image is to be displayed
on both display devices. It also reduces the total amount of display memory required.
Display surfaces 5 and 6 output to two seperate devices from different memory blocks. This
allows two completely different images to be displayed at the same time. When using
display surfaces 5 or 6, some combinations of display modes with a high resolution and/or
high color depth may not be supported within a 2MB display buffer.
13506BMP Demonstration Program
Issue Date: 01/02/06
S1D13506
X25B-B-004-02
Page 6
Epson Research and Development
Vancouver Design Center
13506BMP Examples
To display a bmp image on an LCD, type the following:
13506bmp bmpfile.bmp ds=0
To display a bmp image on a CRT, type the following:
13506bmp bmpfile.bmp ds=1
To display a bmp image on an LCD with 90° SwivelView™ enabled, type the following:
13506bmp bmpfile.bmp ds=0 /r90
To display a bmp image on both the LCD and CRT, type the following:
13506bmp bmpfile.bmp ds=3
To display independent bmp images on the LCD and TV, type the following:
13506bmp bmpfile.bmp ds=6
Comments
• 13506BMP displays only Windows BMP format images.
• A 24-bit true color bitmap will be displayed at a color depth of 16 bit-per-pixel.
• Only the green component of the image will be seen on a monochrome display.
S1D13506
X25B-B-004-02
13506BMP Demonstration Program
Issue Date: 01/02/06
Epson Research and Development
Vancouver Design Center
Page 7
Program Messages
ERROR: Could not detect S1D13506.
The ID register did not indicate the presence of the S1D13506.
ERROR: Could not map memory from evaluation board to host platform.
This message should only be shown for DOS platforms. In this case the DOS extender could not be
initialized, or was unable to get the linear address of the display memory.
ERROR: Failed to open BMP file:'filename'
Could not open the BMP file.
ERROR: 'filename' is not a valid bitmap file.
The filename given on the command line is not a valid BMP file.
ERROR: In the given display surface configuration, the user must select the same BPP for
both LCD and CRT/TV.
When two displays are using an image from the same display memory block, both displays must be
configured for the same color depth (bpp).
ERROR: Invalid display surface number.
The "ds=" command line option included an invalid value. The parameter "ds=?" lists the valid
numbers.
ERROR: LCD and CRT resolutions must be identical.
LCD: (width, height)
CRT: (width, height)
When the LCD and CRT are using an image from the same display memory block, both displays
must be the same resolution.
ERROR: LCD and TV resolutions must be identical.
LCD: (width, height)
TV: (width, height)
When the LCD and TV are using an image from the same display memory block, both displays must
be the same resolution.
ERROR: LCD must be in landscape mode.
The LCD panel must be configured for landscape mode if both the LCD display and CRT/TV are
active.
ERROR: Not enough display buffer memory.
There was insufficient display buffer memory for the given configuration. Memory requirements
depend on:
• the display resolution(s).
• the bit-per-pixel depth(s).
• whether a half-frame buffer is required.
• the number of displays active (LCD or LCD and CRT/TV).
13506BMP Demonstration Program
Issue Date: 01/02/06
S1D13506
X25B-B-004-02
Page 8
Epson Research and Development
Vancouver Design Center
ERROR: Not enough memory for LCD/CRT/TV in 4/8/15/16 bits-per-pixel.
13506BMP is unable to change the color depth due to insufficient display buffer memory. Memory
requirements depend on:
• the display resolution(s).
• the bit-per-pixel depth(s).
• whether a half-frame buffer is required.
• the number of displays active (LCD or LCD and CRT/TV).
ERROR: Not enough memory for virtual display.
A virtual display is required for SwivelView ™. This error message indicates there is insufficient
memory for the given configuration. Memory requirements depend on:
• the display resolution(s).
• the bit-per-pixel depth(s).
• whether a half-frame buffer is required.
• the number of displays active (LCD or LCD and CRT/TV).
ERROR: PCI bridge adapter not found.
The Windows PCI driver did not find the PCI Bridge Adapter.
ERROR: PCI driver not found.
The Windows PCI driver is not loaded.
ERROR: Program not configured for LCD/CRT/TV. Run 13506CFG and configure for
LCD/CRT/TV.
The program was configured by 13506CFG for a display device that is not available. This typically
occurs if the wrong command line was entered for the current configuration.
WARNING: CLKI frequency not in HAL table. Program assumes that external oscillator is
used.
WARNING: CLKI2 frequency not in HAL table. Program assumes that external oscillator is
used.
The correct frequency was not found in the HAL table used to program the clock synthesizer. An
external oscillator may be in use. This warning message will not stop the program.
WARNING: CRT/TV only available in LANDSCAPE mode.
SwivelView™ is only available on LCD only configurations.
S1D13506
X25B-B-004-02
13506BMP Demonstration Program
Issue Date: 01/02/06
S1D13506 Color LCD/CRT/TV Controller
13506FILT Test Utility
Document Number: X25B-B-005-02
Copyright © 2001 Epson Research and Development, Inc. All Rights Reserved.
Information in this document is subject to change without notice.You may download and use this document, but only for your own use in
evaluating Seiko Epson/EPSON products. You may not modify the document. Epson Research and Development, Inc. disclaims any
representation that the contents of this document are accurate or current. The Programs/Technologies described in this document may contain
material protected under U.S. and/or International Patent laws.
EPSON is a registered trademark of Seiko Epson Corporation. Microsoft and Windows are registered trademarks of Microsoft Corporation.
All other trademarks are the property of their respective owners.
Page 2
Epson Research and Development
Vancouver Design Center
THIS PAGE LEFT BLANK
S1D13506
X25B-B-005-02
13506FILT Test Utility
Issue Date: 01/02/06
Epson Research and Development
Vancouver Design Center
Page 3
13506FILT
13506FILT is an interactive Windows® 9x/NT program that enables/disables the
S1D13506 TV Filters. It demonstrates the effect each filter has on a pre-loaded TV image.
13506FILT is particularly useful in a test or demonstration environment where 13506FILT
is run on one display and the effects of enabling/disabling each filter are seen on a TV. An
OEM may find this useful in determining the appropriate filters for their application.
Note
The 13506FILT dialog box doesn’t appear on any display device controlled by the
S1D13506. The 13506FILT dialog box appears on the Win 9x/NT desktop.
13506FILT is designed to operate on a personal computer (PC) within a 32-bit environment
only (Windows 9x/NT). Other embedded platforms are not supported.
S1D13506 Supported Evaluation Platforms
13506FILT supports the following S1D13506 evaluation platforms:
• PC with an Intel 80x86 processor running Windows 9x/NT.
Installation
Copy the file 13506filt.exe to a directory in the path. If desired, create a shortcut on the
Windows 9x/NT desktop to the file 13506filt.exe.
Usage
In Windows ‘9x/NT, double-click the following icon:
Or, at the Windows DOS Prompt, type 13506filt.
13506FILT Test Utility
Issue Date: 01/02/06
S1D13506
X25B-B-005-02
Page 4
Epson Research and Development
Vancouver Design Center
Filter Dialog Box
The filter dialog box controls which TV filters are enabled/disabled during NTSC or PAL
output. The check box for each filter determines if the filter is enabled or disabled. When
the box is checked the filter is enabled. When the box is unchecked the filter is disabled. In
the example below:
• the flicker filter is disabled.
• the chrominance filter is enabled.
• the luminance filter is enabled.
Figure 1: Filter Dialog Box
S1D13506
X25B-B-005-02
13506FILT Test Utility
Issue Date: 01/02/06
Epson Research and Development
Vancouver Design Center
Page 5
Filter Descriptions
When displaying computer images on a TV, several image distortions are likely to arise:
• flickering.
• cross-chrominance distortion.
• cross-luminance distortion.
These distortions are caused by the high-resolution nature of computer images which
typically contain sharp chrominance (color) transitions, and sharp luminance (brightness)
transitions. Three filters are available to reduce these distortions.
Anti-flicker Filter
The “flickering” effect seen on interlaced displays is caused by sharp vertical image transitions that occur over one line (1 vertical pixel). For example, flickering may occur where
there are one pixel high lines, edges of window boxes, etc. Flickering occurs because these
high resolution lines are effectively displayed at half the refresh frequency due to interlacing. To reduce flickering, the anti-flicker filter averages adjacent lines on the TV
display.
Chrominance Filter
The chrominance filter adjusts the color of the TV by limiting the bandwidth of the chrominance signal (reducing cross-luminance distortion). This reduces the “ragged edges” seen
at boundaries between sharp color transitions. This filter is intended for use with composite
video output.
Luminance Filter
The luminance filter adjusts the brightness of the TV by limiting the bandwidth of the
luminance signal (reducing cross-chrominance distortion). This reduces the “rainbow-like”
colors at boundaries between sharp luminance transitions. This filter is intended for use
with composite video output.
13506FILT Test Utility
Issue Date: 01/02/06
S1D13506
X25B-B-005-02
Page 6
Epson Research and Development
Vancouver Design Center
Comments
• The Flicker Filter can’t be enabled unless a TV is present and active.
• 13506FILT is designed to show the effects of the filters on a pre-loaded TV image.
13506BMP may be used to display a static image on the TV (see the 13506BMP Users
Manual, document number X25B-B-004-xx).
• The chrominance and luminance filters are intended for use with composite output.
• For information on manually enabling/disabling the TV filters, refer to the S1D13506
Hardware Functional Specification (document number X25B-A-001-xx) and the
S1D13506 Programming Notes and Examples (document number X25B-G-003-xx).
S1D13506
X25B-B-005-02
13506FILT Test Utility
Issue Date: 01/02/06
S1D13506 Color LCD/CRT/TV Controller
13506SWIVEL Demonstration Utility
Document Number: X25B-B-006-02
Copyright © 2001 Epson Research and Development, Inc. All Rights Reserved.
Information in this document is subject to change without notice.You may download and use this document, but only for your own use in
evaluating Seiko Epson/EPSON products. You may not modify the document. Epson Research and Development, Inc. disclaims any
representation that the contents of this document are accurate or current. The Programs/Technologies described in this document may contain
material protected under U.S. and/or International Patent laws.
EPSON is a registered trademark of Seiko Epson Corporation. Microsoft and Windows are registered trademarks of Microsoft Corporation.
All other trademarks are the property of their respective owners.
Page 2
Epson Research and Development
Vancouver Design Center
THIS PAGE LEFT BLANK
S1D13506
X25B-B-006-02
13506SWIVEL Demonstration Utility
Issue Date: 01/02/06
Epson Research and Development
Vancouver Design Center
Page 3
13506SWIVEL
13506SWIVEL is a command line utility that demonstrates the SwivelView™ feature of
the S1D13506. The SwivelView feature provides hardware rotation of a predefined image
by 90°, 180°, and 270° in a clockwise direction. 13506SWIVEL cycles through each
SwivelView mode, advancing to the next mode when a key is pressed.
13506SWIVEL is designed to operate on a personal computer (PC) within a 32-bit
environment only (Windows 9x/NT). Other embedded platforms are not supported.
The 13506SWIVEL utility must be configured and/or compiled to work with your
hardware configuration. The program 13506CFG.EXE can be used to configure
13506SWIVEL. Consult the 13506CFG Users Manual, document number X25B-B-001xx, for more
information on configuring S1D13506 utilities.
S1D13506 Supported Evaluation Platforms
13506SWIVEL supports the following S1D13506 evaluation platforms:
• PC with an Intel 80x86 processor running Windows 9x/NT.
Installation
Copy the file 13506swivel.exe to a directory in the path. If desired, create a shortcut on the
Windows 9x/NT desktop to the file 13506swivel.exe.
Usage
At the Windows DOS Prompt, type:
13506swivel
Note
Pressing the ESC key exits the program.
13506SWIVEL Demonstration Utility
Issue Date: 01/02/06
S1D13506
X25B-B-006-02
Page 4
Epson Research and Development
Vancouver Design Center
Example
1. Run the utility 13506SWIVEL. At the Windows DOS prompt type:
13506swivel
Note
A pattern of colored numbers appears in SwivelView 0° mode (normal landscape).
2. Press any key to enable SwivelView 90° mode. The displayed image is rotated by 90°.
3. Press any key to enable SwivelView 180° mode. The displayed image is rotated by
180°.
4. Press any key to enable SwivelView 270° mode. The displayed image is rotated by
270°.
5. Press any key to return to SwivelView 0° mode (normal landscape).
6. Press the ESC key to exit the program.
Note
13506SWIVEL will continue to cycle through the SwivelView modes in the above order until the ESC key is pressed.
Comments
• 13506SWIVEL supports LCD panels only (no CRT or TV).
• 13506SWIVEL only supports 8/15/16 bpp color depths.
• 13506SWIVEL must be configured for LCD only using the utility 13506CFG. For
further information on 13506CFG, refer to the 13506CFG Users Manual, document
number X25B-B-001-xx.
• For further information on SwivelView™, refer to the S1D13506 Hardware Functional
Specification (document number X25B-A-001-xx) and the S1D13506 Programming
Notes and Examples (document number X25B-G-003-xx).
S1D13506
X25B-B-006-02
13506SWIVEL Demonstration Utility
Issue Date: 01/02/06
S1D13506 Color LCD/CRT/TV Controller
Windows® CE Display Drivers
Document Number: X25A-E-001-05
Copyright © 2001 Epson Research and Development, Inc. All Rights Reserved.
Information in this document is subject to change without notice.You may download and use this document, but only for your own use in
evaluating Seiko Epson/EPSON products. You may not modify the document. Epson Research and Development, Inc. disclaims any
representation that the contents of this document are accurate or current. The Programs/Technologies described in this document may contain
material protected under U.S. and/or International Patent laws.
EPSON is a registered trademark of Seiko Epson Corporation. Microsoft and Windows are registered trademarks of Microsoft Corporation.
All other trademarks are the property of their respective owners.
Page 2
Epson Research and Development
Vancouver Design Center
THIS PAGE LEFT BLANK
S1D13506
X25A-E-001-05
Windows® CE Display Drivers
Issue Date: 01/02/06
Epson Research and Development
Vancouver Design Center
Page 3
WINDOWS® CE DISPLAY DRIVERS
The Windows CE display drivers are designed to support the S1D13506 Color
LCD/CRT/TV Controller running under the Microsoft Windows CE operating system.
Available drivers include: 4, 8 and 16 bit-per-pixel landscape modes (no rotation), and 8
and 16 bit-per-pixel SwivelView™ 90°, 180° and 270° modes.
Note
The Windows CE display drivers are provided as examples only. The source code contains functionality for all features of the S1D13506. Source code modification is necessary to provide a smaller, more efficent driver for mass production (i.e. TV support may
be removed for products not requiring TV).
This document and the source code for the Windows CE drivers is updated as appropriate.
Please check the Epson Electronics America Website at http://www.eea.epson.com for the
latest revisions before beginning any development.
We appreciate your comments on our documentation. Please contact us via email at
[email protected]
Program Requirements
Windows® CE Display Drivers
Issue Date: 01/02/06
Video Controller
: S1D13506
Display Type
: LCD or CRT
Windows Version
: CE Version 2.0 and 2.11
S1D13506
X25A-E-001-05
Page 4
Epson Research and Development
Vancouver Design Center
Example Driver Builds
Build for CEPC (X86) on Windows CE 2.0
To build a Windows CE v2.0 display driver for the CEPC (X86) platform using a
S5U13506B00C evaluation board, follow the instructions below:
1. Install Microsoft Windows NT v4.0.
2. Install Microsoft Visual C/C++ v5.0.
3. Install the Microsoft Windows CE Embedded Toolkit (ETK) by running SETUP.EXE
from the ETK compact disc #1.
4. Create a new project by following the procedure documented in “Creating a New
Project Directory” from the Windows CE ETK V2.0. Alternately, use the current
“DEMO7” project included with the ETK v2.0. Follow the steps below to create a
“X86 DEMO7” shortcut on the Windows NT v4.0 desktop which uses the current
“DEMO7” project:
a. Right click on the “Start” menu on the taskbar.
b. Click on the item “Open All Users” and the “Start Menu” window will come up.
c. Click on the icon “Programs”.
d. Click on the icon “Windows CE Embedded Development Kit”.
e. Drag the icon “X86 DEMO1” onto the desktop using the right mouse button.
f. Click on “Copy Here”.
g. Rename the icon “X86 DEMO1” on the desktop to “X86 DEMO7” by right clicking on
the icon and choosing “rename”.
h. Right click on the icon “X86 DEMO7” and click on “Properties” to bring up the
“X86 DEMO7 Properties” window.
i. Click on “Shortcut” and replace the string “DEMO1” under the entry “Target” with
“DEMO7”.
j. Click on “OK” to finish.
Note
You may need administrator privilege on your local developing machine to perform the
above steps. If you only have a user privilege, you may refer to step 3 of the Section ,
“Build for CEPC (X86) on Windows CE Platform Builder 2.11” on page 6.
5. Create a sub-directory named S1D13506 under \wince\platform\cepc\drivers\display.
6. Copy the source code to the S1D13506 subdirectory.
7. Add an entry for the S1D13506 in the file \wince\platform\cepc\drivers\display\dirs.
S1D13506
X25A-E-001-05
Windows® CE Display Drivers
Issue Date: 01/02/06
Epson Research and Development
Vancouver Design Center
Page 5
8. Edit the file PLATFORM.BIB (located in X:\wince\platform\cepc\files) to set the default display driver to the file EPSON.DLL. (EPSON.DLL will be created during the
build in step 12)
You may replace the following lines in PLATFORM.BIB:
IF CEPC_DDI_VGA2BPP
ddi.dll
$(_FLATRELEASEDIR)\ddi_vga2.dll
NK SH
ENDIF
IF CEPC_DDI_VGA8BPP
ddi.dll
$(_FLATRELEASEDIR)\ddi_vga8.dll
NK SH
ENDIF
IF CEPC_DDI_VGA2BPP !
IF CEPC_DDI_VGA8BPP !
ddi.dll
$(_FLATRELEASEDIR)\ddi_s364.dll
NK SH
$(_FLATRELEASEDIR)\EPSON.dll
NK SH
ENDIF
ENDIF
with this line:
ddi.dll
9. If the current MODE0.H is not appropriate for your project, generate a new MODE0.H
file using the S1D13506 utility program 13506CFG.EXE. The file MODE0.H (located in
X:\wince\platform\cepc\drivers\display\S1D13506) contains the register values required
to set desired screen resolution, color depth (bpp), panel type, active display(LCD/CRT/TV), rotation, etc.
10. Edit the file PLATFORM.REG to match the screen resolution, color depth (bpp), active
display(LCD/CRT/TV) and rotation information in MODE.H. PLATFORM.REG is
located in X:\wince\platform\cepc\files. For example, the display driver section of
PLATFORM.REG should be as follows when using a 640x480 LCD panel with a color
depth of 8 bpp in SwivelView 0° (landscape) mode.
; Default for EPSON Display Driver
; 640x480 at 8bits/pixel, LCD display, no rotation
; Useful Hex Values
; 1024=0x400, 768=0x300 640=0x280 480=0x1E0 320=140 240=0xF0
[HKEY_LOCAL_MACHINE\Drivers\Display\S1D13506]
“Width”=dword:280
“Height”=dword:1E0
“Bpp”=dword:8
“Flags”=dword:1
“Rotation”=dword:0
Windows® CE Display Drivers
Issue Date: 01/02/06
S1D13506
X25A-E-001-05
Page 6
Epson Research and Development
Vancouver Design Center
11. Remove the X:\wince\release directory, and delete X:\wince\platform\cepc\*.bif
12. Generate the proper building environment by double-clicking on the sample project icon
(i.e. X86 DEMO7).
13. Type BLDDEMO <ENTER> at the DOS prompt of the X86 DEMO7 window to generate
a Windows CE image file (NK.BIN).
Build for CEPC (X86) on Windows CE Platform Builder 2.11
1. Install Microsoft Windows NT v4.0.
2. Install Platform Builder 2.11 by running SETUP.EXE from compact disk #1.
3. Follow the steps below to create a “Build Epson for x86” shortcut which uses the
current “Minshell” project icon/shortcut on the Windows NT 4.0 desktop.
a. Right click on the “Start” menu on the taskbar.
b. Click on the item “Explore”, and “Exploring -- Start Menu” window will come up.
c. Under “\Winnt\Profiles\All Users\Start Menu\Programs\Microsoft Windows CE Platform
Builder\x86 Tools, find the icon “Build Minshell for x86”.
d. Drag the icon “Build Minshell for x86” onto the desktop using the right mouse button.
e. Choose “Copy Here”.
g. Rename the icon “Build Minshell for x86” to “Build Epson for x86” by right clicking on the
icon and choosing “rename”.
h. Right click on the icon “Build Epson for x86” and click on “Properties” to bring up the
“Build Epson for x86 Properties” window.
i. Click on “Shortcut” and replace the string “Minshelll” under the entry “Target” with
“Epson”.
j. Click on “OK” to finish.
4. Create an EPSON project.
a. Make an Epson directory under \WINCE211\PUBLIC.
b. Copy MAXALL and its sub-directories (\WINCE211\PUBLIC\MAXALL) to the
Epson directory.
xcopy /s /e \wince211\public\maxall\*.* \wince211\public\epson
c. Rename \WINCE211\PUBLIC\EPSON\MAXALL.BAT to EPSON.BAT.
d. Edit EPSON.BAT to add the following lines to the end of the file:
@echo on
set CEPC_DDI_S1D13506=1
@echo off
S1D13506
X25A-E-001-05
Windows® CE Display Drivers
Issue Date: 01/02/06
Epson Research and Development
Vancouver Design Center
Page 7
5. Make a S1D13506 directory under \WINCE211\PLATFORM\CEPC\DRIVERS\DISPLAY, and copy the S1D13506 driver source code into \WINCE211\PLATFORM\CEPC\DRIVERS\DISPLAY\S1D13506.
6. Add S1D13506 into the directory list in file -\WINCE211\PLATFORM\CEPC\DRIVERS\DISPLAY\dirs
7. Edit the file \WINCE211\PLATFORM\CEPC\FILES\platform.bib to add the following after the line “IF ODO_NODISPLAY!”:
IF CEPC_DDI_S1D13506
ddi.dll
$(_FLATRELEASEDIR)\epson.dll
NK SH
ENDIF
Replace the section:
IF CEPC_DDI_S3VIRGE !
IF CEPC_DDI_CT655X !
IF CEPC_DDI_VGA8BPP !
ddi.dll
$(_FLATRELEASEDIR)\ddi_s364.dll
NK SH
ENDIF
ENDIF
ENDIF
with the following:
IF CEPC_DDI_S1D13506 !
IF CEPC_DDI_S3VIRGE !
IF CEPC_DDI_CT655X !
IF CEPC_DDI_VGA8BPP !
ddi.dll
$(_FLATRELEASEDIR)\ddi_s364.dll
NK SH
ENDIF
ENDIF
ENDIF
ENDIF
8. If the current MODE0.H is not appropriate for your project, generate a new
MODE0.H using the S1D13506 utility program 13506CFG.EXE. The file MODE0.H
(located in X:\wince\platform\cepc\drivers\display\S1D13506) contains the register
values required to set desired screen resolution, color depth (bpp), panel type, active
display(LCD/CRT/TV), rotation, etc.
Windows® CE Display Drivers
Issue Date: 01/02/06
S1D13506
X25A-E-001-05
Page 8
Epson Research and Development
Vancouver Design Center
9. Edit the file PLATFORM.REG match the screen resolution, color depth (bpp), active
display(LCD/CRT/TV) and rotation information in MODE.H. PLATFORM.REG is
located in X:\wince\platform\cepc\files. For example, the display driver section of
PLATFORM.REG should be as follows when using a 640x480 LCD panel with a color depth of 8 bpp in SwivelView 0° (landscape) mode.
; Default for EPSON Display Driver
; 640x480 at 8bits/pixel, LCD display, no rotation
; Useful Hex Values
; 1024=0x400, 768=0x300 640=0x280 480=0x1E0 320=140 240=0xF0
[HKEY_LOCAL_MACHINE\Drivers\Display\S1D13506]
“Width”=dword:280
“Height”=dword:1E0
“Bpp”=dword:8
“Flags”=dword:1
“Rotation”=dword:0
10. Remove the \wince211\release directory and delete \wince211\platform\cepc\*.bif
11. Generate the proper building environment by double-clicking on the Epson project icon -”Build Epson for x86”.
12. Type BLDDEMO <ENTER> at the DOS prompt of the “Build Epson for x86” window to
generate a Windows CE image file (NK.BIN).
S1D13506
X25A-E-001-05
Windows® CE Display Drivers
Issue Date: 01/02/06
Epson Research and Development
Vancouver Design Center
Page 9
Installation for CEPC Environment
Windows CE v2.0 can be loaded on a PC using a floppy drive or a hard drive. The two methods
are described below:
1. To load CEPC from a floppy drive:
a. Create a DOS bootable floppy disk.
b. Edit CONFIG.SYS on the floppy disk to contain the following line only.
device=a:\himem.sys
c. Edit AUTOEXEC.BAT on the floppy disk to contain the following lines.
mode com1:9600,n,8,1
loadcepc /B:9600 /C:1 c:\wince\release\nk.bin
d. Copy LOADCEPC.EXE from c:\wince\public\common\oak\bin to the bootable
floppy disk.
e. Confirm that NK.BIN is located in c:\wince\release.
f. Reboot the system from the bootable floppy disk.
2. To load CEPC from a hard drive:
a. Copy LOADCEPC.EXE to the root directory of the hard drive.
b. Edit CONFIG.SYS on the hard drive to contain the following line only.
device=c:\himem.sys
c. Edit AUTOEXEC.BAT on the hard drive to contain the following lines.
mode com1:9600,n,8,1
loadcepc /B:9600 /C:1 c:\wince\release\nk.bin
d. Confirm that NK.BIN is located in c:\wince\release.
e. Reboot the system from the hard drive.
Windows® CE Display Drivers
Issue Date: 01/02/06
S1D13506
X25A-E-001-05
Page 10
Epson Research and Development
Vancouver Design Center
Comments
• The display driver is CPU independent allowing use of the driver for other Windows CE
Platform Builder 2.11supported platforms. The file EPSON.CPP may require editing to
return the correct value for PhysicalPortAddr, PhysicalVmemAddr, etc.
• The sample code defaults to a 640x480 color dual passive 16-bit LCD panel at 8 bpp
landscape mode. To support other settings, use 13506CFG.EXE to generate the proper
MODE0.H file. For further information, refer to the 13506CFG user manual, document
number X25B-B-001-xx.
• As the time of printing, the drivers have been tested on the x86 CPUs and have been run
with version 2.0 of the ETK and Platform Builder 2.11. The drivers are will be updated
as appropriate. Before beginning any development, check the Epson Electronics
America Website at www.eea.epson.com for the latest revision of this document.
S1D13506
X25A-E-001-05
Windows® CE Display Drivers
Issue Date: 01/02/06
S1D13506 Color LCD/CRT/TV Controller
Wind River WindML v2.0 Display
Drivers
Document Number: X25B-E-002-03
Copyright © 2001 Epson Research and Development, Inc. All Rights Reserved.
Information in this document is subject to change without notice.You may download and use this document, but only for your own use in
evaluating Seiko Epson/EPSON products. You may not modify the document. Epson Research and Development, Inc. disclaims any
representation that the contents of this document are accurate or current. The Programs/Technologies described in this document may contain
material protected under U.S. and/or International Patent laws.
EPSON is a registered trademark of Seiko Epson Corporation. All other trademarks are the property of their respective owners.
Page 2
Epson Research and Development
Vancouver Design Center
THIS PAGE LEFT BLANK
S1D13506
X25B-E-002-03
Wind River WindML v2.0 Display Drivers
Issue Date: 01/04/06
Epson Research and Development
Vancouver Design Center
Page 3
Wind River WindML v2.0 DISPLAY DRIVERS
The Wind River WindML v2.0 display drivers for the S1D13506 Color LCD/CRT/TV
Controller are intended as “reference” source code for OEMs developing for Wind River’s
WindML v2.0. The driver package provides support for both 8 and 16 bit-per-pixel color
depths. The source code is written for portability and contains functionality for most
features of the S1D13506. Source code modification is required to provide a smaller, more
efficient driver for mass production (e.g. TV support may be removed for products not
requiring TV).
The WindML display drivers are designed around a common configuration include file
called mode0.h which is generated by the configuration utility 13506CFG. This design
allows for easy customization of display type, clocks, decode addresses, rotation, etc. by
OEMs. For further information on 13506CFG, see the 13506CFG Configuration Program
User Manual, document number X25B-B-001-xx.
Note
The WindML display drivers are provided as “reference” source code only. They are intended to provide a basis for OEMs to develop their own drivers for WindML v2.0.
These drivers are not backwards compatible with UGL v1.2. For information on the
UGL v1.2 display drivers, see Wind River UGL v1.2 Display Drivers, document number
X25B-E-003-xx.
This document and the source code for the WindML display drivers is updated as appropriate. Please check the Epson Electronics America website at http://www.eea.epson.com
or the Epson Research and Development website at http://www.erd.epson.com for the latest
revisions before beginning any development.
We appreciate your comments on our documentation. Please contact us via email at
[email protected]
Wind River WindML v2.0 Display Drivers
Issue Date: 01/04/06
S1D13506
X25B-E-002-03
Page 4
Epson Research and Development
Vancouver Design Center
Building a WindML v2.0 Display Driver
The following instructions produce a bootable disk that automatically starts the UGL demo
program. These instructions assume that Wind River’s Tornado platform is already
installed.
Note
For the example steps where the drive letter is given as “x:”. Substitute “x” with the
drive letter that your development environment is on.
1. Create a working directory and unzip the WindML display driver into it.
From a command prompt or GUI interface create a new directory (e.g. x:\13506).
Unzip the file 13506windml.zip to the newly created working directory. The files will
be unzipped to the directories “x:\13506\8bpp” and “x:\13506\16bpp”.
2. Configure for the target execution model.
This example build creates a VxWorks image that fits onto and boots from a single
floppy diskette. In order for the VxWorks image to fit on the disk certain modifications are required.
Replace the file “x:\Tornado\target\config\pcPentium\config.h” with the file
“x:\13506\8bpp\File\config.h” (or “x:\13506\16bpp\File\config.h”). The new config.h
file removes networking components and configures the build image for booting from
a floppy disk.
Note
Rather than simply replacing the original config.h file, rename it so the file can be kept
for reference purposes.
3. Build a boot ROM image.
From the Tornado tool bar, select Build -> Build Boot ROM. Select “pcPentium” as
the BSP and “bootrom_uncmp” as the image.
4. Create a bootable disk (in drive A:).
From a command prompt change to the directory “x:\Tornado\host\x86-win32\bin”
and run the batch file torvars.bat. Next, change to the directory “x:\Tornado\target\config\pcPentium” and type:
mkboot a: bootrom_uncmp
5. If necessary, generate a new mode0.h configuration file.
The file mode0.h contains the register values required to set the screen resolution, color depth (bpp), display type, active display (LCD/CRT/TV), rotation, etc. The
mode0.h file included with the drivers, may not contain applicable values and must be
regenerated. The configuration program 13506CFG can be used to build a new
mode0.h file. If building for 8 bpp, place the new mode0.h file in the directory
“x:\13506\8bpp\File”. If building for 16 bpp, place the new mode0.h file in
“x:\13506\16bpp\File”.
S1D13506
X25B-E-002-03
Wind River WindML v2.0 Display Drivers
Issue Date: 01/04/06
Epson Research and Development
Vancouver Design Center
Page 5
Note
Mode0.h should be created using the configuration utility 13506CFG. For more information on 13506CFG, see the 13506CFG Configuration Program User Manual, document number X25B-B-001-xx available at www.erd.epson.com.
6. Build the WindML v2.0 library.
From a command prompt change to the directory “x:\Tornado\host\x86-win32\bin”
and run the batch file torvars.bat. Next, change to the directory “x:\Tornado\target\src\ugl” and type the command:
make CPU=PENTIUM ugl
7. Open the S1D13506 workspace.
From the Tornado tool bar, select File->Open Workspace...->Existing->Browse... and
select the file “x:\13506\8bpp\13506.wsp” (or “x:\13506\16bpp\13506.wsp”).
8. Add support for single line comments.
The WindML v2.0 display driver source code uses single line comment notation, “//”,
rather than the ANSI conventional comments, “/*...*/”.
To add support for single line comments follow these steps:
a.
In the Tornado “Workspace Views” window, click on the “Builds” tab.
b.
Expand the “8bpp Builds” (or “16bpp Builds”) view by clicking on the “+”
next to it. The expanded view will contain the item “default”. Right-click on
“default” and select “Properties...”. A “Properties:” window will appear.
c.
Select the “C/C++ compiler” tab to display the command switches used in
the build. Remove the “-ansi” switch from the line that contains “-g -mpentium -ansi -nostdinc -DRW_MULTI_THREAD”.
(Refer to GNU ToolKit user's guide for details)
9. Compile the VxWorks image.
Select the “Builds” tab in the Tornado “Workspace Views” window.
Right-click on “8bpp files” (or “16bpp files”) and select “Dependencies...”. Click on
“OK” to regenerate project file dependencies for “All Project files”.
Right-click on “8bpp files” (or “16bpp files”) and select “ReBuild All(vxWorks)” to
build VxWorks.
10. Copy the VxWorks file to the diskette.
From a command prompt or through the Windows interface, copy the file
“x:\13506\8bpp\default\vxWorks” (or “x:\13506\16bpp\default\vxWorks”) to the
bootable disk created in step 4.
11. Start the VxWorks demo.
Boot the target PC with the VxWorks bootable diskette to run the UGLDEMO automatically.
Wind River WindML v2.0 Display Drivers
Issue Date: 01/04/06
S1D13506
X25B-E-002-03
Page 6
Epson Research and Development
Vancouver Design Center
THIS PAGE LEFT BLANK
S1D13506
X25B-E-002-03
Wind River WindML v2.0 Display Drivers
Issue Date: 01/04/06
S1D13506 Color LCD/CRT/TV Controller
Wind River UGL v1.2 Display Drivers
Document Number: X25B-E-003-02
Copyright © 2001 Epson Research and Development, Inc. All Rights Reserved.
Information in this document is subject to change without notice.You may download and use this document, but only for your own use in
evaluating Seiko Epson/EPSON products. You may not modify the document. Epson Research and Development, Inc. disclaims any
representation that the contents of this document are accurate or current. The Programs/Technologies described in this document may contain
material protected under U.S. and/or International Patent laws.
EPSON is a registered trademark of Seiko Epson Corporation. Microsoft and Windows are registered trademarks of Microsoft Corporation.
All other trademarks are the property of their respective owners.
Page 2
Epson Research and Development
Vancouver Design Center
THIS PAGE LEFT BLANK
S1D13506
X25B-E-003-02
Wind River UGL v1.2 Display Drivers
Issue Date: 01/02/06
Epson Research and Development
Vancouver Design Center
Page 3
Wind River UGL v1.2 Display Drivers
The Wind River UGL v1.2 display drivers for the S1D13506 Color LCD/CRT/TV
Controller are intended as “reference” source code for OEMs developing for Wind River’s
UGL v1.2. The drivers provide support for both 8 and 16 bit-per-pixel color depths. The
source code is written for portability and contains functionality for most features of the
S1D13506. Source code modification is required to provide a smaller, more efficient driver
for mass production (e.g. TV support may be removed for products not requiring TV).
The UGL display drivers are designed around a common configuration include file called
mode0.h which is generated by the configuration utility 13506CFG. This design allows for
easy customization of display type, clocks, addresses, rotation, etc. by OEMs. For further
information on 13506CFG, see the 13506CFG Configuration Program User Manual,
document number X25B-B-001-xx.
This document and the source code for the UGL display drivers are updated as appropriate.
Please check the Epson Electronics America website at http://www.eea.epson.com or the
Epson Research and Development website at http://www.erd.epson.com for the latest
revisions before beginning any development.
We appreciate your comments on our documentation. Please contact us via e-mail at
[email protected]
Wind River UGL v1.2 Display Drivers
Issue Date: 01/02/06
S1D13506
X25B-E-003-02
Page 4
Epson Research and Development
Vancouver Design Center
Building a UGL v1.2 Display Driver
The following instructions produce a bootable disk that automatically starts the UGL demo
software. These instructions assume that the Wind River Tornado platform is correctly
installed.
Note
For the example steps where the drive letter is given as “x:”. Substitute “x” with the
drive letter that your development environment is on.
1. Create a working directory and unzip the UGL display driver into it
Using a command prompt or GUI interface create a new directory (e.g. x:\13506).
Unzip the file 13506ugl.zip to the newly created working directory. The files will be
unzipped to the directories “x:\13506\8bpp” and “x:\13506\16bpp”.
2. Configure for the target execution model.
This example build creates a VxWorks image that fits onto and boots from a single
floppy diskette. In order for the VxWorks image to fit on the disk certain modifications are required.
Replace the file “x:\Tornado\target\config\pcPentium\config.h” with the file
“x:\13506\8bpp\File\config.h” (or “x:\13506\16bpp\File\config.h”). The new config.h
file removes networking components and configures the build image for booting from
a floppy disk.
Note
Rather than simply replacing the original config.h file, rename it so the file can be kept
for reference purposes.
3. Build a boot ROM image.
From the Tornado tool bar, select Build -> Build Boot ROM. Select “pcPentium” as
the BSP and “bootrom_uncmp” as the image.
4. Create a bootable disk (in drive A:).
From a command prompt in the directory “x:\Tornado\target\config\pcPentium” type
mkboot a: bootrom_uncmp
5. If necessary, generate a new mode0.h configuration file.
The file mode0.h contains the register values required to set the screen resolution, color depth (bpp), display type, active display (LCD/CRT/TV), rotation, etc. The
mode0.h, included with the drivers, sets the display for 640x480 60 Hz output to a
CRT display.
If this setting is inappropriate then mode0.h must be regenerated. The configuration
program 13506CFG can be used to build a new mode0.h file. If building for 8 bpp,
place the new mode0.h file in “x:\13506\8bpp\File”. If building for 16 bpp, place the
new mode0.h file in “x:\13506\16bpp\File”.
S1D13506
X25B-E-003-02
Wind River UGL v1.2 Display Drivers
Issue Date: 01/02/06
Epson Research and Development
Vancouver Design Center
Page 5
Note
Mode0.h should be created using the configuration utility 13506CFG. For more information on 13506CFG, see the 13506CFG Configuration Program User Manual, document number X25B-B-001-xx available at www.erd.epson.com.
6. Open the S1D13506 workspace.
From the Tornado tool bar, select File->Open Workspace...->Existing->Browse... and
select the file “x:\13506\8bpp\13506.wsp” (or “x:\13506\16bpp\13506.wsp”).
7. Add support for single line comments.
The UGL v1.2 display driver source code uses single line comment notation, “//”,
rather than the ANSI conventional comments, “/* . . . */”.
To add support for single line comments follow these steps:
a. In the Tornado “Workspace” window, click on the “Builds” tab.
b. Expand the “8bpp Builds” (or “16bpp Builds”) view by clicking on
the “+” next to it. The expanded view will contain the item “default”.
Right-click on “default” and select “Properties...”. A properties window will appear.
c. Select the “C/C++ compiler” tab to display the command switches
used in the build. Remove the “-ansi” switch from the line that contains “-g -mpentium -ansi -nostdinc -DRW_MULTI_THREAD”.
(Refer to GNU ToolKit user's guide for details)
8. Compile the VxWorks image.
Select the “Files” tab in the Tornado “Workspace” window.
Right-click on “8bpp files” (or “16bpp files”) and select “Dependencies...”. Click on
“OK” to regenerate project file dependencies for “All Project files”.
Right-click on “8bpp files” (or “16bpp files”) and select “ReBuild All(vxWorks)” to
build VxWorks.
9. Copy the VxWorks file to the diskette.
From a command prompt or through the Windows interface, copy the file
“x:\13506\8bpp\default\vxWorks” (or “x:\13506\16bpp\default\vxWorks”) to the
bootable disk created in step 4.
10. Start the VxWorks demo.
Boot the target PC with the VxWorks bootable diskette to run the UGLDEMO automatically.
Wind River UGL v1.2 Display Drivers
Issue Date: 01/02/06
S1D13506
X25B-E-003-02
Page 6
Epson Research and Development
Vancouver Design Center
THIS PAGE LEFT BLANK
S1D13506
X25B-E-003-02
Wind River UGL v1.2 Display Drivers
Issue Date: 01/02/06
S1D13506 Color LCD/CRT Controller
Linux Console Driver
Document Number: X23B-E-004-01
Copyright © 2001 Epson Research and Development, Inc. All Rights Reserved.
Information in this document is subject to change without notice.You may download and use this document, but only for your own use in
evaluating Seiko Epson/EPSON products. You may not modify the document. Epson Research and Development, Inc. disclaims any
representation that the contents of this document are accurate or current. The Programs/Technologies described in this document may contain
material protected under U.S. and/or International Patent laws.
EPSON is a registered trademark of Seiko Epson Corporation.
Page 2
Epson Research and Development
Vancouver Design Center
THIS PAGE LEFT BLANK
S1D13506
X23B-E-004-01
Linux Console Driver
Issue Date: 01/03/20
Epson Research and Development
Vancouver Design Center
Page 3
Linux Console Driver
The Linux console driver for the S1D13506 Color LCD/CRT Controller is intended as
“reference” source code for OEMs developing for Linux. The console driver is a
non-accelerated driver supporting 4, 8, and 16 bit-per-pixel color depths.
A Graphical User Interface (GUI) such as Gnome can obtain the frame buffer address from
this driver allowing the Linux GUI the ability to update the display.
The console driver is designed around an include file called s1d13506.h which is generated
by the configuration utility 13506CFG. Using 13506CFG the programmer can easily
customize the operation of display type, clocks, addresses, rotation, etc.
This document and the source code for the Linux console drivers are updated as appropriate. Please check the Epson Electronics America website at http://www.eea.epson.com
or the Epson Research and Development website at http://www.erd.epson.com for the latest
revisions or before beginning any development.
We appreciate your comments on our documentation. Please contact us via e-mail at
[email protected]
Linux Console Driver
Issue Date: 01/03/20
S1D13506
X23B-E-004-01
Page 4
Epson Research and Development
Vancouver Design Center
Building the S1D13506 Console Driver
Follow the steps below to construct a copy of the Linux operating system using the
S1D13506 as the console display device. These instructions assume that the GNU development environment is installed and the user is familiar with GNU and the Linux operating
system.
1. Acquire the Linux kernel source code.
You can obtain the Linux kernel source code from your Linux supplier or download
the source from: ftp://ftp.kernel.org.
The S1D13506 reference driver requires Linux kernel 2.2.0 or greater.
For information on building the kernel refer to the readme file at:
ftp://ftp.linuxberg.com/pub/linux/kernel/README
Note
The 13506 reference driver was built using Red Hat Linux 6.1, kernel version 2.2.17.
Before continuing with modifications for the S1D13506, you should ensure that you can
build and start the Linux operating system.
2. Unzip the console driver files.
Using a zip file utility, unzip the S1D13506 archive to a temporary directory. (e.g.
/tmp)
When completed the files:
s1d13xxxfb.c
s1d13506.h
Config.in
fbmem.c
fbcon-cfb4.c, and
Makefile
should be located in the temporary directory.
3. Copy the console driver files to the build directory.
Copy the files
/tmp/s1d13xxxfb.c and
/tmp/s1d13506.h
to the directory /usr/src/linux/drivers/video.
Copy the remaining source files
/tmp/Config.in
/tmp/fbmem.c
/tmp/fbcon-cfb4.c, and
/tmp/Makefile
into the directory /usr/src/linux/drivers/video replacing the files of the same name.
S1D13506
X23B-E-004-01
Linux Console Driver
Issue Date: 01/03/20
Epson Research and Development
Vancouver Design Center
Page 5
If your kernel version is not 2.2.17 or you want to retain greater control of the build
process then use a text editor and cut and paste the sections dealing with the Epson
driver in the corresponding files of the same names.
4. Modify s1d13506.h
The file s1d13506.h contains the register values required to set the screen resolution,
color depth (bpp), display type, active display (LCD/CRT), display rotation, etc.
Before building the console driver, refer to the descriptions in the file s1d13506.h for
the default settings of the console driver. If the default does not match the configuration you are building for then s1d13506.h will have to be regenerated with the correct
information.
Use the program 13506CFG to generate the required header file. For information on
how to use 13506CFG, refer to the 13506CFG Configuration Program User Manual,
document number X25B-B-001-xx, available at www.erd.epson.com
After selecting the desired configuration, choose “File->Export” and select the “C
Header File for S1D13506 Generic Drivers” option. Save the new configuration as
s1d13506.h in the /usr/src/linux/drivers/video, replacing the original configuration
file.
5. Configure the video options.
From the command prompt in the directory /usr/src/linux run the command:
make menuconfig
This command will start a text based interface which allows the selection of build time
parameters. From the text interface under “Console drivers” options, select:
“Support for frame buffer devices”
“Epson LCD/CRT controllers support”
“S1D13506 support”
“Advanced low level driver options”
“xBpp packed pixels support” *
* where x is the color depth being compiled for.
If you are using the Epson PCI evaluation board then you must also select:
“Epson PCI Bridge adapter support”
Once you have configured the kernel options, save and exit the configuration utility.
6. Compile and install the kernel
Build the kernel with the following sequence of commands:
make dep
make clean
make bzImage
/sbin/lilo (if running lilo)
Linux Console Driver
Issue Date: 01/03/20
S1D13506
X23B-E-004-01
Page 6
Epson Research and Development
Vancouver Design Center
7. Boot to the Linux operating system
If you are using lilo (Linux Loader), modify the lilo configuration file as discussed in
the kernel build README file. If there were no errors during the build, from the command prompt run:
lilo
and reboot your system.
Note
In order to use the S1D13506 console driver with X server, you need to configure the X
server to use the FBDEV device. A good place to look for the necessary files and instructions on this process is on the Internet at www.xfree86.org
S1D13506
X23B-E-004-01
Linux Console Driver
Issue Date: 01/03/20
S1D13506 Color LCD/CRT/TV Controller
QNX Photon v2.0 Display Driver
Document Number: X25B-E-005-01
Copyright © 2001 Epson Research and Development, Inc. All Rights Reserved.
Information in this document is subject to change without notice.You may download and use this document, but only for your own use in
evaluating Seiko Epson/EPSON products. You may not modify the document. Epson Research and Development, Inc. disclaims any
representation that the contents of this document are accurate or current. The Programs/Technologies described in this document may contain
material protected under U.S. and/or International Patent laws.
EPSON is a registered trademark of Seiko Epson Corporation. All other trademarks are the property of their respective owners.
Page 2
Epson Research and Development
Vancouver Design Center
THIS PAGE LEFT BLANK
S1D13506
X25B-E-005-01
QNX Photon v2.0 Display Driver
Issue Date: 01/04/17
Epson Research and Development
Vancouver Design Center
Page 3
QNX Photon v2.0 Display Driver
The Photon v2.0 display drivers for the S1D13506 Color LCD/CRT/TV Controller are
intended as “reference” source code for OEMs developing for QNX platforms. The driver
package provides support for 8 and 16 bit-per-pixel color depths. The source code is written
for portability and contains functionality for most features of the S1D13506. Source code
modification is required to provide a smaller driver for mass production.
The current revision of the driver is designed for use with either QNX RTP or QNX4 from
the latest product CD (Dec. 99).
The Photon v2.0 display driver is designed around a common configuration include file
called S1D13506.h, which is generated by the configuration utility 13506CFG. This design
allows for easy customization of display type, clocks, decode addresses, etc. by OEMs. For
further information on 13506CFG, see the 13506CFG Configuration Program User
Manual, document number X25B-B-001-xx.
Note
The QNX display drivers are provided as “reference” source code only. They are intended to provide a basis for OEMs to develop their own drivers for QNX Photon v2.0.
This document and the source code for the QNX display drivers are updated as appropriate.
Please check the Epson Electronics America website at http://www.eea.epson.com or the
Epson Research and Development website at http://www.erd.epson.com for the latest
revisions before beginning any development.
We appreciate your comments on our documentation. Please contact us via e-mail at
[email protected]
QNX Photon v2.0 Display Driver
Issue Date: 01/04/17
S1D13506
X25B-E-005-01
Page 4
Epson Research and Development
Vancouver Design Center
Building the Photon v2.0 Display Driver
The following steps build the Photon v2.0 display driver and integrate it into the QNX
operating system. These instructions assume the QNX developer environment is correctly
installed and the developer is familiar with building for the QNX operating system.
Unpack the Graphics Driver Development Kit Archive
1. Install the QNX ddk package using the Package Manager utility.
For information about the Drivers Development Kit contact QNX directly.
2. Once the ddk package is installed, copy the directory tree /usr/scr/gddk_v1.0 into the
Project directory.
3. Change directory to Project/gddk_1.0/devg.
4. Unpack the display driver files using the commands:
#gunzip S1D13506.tar.gz
#tar –xvf S1D13506.tar
This unpacks the files into the directory Project/gddk_1.0/devg/S1D13506.
Configure the Driver
The files s1d13506_16.h and s1d13506_8.h contain register values required to set the
screen resolution, color depth (bpp), display type, etc. The s1d13506.h file included with
the drivers may not contain applicable values and must be regenerated. The configuration
program 13506CFG can be used to build new s1d13506_16.h and s1d13506_8.h files.
Note
S1d13506.h should be created using the configuration utility 13506CFG. For more information on 13506CFG, see the 13506CFG Configuration Program User Manual,
document number X25B-B-001-xx available at www.erd.epson.com.
Build the Driver
The first time the driver is built, the following command ensures that all drivers and
required libraries are built. At the root of the Project source tree, type make.
Note
To build drivers for X86 NTO type ‘OSLIST=nto CPULIST=x86 make’.
Further builds do not require all libraries to be re-built. To build only the S1D13506 display
driver, change to the directory gddk_1.0/devg/S1D13506 and type make.
S1D13506
X25B-E-005-01
QNX Photon v2.0 Display Driver
Issue Date: 01/04/17
Epson Research and Development
Vancouver Design Center
Page 5
Installing the Driver
The build step produces two library images:
• lib/disputil/nto/x86/libdisputil.so
• lib/disputil/nto/x86/libffb.so
For the loader to locate them, the files need to be renamed and copied to the lib directory.
1. Rename libdisputil.so to libdisputil.so.1 and libffb.so to libffb.so.1.
2. Copy the files new files libdisputil.so.1 and libffb.so.1 to the directory /usr/lib.
3. Copy the file devg-S1D13506.so to the /lib/dll directory.
Note
To locate the file devg-S1D13506.so, watch the output of the ‘true’ command during the
makefile build.
4. Modify the trap file crt.$NODE in the /etc/config/trap directory by inserting the following lines at the top of the file.
io-graphics -g640x480x16 -dldevg-S1D13506.so -I0 -d0x0,0x0;#640,480,16 Epson
io-graphics -g640x480x8 -dldevg-S1D13506.so -I0 -d0x0,0x0;#640,480,8 Epson
Run the Driver
Note
For the remaining steps the S5U13506B00C evaluation board must be installed on the
test platform.
It is recommended that the driver be verified before starting QNX with the S1D13506 as
the primary display. To verify the driver, type the following command at the root of the
Project source tree (gddk_1.0 directory).
util/bench/nto/x86/o/devg-bench -dldevg/S1D13506/nto/x86/dll/devg-S1D13506.so mW,H,C,F -d0x0,0x0
Where:
W is the configured width of the display
H is the configured height of the display
C is the color depth in bpp (either 8 or 16)
F is the configured frame rate
This command starts the bench utility which will initialize the driver as the secondary
display and exercise the drivers main functions. If the display appears satisfactory, restart
QNX Photon and the restart will result in the S1D13506 display driver becoming the
primary display device.
QNX Photon v2.0 Display Driver
Issue Date: 01/04/17
S1D13506
X25B-E-005-01
Page 6
Epson Research and Development
Vancouver Design Center
Comments
• To restore the display driver to the default, comment out changes made to the trap file
crt.$NODE.
S1D13506
X25B-E-005-01
QNX Photon v2.0 Display Driver
Issue Date: 01/04/17
S1D13XXX 32-Bit Windows Device Driver
Installation Guide
Document No. X00A-E-003-04
Copyright © 1999, 2001 Epson Research and Development, Inc. All Rights Reserved.
Information in this document is subject to change without notice.You may download and use this document, but only for your own use in
evaluating Seiko Epson/EPSON products. You may not modify the document. Epson Research and Development, Inc. disclaims any
representation that the contents of this document are accurate or current. The Programs/Technologies described in this document may contain
material protected under U.S. and/or International Patent laws.
EPSON is a registered trademark of Seiko Epson Corporation. All Trademarks are the property of their respective owners
Page 2
Epson Research and Development
Vancouver Design Center
THIS PAGE LEFT BLANK
X00A-E-003-04
S1D13XXX 32-Bit Windows Device Driver Installation Guide
Issue Date: 01/04/17
Epson Research and Development
Vancouver Design Center
Page 3
S1D13XXX 32-Bit Windows Device Driver
Installation Guide
This manual describes the installation of the Windows 9x/ME/NT 4.0/2000 device drivers
for the S5U13xxxB00x series of Epson Evaluation Boards.
The file S1D13XXX.VXD is required for using the Epson supplied Intel32 evaluation and
test programs for the S1D13xxx family of LCD controllers with Windows 9x/ME.
The file S1D13XXX.SYS is required for using the Epson supplied Intel32 evaluation and
test programs for the S1D13xxx family of LCD controllers with Windows NT 4.0/2000.
The file S1D13XXX.INF is the install script.
For updated drivers, ask your Sales Representative or visit Epson Electronics America on
the World Wide Web at www.eea.epson.com.
Driver Requirements
Video Controller
: S1D13xxx
Display Type
: N/A
BIOS
: N/A
DOS Program
: No
Dos Version
: N/A
Windows Program
: Yes, Windows 9x/ME/NT
Windows DOS Box
: N/A
Windows Full Screen
: N/A
OS/2
: N/A
4.0/2000 device driver
Installation
Windows NT Version 4.0
All evaluation boards require the driver to be installed as follows.
1. Install the evaluation board in the computer and boot the computer.
2. Copy the files S1D13XXX.INF and S1D13XXX.SYS to a directory on a local hard
drive.
3. Right click your mouse on the file S1D13XXX.INF and select INSTALL from the
menu.
4. Windows will install the device driver and ask you to restart.
S1D13XXX 32-Bit Windows Device Driver Installation Guide
Issue Date: 01/04/17
X00A-E-003-04
Page 4
Epson Research and Development
Vancouver Design Center
Windows 2000
All PCI Bus Evaluation Cards
1. Install the evaluation board in the computer and boot the computer.
2. Windows will detect the new hardware as a new PCI Device and bring up the FOUND
NEW HARDWARE dialog box.
3. Click NEXT.
4. The New Hardware Wizard will bring up the dialog box to search for a suitable driver.
5. Click NEXT.
6. When Windows does not find the driver it will allow you to specify the location of it.
Type the driver location or select BROWSE to find it.
7. Click NEXT.
8. Windows 2000 will open the installation file and show the option EPSON PCI Bridge
Card. Select this file and click OPEN.
9. Windows then shows the path to the file. Click OK.
10. Click NEXT.
11. Click FINISH.
All ISA Bus Evaluation Cards
1. Install the evaluation board in the computer and boot the computer.
2. Go to the CONTROL PANEL and select ADD/REMOVE HARDWARE, click
NEXT.
3. Select ADD/TROUBLESHOOT A DEVICE, and click NEXT. Windows 2000 will
attempt to detect any new plug and play device and fail.
4. The CHOOSE HARDWARE DEVICE dialog box appears. Select ADD NEW
HARDWARE and click NEXT.
5. Select NO I WANT TO SELECT FROM A LIST and click NEXT.
6. Select OTHER DEVICE from the list and click NEXT.
7. Click HAVE DISK.
8. Specify the location of the driver files, select the S1D13XXX INF file and click
OPEN.
9. Click OK.
X00A-E-003-04
S1D13XXX 32-Bit Windows Device Driver Installation Guide
Issue Date: 01/04/17
Epson Research and Development
Vancouver Design Center
Page 5
Windows 98/ME
All PCI Bus Evaluation Cards
1. Install the evaluation board in the computer and boot the computer.
2. Windows will detect the new hardware as a new PCI Device and bring up the ADD
NEW HARDWARE dialog box.
3. Click NEXT.
4. Windows will look for the driver. When Windows does not find the driver it will allow you to specify the location of it. Type the driver location or select BROWSE to
find it.
5. Click NEXT.
6. Windows will open the installation file and show the option EPSON PCI Bridge Card.
7. Click FINISH.
All ISA Bus Evaluation Cards
1. Install the evaluation board in the computer and boot the computer.
2. Go to the CONTROL PANEL and double-click on ADD NEW HARDWARE to
launch the ADD NEW HARDWARE WIZARD. Click NEXT.
3. Windows will attempt to detect any new plug and play device and fail. Click NEXT.
4. Windows will ask you to let it detect the hardware, or allow you to select from a list.
Select NO, I WANT TO SELECT THE HARDWARE FROM A LIST and click
NEXT.
5. From the list select OTHER DEVICES and click NEXT.
6. Click HAVE DISK and type the path to the driver files, or select browse to find the
driver.
7. Click OK.
8. The driver will be identified as EPSON PCI Bridge Card. Click NEXT.
9. Click FINISH.
S1D13XXX 32-Bit Windows Device Driver Installation Guide
Issue Date: 01/04/17
X00A-E-003-04
Page 6
Epson Research and Development
Vancouver Design Center
Windows 95 OSR2
All PCI Bus Evaluation Cards
1. Install the evaluation board in the computer and boot the computer.
2. Windows will detect the card as a new PCI Device and launch the
UPDATE DEVICE DRIVER wizard.
If The Driver is on Floppy Disk
3. Place the disk into drive A: and click NEXT.
4. Windows will find the EPSON PCI Bridge Card.
5. Click FINISH to install the driver.
6. Windows will ask you to restart the system.
If The Driver is not on Floppy Disk
3. Click NEXT, Windows will search the floppy drive and fail.
4. Windows will attempt to load the new hardware as a Standard VGA Card.
5. Click CANCEL. The Driver must be loaded from the CONTROL PANEL under
ADD/NEW HARDWARE.
6. Select NO for Windows to DETECT NEW HARDWARE.
7. Click NEXT.
8. Select OTHER DEVICES from HARDWARE TYPE and Click NEXT.
9. Click HAVE DISK.
10. Specify the location of the driver and click OK.
11. Click OK.
12. EPSON PCI Bridge Card will appear in the list.
13. Click NEXT.
14. Windows will install the driver.
15. Click FINISH.
16. Windows will ask you to restart the system.
17. Windows will re-detect the card and ask you to restart the system.
X00A-E-003-04
S1D13XXX 32-Bit Windows Device Driver Installation Guide
Issue Date: 01/04/17
Epson Research and Development
Vancouver Design Center
Page 7
All ISA Bus Evaluation Cards
1. Install the evaluation board in the computer and boot the computer.
2. Go to the CONTROL PANEL and select ADD NEW HARDWARE.
3. Click NEXT.
4. Select NO and click NEXT.
5. Select OTHER DEVICES and click NEXT.
6. Click Have Disk.
7. Specify the location of the driver files and click OK.
8. Click Next.
9. Click Finish.
Previous Versions of Windows 95
All PCI Bus Evaluation Cards
1. Install the evaluation board in the computer and boot the computer.
2. Windows will detect the card.
3. Select DRIVER FROM DISK PROVIDED BY MANUFACTURER.
4. Click OK.
5. Specify a path to the location of the driver files.
6. Click OK.
7. Windows will find the S1D13XXX.INF file.
8. Click OK.
9. Click OK and Windows will install the driver.
S1D13XXX 32-Bit Windows Device Driver Installation Guide
Issue Date: 01/04/17
X00A-E-003-04
Page 8
Epson Research and Development
Vancouver Design Center
All ISA Bus Evaluation Cards
1. Install the evaluation board in the computer and boot the computer.
2. Go to the CONTROL PANEL and select ADD NEW HARDWARE.
3. Click NEXT.
4. Select NO and click NEXT.
5. Select OTHER DEVICES from the HARDWARE TYPES list.
6. Click HAVE DISK.
7. Specify the location of the driver files and click OK.
8. Select the file S1D13XXX.INF and click OK.
9. Click OK.
10. The EPSON PCI Bridge Card should be selected in the list window.
11. Click NEXT.
12. Click NEXT.
13. Click Finish.
X00A-E-003-04
S1D13XXX 32-Bit Windows Device Driver Installation Guide
Issue Date: 01/04/17
S1D13506 Color LCD/CRT/TV Controller
S5U13506B00C Evaluation Board
User Manual
Document Number: X25B-G-004-06
Copyright © 1999, 2001 Epson Research and Development, Inc. All Rights Reserved.
Information in this document is subject to change without notice.You may download and use this document, but only for your own use in
evaluating Seiko Epson/EPSON products. You may not modify the document. Epson Research and Development, Inc. disclaims any
representation that the contents of this document are accurate or current. The Programs/Technologies described in this document may contain
material protected under U.S. and/or International Patent laws.
EPSON is a registered trademark of Seiko Epson Corporation. All other Trademarks are the property of their respective owners.
Page 2
Epson Research and Development
Vancouver Design Center
THIS PAGE LEFT BLANK
S1D13506
X25B-G-004-06
S5U13506B00C Evaluation Board User Manual
Issue Date: 01/02/06
Epson Research and Development
Vancouver Design Center
Page 3
Table of Contents
1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3
Installation and Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.1 Configuration DIP Switches . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.2 Configuration Jumpers . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4
Technical Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.1 PCI Bus Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.1.1 On-Board PCI Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . .
4.1.2 Utility Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2 Non-PCI Host Interface Support . . . . . . . . . . . . . . . . . . . . . . .
4.2.1 CPU Interface Pin Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2.2 CPU Bus Connector Pin Mapping . . . . . . . . . . . . . . . . . . . . . . . . . .
4.3 LCD Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.3.1 LCD Interface Pin Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.3.2 Buffered LCD Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.3.3 16-bit Passive Color Panel Support with MediaPlug Enabled . . . . . . . . . . . .
4.3.4 Adjustable LCD Panel Positive Power Supply . . . . . . . . . . . . . . . . . . . .
4.3.5 Adjustable LCD Panel Negative Power Supply . . . . . . . . . . . . . . . . . . . .
4.4 CRT/TV Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.4.1 CRT/TV Interface Pin Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.4.2 CRT Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.4.3 TV Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.5 MediaPlug Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.6 Clock Synthesizer and Clock Options . . . . . . . . . . . . . . . . . . . . .
4.6.1 Clock Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.1 Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.2 Document Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
6
Parts List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
7
Schematic Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
8
Technical Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
8.1 EPSON LCD/CRTControllers (S1D13506) . . . . . . . . . . . . . . . . . . . 33
S5U13506B00C Evaluation Board User Manual
Issue Date: 01/02/06
11
11
12
12
13
13
14
16
17
18
18
19
19
20
20
20
20
21
22
22
S1D13506
X25B-G-004-06
Page 4
Epson Research and Development
Vancouver Design Center
THIS PAGE LEFT BLANK
S1D13506
X25B-G-004-06
S5U13506B00C Evaluation Board User Manual
Issue Date: 01/02/06
Epson Research and Development
Vancouver Design Center
Page 5
List of Tables
Table 3-1:
Table 3-2:
Table 3-3:
Table 4-1:
Table 4-2:
Table 4-3:
Table 4-4:
Table 4-5:
Table 4-6:
Table 4-7:
Table 4-8:
Table 4-9:
Table 6-1:
Configuration DIP Switch Settings . . . . . . . . . . . . . . .
Host Bus Selection . . . . . . . . . . . . . . . . . . . . . . . .
Jumper Settings . . . . . . . . . . . . . . . . . . . . . . . . .
S1D13506 Memory Mapping onto 4M byte PCI Address Block
PCI Configuration Register Read Values . . . . . . . . . . . .
PCI Configuration Register Write Values . . . . . . . . . . . .
CPU Interface Pin Mapping . . . . . . . . . . . . . . . . . . .
CPU/BUS Connector (H1) Pinout . . . . . . . . . . . . . . . .
CPU/BUS Connector (H2) Pinout . . . . . . . . . . . . . . . .
LCD Signal Connector (J1) . . . . . . . . . . . . . . . . . . .
CRT/TV Interface Pin Mapping . . . . . . . . . . . . . . . . .
MediaPlug Connector (J5) Pin Mapping . . . . . . . . . . . .
Parts List . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
. . . . . . . . . . .
. . . . . . . . . . .
. . . . . . . . . . .
. . . . . . . . . . .
. . . . . . . . . . .
. . . . . . . . . . .
. . . . . . . . . . .
. . . . . . . . . . .
. . . . . . . . . . .
. . . . . . . . . . .
. . . . . . . . . . .
. . . . . . . . . . .
. . . . . . . . . . .
.9
10
10
11
12
12
13
14
15
17
20
21
24
List of Figures
Figure 4-1:
Figure 4-2:
Figure 4-3:
Figure 7-1:
Figure 7-2:
Figure 7-3:
Figure 7-4:
Figure 7-5:
Figure 7-6:
Figure 7-7:
External Circuit for Color Single 16-Bit Panel with MediaPlug Enabled . . . . . . . . . 18
External Circuit for Color Dual 16-Bit Panel with MediaPlug Enabled . . . . . . . . . . 18
Symbolic Clock Synthesizer Connections . . . . . . . . . . . . . . . . . . . . . . . . . 22
S5U13506B00C Schematic Diagram (1 of 7) . . . . . . . . . . . . . . . . . . . . . . . 26
S5U13506B00C Schematic Diagram (2 of 7) . . . . . . . . . . . . . . . . . . . . . . . 27
S5U13506B00C Schematic Diagram (3 of 7) . . . . . . . . . . . . . . . . . . . . . . . 28
S5U13506B00C Schematic Diagram (4 of 7) . . . . . . . . . . . . . . . . . . . . . . . 29
S5U13506B00C Schematic Diagram (5 of 7) . . . . . . . . . . . . . . . . . . . . . . . 30
S5U13506B00C Schematic Diagram (6 of 7) . . . . . . . . . . . . . . . . . . . . . . . 31
S5U13506B00C Schematic Diagram (7 of 7) . . . . . . . . . . . . . . . . . . . . . . . 32
S5U13506B00C Evaluation Board User Manual
Issue Date: 01/02/06
S1D13506
X25B-G-004-06
Page 6
Epson Research and Development
Vancouver Design Center
THIS PAGE LEFT BLANK
S1D13506
X25B-G-004-06
S5U13506B00C Evaluation Board User Manual
Issue Date: 01/02/06
Epson Research and Development
Vancouver Design Center
Page 7
1 Introduction
This manual describes the setup and operation of the S5U13506B00C Evaluation Board.
The S5U13506B00C is designed as an evaluation platform for the S1D13506 Color
LCD/CRT/TV Controller chip.
This user manual will be updated as appropriate. Please check the Epson Electronics
America Website at http://www.eea.epson.com for the latest revision of this document
before beginning any development.
We appreciate your comments on our documentation. Please contact us via email at
[email protected]
S5U13506B00C Evaluation Board User Manual
Issue Date: 01/02/06
S1D13506
X25B-G-004-06
Page 8
Epson Research and Development
Vancouver Design Center
2 Features
The S5U13506B00C features the following:
• S1D13506 Color LCD/CRT/TV controller chip.
• Headers for connecting to a 3.3V or 5V host bus interface.
• 1Mx16 EDO DRAM.
• Configuration options.
• Adjustable positive LCD bias power supplies from +24V to +40V.
• Adjustable negative LCD bias power supplies from -23V to -14V.
• 4/8-bit 3.3V or 5V monochrome passive LCD panel support.
• 4/8/16-bit 3.3V or 5V color passive LCD panel support.
• 9/12/18-bit 3.3V or 5V TFT/D-TFD LCD panel support.
• Embedded RAMDAC for CRT and TV support.
• WINNOV VideumCam digital camera support at 320x240x256 colors at 30 frames per
second.
• Clock synthesizer for maximum clock flexibility.
• Software initiated Power Save Mode.
• Selectable clock source for BUSCLK and CLKI.
S1D13506
X25B-G-004-06
S5U13506B00C Evaluation Board User Manual
Issue Date: 01/02/06
Epson Research and Development
Vancouver Design Center
Page 9
3 Installation and Configuration
The S5U13506B00C is designed to support as many platforms as possible. The
S5U13506B00C incorporates a DIP switch and several jumpers which allow both evaluation board and S1D13506 LCD controller settings to be configured for a specified evaluation platform.
3.1 Configuration DIP Switches
The S1D13506 LCD controller has 16 configuration inputs (MD[15:0]) which are read on
the rising edge of RESET#. Where appropriate, the S5U13506B00C hard-wires some of
these configuration inputs, but in order to configure the S1D13506 for multiple host bus
interfaces a ten-position DIP switch is required. The following DIP switch settings
configure the S1D13506.
Table 3-1: Configuration DIP Switch Settings
value of this pin at rising edge of RESET# is used to configure:(1/0)
Switch Signal
Closed/On=1
Open/Off=0
S1-1
MD1
S1-2
MD2
S1-3
MD3
S1-4
MD4
Little Endian
Big Endian
S1-5
MD5
WAIT# is active high
WAIT# is active low
S1-6
MD10
Reserved. This switch must be in the closed position.
S1-7
MD11
See Table 3-2:, “Host Bus Selection” on page 10
S1-8
MD12
BUSCLK input divided by 2
BUSCLK input not divided
MD13,
MD13: FPDAT[15:8] is MediaPlug interface;
external latches required for 16-bit STN panels.
MD13: support 16-bit STN panels directly.
S1-9
S1-10
MD14
See Table 3-2:, “Host Bus Selection” on page 10
MD14: MA11 is VMPEPWR.
WAIT# is always driven.
MD15
MD14: MA11 is GPIO2.
WAIT# is tristated when S1D13506 is not selected.
= Required configuration when used in a PCI environment with MediaPlug disabled
Note
MD13 and MD14 are configured using the same switch, for further information see Section 7, “Schematic Diagrams” on page 28.
S5U13506B00C Evaluation Board User Manual
Issue Date: 01/02/06
S1D13506
X25B-G-004-06
Page 10
Epson Research and Development
Vancouver Design Center
The following table shows the Host Bus Interface options available. The Host Bus Interface
chosen will depend on the evaluation platform to be used.
Table 3-2: Host Bus Selection
MD11
MD3
MD2
MD1
Host Bus Interface
0
0
0
0
SH-4/SH-3
0
0
0
1
MC68K Bus 1
0
0
1
0
MC68K Bus 2
0
0
1
1
Generic
0
1
0
0
Reserved
0
1
0
1
MIPS/ISA
0
1
1
0
PowerPC
0
1
1
1
PC Card
1
1
1
1
Philips PR31500/PR31700 / Toshiba TX3912
= Required configuration when used in a PCI environment
3.2 Configuration Jumpers
The S5U13506B00C has seven jumper blocks which configure various board settings. The
jumper positions for each function are shown below.
Table 3-3: Jumper Settings
Jumper
Function
Position 1-2
Position 2-3
Jumper Off
JP1
S1D13506 VDD
Selection
3.3V
5V
n/a
JP2
LCD panel signalling
5V
3.3V
n/a
MediaPlug interface (eight jumpers at 1-2,
3-4, 5-6, 7-8, 9-10, 11-12, 13-14 and 15-16)
JP3
FPDAT[15:8] function
JP4
BUSCLK
Buffered 33MHz from PCI bus
JP5
GPIO2 to VMPEPWR
JP6
16-bit LCD panel MSBs
(all jumpers disconnected)
From header
n/a
MediaPlug interface used
n/a
MediaPlug interface not used
CLKI
From clock synthesizer
From header
n/a
JP7
IREF for CRT/TV DAC
4.6mA for CRT
9.2mA for TV
n/a
JP8
FPDAT[15:8] output
Always use this position
Do not use this position
n/a
JP9
PCI bridge FPGA
Disabled for non-PCI host
n/a
Enabled for PCI host
= Default configuration
S1D13506
X25B-G-004-06
S5U13506B00C Evaluation Board User Manual
Issue Date: 01/02/06
Epson Research and Development
Vancouver Design Center
Page 11
4 Technical Description
The S5U13506B00C operates with both PCI and non-PCI evaluation platforms. It supports
display types such as, passive LCD panels (4/8/16-bit), TFT/D-TFD panels (9/12/18-bit),
CRT and TV (NTSC and PAL). Additionally, it supports a variety of clock options.
4.1 PCI Bus Support
As a PCI device, the S5U13506B00C has the following characteristics.
• 33MHz bus clock.
• Target with no interrupts.
• Non-cacheable memory read and write.
• 3.3V or 5V PCI signalling.
Note
In a 3.3V PCI system, the S1D13506 must be powered at 3.3V by setting jumper JP1. In
a 5V PCI system, the S1D13506 may be powered at either 3.3V or 5V.
Although the S1D13506 does not support the PCI bus directly, the S5U13506B00C
supports the PCI bus using a PCI Bridge Adapter FPGA. The FPGA translates PCI accesses
into PC Card accesses which are then decoded by the S1D13506.
A 4M byte PCI address range is allocated to the S5U13506B00C by the system BIOS. The
S1D13506 uses this address range to map the internal registers and the 2M byte display
buffer. The following table shows the memory mapping of the PCI address block.
Table 4-1: S1D13506 Memory Mapping onto 4M byte PCI Address Block
PCI Memory Offset
Description
S1D13506 M/R#
S1D13506 AB[20:0]
00 0000h to 00 01FFh
General registers (512 byte)
0
00 0000h to 00 01FFh
00 1000h to 00 1FFFh
MediaPlug registers (4K byte)
0
00 1000h to 00 1FFFh
10 0000h to 1F FFFFh
BitBlt data registers (1M byte)
0
10 0000h to 1F FFFFh
20 0000h to 3F FFFFh
Display Buffer (2M byte)
1
00 0000h to 1F FFFFh
S5U13506B00C Evaluation Board User Manual
Issue Date: 01/02/06
S1D13506
X25B-G-004-06
Page 12
Epson Research and Development
Vancouver Design Center
4.1.1 On-Board PCI Configuration Registers
Read-Only Registers
The PCI Bridge Adapter FPGA provides configuration registers which contain
identification information required by the PCI interface. The following values are
hard-wired into these registers.
Table 4-2: PCI Configuration Register Read Values
Name
Address
Register size
Value
Vendor ID
0h
16 bits
10F4h
Device ID
2h
16 bits
1300h
Status
6h
16 bits
400h
Revision ID
8h
8 bits
1
Class Code
9h
24 bits
FF 0000h
Subsystem Vendor ID
2Ch
16 bits
10F4h
Subsystem ID
2Dh
16 bits
8000h
Header Type
Eh
8 bits
0
n/a
Fh-FFh
32 bits
0
Read/Write Registers
The PCI Bridge Adapter FPGA provides two read/write registers which are used for access
enabling and memory mapping as follows.
Table 4-3: PCI Configuration Register Write Values
Name
Address
Register size
Valid bits
Meaning
Command
4h
16 bits
Bit 1 only; other bits are zero.
Access enabled if high
Base Address
10h
32 bits
Bits 31 to 22; other bits are zero.
Position of 4M byte reserved window
4.1.2 Utility Software
All utility software for the S5U13506B00C evaluation board is fully PCI compliant and
handles the PCI configuration registers automatically.
S1D13506
X25B-G-004-06
S5U13506B00C Evaluation Board User Manual
Issue Date: 01/02/06
Epson Research and Development
Vancouver Design Center
Page 13
4.2 Non-PCI Host Interface Support
The S5U13506B00C is specifically designed to support a standard PCI bus environment
(using the PCI Bridge Adapter FPGA). However, the S5U13506B00C can directly support
many other Host Bus Interfaces. When the FPGA is disabled (using jumper JP9), headers
H1 and H2 provide the necessary IO pins to interface to the Host Bus Interfaces listed in
Table 4-4:, “CPU Interface Pin Mapping”. The S1D13506 power supply must be set to
3.3V or 5V (using jumper JP1) according to the host CPU signalling voltage.
4.2.1 CPU Interface Pin Mapping
The functions of the S1D13506 host interface pins are mapped to each host bus interface
according to the following table.
Table 4-4: CPU Interface Pin Mapping
S1D1350
6
Pin
Names
Generic
Hitachi
SH-4/SH-3
MIPS/ISA
Motorola
MC68K
Bus 1
Motorola
MC68K
Bus 2
AB20
A20
A20
LatchA20
A20
A20
A11
AB19
A19
A19
SA19
A19
A19
AB18
A18
A18
SA18
A18
AB17
A17
A17
SA17
AB[16:13] A[16:13]
A[16:13]
AB[12:1]
A[12:1]
A[12:1]
AB0
A01
A01
SA0
LDS#
DB[15:8]
D[15:0]
D[15:8]
SD[15:0]
DB[7:0]
D[7:0]
D[7:0]
WE1#
WE1#
WE1#
Philips
PR31500
/PR31700
Toshiba
TX3912
A20
ALE
ALE
A12
A19
/CARDREG
CARDREG*
A18
A13
A18
/CARDIORD
CARDIORD*
A17
A17
A14
A17
/CARDIOWR
CARDIOWR*
SA[16:13]
A[16:13]
A[16:13]
A[15:18]
A[16:13]
SA[12:1]
A[12:1]
A[12:1]
A[19:30]
A[12:1]
A[12:1]
A[12:1]
A0
A31
A01
A0
A0
D[15:8]
D[31:24]
D[0:7]
D[15:0]
D[23:16]
D[23:16]
SD[7:0]
D[7:0]
D[23:16]
D[8:15]
D[7:0]
D[31:24]
D[31:24]
SBHE#
UDS#
DS#
BI
-CE2
/CARDxCSH
CARDxCSH*
Motorola
PC Card
PowerPC
Connected to VDD
M/R#
External Decode
Connected to VDD
CS#
External Decode
Connected to VDD
BUSCLK
BCLK
CKIO
CLK
BS#
Connected
to VDD
BS#
Connected to
VDD
CLKOUT
CLK
AS#
TS
Connected
to VDD
AS#
RD/WR#
RD1#
RD/WR#
Connected to
VDD
R/W#
R/W#
RD/WR
-CE1
/CARDxCSL
CARDxCSL*
RD#
RD0#
RD#
MEMR#
Connected
to VDD
SIZ1
TSIZ0
-OE
/RD
RD*
WE0#
WE0#
WE0#
MEMW#
Connected
to VDD
SIZ0
TSIZ1
-WE
/WE
WE*
WAIT#
WAIT#
RDY#
/WAIT#
IOCHRDY
TA
-WAIT
RESET#
RESET#
RESET#
inverted
RESET
RESET#
inverted
RESET
S5U13506B00C Evaluation Board User Manual
Issue Date: 01/02/06
CLK
CLK
DTACK# DSACK1#
RESET#
RESET#
DCLKOUT
DCLKOUT
Connected to VDD
/CARDxWAIT CARDxWAIT*
RESET#
PON*
S1D13506
X25B-G-004-06
Page 14
Epson Research and Development
Vancouver Design Center
Note
1
S1D13506
X25B-G-004-06
A0 for these busses is not used internally by the S1D13506.
S5U13506B00C Evaluation Board User Manual
Issue Date: 01/02/06
Epson Research and Development
Vancouver Design Center
Page 15
4.2.2 CPU Bus Connector Pin Mapping
The pinouts for Connector H1 are listed in the following table.
Table 4-5: CPU/BUS Connector (H1) Pinout
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
S5U13506B00C Evaluation Board User Manual
Issue Date: 01/02/06
Function
Connected to DB0 of the S1D13506
Connected to DB1 of the S1D13506
Connected to DB2 of the S1D13506
Connected to DB3 of the S1D13506
Ground
Ground
Connected to DB4 of the S1D13506
Connected to DB5 of the S1D13506
Connected to DB6 of the S1D13506
Connected to DB7 of the S1D13506
Ground
Ground
Connected to DB8 of the S1D13506
Connected to DB9 of the S1D13506
Connected to DB10 of the S1D13506
Connected to DB11 of the S1D13506
Ground
Ground
Connected to DB12 of the S1D13506
Connected to DB13 of the S1D13506
Connected to DB14 of the S1D13506
Connected to DB15 of the S1D13506
Connected to RESET# of the S1D13506
Ground
Ground
Ground
+12 volt supply, required in non-PCI applications
+12 volt supply, required in non-PCI applications
Connected to WE0# of the S1D13506
Connected to WAIT# of the S1D13506
Connected to CS# of the S1D13506
Connected to MR# of the S1D13506
Connected to WE1# of the S1D13506
S1D13506 supply, provided by the S5U13506B00C
S1D13506
X25B-G-004-06
Page 16
Epson Research and Development
Vancouver Design Center
The pinouts for Connector H2 are listed in the following table.
Table 4-6: CPU/BUS Connector (H2) Pinout
Pin No.
S1D13506
X25B-G-004-06
Function
1
Connected to AB0 of the S1D13506
2
Connected to AB1 of the S1D13506
3
Connected to AB2 of the S1D13506
4
Connected to AB3 of the S1D13506
5
Connected to AB4 of the S1D13506
6
Connected to AB5 of the S1D13506
7
Connected to AB6 of the S1D13506
8
Connected to AB7 of the S1D13506
9
Ground
10
Ground
11
Connected to AB8 of the S1D13506
12
Connected to AB9 of the S1D13506
13
Connected to AB10 of the S1D13506
14
Connected to AB11 of the S1D13506
15
Connected to AB12 of the S1D13506
16
Connected to AB13 of the S1D13506
17
Ground
18
Ground
19
Connected to AB14 of the S1D13506
20
Connected to AB15 of the S1D13506
21
Connected to AB16 of the S1D13506
22
Connected to AB17 of the S1D13506
23
Connected to AB18 of the S1D13506
24
Connected to AB19 of the S1D13506
25
Ground
26
Ground
27
+5 volt supply, required in non-PCI applications
28
+5 volt supply, required in non-PCI applications
29
Connected to RD/WR# of the S1D13506
30
Connected to BS# of the S1D13506
31
Connected to S1D13506 BUSCLK if JP4 is in position 2-3
32
Connected to RD# of the S1D13506
33
Connected to AB20 of the S1D13506
34
Connected to S1D13506 CLKI if JP6 is in position 2-3
S5U13506B00C Evaluation Board User Manual
Issue Date: 01/02/06
Epson Research and Development
Vancouver Design Center
Page 17
4.3 LCD Support
The S1D13506 supports 4/8-bit dual and single passive monochrome panels, 4/8/16-bit
dual and single passive color panels, and 9/12/18-bit active matrix color TFT/D-TFD
panels. All necessary signals are provided on the 40-pin LCD connector (J1). The interface
signals are alternated with grounds on the cable to reduce cross-talk and noise. When
supporting an
18-bit TFT/D-TFD panel, the S1D13506 can display 64K of a possible 256K colors
because only 16 of the18 bits of LCD data are available from the S1D13506. For details,
refer to the S1D13506 Hardware Functional Specification, document number X25B-A001-xx.
For S1D13506 FPDAT[15:0] pin mapping for various types of panel see Table 4-7:, “LCD
Signal Connector (J1)” on page 18.
S5U13506B00C Evaluation Board User Manual
Issue Date: 01/02/06
S1D13506
X25B-G-004-06
Page 18
Epson Research and Development
Vancouver Design Center
4.3.1 LCD Interface Pin Mapping
Table 4-7: LCD Signal Connector (J1)
S1D13506
Pin Names
Connector
Pin No.
FPDAT0
1
FPDAT1
FPDAT2
Monochrome Passive
Panels
Single
Color Passive Panels
Single
Single
Format 1
Format 2
Color TFT/D-TFD
Panels
Dual
Single
8-bit
8-bit
4-bit
8-bit
8-bit
16-Bit
8-bit
16-bit
9-bit
12-bit
18-bit
D0
LD0
D0
D0
D0
LD0
LD0
R2
R3
R5
3
D1
LD1
D1
D1
D1
LD1
LD1
R1
R2
R4
5
D2
LD2
D2
D2
D2
LD2
LD2
R0
R1
R3
4-bit
Single
Dual
FPDAT3
7
D3
LD3
D3
D3
D3
LD3
LD3
G2
G3
G5
FPDAT4
9
D0
D4
UD0
D0
D4
D4
D4
UD0
UD0
G1
G2
G4
FPDAT5
11
D1
D5
UD1
D1
D5
D5
D5
UD1
UD1
G0
G1
G3
FPDAT6
13
D2
D6
UD2
D2
D6
D6
D6
UD2
UD2
B2
B3
B5
FPDAT7
15
D3
D7
UD3
D3
D7
D7
D7
UD3
UD3
B1
B2
B4
FPDAT8
17
D8
LD4
B0
B1
B3
FPDAT9
19
D9
LD5
FPDAT10
21
D10
LD6
FPDAT11
23
D11
LD7
R0
R2
R1
G0
G2
FPDAT12
25
D12
UD4
G1
FPDAT13
27
D13
UD5
G0
FPDAT14
29
D14
UD6
D15
UD7
FPDAT15
31
FPSHIFT
33
DRDY
35 and 38
B0
B2
B1
FPSHIFT
MOD
MOD
FPSHIFT2
FPLINE
37
FPSHIFT
FPFRAME
39
FPFRAME
GND
2-26
(Even Pins)
GND
N/C
28
N/C
VLCD
30
Adjustable -23 to -14V negative LCD bias
LCDVCC
32
+5V or +3.3V according to JP2
+12V
34
+12V
VDDH
36
Adjustable +24 to +40V positive LCD bias
NC (pin 75)2
40
Panel Enable, active low (LCDPWR)2
DRDY
= Driven low
Note
1
For FPDATxx to LCD interface hardware connections refer to the Display Interface
AC Timing section of the S1D13506 Hardware Functional Specification, document
number X25B-A-001-xx.
2
The S5U13506B00C was designed using S1D13506 pin 75 (LCDPWR) to control the
LCD bias power. This design is no longer supported. Applications should use one of
the available GPIO pins to control the LCD bias power allowing for software control
S1D13506
X25B-G-004-06
S5U13506B00C Evaluation Board User Manual
Issue Date: 01/02/06
Epson Research and Development
Vancouver Design Center
Page 19
of power sequencing delays. For further information on LCD power sequencing, see
the S1D13506 Programming Notes and Examples, document number X25B-G-003xx.
S5U13506B00C Evaluation Board User Manual
Issue Date: 01/02/06
S1D13506
X25B-G-004-06
Page 20
Epson Research and Development
Vancouver Design Center
4.3.2 Buffered LCD Connector
J1 provides the same LCD panel signals as those directly from S1D13506, but with
voltage-adapting buffers which can be set to 3.3V or 5V. Pin 32 on this connector provides
power for the LCD panel logic at the same voltage as the buffer power supply.
4.3.3 16-bit Passive Color Panel Support with MediaPlug Enabled
When the MediaPlug option is enabled, (MD13 and MD14 set to “On”, see Table 3-1:,
“Configuration DIP Switch Settings” on page 9) S1D13506 pins FPDAT[15:8] are used for
the MediaPlug interface and are not available for panel connection. Instead, S1D13506 pins
FPDAT[7:0] are multiplexed for 16-bit panel operation. If the MediaPlug option is selected
and 16-bit panel operation is desired, demultiplexing circuitry must be built externally
according to the schematic below. Refer to Table 4-7:, “LCD Signal Connector (J1)” on
page 18 for connector pin mapping.
Single color 16-bit passive panels can be used with the following modifications.
D[7:0]
To 16-bit panel
FPDAT[7:0]
D
Q
D[15:8]
FROM
S5U13506B00C
FPSHIFT
CK
74AHC374
Figure 4-1: External Circuit for Color Single 16-Bit Panel with MediaPlug Enabled
Dual color 16-bit passive panels can be used with the following modifications.
UD [3:0]
LD [3:0]
FROM
S5U13506B00C
FPDAT[7:4]
FPDAT[3:0]
FPSHIFT
D
Q
UD [7:4]
LD [7:4]
To 16-bit panel
CK
74AHC374
Figure 4-2: External Circuit for Color Dual 16-Bit Panel with MediaPlug Enabled
S1D13506
X25B-G-004-06
S5U13506B00C Evaluation Board User Manual
Issue Date: 01/02/06
Epson Research and Development
Vancouver Design Center
Page 21
4.3.4 Adjustable LCD Panel Positive Power Supply
For LCD panels which require a positive bias voltage between +24V and +40V
(Iout=45mA), a power supply has been provided as an integral part of the S5U13506B00C
design. The voltage on VDDH can be adjusted using R15 to provide an output voltage from
+24V to +40V and can be enabled and disabled by LCDPWR (S1D13506 pin 75).
The S5U13506B00C was designed using LCDPWR (pin 75) to control the LCD bias
power. This design is no longer supported. Applications should use one of the available
GPIO pins to control the LCD bias power allowing for software control of power
sequencing delays. For further information on LCD power sequencing, see the S1D13506
Programming Notes and Examples, document number X25B-G-003-xx.
Note
Before connecting the panel, set the potentiometer according to the panel’s specific
voltage requirements.
4.3.5 Adjustable LCD Panel Negative Power Supply
For LCD panels which require a negative bias voltage between -23V and -14V
(Iout=25mA), a power supply has been provided as an integral part of the S5U13506B00C
design. The voltage on VLCD can be adjusted using R21 to provide an output voltage from
-23V to -14V, and can be enabled and disabled by LCDPWR (S1D13506 pin 75).
The S5U13506B00C was designed using LCDPWR (pin 75) to control the LCD bias
power. This design is no longer supported. Applications should use one of the available
GPIO pins to control the LCD bias power allowing for software control of power
sequencing delays. For further information on LCD power sequencing, see the S1D13506
Programming Notes and Examples, document number X25B-G-003-xx.
Note
Before connecting the panel, set the potentiometer according to the panel’s specific
voltage requirements.
S5U13506B00C Evaluation Board User Manual
Issue Date: 01/02/06
S1D13506
X25B-G-004-06
Page 22
Epson Research and Development
Vancouver Design Center
4.4 CRT/TV Support
4.4.1 CRT/TV Interface Pin Mapping
CRT/TV signals are supplied on a standard CRT connector (J3), Composite Video
connector (J2), and S-Video connector (J4):
Table 4-8: CRT/TV Interface Pin Mapping
S1D13506
Pin Name
CRT
Composite Video
S-Video
HRTC
Horizontal retrace
N/A
N/A
VRTC
Vertical retrace
N/A
N/A
RED
Red
N/A
Luminance
GREEN
Green
Composite
N/A
BLUE
Blue
N/A
Chrominance
4.4.2 CRT Support
CRT support is provided on connector J3 via the S1D13506 embedded RAMDAC. An
external current reference is implemented to provide the necessary RAMDAC output gain.
The reference current (IREF) should be set to 4.6mA using jumper JP7.
Note
When IREF is set to 4.6mA, the DAC Output Select bit (REG[05Bh] bit 3) must be set
to 1.
CRT output is not available when TV output is enabled.
4.4.3 TV Support
The S1D13506 supports PAL or NTSC TV output. Composite Video is available on
connector J2 and S-Video is available on connector J4. An external current reference is
implemented to provide the necessary RAMDAC output gain. The reference current should
be set to 9.2mA using jumper JP7.
TV output is not available when CRT output is enabled. PAL and NTSC modes cannot be
enabled at the same time.
S1D13506
X25B-G-004-06
S5U13506B00C Evaluation Board User Manual
Issue Date: 01/02/06
Epson Research and Development
Vancouver Design Center
Page 23
4.5 MediaPlug Interface
The S5U13506B00C supports the Winnov Videum®Cam digital camera through the
S1D13506 built-in MediaPlug interface. The Winnov Videum®Cam digital camera inputs
are TTL compatible and can be driven by the S1D13506 powered at 3.3V or 5V. Therefore,
the power supply to the camera is 5V while the S1D13506 can powered at 3.3V or 5V.
However, if the S1D13506 is powered at 5V, then 150nH inductors must be added at
locations L8, L10, L11, L12 and L13.
Jumper JP5 selects whether MA11/GPIO2 is used to enable the video camera power. For
more information, see the note from Section 3.2, “Configuration Jumpers” on page 10.
Eight jumpers identified globally as JP3 must be set for MediaPlug operation.
The table below describes the S1D13506 pin mapping for the MediaPlug interface.
Table 4-9: MediaPlug Connector (J5) Pin Mapping
S1D13506
Pin Names
Connector Pin
No.
IO Type
FPDAT8
1
O
VMPLCTL
FPDAT9
2
I
VMPRCTL
FPDAT10
3
IO
VMPD0
FPDAT11
4
IO
VMPD1
FPDAT12
6
IO
VMPD2
FPDAT13
5
IO
VMPD3
FPDAT14
8
O
VMPCLK
FPDAT15
7
O
VMPCLKN
MA11/GPIO2
9
O
VMPEPWR
GND
Shield
-
Ground
MediaPlug I/F
Note
When MediaPlug is enabled, 16-bit passive panels support requires an external circuit.
See Section 4.3.3, “16-bit Passive Color Panel Support with MediaPlug Enabled” on
page 20.
S5U13506B00C Evaluation Board User Manual
Issue Date: 01/02/06
S1D13506
X25B-G-004-06
Page 24
Epson Research and Development
Vancouver Design Center
4.6 Clock Synthesizer and Clock Options
For maximum flexibility, the S5U13506B00C implements a Cypress ICD2061A Clock
Generator. MCLKOUT from the clock chip is connected to CLKI of the S1D13506 and
VCLKOUT from the clock chip is connected to CLKI2 of the S1D13506. A 14.31818MHz
crystal (Y1) is connected to XTALIN of the clock chip and a 17.734475MHz oscillator
(U14) is connected to the FEATCLK input of the clock chip. The diagram below shows a
simplified representation of the clock synthesizer connections.
ICD2061A
Synthesizer reference
14.31818 MHz
Feature clock for PAL TV
17.734475 MHz
XTALIN
MCLKOUT
CLKI
FEATCLK
VCLKOUT
CLKI2
Figure 4-3: Symbolic Clock Synthesizer Connections
Upon power-up, CLKI (MCLKOUT) is 40MHz and CLKI2 (VCLKOUT) is configured to
25.175MHz.
4.6.1 Clock Programming
The S1D13506 utilities automatically program the clock generator. If manual programming
of the clock generator is required, refer to the source code for the S1D13506 utilities
available on the internet at www.eea.epson.com.
For further information on programming the clock generator, refer to the Cypress
ICD2061A specification.
Note
When CLKI and CLKI2 are programmed to multiples of each other (e.g. CLKI =
20MHz, CLKI2 = 40MHz), the clock output signals from the Cypress clock generator
may jitter. Refer to the Cypress ICD2061A specification for details.
To avoid this problem, set CLKI and CLKI2 to different frequencies and configure both
LCD PCLK and CRT/TV PCLK to use the same clock input (CLKI or CLKI2).Then use
the S1D13506 internal clock divides (LCD PCLK Divide Select REG[014h] bits 5-4,
CRT/TV PCLK Divide Select REG[018h] bits 5-4) to obtain the lower frequencies.
S1D13506
X25B-G-004-06
S5U13506B00C Evaluation Board User Manual
Issue Date: 01/02/06
Epson Research and Development
Vancouver Design Center
Page 25
5 References
5.1 Documents
• Epson Research and Development, Inc., S1D13506 Hardware Functional Specification,
Document Number X25B-A-001-xx.
• Epson Research and Development, Inc., S1D13506 Programming Notes and Examples,
Document Number X25B-G-003-xx.
• Cypress Semiconductor Corporation, ICD2061A Data Sheet.
5.2 Document Sources
• Epson Electronics America Website: http://www.eea.epson.com.
• Cypress Semiconductor Corporation Website: http://www.cypress.com.
S5U13506B00C Evaluation Board User Manual
Issue Date: 01/02/06
S1D13506
X25B-G-004-06
Page 26
Epson Research and Development
Vancouver Design Center
6 Parts List
Table 6-1: Parts List
Item
Quantity
Reference
Part
Description
1
22
C1-C6,C10,C13-C16,C32-C34,
C46-C49,C52,C54,C55,C57
0.1uF
1206 capacitor +/-20% 50V
2
4
C7,C8,C9,C38
0.01uF
1206 capacitor +/-20% 50V
3
6
C11,C12,C40,C45,C53,C56
10uF/16V
Tantalum size C, 10uF 16V +/-10%
4
2
C17,C21
47uF/10V
Tantalum size C, 47uF 10V +/-10%
5
3
C18,C19,C20
4.7uF/50V
Tantalum size D, 4.7uF 50V +/-10%
6
1
C22
56uF/35V
Low-ESR radial electrolytic capacitor
7
9
C23,C24,C25,C26,C27,C28,C29,
C30,C31
0.22uF
1206 capacitor +/-20% 50V
8
6
C35,C36,C37,C39,C41,C42
33pF
1206 capacitor +/-20% 50V
9
2
C43,C44
220pF
1206 capacitor +/-20% 50V
10
2
C50,C51
not populated
1206 capacitor, not populated
11
4
D1,D2,D3,D5
BAV99L
Diode BAV99L
12
1
D4
BAT54
Diode BAT54
13
2
H1,H2
Header 17X2
0.1" x 0.1" 2 rows by 17 header
14
2
JP5,JP9
Header 2
0.1" 1 row by 2 header
15
6
JP1,JP2,JP4,JP6,JP7,JP8
Header 3
0.1" 1 row by 3 header
16
1
JP3
Header 8X2
Not populated
17
1
J1
Header 20x2
2x20, .025" sq. shrouded connector,
ctr-key, t/h
18
1
J2
C-Video
Keystone 901 or equivalent
19
1
J3
CRT
AMP 749264 or equivalent
20
1
J4
S-Video
Assman A-HDF 15 A KG/T or equivalent
21
1
J5
MediaPlug Connector
CUI Stack P/N:MD-90S or Digi-Key
P/N:CP-2490-ND
22
8
L1,L2,L3,L5,L6,L7,L14,L15
Ferrite
Philips BDS3/3/8.9-4S2
23
1
L4
1uH
RCD MCI-1812 1uH MT or MSI-1812 1uH
MT
24
1
L9
150nH
Panasonic ELJNCR15JF or
Delevan 1008-151K
25
3
Q1,Q5,Q6
MMBT2222A
Transistor MMBT2222A
26
1
Q2
MMBT3906
Transistor MMBT3906
27
1
Q3
MMBT3904
Transistor MMBT3904
28
1
Q4
NDS9400A
National Semi NDS9400A
29
16
R1-R11,R17,R26,R29,R61,R62
15K
1206 resistor +/-5%
30
1
R13
470K
1206 resistor +/-5%
31
6
R14,R16,R18,R19,R47,R50
10K
1206 resistor +/-5%
32
1
R15
200K potentiometer
Spectrol 63S204T607
33
4
R20,R21,R23,R56
100K
1206 resistor +/-5%
S1D13506
X25B-G-004-06
S5U13506B00C Evaluation Board User Manual
Issue Date: 01/02/06
Epson Research and Development
Vancouver Design Center
Page 27
Table 6-1: Parts List (Continued)
Item
Quantity
Reference
Part
Description
34
1
R22
100K potentiometer
Spectrol 63S104T607
35
3
R24,R25,R30
1K
1206 resistor +/-5%
36
3
R31,R32,R33
150 1%
1206 resistor +/-1%
37
1
R34
6.04K 1%
1206 resistor +/-1%
38
6
R35,R38,R41,R44,R48,R53
68 Ohms
1206 resistor +/-5%
39
1
R36
1.5K 1%
1206 resistor +/-1%
40
3
R37,R43,R46
316 1%
1206 resistor +/-1%
41
3
R39,R45,R49
357 1%
1206 resistor +/-1%
42
2
R40,R42
137 1%
1206 resistor +/-1%
43
2
R51,R54
22 Ohms
1206 resistor +/-5%
44
2
R52,R55
33 Ohms
1206 resistor +/-5%
45
1
R57
1.5K 1%
1206 resistor +/-1%
46
1
R58
1K 1%
1206 resistor +/-1%
47
1
R59
140 Ohms 1%
1206 resistor +/-1%
48
1
R60
69.8 Ohms 1%
1206 resistor +/-1%
49
1
R63
4.7K
1206 resistor +/-5%
50
1
S1
SW DIP-10
10-position DIP switch
51
1
S2
SW DIP-4
Not populated
52
1
U1
S1D13506F00A
Epson S1D13506F00A
53
1
U2
DRAM 1Mx16-SOJ
Alliance AS4LC1M16E5-50JC or
ISSI IS41LV16100K-50 or
OKI MSM51V18165D50-JS
54
1
U3
RD-0412
Xentek RD-0412
55
1
U4
74AHC04
TI 74AHC04 or National 74VHC04 SO-14
package
56
1
U5
EPN001
Xentek EPN001
57
1
U6
EPF6016TC144-2
Altera EPF6016TC144-2
58
1
U7
EPC1441PC8
Altera EPC1441PC8
59
3
U8,U9,U10
74AHC244
TI 74AHC244 or National 74VHC244
SO-20 package
60
1
U11
LT1117CST-5
Linear Technology LT1117CST-5 or
SGS-Thomson LD1117S50C
61
1
U12
ICD2061A
Cypress ICD2061A
62
1
U13
LT1117CST-3.3
Linear Technology LT1117CST-3.3 or
SGS-Thomson LD1117S33C
63
1
U15
LT1117CM-3.3
Linear Technology LT1117CM-3.3 or
SGS-Thomson LD1117DT33C
64
1
U14
17.734475MHz 14-DIP
oscillator
DIP-14 oscillator
65
1
U16
74AHC374
TI 74AHC374 or National 74VHC374,
SO-20 package
66
1
Y1
14.31818MHz crystal
14.31818MHz crystal HC-49 Fox
FoxS/143-20
S5U13506B00C Evaluation Board User Manual
Issue Date: 01/02/06
S1D13506
X25B-G-004-06
S1D13506
X25B-G-004-06
1
2
3
4
1
2
3
C1
0.1u
ChipVdd
WAIT#
CLKI
CLKI2
P2,4
P7
P7
+5V
A
C2
0.1u
C3
0.1u
ChipVdd
ChipVdd
RESET#
P2,4
+3.3V
CS#
M/R#
RD/WR#
WE1#
WE0#
RD#
BS#
P2,4
P2,4
P2,4
P2,4
P2,4
P2,4
P2,4
DB[15:0]
AB[20:0]
BUSCLK
P2,4
P2,4
P7
ChipVdd
HEADER 3
JP1
A
C4
0.1u
ChipVdd
DB[15:0]
AB[20:0]
C5
0.1u
ChipVdd
C6
0.1u
ChipVdd
B
B
ChipVdd
ChipVdd
ChipVdd
ChipVdd
ChipVdd
ChipVdd
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
DB8
DB9
DB10
DB11
DB12
DB13
DB14
DB15
14
32
50
68
78
87
96
110
12
33
55
72
97
109
70
71
69
15
11
4
5
10
9
8
7
6
13
3
2
1
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
AB0
AB1
AB2
AB3
AB4
AB5
AB6
AB7
AB8
AB9
AB10
AB11
AB12
AB13
AB14
AB15
AB16
AB17
AB18
AB19
AB20
S1D13506F00A
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VDD
TESTEN
CLKI2
CLKI
WAIT#
RESET#
CS#
M/R#
RD/WR#
WE1#
WE0#
RD#
BS#
BUSCLK
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
DB8
DB9
DB10
DB11
DB12
DB13
DB14
DB15
AB0
AB1
AB2
AB3
AB4
AB5
AB6
AB7
AB8
AB9
AB10
AB11
AB12
AB13
AB14
AB15
AB16
AB17
AB18
AB19
AB20
U1
C
DACVSS
DACVSS
DACVDD
DACVDD
DACVDD
IREF
HRTC
VRTC
RED
GREEN
BLUE
NC
FPFRAME
FPLINE
FPSHIFT
DRDY
FPDAT0
FPDAT1
FPDAT2
FPDAT3
FPDAT4
FPDAT5
FPDAT6
FPDAT7
FPDAT8
FPDAT9
FPDAT10
FPDAT11
FPDAT12
FPDAT13
FPDAT14
FPDAT15
RAS#
LCAS#
UCAS#
WE#
MD0
MD1
MD2
MD3
MD4
MD5
MD6
MD7
MD8
MD9
MD10
MD11
MD12
MD13
MD14
MD15
MA0
MA1
MA2
MA3
MA4
MA5
MA6
MA7
MA8
MA9/GPIO3
MA10/GPIO1
MA11/GPIO2
C
98
106
99
102
104
101
107
108
100
103
105
75
73
74
77
76
79
80
81
82
83
84
85
86
88
89
90
91
92
93
94
95
AVDD
AVDD
AVDD
FPDAT0
FPDAT1
FPDAT2
FPDAT3
FPDAT4
FPDAT5
FPDAT6
FPDAT7
FPDAT8
FPDAT9
FPDAT10
FPDAT11
FPDAT12
FPDAT13
FPDAT14
FPDAT15
MD0
MD1
MD2
MD3
MD4
MD5
MD6
MD7
MD8
MD9
MD10
MD11
MD12
MD13
MD14
MD15
35
37
39
41
43
45
47
49
48
46
44
42
40
38
36
34
54
51
52
53
MA0
MA1
MA2
MA3
MA4
MA5
MA6
MA7
MA8
MA9
61
63
65
67
66
64
62
60
58
56
59
57
AVDD
C7
0.01u
AVDD
D
C8
0.01u
AVDD
D
C9
0.01u
FPDAT[15:0]
MD[15:0]
MA[9:0]
IREF
HRTC
VRTC
RED
GREEN
BLUE
LCDPWR
FPFRAME
FPLINE
FPSHIFT
DRDY
FPDAT[15:0]
RAS#
LCAS#
UCAS#
WE#
MD[15:0]
GPIO1
GPIO2
MA[9:0]
Date:
Size
B
Title
P7
P5
P5
P5
P5
P5
P3,5
P5
P5
P5
P5
P5,6
P3
P3
P3
P3
P3
P7
P7
P3
L1
Ferrite
L2
Ferrite
Thursday, April 01, 1999
Document Number
{Doc}
S5U13506B00C Evaluation Board
+3.3V
Sheet
E
E
1
C10
0.1u
of
AVDD
7
Rev
1
1
2
3
4
Page 28
Epson Research and Development
Vancouver Design Center
7 Schematic Diagrams
Figure 7-1: S5U13506B00C Schematic Diagram (1 of 7)
S5U13506B00C Evaluation Board User Manual
Issue Date: 01/02/06
S5U13506B00C Evaluation Board User Manual
Issue Date: 01/02/06
1
2
3
4
TRDY#
STOP#
PAR
P4
P4
P4
C/BE0#
FRAME#
P4
P4
IDSEL
RST#
AD[31:0]
P4
P4
P4
A
A
AD2
AD0
AD6
AD4
AD9
AD13
AD11
AD15
AD18
AD16
AD22
AD20
AD24
AD28
AD26
AD30
52
53
54
55
56
57
58
59
60
61
62
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
1
2
3
4
5
6
7
8
9
10
11
PCI-A
C/BE0#
+3.3V
AD6
AD4
GND
AD2
AD0
+VI/O
REQ64#
+5V
+5V
RESERVED
RST#
+VI/O
GNT#
GND
RESERVED
AD30
+3.3V
AD28
AD26
GND
AD24
IDSEL
+3.3V
AD22
AD20
GND
AD18
AD16
+3.3V
FRAME#
GND
TRDY#
GND
STOP#
+3.3V
SDONE
SBO#
GND
PAR
AD15
+3.3V
AD13
AD11
GND
AD9
TRST#
+12V
TMS
TDI
+5V
INTA#
INTC#
+5V
RESERVED
+VI/O
RESERVED
PCIA1
+ C11
10uF/16V
+5V
+5V +12V
AD[31:0]
B
B
PCI-B
AD8
AD7
+3.3V
AD5
AD3
GND
AD1
+VI/O
ACK64#
+5V
+5V
RESERVED
GND
CLK
GND
REQ#
+VI/O
AD31
AD29
GND
AD27
AD25
+3.3V
C/BE3#
AD23
GND
AD21
AD19
+3.3V
AD17
C/BE2#
GND
IRDY#
+3.3V
DEVSEL#
GND
LOCK#
PERR#
+3.3V
SERR#
3.3V
C/BE1#
AD14
GND
AD12
AD10
GND
-12V
TCK
GND
TDO
+5V
+5V
INTB#
INTD#
PRSNT#1
RESERVED
PRSNT#2
PCIB1
52
53
54
55
56
57
58
59
60
61
62
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
1
2
3
4
5
6
7
8
9
10
11
+ C12
10uF/16V
+5V
+5V
AD1
AD5
AD3
AD8
AD7
AD12
AD10
AD14
AD17
AD21
AD19
AD23
AD27
AD25
AD31
AD29
C
P1,4
P4
P4
SERR#
C/BE1#
P4
P4
P4
P4
P4
P4
P1,4
PERR#
DEVSEL#
IRDY#
C/BE2#
C/BE3#
CLK
C
AB[20:0]
DB[15:0]
P1,4
P7
P1,4
P1,4
P1,4
P1,4
RD/WR#
EXTBCLK
WE0#
CS#
WE1#
RESET#
D
AB[20:0]
AB20
AB14
AB16
AB18
AB8
AB10
AB12
AB0
AB2
AB4
AB6
DB12
DB14
DB8
DB10
DB4
DB6
DB0
DB2
DB[15:0]
D
+5V
+12V
Date:
Size
B
Title
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
+5V
+12V
Thursday, April 01, 1999
Document Number
{Doc}
WAIT#
M/R#
P1,4
P1,4
Sheet
E
BS#
RD#
EXTCLKI
AB15
AB17
AB19
AB9
AB11
AB13
AB1
AB3
AB5
AB7
2
P1,4
P1,4
P7
of
(Provided by the S5U13506B00C)
ChipVdd
DB13
DB15
DB9
DB11
DB5
DB7
DB1
DB3
S5U13506B00C Evaluation Board
HEADER 17X2
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
H2
HEADER 17X2
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
H1
E
7
Rev
1
1
2
3
4
Epson Research and Development
Vancouver Design Center
Page 29
Figure 7-2: S5U13506B00C Schematic Diagram (2 of 7)
S1D13506
X25B-G-004-06
1
2
3
P1,5
A
LCDPWR
ChipVdd
1
Ferrite
L3
WE#
P1
+5V
RAS#
UCAS#
LCAS#
P1
P1
P1
2
74AHC04
U4A
C16
0.1u
U5
EPN001
1
47uF/10V
R22
100K Pot.
+ C21
R16
10K
R14
10K
B
2
3
4
5
7
8
9
10
33
34
35
36
38
39
40
41
U3
RD-0412
VCC 1
VCC 6
VCC 21
VSS 22
VSS 37
VSS 42
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
47uF/10V
+ C17
3
Q1
2MMBT2222A
+5V
DRAM 1Mx16-SOJ
11 NC
12 NC
32 NC
29 /OE
14 /RAS
30 /UCAS
31 /LCAS
13 /W
A0
A1
A2
A3
A4
A5
A6
A7
A8R/A8
A9R/A9
A10/NC
A11/NC
U2
VOUT_ADJ
6
4
17
18
19
20
23
24
25
26
27
28
16
15
GND
GND
5
4
MA0
MA1
MA2
MA3
MA4
MA5
MA6
MA7
MA8
MA9
NC
NC
NC
NC
9
8
7
3
MA[9:0]
DC_OUT
2
P1
MD0
MD1
MD2
MD3
MD4
MD5
MD6
MD7
MD8
MD9
MD10
MD11
MD12
MD13
MD14
MD15
C13
0.1u
1
2
C22
56uF/35V
Low ESR
100K
R20
10K
R18
Q3
MMBT3904
3
R19
10K
Q2
3 MMBT3906
2
+5V
DC_IN
2
1
MA[9:0]
REMOTE
3
DC_OUT
MD[15:0]
GND
GND
GND
GND
GND
GND
GND
MD[15:0]
NC
4
5
6
7
8
10
11
1
B
VOUT_ADJ
9
P1
11 DC_IN
10 DC_IN
DC_OUT
12
1
S1D13506
X25B-G-004-06
+
A
C
+5V
R17
15K
MD1
MD2
MD3
MD4
MD5
MD10
MD11
MD12
MD13
MD15
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
VLCD
4.7uF/50V
1uH
L4
SW DIP-10
S1
+ C19
MD6
MD14
4.7uF/50V
+ C18
ChipVdd
C15
0.1u
R21
100K
R15
200K Pot.
R13
470K
C14
0.1u
C
D
P5
R11
15K
R12
n/p
R2
15K
Date:
Size
B
Title
ChipVdd
R3
15K
4.7uF/50V
+ C20
R1
15K
D
MD14
MD13
R5
15K
R6
15K
R63
4.7K
R7
15K
R8
15K
Monday, June 14, 1999
Document Number
{Doc}
E
Sheet
S5U13506B00C Evaluation Board
Rework
R4
15K
E
3
VDDH
R9
15K
of
R10
15K
7
P5
Rev
1
ChipVdd
1
2
3
4
Page 30
Epson Research and Development
Vancouver Design Center
Figure 7-3: S5U13506B00C Schematic Diagram (3 of 7)
S5U13506B00C Evaluation Board User Manual
Issue Date: 01/02/06
1
2
3
AD[31:0]
C/BE3#
IDSEL
C/BE2#
FRAME#
IRDY#
TRDY#
DEVSEL#
STOP#
PERR#
SERR#
PAR
C/BE1#
C/BE0#
P2
P2
P2
P2
P2
P2
P2
P2
P2
P2
P2
P2
P2
RST#
P2
P2
CLK
P2
A
AD28
AD27
AD26
AD31
AD30
AD29
AB20
AB17
AB18
AB19
AD[31:0]
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
IO1
IO2
IO3
nCE
GND
Vccint
Vccio
IO8
IO9
IO10
IO11
IO12
IO13
IO14
IO15
IO16
I17
GND
Vccio
I20
IO21
IO22
IO23
IO24
IO25
IO26
IO27
IO28
IO29
GND
Vccint
Vccio
MSEL
IO34
IO35
IO36
AD25
AD24
AB14
AB15
AB16
AB13
AB12
AB11
AB10
AB9
AB8
AB7
AB6
AB5
AB4
AB3
AB2
AB1
AB0
AD23
AD22
AD21
AD20
AD19
AD18
AD17
AD16
U6
DATA
B
nSTATUS
+5V
ChipVdd
DCLK
B
DB11
DB10
DB13
DB12
DB15
DB14
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
DB[15:0]
AB[20:0]
C
IO108
IO107
IO106
CONF_DONE
Vccio
Vccint
GND
IO101
IO100
IO99
IO98
IO97
IO96
IO95
IO94
IO93
I92
Vccio
GND
I89
IO88
IO87
IO86
IO85
IO84
IO83
IO82
IO81
IO80
IO79
Vccio
Vccint
GND
IO75
IO74
IO73
C
nCONFIG
108
DB9
107
DB8
106
DB7
105 CONF_DONE
104
103
102
101
DB6
100
DB5
99
DB4
98
DB3
97
96
DB2
95
DB1
94
93
DB0
92
91
90
89
88
87
86
85
84
AD0
83
AD1
82
AD2
81
AD3
80
AD4
79
78
77
76
AD5
75
AD6
74
AD7
73
EPF6016TC144-2
IO144
IO143
IO142
IO141
IO140
IO139
IO138
IO137
IO136
IO135
IO134
IO133
IO132
IO131
IO130
IO129
DCLK
Vccio
GND
DATA
IO124
IO123
IO122
IO121
IO120
IO119
IO118
IO117
IO116
IO115
IO114
IO113
IO112
IO111
IO110
IO109
IO37
IO38
IO39
IO40
IO41
IO42
IO43
IO44
IO45
IO46
IO47
IO48
IO49
IO50
IO51
IO52
nCONFIG
GND
Vccio
nSTATUS
IO57
IO58
IO59
IO60
IO61
IO62
IO63
IO64
IO65
IO66
IO67
IO68
IO69
IO70
IO71
IO72
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
AD15
AD14
AD13
AD12
AD11
AD10
AD9
S5U13506B00C Evaluation Board User Manual
Issue Date: 01/02/06
AD8
4
A
R30
1K
HEADER 2
1
2
JP9
R27
15K
Place jumper to disable FPGA
+5V
R26
15K
R23
100K
R28
15K
P1,2
P1,2
P7
P1,2
P1,2
P1,2
P1,2
P1,2
P1,2
P1,2
P1,2
P1,2
D
1
2
3
4
+5V
R25
1K
1
2
3
4
U7
+5V
C24
0.22u
+5V
+5V
+5V
+5V
Date:
Size
B
Title
C28
0.22u
C25
0.22u
C30
0.22u
ChipVdd
C26
0.22u
8
7
6
5
Thursday, April 01, 1999
Document Number
{Doc}
E
Sheet
E
C31
0.22u
ChipVdd
C27
0.22u
+5V
+5V
+5V
S5U13506B00C Evaluation Board
C29
0.22u
ChipVdd
+5V
+5V
EPC1441PC8
VCC
DATA
DCLK
VCC
OE
nCASC
nCS
GND
FPGA configuration EPROM
R24
1K
ChipVdd
8
7
6
5
+5V
SW DIP-4
S2
DATA
DCLK
nSTATUS
CONF_DONE
R29
15K
DB[15:0]
AB[20:0]
BCLK
RD#
BS#
RD/WR#
WE1#
M/R#
CS#
WAIT#
WE0#
RESET#
D
+5V
4
C23
0.22u
of
7
Rev
1
1
2
3
4
Epson Research and Development
Vancouver Design Center
Page 31
Figure 7-4: S5U13506B00C Schematic Diagram (4 of 7)
S1D13506
X25B-G-004-06
1
2
3
4
1
2
3
P1
P1
P1
P1
P1,3
FPSHIFT
DRDY
FPLINE
FPFRAME
LCDPWR
HEADER 3
JP8
P1,6 FPDAT[15:0]
A
MUXED
DIRECT
VRTC
P1
P1
HRTC
GREEN
BLUE
P1
P1
RED
R61
15K
P1
ChipVdd
FPDAT8
FPDAT9
FPDAT10
FPDAT11
FPDAT12
FPDAT13
FPDAT14
FPDAT15
FPDAT0
FPDAT1
FPDAT2
FPDAT3
FPDAT4
FPDAT5
FPDAT6
FPDAT7
1
11
3
4
7
8
13
14
17
18
1
19
2
4
6
8
11
13
15
17
VCC
GND
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
20
10
2
5
6
9
12
15
16
19
VCC
GND
1Y1
1Y2
1Y3
1Y4
2Y1
2Y2
2Y3
2Y4
R31
150 1%
FPSHIFT
DRDY
FPLINE
FPFRAME
LCDPWR
74AHC374
OC
CLK
D0
D1
D2
D3
D4
D5
D6
D7
U16
74AHC244
1G
2G
1A1
1A2
1A3
1A4
2A1
2A2
2A3
2A4
U8
B
R32
150 1%
C57
0.1u
LCDVCC
R33
150 1%
1
19
Ferrite
Ferrite
L7
Ferrite
L6
L5
VCC
GND
1Y1
1Y2
1Y3
1Y4
2Y1
2Y2
2Y3
2Y4
FPDAT8
FPDAT9
FPDAT10
FPDAT11
FPDAT12
FPDAT13
FPDAT14
FPDAT15
74AHC244
1G
2G
1A1
1A2
1A3
1A4
2A1
2A2
2A3
2A4
U10
R62
15K
2
4
6
8
11
13
15
17
ChipVdd
DIRECT
C32
0.1u
LCDVCC
BFPDAT0
BFPDAT1
BFPDAT2
BFPDAT3
BFPDAT4
BFPDAT5
BFPDAT6
BFPDAT7
BFPDAT8
BFPDAT9
BFPDAT10
BFPDAT11
BFPDAT12
BFPDAT13
BFPDAT14
BFPDAT15
20
10
18
16
14
12
9
7
5
3
20
10
18
16
14
12
9
7
5
3
1
19
2
4
6
8
11
13
15
17
VCC
GND
1Y1
1Y2
1Y3
1Y4
2Y1
2Y2
2Y3
2Y4
C
AVDD
D1
BAV99L
3
20
10
18
16
14
12
9
7
5
3
C
C34
0.1u
D2
BAV99L
3
C33
0.1u
LCDVCC
BFPDAT8
BFPDAT9
BFPDAT10
BFPDAT11
BFPDAT12
BFPDAT13
BFPDAT14
BFPDAT15
AVDD
LCDVCC
BFPSHIFT
BDRDY
BFPLINE
BFPFRAME
BLCDPWR
74AHC244
1G
2G
1A1
1A2
1A3
1A4
2A1
2A2
2A3
2A4
U9
2
1
B
2
1
A
AVDD
2
1
D3
BAV99L
3
BFPDAT0
BFPDAT1
BFPDAT2
BFPDAT3
BFPDAT4
BFPDAT5
BFPDAT6
BFPDAT7
BFPDAT8
BFPDAT9
BFPDAT10
BFPDAT11
BFPDAT12
BFPDAT13
BFPDAT14
BFPDAT15
BFPSHIFT
BDRDY
BFPLINE
BFPFRAME
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
D
Header 20x2
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
J1
D
6
1
11
7
2
12
8
3
13
9
4
14
10
5
15
CRT
J3
Date:
Size
B
Title
J4
G
S-VIDEO
G
C Y
J2
1
3
C-VIDEO
LCDVCC
Thursday, April 01, 1999
Document Number
{Doc}
S5U13506B00C Evaluation Board
2
4
P3
+12V
VDDH
1
P3
VLCD
2
S1D13506
X25B-G-004-06
FPDAT[15:0]
Sheet
E
+3.3V
+5V
E
5
of
7
HEADER 3
1
2
3
JP2
Rev
1
1
2
3
4
Page 32
Epson Research and Development
Vancouver Design Center
Figure 7-5: S5U13506B00C Schematic Diagram (5 of 7)
S5U13506B00C Evaluation Board User Manual
Issue Date: 01/02/06
S5U13506B00C Evaluation Board User Manual
Issue Date: 01/02/06
1
2
3
4
P1,5 FPDAT[15:0]
A
FPDAT[15:0]
A
FPDAT9
FPDAT8
FPDAT10
FPDAT11
FPDAT13
FPDAT12
FPDAT15
FPDAT14
2
4
6
8
10
12
14
16
HEADER 8X2
1
3
5
7
9
11
13
15
JP3
B
ChipVdd
B
VMPCLK
R42
137 1%
R40
137 1%
C41
33pF
ChipVdd
VMPCLKN
VMPD2
R45
357 1%
VMPD3
R43
316 1%
VMPD1
VMPD0
VMPLCTL
VMPRCTL
2
3
ChipVdd
2
1
3
22
R54
22
R51
BAV99L
D5
BAT54
D4
ChipVdd
R49
357 1%
C43
220pF
C
C44
220pF
33
R55
33
R52
C42
33pF
R53
68
n/p
68
L13
R48
n/p
68
L12
R44
n/p
L11
68
1
0.01u
C37
33pF
C35
33pF
68
R35
n/p
L8
R41
C39
33pF
R39
357 1%
R37
316 1%
R36
1.5K 1%
R34
6.04K 1%
C38
R46
316 1%
ChipVdd
ChipVdd
C
R38
n/p
L10
68
D
D
150nH
L9
Date:
Size
B
Title
P7
3
ChipVdd
4
4
Wednesday, June 16, 1999
Document Number
{Doc}
Sheet
E
10K
R50
+ C40
10uF/16V
74AHC04
U4B
Q4
NDS9400A
8
7
6
5
3
2
1
MPLCTL
MPRCTL
MPD0
MPD1
MPD3
MPD2
MPCLKN
MPCLK
MPPWR
S5U13506B00C Evaluation Board
VMPEPWR
+5V
C36
33pF
E
6
1
R47
10K
7
Rev
1
3
Q5
2MMBT2222A
of
+5V
MediaPlug Conn.
1
2
3
4
5
6
7
8
9
10
J5
1
2
3
4
Epson Research and Development
Vancouver Design Center
Page 33
Figure 7-6: S5U13506B00C Schematic Diagram (6 of 7)
S1D13506
X25B-G-004-06
1
2
3
4
P1
P1
GPIO2
GPIO1
+5V
+ C45
10uF/16V
A
13
ChipVdd
11
ChipVdd
C54
0.1u
C50
n/p
C46
0.1u
JP5
74AHC04
U4F
74AHC04
U4E
7
14
C47
0.1u
OUT
NC
12
10
8
1
2
11
15
6
7
16
4
12
14
1
2
VMPEPWR
B
ICD2061A
FEATCLK
INTCLK
XTALIN
XTALOUT
PWRDWN#
OE
INIT0
INIT1
S0/CLK
S1/DATA
U12
P6
+5V
C48
0.1u
OSCVDD
L15
Ferrite
8
P4
2
BCLK
C
ChipVdd
5
JP4
C55
0.1u
ERROUT#
VCLKOUT
MCLKOUT
3
C49
0.1u
VIN
U15
LT1117CM-3.3
10
9
VOUT
C
+ C56
10uF/16V
+5V
ChipVdd
8
6
C52
0.1u
74AHC04
U4D
+3.3V
9
74AHC04
U4C
HEADER 3
VOUT
3
ADJ
OSCVDD
VIN
C51
n/p
17.734475MHz
GND
VCC
U14
3
R56
100K
HEADER 2
14.31818MHz
Y1
Ferrite
1
2
L14
B
13
VDD
GND
5
AVDD
1
U11
LT1117CST-5
3
VIN
U13
LT1117CST-3.3
BUSCLK
EXTBCLK
ADJ
1
+12V
A
VOUT
P1
P2
2
D
D
+ C53
10uF/16V
HEADER 3
JP6
Date:
Size
B
Title
1
2
3
1
2
3
ADJ
P1
CLKI2
1
Thursday, April 01, 1999
Document Number
{Doc}
S5U13506B00C Evaluation Board
R58
1K 1%
HEADER 3
JP7
IREF
3
Q6
2
MMBT2222A
P1
CLKI
R57
1.5K 1%
P2
EXTCLKI
E
P1
Sheet
E
R59
140 1%
1
2
3
S1D13506
X25B-G-004-06
1
7
of
R60
69.8 1%
7
Rev
1
1
2
3
4
Page 34
Epson Research and Development
Vancouver Design Center
Figure 7-7: S5U13506B00C Schematic Diagram (7 of 7)
S5U13506B00C Evaluation Board User Manual
Issue Date: 01/02/06
Epson Research and Development
Vancouver Design Center
Page 35
8 Technical Support
8.1 EPSON LCD/CRTControllers (S1D13506)
Japan
Seiko Epson Corporation
Electronic Devices Marketing Division
421-8, Hino, Hino-shi
Tokyo 191-8501, Japan
Tel: 042-587-5812
Fax: 042-587-5564
http://www.epson.co.jp
Hong Kong
Epson Hong Kong Ltd.
20/F., Harbour Centre
25 Harbour Road
Wanchai, Hong Kong
Tel: 2585-4600
Fax: 2827-4346
S5U13506B00C Evaluation Board User Manual
Issue Date: 01/02/06
North America
Epson Electronics America, Inc.
150 River Oaks Parkway
San Jose, CA 95134, USA
Tel: (408) 922-0200
Fax: (408) 922-0238
http://www.eea.epson.com
Taiwan, R.O.C.
Epson Taiwan Technology
& Trading Ltd.
10F, No. 287
Nanking East Road
Sec. 3, Taipei, Taiwan, R.O.C.
Tel: 02-2717-7360
Fax: 02-2712-9164
Europe
Epson Europe Electronics GmbH
Riesstrasse 15
80992 Munich, Germany
Tel: 089-14005-0
Fax: 089-14005-110
Singapore
Epson Singapore Pte., Ltd.
No. 1
Temasek Avenue #36-00
Millenia Tower
Singapore, 039192
Tel: 337-7911
Fax: 334-2716
S1D13506
X25B-G-004-06
Page 36
Epson Research and Development
Vancouver Design Center
THIS PAGE LEFT BLANK
S1D13506
X25B-G-004-06
S5U13506B00C Evaluation Board User Manual
Issue Date: 01/02/06
S1D13506 Color LCD/CRT/TV Controller
Interfacing to the PC Card Bus
Document Number: X25B-G-005-03
Copyright © 1999, 2001 Epson Research and Development, Inc. All Rights Reserved.
Information in this document is subject to change without notice.You may download and use this document, but only for your own use in
evaluating Seiko Epson/EPSON products. You may not modify the document. Epson Research and Development, Inc. disclaims any
representation that the contents of this document are accurate or current. The Programs/Technologies described in this document may contain
material protected under U.S. and/or International Patent laws.
EPSON is a registered trademark of Seiko Epson Corporation. All other trademarks are the property of their respective owners.
Page 2
Epson Research and Development
Vancouver Design Center
THIS PAGE LEFT BLANK
S1D13506
X25B-G-005-03
Interfacing to the PC Card Bus
Issue Date: 01/02/06
Epson Research and Development
Vancouver Design Center
Page 3
Table of Contents
1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2
Interfacing to the PC Card Bus
2.1 The PC Card System Bus . .
2.1.1 PC Card Overview . .
2.1.2 Memory Access Cycles
3
S1D13506 Host Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.1 PC Card Host Bus Interface Pin Mapping . . . . . . . . . . . . . . . . . . . 11
3.2 PC Card Host Bus Interface Signals . . . . . . . . . . . . . . . . . . . . . . 12
4
PC Card to S1D13506 Interface . .
4.1 Hardware Description . . . . .
4.2 S1D13506 Hardware Configuration
4.3 Performance . . . . . . . . .
4.4 Register/Memory Mapping . . .
5
Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
6
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.1 Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.2 Document Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
7
Technical Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
7.1 Epson LCD/CRT Controllers (S1D13506) . . . . . . . . . . . . . . . . . . . 19
7.2 PC Card Standard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Interfacing to the PC Card Bus
Issue Date: 01/02/06
. .
. .
. . .
. . .
.
.
.
.
.
.
.
.
.
. . .
. .
. . .
. . .
. . .
. .
. .
. .
. .
. . . . . . .
. . . . . .
. . . . . . . .
. . . . . . . .
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
. . .
. .
. .
. .
. .
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
. . . . . .
. . . . .
. . . . . . .
. . . . . . .
. . .
. .
. .
. .
. .
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
. . .
. .
. . .
. . .
. . .
. .
. .
. .
. .
.
.
.
.
.
. . . . 8
. . . .8
. . . . .8
. . . . .8
.
.
.
.
.
.
.
.
.
.
. 13
. 13
. 15
. 15
. 16
S1D13506
X25B-G-005-03
Page 4
Epson Research and Development
Vancouver Design Center
THIS PAGE LEFT BLANK
S1D13506
X25B-G-005-03
Interfacing to the PC Card Bus
Issue Date: 01/02/06
Epson Research and Development
Vancouver Design Center
Page 5
List of Tables
Table 3-1: PC Card Host Bus Interface Pin Mapping . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 4-1: Summary of Power-On/Reset Options . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 4-2: Register/Memory Mapping for Typical Implementation . . . . . . . . . . . . . . . . . 16
List of Figures
Figure 2-1: PC Card Read Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 2-2: PC Card Write Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 4-1: Typical Implementation of PC Card to S1D13506 Interface . . . . . . . . . . . . . . . . 14
Interfacing to the PC Card Bus
Issue Date: 01/02/06
S1D13506
X25B-G-005-03
Page 6
Epson Research and Development
Vancouver Design Center
THIS PAGE LEFT BLANK
S1D13506
X25B-G-005-03
Interfacing to the PC Card Bus
Issue Date: 01/02/06
Epson Research and Development
Vancouver Design Center
Page 7
1 Introduction
This application note describes the hardware and software environment required to provide
an interface between the S1D13506 Color LCD/CRT/TV Controller and the PC Card
(PCMCIA) bus.
The designs described in this document are presented only as examples of how such
interfaces might be implemented. This application note will be updated as appropriate.
Please check the Epson Electronics America website at http://www.eea.epson.com for the
latest revision of this document before beginning any development.
We appreciate your comments on our documentation. Please contact us via email at
[email protected]
Interfacing to the PC Card Bus
Issue Date: 01/02/06
S1D13506
X25B-G-005-03
Page 8
Epson Research and Development
Vancouver Design Center
2 Interfacing to the PC Card Bus
2.1 The PC Card System Bus
PC Card technology has gained wide acceptance in the mobile computing field as well as
in other markets due to its portability and ruggedness. This section is an overview of the
operation of the 16-bit PC Card interface conforming to the PCMCIA 2.0/JEIDA 4.1
Standard (or later).
2.1.1 PC Card Overview
The 16-bit PC Card provides a 26-bit address bus and additional control lines which allow
access to three 64M byte address ranges. These ranges are used for common memory space,
IO space, and attribute memory space. Common memory may be accessed by a host system
for memory read and write operations. Attribute memory is used for defining card specific
information such as configuration registers, card capabilities, and card use. IO space
maintains software and hardware compatibility with hosts such as the Intel x86
architecture, which address peripherals independently from memory space.
Bit notation follows the convention used by most micro-processors, the high bit being the
most significant. Therefore, signals A25 and D15 are the most significant bits for the
address and data busses respectively.
Support is provided for on-chip DMA controllers. To find further information on these
topics, refer to Section 6, “References” on page 18.
PC Card bus signals are asynchronous to the host CPU bus signals. Bus cycles are started
with the assertion of the CE1# and/or the CE2# card enable signals. The cycle ends once
these signals are de-asserted. Bus cycles can be lengthened using the WAIT# signal.
Note
The PCMCIA 2.0/JEIDA 4.1 (and later) PC Card Standard support the two signals
WAIT# and RESET which are not supported in earlier versions of the standard. The
WAIT# signal allows for asynchronous data transfers for memory, attribute, and IO
access cycles. The RESET signal allows resetting of the card configuration by the reset
line of the host CPU.
2.1.2 Memory Access Cycles
A data transfer is initiated when a memory address is placed on the PC Card bus and one,
or both, of the card enable signals (CE1# and CE2#) are driven low. REG# must be inactive.
If only CE1# is driven low, 8-bit data transfers are enabled and A0 specifies whether the
even or odd data byte appears on data bus lines D[7:0]. If both CE1# and CE2# are driven
low, a 16-bit word transfer takes place. If only CE2# is driven low, an odd byte transfer
occurs on data lines D[15:8].
S1D13506
X25B-G-005-03
Interfacing to the PC Card Bus
Issue Date: 01/02/06
Epson Research and Development
Vancouver Design Center
Page 9
During a read cycle, OE# (output enable) is driven low. A write cycle is specified by
driving OE# high and driving the write enable signal (WE#) low. The cycle can be
lengthened by driving WAIT# low for the time needed to complete the cycle.
Figure 2-1: illustrates a typical memory access read cycle on the PC Card bus.
A[25:0]
REG#
ADDRESS VALID
CE1#
CE2#
OE#
WAIT#
D[15:0]
Hi-Z
DATA VALID
Transfer Start
Hi-Z
Transfer Complete
Figure 2-1: PC Card Read Cycle
Interfacing to the PC Card Bus
Issue Date: 01/02/06
S1D13506
X25B-G-005-03
Page 10
Epson Research and Development
Vancouver Design Center
Figure 2-2: illustrates a typical memory access write cycle on the PC Card bus.
A[25:0]
REG#
ADDRESS VALID
CE1#
CE2#
OE#
WE#
WAIT#
D[15:0]
Hi-Z
Hi-Z
DATA VALID
Transfer Start
Transfer Complete
Figure 2-2: PC Card Write Cycle
S1D13506
X25B-G-005-03
Interfacing to the PC Card Bus
Issue Date: 01/02/06
Epson Research and Development
Vancouver Design Center
Page 11
3 S1D13506 Host Bus Interface
The S1D13506 implements a 16-bit PC Card (PCMCIA) Host Bus Interface which is used
to interface to the PC Card bus.
The PC Card Host Bus Interface is selected by the S1D13506 on the rising edge of
RESET#. After releasing reset the bus interface signals assume their selected configuration.
For details on S1D13506 configuration, see Section 4.2, “S1D13506 Hardware Configuration” on page 15.
Note
At reset, the Register/Memory Select bit in the Miscellaneous Register (REG[001h] bit
7) is set to 1. This means that only REG[000h] (read-only) and REG[001h] are
accessible until a write to REG[001h] sets bit 7 to 0 making all registers accessible.
When debugging a new hardware design, this can sometimes give the appearance that
the interface is not working, so it is important to remember to clear this bit before
proceeding with debugging.
3.1 PC Card Host Bus Interface Pin Mapping
The following table shows the functions of each Host Bus Interface signal.
Table 3-1: PC Card Host Bus Interface Pin Mapping
S1D13506 Pin Name
AB[20:1]
DB[15:0]
WE1#
M/R#
CS#
BUSCLK
BS#
RD/WR#
RD#
WE0#
WAIT#
RESET#
PC Card (PCMCIA)
A[20:1]1
D[15:0]
CE2#
External Decode
External Decode
n/a2
VDD
CE1#
OE#
WE#
WAIT#
Inverted RESET
Note
1
The bus signal A0 is not used by the S1D13506 internally.
2Although a
clock is not directly supplied by the PC Card interface, one is required by
the S1D13506 PC Card Host Bus Interface. For an example of how this can be accomplished see the discussion on BUSCLK in Section 3.2, “PC Card Host Bus Interface
Signals” on page 12.
Interfacing to the PC Card Bus
Issue Date: 01/02/06
S1D13506
X25B-G-005-03
Page 12
Epson Research and Development
Vancouver Design Center
3.2 PC Card Host Bus Interface Signals
The S1D13506 PC Card Host Bus Interface is designed to support processors which
interface the S1D13506 through the PC Card bus.
The S1D13506 PC Card Host Bus Interface requires the following signals from the PC
Card bus.
• BUSCLK is a clock input which is required by the S1D13506 Host Bus Interface. It is
separate from the input clock (CLKI) and is typically driven by the host CPU system
clock. Since PC Card signalling is independent of any clock, BUSCLK can come from
any oscillator already implemented. For example, the source for the CLKI input of the
S1D13506 may be used.
• The address inputs AB[20:1], and the data bus DB[15:0], connect directly to the PC
Card address (A[20:1]) and data bus (D[15:0]), respectively. MD4 must be set to select
little endian mode upon reset.
• M/R# (memory/register) selects between memory or register access. It may be
connected to an address line, allowing system address A21 to be connected to the M/R#
line.
• Chip Select (CS#) must be driven low whenever the S1D13506 is accessed by the PC
Card bus.
• WE1# and RD/WR# connect to CE2# and CE1# (the byte enables for the high-order and
low-order bytes). They are driven low when the PC Card bus is accessing the
S1D13506.
• RD# connects to OE# (the read enable signal from the PC Card bus).
• WE0# connects to WE# (the write enable signal from the PC Card bus).
• WAIT# is a signal output from the S1D13506 that indicates the PC Card bus must wait
until data is ready (read cycle) or accepted (write cycle) on the host bus. Since PC Card
bus accesses to the S1D13506 may occur asynchronously to the display update, it is
possible that contention may occur in accessing the S1D13506 internal registers and/or
display buffer. The WAIT# line resolves these contentions by forcing the host to wait
until the resource arbitration is complete. For PC Card applications, this signal should
be set active low using the MD5 configuration input.
• The Bus Start (BS#) signal is not used for the PC Card Host Bus Interface and should be
tied high (connected to VDD).
• The RESET# (active low) input of the S1D13506 may be connected to the PC Card
RESET (active high) using an inverter.
S1D13506
X25B-G-005-03
Interfacing to the PC Card Bus
Issue Date: 01/02/06
Epson Research and Development
Vancouver Design Center
Page 13
4 PC Card to S1D13506 Interface
4.1 Hardware Description
The S1D13506 is designed to directly support a variety of CPUs, providing an interface to
each processor’s unique “local bus”. However, in order to provide support for processors
not having an appropriate local bus, the S1D13506 supports a specific PC Card interface.
The S1D13506 provides a “glueless” interface to the PC Card bus except for the following.
• The RESET# signal on the S1D13506 is active low and must be inverted to support the
active high RESET provided by the PC Card interface.
• Although the S1D13506 supports an asynchronous bus interface, a clock source is
required on the BUSCLK input pin.
In this implementation, the address inputs (AB[20:1]) and data bus (DB[15:0]) connect
directly to the CPU address (A[20:1]) and data bus (D[15:0]). M/R# is treated as an address
line so that it can be controlled using system address A21.
The PC Card interface does not provide a bus clock, so one must be supplied for the
S1D13506. Since the bus clock frequency is not critical, nor does it have to be synchronous
to the bus signals, it may be the same as CLKI. BS# (bus start) is not used and should be
tied high (connected to VDD).
Interfacing to the PC Card Bus
Issue Date: 01/02/06
S1D13506
X25B-G-005-03
Page 14
Epson Research and Development
Vancouver Design Center
The following shows a typical implementation of the PC Card to S1D13506 interface.
PC Card socket
S1D13506
OE#
RD#
WE0#
WE#
CE1#
RD/WR#
WE1#
CE2#
RESET
VDD
A21
RESET#
BS#
CS#
M/R#
AB[20:1]
A[20:1]
D[15:0]
DB[15:0]
15K
WAIT#
WAIT#
BUSCLK
Oscillator
CLKI
Note:
When connecting the S1D13506 RESET# pin, the system designer should be aware of all
conditions that may reset the S1D13506 (e.g. CPU reset can be asserted during wake-up
from power-down modes, or during debug states).
Figure 4-1: Typical Implementation of PC Card to S1D13506 Interface
S1D13506
X25B-G-005-03
Interfacing to the PC Card Bus
Issue Date: 01/02/06
Epson Research and Development
Vancouver Design Center
Page 15
4.2 S1D13506 Hardware Configuration
The S1D13506 latches MD15 through MD0 to allow selection of the bus mode and other
configuration data on the rising edge of RESET#. For details on configuration, refer to the
S1D13506 Hardware Functional Specification, document number X25B-A-001-xx.
The table below shows only those configuration settings important to the PC Card Host Bus
Interface.
Table 4-1: Summary of Power-On/Reset Options
MD[3:1]
MD4
MD5
value on this pin at rising edge of RESET# is used to configure:(1/0)
1
0
111 = PC Card Host Bus Interface selected
Little Endian
Big Endian
WAIT# is active high (1 = insert wait state)
WAIT# is active low (0 = insert wait state)
MD11
MD12
Alternate Host Bus Interface Selected
BUSCLK input divided by two
Primary Host Bus Interface Selected
BUSCLK input not divided by two
MD15
WAIT# is always driven
WAIT# is floating if S1D13506 is not selected
S1D13506
Pin Name
= configuration for PC Card Host Bus Interface
4.3 Performance
The S1D13506 PC Card Interface specification supports a BCLK up to 50MHz, and
therefore can provide a high performance display solution.
Interfacing to the PC Card Bus
Issue Date: 01/02/06
S1D13506
X25B-G-005-03
Page 16
Epson Research and Development
Vancouver Design Center
4.4 Register/Memory Mapping
The S1D13506 is a memory mapped device. The internal registers require 47 bytes and are
mapped in the lower PC Card memory address space starting at zero.The display buffer
requires 2M bytes and is mapped in the third and fourth megabytes of the PC Card address
space (ranging from 200000h to 3FFFFFh).
A typical implementation as shown in Figure 4-1: “Typical Implementation of PC Card to
S1D13506 Interface,” on page 14 has Chip Select (CS#) connected to ground (always
enabled) and the Memory/Register select pin (M/R#) connected to address bit A21. This
provides the following decoding:
Table 4-2: Register/Memory Mapping for Typical Implementation
CS#
M/R# (A21)
Address Range
Function
0
0
0 - 1F FFFFh
Internal Register
Set decoded
0
1
20 0000h - 3F FFFFh
Display Buffer
decode
The PC Card socket provides 64M byte of address space. Without further resolution on the
decoding logic (M/R# connected to A21), the entire register set is aliased for every 64 byte
boundary within the specified address range above. Since address bits A[25:22] are
ignored, the S1D13506 registers and display buffer are aliased 16 times.
Note
If aliasing is not desirable, the upper addresses must be fully decoded.
S1D13506
X25B-G-005-03
Interfacing to the PC Card Bus
Issue Date: 01/02/06
Epson Research and Development
Vancouver Design Center
Page 17
5 Software
Test utilities and Windows® CE display drivers are available for the S1D13506. Full
source code is available for both the test utilities and the drivers.
The test utilities are configurable for different panel types using a program called
13506CFG, or by directly modifying the source. The Windows CE display drivers can be
customized by the OEM for different panel types, resolutions and color depths only by
modifying the source.
The S1D13506 test utilities and Windows CE display drivers are available from your sales
support contact or on the internet at http://www.eea.epson.com.
Interfacing to the PC Card Bus
Issue Date: 01/02/06
S1D13506
X25B-G-005-03
Page 18
Epson Research and Development
Vancouver Design Center
6 References
6.1 Documents
• PC Card (PCMCIA) Standard, March 1997
• Epson Research and Development, Inc., S1D13506 Hardware Functional Specification,
Document Number X25B-A-001-xx.
• Epson Research and Development, Inc., S1D13506 Programming Notes and Examples,
Document Number X25B-G-003-xx.
• Epson Research and Development, Inc., S5U13506B00C Rev. 1.0 ISA Bus Evaluation
Board User Manual, Document Number X25B-G-004-xx.
6.2 Document Sources
• PC Card Website: http://www.pc-card.com.
• Epson Electronics America Website: http://www.eea.epson.com.
S1D13506
X25B-G-005-03
Interfacing to the PC Card Bus
Issue Date: 01/02/06
Epson Research and Development
Vancouver Design Center
Page 19
7 Technical Support
7.1 Epson LCD/CRT Controllers (S1D13506)
Japan
Seiko Epson Corporation
Electronic Devices Marketing Division
421-8, Hino, Hino-shi
Tokyo 191-8501, Japan
Tel: 042-587-5812
Fax: 042-587-5564
http://www.epson.co.jp
North America
Epson Electronics America, Inc.
150 River Oaks Parkway
San Jose, CA 95134, USA
Tel: (408) 922-0200
Fax: (408) 922-0238
http://www.eea.epson.com
Taiwan, R.O.C.
Epson Taiwan Technology
& Trading Ltd.
10F, No. 287
Nanking East Road
Sec. 3, Taipei, Taiwan, R.O.C.
Tel: 02-2717-7360
Fax: 02-2712-9164
Hong Kong
Epson Hong Kong Ltd.
20/F., Harbour Centre
25 Harbour Road
Wanchai, Hong Kong
Tel: 2585-4600
Fax: 2827-4346
Europe
Epson Europe Electronics GmbH
Riesstrasse 15
80992 Munich, Germany
Tel: 089-14005-0
Fax: 089-14005-110
Singapore
Epson Singapore Pte., Ltd.
No. 1
Temasek Avenue #36-00
Millenia Tower
Singapore, 039192
Tel: 337-7911
Fax: 334-2716
7.2 PC Card Standard
PCMCIA
(Personal Computer Memory Card International Association)
2635 North First Street, Suite 209
San Jose, CA 95134, USA
Tel: (408) 433-2273
Fax: (408) 433-9558
http://www.pc-card.com
Interfacing to the PC Card Bus
Issue Date: 01/02/06
S1D13506
X25B-G-005-03
Page 20
Epson Research and Development
Vancouver Design Center
THIS PAGE LEFT BLANK
S1D13506
X25B-G-005-03
Interfacing to the PC Card Bus
Issue Date: 01/02/06
S1D13506 Color LCD/CRT/TV Controller
Power Consumption
Document Number: X25B-G-006-02
Copyright © 2001 Epson Research and Development, Inc. All Rights Reserved.
Information in this document is subject to change without notice.You may download and use this document, but only for your own use in
evaluating Seiko Epson/EPSON products. You may not modify the document. Epson Research and Development, Inc. disclaims any
representation that the contents of this document are accurate or current. The Programs/Technologies described in this document may contain
material protected under U.S. and/or International Patent laws.
EPSON is a registered trademark of Seiko Epson Corporation. All other trademarks are the property of their respective owners.
Page 2
Epson Research and Development
Vancouver Design Center
THIS PAGE LEFT BLANK
S1D13506
X25B-G-006-02
Power Consumption
Issue Date: 01/02/08
Epson Research and Development
Vancouver Design Center
Page 3
1 S1D13506 Power Consumption
S1D13506 power consumption is affected by many system design variables.
• Input clock frequency (CLKI/CLKI2): the CLKI/CLKI2 frequency determines the
LCD/CRT frame-rate, CPU performance to memory, and other functions – the higher
the input clock frequency, the higher the frame-rate, performance and power
consumption.
• CPU interface: the S1D13506 current consumption depends on the BUSCLK frequency,
data width, number of toggling pins, and other factors – the higher the BUSCLK, the
higher the CPU performance and power consumption.
• VDD voltage level: the voltage level affects power consumption – the higher the voltage,
the higher the consumption.
• Display mode: the resolution and color depth affect power consumption – the higher the
resolution/color depth, the higher the consumption.
• Internal CLK divide: internal registers allow the input clock to be divided before going
to the internal logic blocks – the higher the divide, the lower the power consumption.
There is a power save mode in the S1D13506. The power consumption is affected by
various system design variables.
• DRAM refresh mode (CBR or self-refresh): self-refresh capable DRAM allows the
S1D13506 to disable the internal memory clock thereby saving power.
• Clock states during the power save mode: disabling the clocks during power save mode
has substantial power savings.
Power Consumption
Issue Date: 01/02/08
S1D13506
X25B-G-006-02
Page 4
Epson Research and Development
Vancouver Design Center
1.1 Conditions
Table 1-1: “S1D13506 Power Consumption” gives an example of a specific environment
and its effects on power consumption.
Table 1-1: S1D13506 Power Consumption
Test Condition
VDD = 3.3V, BUSCLK = 8MHz
1
CLKI = 6MHz
LCD Panel = 60Hz 320x240 4-bit Single Monochrome
2
CLKI = 6 MHz
LCD Panel = 60Hz 320x240 8-bit Single Color
3
CLKI = 25MHz
LCD Panel = 60Hz 640x480 8-bit Dual Monochrome
4
CLKI = 25MHz
LCD Panel = 60Hz 640x480 16-bit Dual Color
5
6
7
CLKI = 33.333MHz, CLKI2 = 25.175MHz
CRT = 60Hz 640x480 Color
CLKI = 33.333MHz, CLKI2 = 14.31818MHz
NTSC TV = 640x480 Color, S-Video output, no filter
CLKI = 33.333MHz, CLKI2 = 17.734475MHz
PAL TV = 640x480 Color, S-Video output, no filter
Color
Depth
S1D13506
Active
(mW)
4 bpp
21.22
4 bpp
23.30
8 bpp
24.98
16 bpp
26.73
4 bpp
70.75
4 bpp
91.74
8 bpp
96.89
16 bpp
99.03
4 bpp
224.86
8 bpp
233.44
16 bpp
242.68
4 bpp
359.83
8 bpp
365.11
16 bpp
372.04
4 bpp
364.78
8 bpp
369.07
16 bpp
374.02
Power Save Mode
Clocks
Active
(mW) 1
Clocks
Removed
(mW) 2
3.14
.13
3.14
.13
10.36
.13
10.40
.13
11.72
.13
10.00
.13
10.53
.13
Note
1. Conditions for software suspend with Clocks active:
• CPU interface inactive
• CLKI, CLKI2, BUSCLK active
• Self-Refresh DRAM
2. Conditions for software suspend with Clocks inactive:
• CPU interface inactive
• CLKI, CLKI2, BUSCLK stopped
• Self-Refresh DRAM
S1D13506
X25B-G-006-02
Power Consumption
Issue Date: 01/02/08
Epson Research and Development
Vancouver Design Center
Page 5
Summary
The system design variables in Section 1, “S1D13506 Power Consumption” and in Table
1-1: “S1D13506 Power Consumption” show that S1D13506 power consumption depends
on the specific implementation. Active Mode power consumption depends on the desired
CPU performance and LCD/CRT frame-rate, whereas power save mode consumption
depends on the CPU Interface and Input Clock state.
In a typical design environment, the S1D13506 can be configured to be an extremely
power-efficient LCD/CRT/TV Controller with high performance and flexibility.
Power Consumption
Issue Date: 01/02/08
S1D13506
X25B-G-006-02
Page 6
Epson Research and Development
Vancouver Design Center
THIS PAGE LEFT BLANK
S1D13506
X25B-G-006-02
Power Consumption
Issue Date: 01/02/08
S1D13506 Color LCD/CRT/TV Controller
Interfacing to the NEC
VR4102/VR4111™ Microprocessors
Document Number: X25B-G-007-02
Copyright © 2001 Epson Research and Development, Inc. All Rights Reserved.
Information in this document is subject to change without notice.You may download and use this document, but only for your own use in
evaluating Seiko Epson/EPSON products. You may not modify the document. Epson Research and Development, Inc. disclaims any
representation that the contents of this document are accurate or current. The Programs/Technologies described in this document may contain
material protected under U.S. and/or International Patent laws.
EPSON is a registered trademark of Seiko Epson Corporation. All other trademarks are the property of their respective owners.
Microsoft and Windows are registered trademarks of Microsoft Corporation.
Page 2
Epson Research and Development
Vancouver Design Center
THIS PAGE LEFT BLANK
S1D13506
X25B-G-007-02
Interfacing to the NEC VR4102/VR4111™ Microprocessors
Issue Date: 01/02/08
Epson Research and Development
Vancouver Design Center
Page 3
Table of Contents
1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2
Interfacing to the VR4102/VR4111 . . . . .
2.1 The NEC VR4102/VR4111 System Bus .
2.1.1 Overview . . . . . . . . . . . . . .
2.1.2 LCD Memory Access Cycles . . . .
3
S1D13506 Host Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.1 Host Bus Interface Pin Mapping . . . . . . . . . . . . . . . . . . . . . . . 10
3.2 Host Bus Interface Signal Descriptions . . . . . . . . . . . . . . . . . . . . 11
4
VR4102/VR4111 to S1D13506 Interface
4.1 Hardware Description . . . . . . .
4.2 S1D13506 Hardware Configuration . .
4.3 NEC VR4102/VR4111 Configuration .
5
Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
6
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
6.1 Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
6.2 Document Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
7
Technical Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
7.1 EPSON LCD/CRT Controllers (S1D13506) . . . . . . . . . . . . . . . . . . 16
7.2 NEC Electronics Inc. (VR4102/VR4111). . . . . . . . . . . . . . . . . . . . 16
Interfacing to the NEC VR4102/VR4111™ Microprocessors
Issue Date: 01/02/08
. .
.
.
.
. . . . . . .
. . . . . .
. . . . . . . .
. . . . . . . .
.
.
.
.
.
.
.
.
.
.
.
.
. . .
. .
. .
. .
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
. . . . . .
. . . . .
. . . . . . .
. . . . . . .
. . .
. .
. .
. .
.
.
.
.
.
.
.
.
.
.
.
.
. . .
. .
. . .
. . .
. . .
. .
. .
. .
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
. . . 8
. . .8
. . . .8
. . . .9
.
.
.
.
.
.
.
.
12
12
13
13
S1D13506
X25B-G-007-02
Page 4
Epson Research and Development
Vancouver Design Center
THIS PAGE LEFT BLANK
S1D13506
X25B-G-007-02
Interfacing to the NEC VR4102/VR4111™ Microprocessors
Issue Date: 01/02/08
Epson Research and Development
Vancouver Design Center
Page 5
List of Tables
Table 3-1: Host Bus Interface Pin Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 4-1: Summary of Power-On/Reset Options . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
List of Figures
Figure 2-1: NEC VR4102/VR4111 Read/Write Cycles . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 4-1: NEC VR4102/VR4111 to S1D13506 Configuration Schematic . . . . . . . . . . . . . . 12
Interfacing to the NEC VR4102/VR4111™ Microprocessors
Issue Date: 01/02/08
S1D13506
X25B-G-007-02
Page 6
Epson Research and Development
Vancouver Design Center
THIS PAGE LEFT BLANK
S1D13506
X25B-G-007-02
Interfacing to the NEC VR4102/VR4111™ Microprocessors
Issue Date: 01/02/08
Epson Research and Development
Vancouver Design Center
Page 7
1 Introduction
This application note describes the hardware and software environment necessary to
provide an interface between the S1D13506 Color LCD/CRT/TV Controller and the NEC
VR4102TM (µPD30102) or VR4111TM (µPD30111) Microprocessors.
The designs described in this document are presented only as examples of how such
interfaces might be implemented. This application note will be updated as appropriate.
Please check the Epson Electronics America Website at http://www.eea.epson.com for the
latest revision of this document before beginning any development.
We appreciate your comments on our documentation. Please contact us via email at
[email protected]
Interfacing to the NEC VR4102/VR4111™ Microprocessors
Issue Date: 01/02/08
S1D13506
X25B-G-007-02
Page 8
Epson Research and Development
Vancouver Design Center
2 Interfacing to the VR4102/VR4111
2.1 The NEC VR4102/VR4111 System Bus
The VR-Series family of microprocessors features a high-speed synchronous system bus
typical of modern microprocessors. Designed with external LCD controller support and
Windows CE based embedded consumer applications in mind, the VR4102/VR4111 offers
a highly integrated solution for portable systems. This section provides an overview of the
operation of the CPU bus in order to establish interface requirements.
2.1.1 Overview
The NEC VR4102/VR4111 is designed around the RISC architecture developed by MIPS.
This microprocessor is based on the 66MHz VR4100 CPU core which supports 64-bit
processing. The CPU communicates with the Bus Control Unit (BCU) using its internal
SysAD bus. The BCU in turn communicates with external devices using its ADD and DAT
buses which can be dynamically sized for 16 or 32-bit operation.
The NEC VR4102/VR4111 has direct support for an external LCD controller. Specific
control signals are assigned for an external LCD controller providing an easy interface to
the CPU. A 16M byte block of memory is assigned for the LCD controller and its own chip
select and ready signals are available. Word or byte accesses are controlled by the system
high byte signal (SHB#).
S1D13506
X25B-G-007-02
Interfacing to the NEC VR4102/VR4111™ Microprocessors
Issue Date: 01/02/08
Epson Research and Development
Vancouver Design Center
Page 9
2.1.2 LCD Memory Access Cycles
Once an address in the LCD block of memory is placed on the external address bus
(ADD[25:0]), the LCD chip select (LCDCS#) is driven low. The read or write enable
signals (RD# or WR#) are driven low for the appropriate cycle and LCDRDY is driven low
to insert wait states into the cycle. The high byte enable (SHB#) in conjunction with address
bit 0 allows for byte steering.
The following figure illustrates typical NEC VR4102/VR4111 memory read and write
cycles to the LCD controller interface.
TCLK
ADD[25:0]
VALID
SHB#
LCDCS#
WR#,RD#
D[15:0]
(write)
D[15:0]
(read)
VALID
Hi-Z
VALID
Hi-Z
LCDRDY
Figure 2-1: NEC VR4102/VR4111 Read/Write Cycles
Interfacing to the NEC VR4102/VR4111™ Microprocessors
Issue Date: 01/02/08
S1D13506
X25B-G-007-02
Page 10
Epson Research and Development
Vancouver Design Center
3 S1D13506 Host Bus Interface
The S1D13506 directly supports multiple processors. The S1D13506 implements a 16-bit
MIPS/ISA Host Bus Interface which is most suitable for direct connection to the
VR4102/VR4111 microprocessor.
The MIPS/ISA Host Bus Interface is selected by the S1D13506 on the rising edge of
RESET#. After releasing reset the bus interface signals assume their selected configuration.
For details on S1D13506 configuration, see Section 4.2, “S1D13506 Hardware Configuration” on page 13.
Note
At reset, the Register/Memory Select bit in the Miscellaneous Register (REG[001h] bit
7) is set to 1. This means that only REG[000h] (read-only) and REG[001h] are
accessible until a write to REG[001h] sets bit 7 to 0 making all registers accessible.
When debugging a new hardware design, this can sometimes give the appearance that
the interface is not working, so it is important to remember to clear this bit before
proceeding with debugging.
3.1 Host Bus Interface Pin Mapping
The following table shows the functions of each Host Bus Interface signal.
Table 3-1: Host Bus Interface Pin Mapping
S1D13506 Pin Name
AB20
AB[19:0]
DB[15:0]
WE1#
M/R#
CS#
BUSCLK
BS#
RD/WR#
RD#
WE0#
WAIT#
RESET#
S1D13506
X25B-G-007-02
NEC VR4102/VR4111 Pin Name
ADD20
ADD[19:0]
DAT[15:0]
SHB#
ADD21
LCDCS#
BUSCLK
VDD
VDD
RD#
WR#
LCDRDY
connected to system reset
Interfacing to the NEC VR4102/VR4111™ Microprocessors
Issue Date: 01/02/08
Epson Research and Development
Vancouver Design Center
Page 11
3.2 Host Bus Interface Signal Descriptions
The S1D13506 MIPS/ISA Host Bus Interface requires the following signals.
• BUSCLK is a clock input which is required by the S1D13506 Host Bus Interface. It is
separate from the input clock (CLKI) and is typically driven by the host CPU system
clock.
• The address inputs AB[20:0], and the data bus DB[15:0], connect directly to the
VR4102/VR4111 address (ADD[20:0]) and data bus (DAT[15:0]), respectively. MD4
must be set to select the proper endian mode upon reset.
• M/R# (memory/register) selects between memory or register access. It may be
connected to an address line, allowing system address ADD21 to be connected to the
M/R# line.
• Chip Select (CS#) must be driven low by LCDCS# whenever the S1D13506 is accessed
by the VR4102/VR4111.
• WE1# connects to SHB# (the high byte enable signal from the VR4102/VR4111) which
in conjunction with address bit 0 allows byte steering of read and write operations.
• WE0# connects to WR# (the write enable signal from the VR4102/VR4111) and must
be driven low when the VR4102/VR4111 is writing data to the S1D13506.
• RD# connects to RD# (the read enable signal from the VR4102/VR4111) and must be
driven low when the VR4102/VR4111 is reading data from the S1D13506.
• WAIT# connects to LCDRDY and is a signal output from the S1D13506 that indicates
the VR4102/VR4111 must wait until data is ready (read cycle) or accepted (write cycle)
on the host bus. Since VR4102/VR4111 accesses to the S1D13506 may occur asynchronously to the display update, it is possible that contention may occur in accessing the
S1D13506 internal registers and/or display buffer. The WAIT# line resolves these
contentions by forcing the host to wait until the resource arbitration is complete.
• The BS# and RD/WR# signals are not used for the MIPS/ISA Host Bus Interface and
should be tied high (connected to VDD).
Interfacing to the NEC VR4102/VR4111™ Microprocessors
Issue Date: 01/02/08
S1D13506
X25B-G-007-02
Page 12
Epson Research and Development
Vancouver Design Center
4 VR4102/VR4111 to S1D13506 Interface
4.1 Hardware Description
The NEC VR4102/VR4111 Microprocessors are specifically designed to support an external
LCD controller. They provide the necessary internal address decoding and control signals.
The diagram below shows a typical implementation utilizing the S1D13506.
NEC VR4102/VR4111
S1D13506
WR#
WE0#
SHB#
WE1#
RD#
RD#
LCDCS#
CS#
Pull-up
LCDRDY
WAIT#
System RESET
RESET#
ADD21
M/R#
ADD[25:0]
AB[20:0]
DAT[15:0]
DB[15:0]
BUSCLK
BUSCLK
VDD
VDD
BS#
RD/WR#
Note:
When connecting the S1D13506 RESET# pin, the system designer should be aware of all
conditions that may reset the S1D13506 (e.g. CPU reset can be asserted during wake-up
from power-down modes, or during debug states).
Figure 4-1: NEC VR4102/VR4111 to S1D13506 Configuration Schematic
Note
For pin mapping see Table 3-1:, “Host Bus Interface Pin Mapping,” on page 10.
S1D13506
X25B-G-007-02
Interfacing to the NEC VR4102/VR4111™ Microprocessors
Issue Date: 01/02/08
Epson Research and Development
Vancouver Design Center
Page 13
4.2 S1D13506 Hardware Configuration
The S1D13506 latches MD15 through MD0 to allow selection of the bus mode and other
configuration data on the rising edge of RESET#. For details on configuration, refer to the
S1D13506 Hardware Functional Specification, document number X25B-A-001-xx.
The table below shows those configuration settings important to the NEC VR4102/VR4111
CPU interface.
Table 4-1: Summary of Power-On/Reset Options
MD[3:1]
MD4
MD5
value on this pin at rising edge of RESET# is used to configure:(1/0)
1
0
101 = MIPS/ISA Host Bus Interface
Little Endian
Big Endian
WAIT# is active high (1 = insert wait state)
WAIT# is active low (0 = insert wait state)
MD11
Alternate Host Bus Interface Selected
Primary Host Bus Interface Selected
MD12
BUSCLK input divided by two
BUSCLK input not divided
MD15
WAIT# is always driven
WAIT# is floating if S1D13506 is not selected
S1D13506
Pin Name
= configuration for NEC VR4102/VR4111 microprocessor
4.3 NEC VR4102/VR4111 Configuration
NEC VR4102/VR4111The NEC VR4102/VR4111 provides the internal address decoding
necessary to map an external LCD controller. Physical address 0A00 0000h to 0AFF
FFFFh (16M bytes) is reserved for an external LCD controller.
The S1D13506 supports up to 2M bytes of display buffer. The NEC VR4102/VR4111
address line A21 is used to select between the S1D13506 display buffer (A21=1) and
internal registers (A21=0).
The NEC VR4102/VR4111 has a 16-bit internal register named BCUCNTREG2 located at
address 0B00 0002h. It must be set to the value of 0001h to indicate that LCD controller
accesses using a non-inverting data bus.
Interfacing to the NEC VR4102/VR4111™ Microprocessors
Issue Date: 01/02/08
S1D13506
X25B-G-007-02
Page 14
Epson Research and Development
Vancouver Design Center
5 Software
Test utilities and Windows® CE v2.0 display drivers are available for the S1D13506. Full
source code is available for both the test utilities and the drivers.
The test utilities are configurable for different panel types using a program called
13506CFG, or by directly modifying the source. The Windows CE v2.0 display drivers can
be customized by the OEM for different panel types, resolutions and color depths only by
modifying the source.
The S1D13506 test utilities and Windows CE v2.0 display drivers are available from your
sales support contact or on the internet at http://www.eea.epson.com.
S1D13506
X25B-G-007-02
Interfacing to the NEC VR4102/VR4111™ Microprocessors
Issue Date: 01/02/08
Epson Research and Development
Vancouver Design Center
Page 15
6 References
6.1 Documents
• NEC Electronics Inc., VR4102 Preliminary Users Manual, Document Number
U12739EJ2V0UM00.
• NEC Electronics Inc., VR4111 Preliminary Users Manual, Document Number
U13137EJ2V0UM00.
• Epson Research and Development, Inc., S1D13506 Hardware Functional Specification,
Document Number X25B-A-001-xx.
• Epson Research and Development, Inc., S5U13506B00C Rev. 1.0 ISA Bus Evaluation
Board User Manual, Document Number X25B-G-004-xx.
• Epson Research and Development, Inc., S1D13506 Programming Notes and Examples,
Document Number X25B-G-003-xx.
6.2 Document Sources
• NEC Electronics Website: http://www.necel.com.
• Epson Electronics America Website: http://www.eea.epson.com.
Interfacing to the NEC VR4102/VR4111™ Microprocessors
Issue Date: 01/02/08
S1D13506
X25B-G-007-02
Page 16
Epson Research and Development
Vancouver Design Center
7 Technical Support
7.1 EPSON LCD/CRT Controllers (S1D13506)
Japan
Seiko Epson Corporation
Electronic Devices Marketing Division
421-8, Hino, Hino-shi
Tokyo 191-8501, Japan
Tel: 042-587-5812
Fax: 042-587-5564
http://www.epson.co.jp
Hong Kong
Epson Hong Kong Ltd.
20/F., Harbour Centre
25 Harbour Road
Wanchai, Hong Kong
Tel: 2585-4600
Fax: 2827-4346
North America
Epson Electronics America, Inc.
150 River Oaks Parkway
San Jose, CA 95134, USA
Tel: (408) 922-0200
Fax: (408) 922-0238
http://www.eea.epson.com
Taiwan, R.O.C.
Epson Taiwan Technology
& Trading Ltd.
10F, No. 287
Nanking East Road
Sec. 3, Taipei, Taiwan, R.O.C.
Tel: 02-2717-7360
Fax: 02-2712-9164
Europe
Epson Europe Electronics GmbH
Riesstrasse 15
80992 Munich, Germany
Tel: 089-14005-0
Fax: 089-14005-110
Singapore
Epson Singapore Pte., Ltd.
No. 1
Temasek Avenue #36-00
Millenia Tower
Singapore, 039192
Tel: 337-7911
Fax: 334-2716
7.2 NEC Electronics Inc. (VR4102/VR4111).
NEC Electronics Inc. (U.S.A.)
Corporate Headquarters
2880 Scott Blvd.
Santa Clara, CA 95050-8062, USA
Tel: (800) 366-9782
Fax: (800) 729-9288
http://www.nec.com
S1D13506
X25B-G-007-02
Interfacing to the NEC VR4102/VR4111™ Microprocessors
Issue Date: 01/02/08
S1D13506 Color LCD/CRT/TV Controller
Interfacing to the Motorola MPC821
Microprocessor
Document Number: X25B-G-008-03
Copyright © 1999, 2001 Epson Research and Development, Inc. All Rights Reserved.
Information in this document is subject to change without notice.You may download and use this document, but only for your own use in
evaluating Seiko Epson/EPSON products. You may not modify the document. Epson Research and Development, Inc. disclaims any
representation that the contents of this document are accurate or current. The Programs/Technologies described in this document may contain
material protected under U.S. and/or International Patent laws.
EPSON is a registered trademark of Seiko Epson Corporation. All other trademarks are the property of their respective owners.
Page 2
Epson Research and Development
Vancouver Design Center
THIS PAGE LEFT BLANK
S1D13506
X25B-G-008-03
Interfacing to the Motorola MPC821 Microprocessor
Issue Date: 01/02/08
Epson Research and Development
Vancouver Design Center
Page 3
Table of Contents
1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2
Interfacing to the MPC821 . . . . . . . . . . . . . . . .
2.1 The MPC8xx System Bus . . . . . . . . . . . . .
2.2 MPC821 Bus Overview . . . . . . . . . . . . .
2.2.1 Normal (Non-Burst) Bus Transactions . . . . . . .
2.2.2 Burst Cycles . . . . . . . . . . . . . . . . . . . . .
2.3 Memory Controller Module . . . . . . . . . . . .
2.3.1 General-Purpose Chip Select Module (GPCM) . . .
2.3.2 User-Programmable Machine (UPM) . . . . . . . .
3
S1D13506 Host Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.1 PowerPC Host Bus Interface Pin Mapping . . . . . . . . . . . . . . . . . . . 13
3.2 PowerPC Host Bus Interface Signals . . . . . . . . . . . . . . . . . . . . . 14
4
MPC821 to S1D13506 Interface . .
4.1 Hardware Description . . . . .
4.2 Hardware Connections . . . . .
4.3 S1D13506 Hardware Configuration
4.4 Register/Memory Mapping . . .
4.5 MPC821 Chip Select Configuration
4.6 Test Software . . . . . . . .
5
Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
6
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
6.1 Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
6.2 Document Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
7
Technical Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
7.1 EPSON LCD/CRT Controllers (S1D13506) . . . . . . . . . . . . . . . . . . 23
7.2 Motorola MPC821 Processor . . . . . . . . . . . . . . . . . . . . . . . . 23
Interfacing to the Motorola MPC821 Microprocessor
Issue Date: 01/02/08
.
.
.
.
.
.
.
. . .
. .
. .
. .
. .
. .
. .
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
. . .
. .
. .
. .
. .
. .
. .
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
. . . . . . . . . .
. . . . . . . .
. . . . . . . .
. . . . . . . . . . .
. . . . . . . . . . .
. . . . . . . .
. . . . . . . . . . .
. . . . . . . . . . .
.
.
.
.
.
.
.
. . .
. .
. .
. .
. .
. .
. .
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
. . .
. .
. .
. .
. .
. .
. .
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
. . . 8
. . .8
. . .8
. . . .9
. . . 10
. . 11
. . . 11
. . . 12
.
.
.
.
.
.
.
. 15
. 15
. 16
. 18
. 18
. 19
. 20
S1D13506
X25B-G-008-03
Page 4
Epson Research and Development
Vancouver Design Center
THIS PAGE LEFT BLANK
S1D13506
X25B-G-008-03
Interfacing to the Motorola MPC821 Microprocessor
Issue Date: 01/02/08
Epson Research and Development
Vancouver Design Center
Page 5
List of Tables
Table 3-1: PowerPC Host Bus Interface Pin Mapping . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 4-1: List of Connections from MPC821ADS to S1D13506 . . . . . . . . . . . . . . . . . . 16
Table 4-2: Summary of Power-On/Reset Options . . . . . . . . . . . . . . . . . . . . . . . . . . 18
List of Figures
Figure 2-1: Power PC Memory Read Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 2-2: Power PC Memory Write Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 4-1: Typical Implementation of MPC821 to S1D13506 Interface . . . . . . . . . . . . . . . 15
Interfacing to the Motorola MPC821 Microprocessor
Issue Date: 01/02/08
S1D13506
X25B-G-008-03
Page 6
Epson Research and Development
Vancouver Design Center
THIS PAGE LEFT BLANK
S1D13506
X25B-G-008-03
Interfacing to the Motorola MPC821 Microprocessor
Issue Date: 01/02/08
Epson Research and Development
Vancouver Design Center
Page 7
1 Introduction
This application note describes the hardware and software environment required to provide
an interface between the S1D13506 Color LCD/CRT/TV Controller and the Motorola
MPC821 processor.
The designs described in this document are presented only as examples of how such
interfaces might be implemented. This application note will be updated as appropriate.
Please check the Epson Electronics America Website at http://www.eea.epson.com for the
latest revision of this document before beginning any development.
We appreciate your comments on our documentation. Please contact us via email at
[email protected]
Interfacing to the Motorola MPC821 Microprocessor
Issue Date: 01/02/08
S1D13506
X25B-G-008-03
Page 8
Epson Research and Development
Vancouver Design Center
2 Interfacing to the MPC821
2.1 The MPC8xx System Bus
The MPC8xx family of processors feature a high-speed synchronous system bus typical of
modern RISC microprocessors. This section provides an overview of the operation of the
CPU bus in order to establish interface requirements.
2.2 MPC821 Bus Overview
The MPC8xx microprocessor family uses a synchronous address and data bus. All IO is
synchronous to a square-wave reference clock called MCLK (Master Clock). This clock
runs at the machine cycle speed of the CPU core (typically 25 to 50 MHz). Most outputs
from the processor change state on the rising edge of this clock. Similarly, most inputs to
the processor are sampled on the rising edge.
Note
The external bus can run at one-half the CPU core speed using the clock control register.
This is typically used when the CPU core is operated above 50 MHz.
The MPC821 can generate up to eight independent chip select outputs, each of which may
be controlled by one of two types of timing generators: the General Purpose Chip Select
Module (GPCM) or the User-Programmable Machine (UPM). Examples are given using
the GPCM.
It should be noted that all Power PC microprocessors, including the MPC8xx family, use
bit notation opposite from the convention used by most other microprocessor systems. Bit
numbering for the MPC8xx always starts with zero as the most significant bit, and increments in value to the least-significant bit. For example, the most significant bits of the
address bus and data bus are A0 and D0, while the least significant bits are A31 and D31.
The MPC8xx uses both a 32-bit address and data bus. A parity bit is supported for each of
the four byte lanes on the data bus. Parity checking is done when data is read from external
memory or peripherals, and generated by the MPC8xx bus controller on write cycles. All
IO accesses are memory-mapped meaning there is no separate IO space in the Power PC
architecture.
Support is provided for both on-chip (DMA controllers) and off-chip (other processors and
peripheral controllers) bus masters. For further information on this topic, refer to Section
6, “References” on page 22.
The bus can support both normal and burst cycles. Burst memory cycles are used to fill
on-chip cache memory, and for certain on-chip DMA operations. Normal cycles are used
for all other data transfers.
S1D13506
X25B-G-008-03
Interfacing to the Motorola MPC821 Microprocessor
Issue Date: 01/02/08
Epson Research and Development
Vancouver Design Center
Page 9
2.2.1 Normal (Non-Burst) Bus Transactions
A data transfer is initiated by the bus master by placing the memory address on address
lines A0 through A31 and driving TS (Transfer Start) low for one clock cycle. Several
control signals are also provided with the memory address:
• TSIZ[0:1] (Transfer Size) -- indicates whether the bus cycle is 8, 16, or 32-bit.
• RD/WR -- set high for read cycles and low for write cycles.
• AT[0:3] (Address Type Signals) -- provides more detail on the type of transfer being
attempted.
When the peripheral device being accessed has completed the bus transfer, it asserts TA
(Transfer Acknowledge) for one clock cycle to complete the bus transaction. Once TA has
been asserted, the MPC821 will not start another bus cycle until TA has been de-asserted.
The minimum length of a bus transaction is two bus clocks.
Figure 2-1: “Power PC Memory Read Cycle” on page 9 illustrates a typical memory read
cycle on the Power PC system bus.
SYSCLK
TS
TA
A[0:31]
RD/WR
TSIZ[0:1], AT[0:3]
Sampled when TA low
D[0:31]
Transfer Start
Wait States
Transfer
Complete
Next Transfer
Starts
Figure 2-1: Power PC Memory Read Cycle
Interfacing to the Motorola MPC821 Microprocessor
Issue Date: 01/02/08
S1D13506
X25B-G-008-03
Page 10
Epson Research and Development
Vancouver Design Center
Figure 2-2: “Power PC Memory Write Cycle” on page 10 illustrates a typical memory
write cycle on the Power PC system bus.
SYSCLK
TS
TA
A[0:31]
RD/WR
TSIZ[0:1], AT[0:3]
D[0:31]
Transfer Start
Valid
Wait States
Transfer
Complete
Next Transfer
Starts
Figure 2-2: Power PC Memory Write Cycle
If an error occurs, TEA (Transfer Error Acknowledge) is asserted and the bus cycle is
aborted. For example, a peripheral device may assert TEA if a parity error is detected, or
the MPC821 bus controller may assert TEA if no peripheral device responds at the
addressed memory location within a bus time-out period.
For 32-bit transfers, all data lines (D[0:31]) are used and the two low-order address lines
A30 and A31 are ignored. For 16-bit transfers, data lines D[0:15] are used and address line
A31 is ignored. For 8-bit transfers, data lines D[0:7] are used and all address lines (A[0:31])
are used.
Note
This assumes that the Power PC core is operating in big endian mode (typically the case
for embedded systems).
2.2.2 Burst Cycles
Burst memory cycles are used to fill on-chip cache memory and to carry out certain on-chip
DMA operations. They are very similar to normal bus cycles with the following exceptions:
• Always 32-bit.
• Always attempt to transfer four 32-bit words sequentially.
• Always address longword-aligned memory (i.e. A30 and A31 are always 0:0).
• Do not increment address bits A28 and A29 between successive transfers; the addressed
device must increment these address bits internally.
S1D13506
X25B-G-008-03
Interfacing to the Motorola MPC821 Microprocessor
Issue Date: 01/02/08
Epson Research and Development
Vancouver Design Center
Page 11
If a peripheral is not capable of supporting burst cycles, it can assert Burst Inhibit (BI)
simultaneously with TA, and the processor will revert to normal bus cycles for the
remaining data transfers.
Burst cycles are mainly intended to facilitate cache line fills from program or data memory.
They are normally not used for transfers to/from IO peripheral devices such as the
S1D13506, therefore the interfaces described in this document do not attempt to support
burst cycles. However, the example interfaces include circuitry to detect the assertion of
BDIP and respond with BI if caching is accidently enabled for the S1D13506 address space.
2.3 Memory Controller Module
2.3.1 General-Purpose Chip Select Module (GPCM)
The General-Purpose Chip Select Module (GPCM) is used to control memory and
peripheral devices which do not require special timing or address multiplexing. In addition
to the chip select output, it can generate active-low Output Enable (OE) and Write Enable
(WE) signals compatible with most memory and x86-style peripherals. The MPC821 bus
controller also provides a Read/Write (RD/WR) signal which is compatible with most 68K
peripherals.
The GPCM is controlled by the values programmed into the Base Register (BR) and Option
Register (OR) of the respective chip select. The Option Register sets the base address, the
block size of the chip select, and controls the following timing parameters:
• The ACS bit field allows the chip select assertion to be delayed by 0, ¼, or ½ clock
cycle with respect to the address bus valid.
• The CSNT bit causes chip select and WE to be negated ½ clock cycle earlier than
normal.
• The TRLX (relaxed timing) bit will insert an additional one clock delay between
assertion of the address bus and chip select. This accommodates memory and
peripherals with long setup times.
• The EHTR (Extended hold time) bit will insert an additional 1 clock delay on the first
access to a chip select.
• Up to 15 wait states may be inserted, or the peripheral can terminate the bus cycle itself
by asserting TA (Transfer Acknowledge).
• Any chip select may be programmed to assert BI (Burst Inhibit) automatically when its
memory space is addressed by the processor core.
Interfacing to the Motorola MPC821 Microprocessor
Issue Date: 01/02/08
S1D13506
X25B-G-008-03
Page 12
Epson Research and Development
Vancouver Design Center
2.3.2 User-Programmable Machine (UPM)
The UPM is typically used to control memory types, such as Dynamic RAMs, which have
complex control or address multiplexing requirements. The UPM is a general purpose
RAM-based pattern generator which can control address multiplexing, wait state generation, and five general-purpose output lines on the MPC821. Up to 64 pattern locations are
available, each 32 bits wide. Separate patterns may be programmed for normal accesses,
burst accesses, refresh (timer) events, and exception conditions. This flexibility allows
almost any type of memory or peripheral device to be accommodated by the MPC821.
In this application note, the GPCM is used instead of the UPM, since the GPCM has enough
flexibility to accommodate the S1D13506 and it is desirable to leave the UPM free to
handle other interfacing duties, such as EDO DRAM.
S1D13506
X25B-G-008-03
Interfacing to the Motorola MPC821 Microprocessor
Issue Date: 01/02/08
Epson Research and Development
Vancouver Design Center
Page 13
3 S1D13506 Host Bus Interface
The S1D13506 implements a 16-bit native PowerPC host bus interface which is used to
interface to the MPC821 microprocessor.
The PowerPC host bus interface is selected by the S1D13506 on the rising edge of
RESET#. After releasing reset the bus interface signals assume their selected configuration.
For details on S1D13506 configuration, see Section 4.3, “S1D13506 Hardware Configuration” on page 18.
Note
At reset, the Register/Memory Select bit in the Miscellaneous Register (REG[001h] bit
7) is set to 1. This means that only REG[000h] (read-only) and REG[001h] are
accessible until a write to REG[001h] sets bit 7 to 0 making all registers accessible.
When debugging a new hardware design, this can sometimes give the appearance that
the interface is not working, so it is important to remember to clear this bit before
proceeding with debugging.
3.1 PowerPC Host Bus Interface Pin Mapping
The following table shows the functions of each host bus interface signal.
Table 3-1: PowerPC Host Bus Interface Pin Mapping
S1D13506 Pin Names
PowerPC
AB[20:0]
A[11:31]
DB[15:0]
D[0:15]
WE1#
BI
M/R#
External Decode
CS#
External Decode
BUSCLK
CLKOUT
BS#
TS
RD/WR#
RD/WR
RD#
TSIZ0
WE0#
TSIZ1
WAIT#
TA
RESET#
RESET#
Interfacing to the Motorola MPC821 Microprocessor
Issue Date: 01/02/08
S1D13506
X25B-G-008-03
Page 14
Epson Research and Development
Vancouver Design Center
3.2 PowerPC Host Bus Interface Signals
The S1D13506 PowerPC host bus interface is designed to support processors which
interface the S1D13506 through the PowerPC bus.
The S1D13506 PowerPC host bus interface requires the following signals:
• BUSCLK is a clock input which is required by the S1D13506 host bus interface. It is
separate from the input clock (CLKI) and is typically driven by the host CPU system
clock.
• The address inputs AB[20:0], and the data bus DB[15:0], connect directly to the
PowerPC bus address (A[11:31]) and data bus (D[0:15]), respectively. MD4 must be set
to select the proper endian mode upon reset.
• M/R# (memory/register) selects between memory or register access. It may be
connected to an address line, allowing system address A10 to be connected to the M/R#
line.
• Chip Select (CS#) must be driven low whenever the S1D13506 is accessed by the
PowerPC bus.
• RD/WR# connects to RD/WR which indicates whether a read or a write access is being
performed on the S1D13506.
• WE1# connects to BI (burst inhibit signal). WE1# is output by the S1D13506 to indicate
whether the S1D13506 is able to perform burst accesses.
• WE0# and RD# connect to TSIZ1 and TSIZ0 (high and low byte enable signals). These
signals must be driven by the PowerPC bus to indicate the size of the transfer taking
place on the bus.
• WAIT# connects to TA and is output from the S1D13506 to indicate the PowerPC bus
must wait until data is ready (read cycle) or accepted (write cycle) on the host bus. Since
PowerPC bus accesses to the S1D13506 may occur asynchronously to the display
update, it is possible that contention may occur while accessing the S1D13506 internal
registers and/or display buffer. The WAIT# line resolves these contentions by forcing
the host to wait until resource arbitration is complete.
• The Bus Start (BS#) signal connects to TS (the transfer start signal).
S1D13506
X25B-G-008-03
Interfacing to the Motorola MPC821 Microprocessor
Issue Date: 01/02/08
Epson Research and Development
Vancouver Design Center
Page 15
4 MPC821 to S1D13506 Interface
4.1 Hardware Description
The S1D13506 provides native Power PC bus support, making it very simple to interface
the two devices. This application note describes the environment necessary to connect the
S1D13506 to the MPC821 native system bus and the connections between the
S5U13506B00B Evaluation Board and the Motorola MPC821 Application Development
System (ADS).
The S1D13506, by implementing a dedicated display buffer, can reduce system power
consumption, improve image quality, and increase system performance as compared to the
MPC821’s on-chip LCD controller.
The S1D13506, through the use of the MPC821 chip selects, can share the system bus with
all other MPC821 peripherals. The following figure demonstrates a typical implementation
of the S1D13506 to MPC821 interface.
S1D13506
MPC821
M/R#
A10
A[11:31]
AB[20:0]
D[0:15]
DB[15:0]
CS4
CS#
TS
BS#
TA
WAIT#
RD/WR
RD/WR#
TSIZ0
RD#
TSIZ1
WE0#
BI
WE1#
BUSCLK
SYSCLK
System RESET
Note:
RESET#
When connecting the S1D13506 RESET# pin, the system designer should be aware of all
conditions that may reset the S1D13506 (e.g. CPU reset can be asserted during wake-up
from power-down modes, or during debug states).
Figure 4-1: Typical Implementation of MPC821 to S1D13506 Interface
Interfacing to the Motorola MPC821 Microprocessor
Issue Date: 01/02/08
S1D13506
X25B-G-008-03
Page 16
Epson Research and Development
Vancouver Design Center
Table 4-1:,“List of Connections from MPC821ADS to S1D13506” on page 16 shows the
connections between the pins and signals of the MPC821 and the S1D13506.
Note
The interface was designed using a Motorola MPC821 Application Development
System (ADS). The ADS board has 5 volt logic connected to the data bus, so the
interface included two 74F245 octal buffers on D[0:15] between the ADS and the
S1D13506. In a true 3 volt system, no buffering is necessary.
4.2 Hardware Connections
The following table details the connections between the pins and signals of the MPC821
and the S1D13506.
Table 4-1: List of Connections from MPC821ADS to S1D13506
MPC821 Signal Name
Vcc
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
D0
D1
D2
D3
D4
D5
D6
D7
S1D13506
X25B-G-008-03
MPC821ADS Connector and Pin Name
P6-A1, P6-B1
P6-C23
P6-A22
P6-B22
P6-C21
P6-C20
P6-D20
P6-B24
P6-C24
P6-D23
P6-D22
P6-D19
P6-A19
P6-D28
P6-A28
P6-C27
P6-A26
P6-C26
P6-A25
P6-D26
P6-B25
P6-B19
P6-D17
P12-A9
P12-C9
P12-D9
P12-A8
P12-B8
P12-D8
P12-B7
P12-C7
S1D13506 Signal Name
Vcc
M/R#
AB20
AB19
AB18
AB17
AB16
AB15
AB14
AB13
AB12
AB11
AB10
AB9
AB8
AB7
AB6
AB5
AB4
AB3
AB2
AB1
AB0
DB15
DB14
DB13
DB12
DB11
DB10
DB9
DB8
Interfacing to the Motorola MPC821 Microprocessor
Issue Date: 01/02/08
Epson Research and Development
Vancouver Design Center
Page 17
Table 4-1: List of Connections from MPC821ADS to S1D13506 (Continued)
MPC821 Signal Name
D8
D9
D10
D11
D12
D13
D14
D15
SRESET
SYSCLK
CS4
TS
TA
R/W
TSIZ0
TSIZ1
BI
Gnd
MPC821ADS Connector and Pin Name
P12-A15
P12-C15
P12-D15
P12-A14
P12-B14
P12-D14
P12-B13
P12-C13
P9-D15
P9-C2
P6-D13
P6-B7
P6-B6
P6-D8
P6-B18
P6-C18
P6-B9
P12-A1, P12-B1, P12-A2, P12-B2,
P12-A3, P12-B3, P12-A4, P12-B4,
P12-A5, P12-B5, P12-A6, P12-B6,
P12-A7
S1D13506 Signal Name
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
RESET#
BUSCLK
CS#
BS#
WAIT#
RD/WR#
RD#
WE0#
WE1#
Vss
Note
Note that the bit numbering of the Power PC bus signals is reversed. e.g. the most
significant address bit is A0, the next is A1, A2, etc.
Interfacing to the Motorola MPC821 Microprocessor
Issue Date: 01/02/08
S1D13506
X25B-G-008-03
Page 18
Epson Research and Development
Vancouver Design Center
4.3 S1D13506 Hardware Configuration
The S1D13506 latches MD15 through MD0 to allow selection of the bus mode and other
configuration data on the rising edge of RESET#. For details on configuration, refer to the
S1D13506 Hardware Functional Specification, document number X25B-A-001-xx.
The following table shows those configuration settings important to the MPC821 host bus
interface.
Table 4-2: Summary of Power-On/Reset Options
S1D13506
Pin Name
MD[3:1]
MD4
MD5
value on this pin at rising edge of RESET# is used to configure: (1/0)
1
0
110 = PowerPC host bus interface selected
Little Endian
Big Endian
Wait# signal is active high
Wait# signal is active low
MD9
Reserved
Configure SUSPEND# pin as Hardware Suspend
Enable
MD11
MD12
Alternate Host Bus Interface Selected
BUSCLK input divided by two
Primary Host Bus Interface Selected
BUSCLK input not divided
MD15
WAIT# is always driven
WAIT# is floating if S1D13506 is not selected
= required settings for MPC821 support.
4.4 Register/Memory Mapping
The DRAM on the MPC821 ADS board extends from address 0 through 3F FFFFh, so the
S1D13506 is addressed starting at 40 0000h. A total of 4M bytes of address space is used,
where the lower 2M bytes is reserved for the S1D13506 on-chip registers and the upper 2M
bytes is used to access the S1D13506 display buffer.
S1D13506
X25B-G-008-03
Interfacing to the Motorola MPC821 Microprocessor
Issue Date: 01/02/08
Epson Research and Development
Vancouver Design Center
Page 19
4.5 MPC821 Chip Select Configuration
Chip select 4 is used to control the S1D13506. The following options are selected in the
base address register (BR4):
• BA[0:16] = 0000 0000 0100 0000 0 – set starting address of S1D13506 to 40 0000h.
• AT[0:2] = 0 – ignore address type bits.
• PS[0:1] = 1:0 – memory port size is 16-bit.
• PARE = 0 – disable parity checking.
• WP = 0 – disable write protect.
• MS[0:1] = 0:0 – select General Purpose Chip Select module to control this chip select.
• V = 1 – set valid bit to enable chip select.
The following options were selected in the option register (OR4):
• AM[0:16] = 1111 1111 1100 0000 0 – mask all but upper 10 address bits; S1D13506
consumes 4M byte of address space.
• ATM[0:2] = 0 – ignore address type bits.
• CSNT = 0 – normal CS/WE negation.
• ACS[0:1] = 1:1 – delay CS assertion by ½ clock cycle from address lines.
• BI = 0 – do not assert Burst Inhibit.
• SCY[0:3] = 0 – wait state selection; this field is ignored since external transfer acknowledge is used; see SETA below.
• SETA = 1 – the S1D13506 generates an external transfer acknowledge using the
WAIT# line.
• TRLX = 0 – normal timing.
• EHTR = 0 – normal timing.
Interfacing to the Motorola MPC821 Microprocessor
Issue Date: 01/02/08
S1D13506
X25B-G-008-03
Page 20
Epson Research and Development
Vancouver Design Center
4.6 Test Software
The test software is very simple. It configures chip select 4 (CS4) on the MPC821 to map
the S1D13506 to an unused 4M byte block of address space. Next, it loads the appropriate
values into the option register for CS4 and writes the value 0 to the S1D13506 register
REG[001h] to enable full S1D13506 memory/register decoding. Lastly, the software runs
a tight loop that reads the S1D13506 Revision Code Register REG[000h]. This allows
monitoring of the bus timing on a logic analyzer.
The following source code was entered into the memory of the MPC821ADS using the
line-by-line assembler in MPC8BUG (the debugger provided with the ADS board). Once
the program was executed on the ADS, a logic analyzer was used to verify operation of the
interface hardware.
It is important to note that when the MPC821 comes out of reset, the on-chip caches and
MMU are disabled. If the data cache is enabled, then the MMU must be set so that the
S1D13506 memory block is tagged as non-cacheable. This ensures the MPC821 does not
attempt to cache any data read from, or written to, the S1D13506 or its display buffer.
BR4
OR4
MemStart
DisableReg
RevCodeReg
equ
equ
equ
equ
equ
$120
$124
$40
$1
$0
Start
mfspr
andis.
andis.
oris
ori
stw
andis.
oris
ori
r1,IMMR
r1,r1,$ffff
r2,r0,0
r2,r2,MemStart
r2,r2,$0801
r2,BR4(r1)
r2,r0,0
r2,r2,$ffc0
r2,r2,$0608
Loop
stw
andis.
oris
stb
lbz
b
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
r2,OR4(r1)
;
r1,r0,0
;
r1,r1,MemStart
;
r1,DisableReg(r1) ;
r0,RevCodeReg(r1) ;
Loop
;
CS4 base register
CS4 option register
upper word of S1D13506 start address
address of S1D13506 Disable Register
address of Revision Code Register
get base address of internal registers
clear lower 16 bits to 0
clear r2
write base address
port size 16 bits; select GPCM; enable
write value to base register
clear r2
address mask – use upper 10 bits
normal CS negation; delay CS ½ clock;
no burst inhibit (13506 does this)
write to option register
clear r1
point r1 to start of S1D13506 mem space
write 0 to disable register
read revision code into r1
branch forever
end
Note
MPC8BUG does not support comments or symbolic equates; these have been added for
clarity.
S1D13506
X25B-G-008-03
Interfacing to the Motorola MPC821 Microprocessor
Issue Date: 01/02/08
Epson Research and Development
Vancouver Design Center
Page 21
5 Software
Test utilities and Windows® CE display drivers are available for the S1D13506. Full
source code is available for both the test utilities and the drivers.
The test utilities are configurable for different panel types using a program called
13506CFG, or by directly modifying the source. The Windows CE display drivers can be
customized by the OEM for different panel types, resolutions and color depths only by
modifying the source.
The S1D13506 test utilities and Windows CE display drivers are available from your sales
support contact or on the internet at http://www.eea.epson.com.
Interfacing to the Motorola MPC821 Microprocessor
Issue Date: 01/02/08
S1D13506
X25B-G-008-03
Page 22
Epson Research and Development
Vancouver Design Center
6 References
6.1 Documents
• Motorola Inc., Power PC MPC821 Portable Systems Microprocessor User’s Manual;
Motorola Publication no. MPC821UM/AD.
• Epson Research and Development, Inc., S1D13506 Hardware Functional Specification,
Document Number X25B-A-001-xx.
• Epson Research and Development, Inc., S5U13506B00B Rev. 1.0 ISA Bus Evaluation
Board User Manual, Document Number X25B-G-001-xx.
• Epson Research and Development, Inc., S1D13506 Programming Notes and Examples,
Document Number X25B-G-003-xx.
6.2 Document Sources
• Motorola Literature Distribution Center: (800) 441-2447.
• Epson Electronics America Website: www.eea.epson.com.
S1D13506
X25B-G-008-03
Interfacing to the Motorola MPC821 Microprocessor
Issue Date: 01/02/08
Epson Research and Development
Vancouver Design Center
Page 23
7 Technical Support
7.1 EPSON LCD/CRT Controllers (S1D13506)
Japan
Seiko Epson Corporation
Electronic Devices Marketing Division
421-8, Hino, Hino-shi
Tokyo 191-8501, Japan
Tel: 042-587-5812
Fax: 042-587-5564
http://www.epson.co.jp
North America
Epson Electronics America, Inc.
150 River Oaks Parkway
San Jose, CA 95134, USA
Tel: (408) 922-0200
Fax: (408) 922-0238
http://www.eea.epson.com
Taiwan
Epson Taiwan Technology
& Trading Ltd.
10F, No. 287
Nanking East Road
Sec. 3, Taipei, Taiwan
Tel: 02-2717-7360
Fax: 02-2712-9164
Hong Kong
Epson Hong Kong Ltd.
20/F., Harbour Centre
25 Harbour Road
Wanchai, Hong Kong
Tel: 2585-4600
Fax: 2827-4346
Europe
Epson Europe Electronics GmbH
Riesstrasse 15
80992 Munich, Germany
Tel: 089-14005-0
Fax: 089-14005-110
Singapore
Epson Singapore Pte., Ltd.
No. 1
Temasek Avenue #36-00
Millenia Tower
Singapore, 039192
Tel: 337-7911
Fax: 334-2716
7.2 Motorola MPC821 Processor
• Motorola Design Line, (800) 521-6274.
• Local Motorola sales office or authorized distributor.
Interfacing to the Motorola MPC821 Microprocessor
Issue Date: 01/02/08
S1D13506
X25B-G-008-03
Page 24
Epson Research and Development
Vancouver Design Center
THIS PAGE LEFT BLANK
S1D13506
X25B-G-008-03
Interfacing to the Motorola MPC821 Microprocessor
Issue Date: 01/02/08
S1D13506 Color LCD/CRT/TV Controller
Interfacing to the Philips MIPS
PR31500/PR31700 Processor
Document Number: X25B-G-009-02
Copyright © 2001 Epson Research and Development, Inc. All Rights Reserved.
Information in this document is subject to change without notice.You may download and use this document, but only for your own use in
evaluating Seiko Epson/EPSON products. You may not modify the document. Epson Research and Development, Inc. disclaims any
representation that the contents of this document are accurate or current. The Programs/Technologies described in this document may contain
material protected under U.S. and/or International Patent laws.
EPSON is a registered trademark of Seiko Epson Corporation. All other trademarks are the property of their respective owners.
Page 2
Epson Research and Development
Vancouver Design Center
THIS PAGE LEFT BLANK
S1D13506
X25B-G-009-02
Interfacing to the Philips MIPS PR31500/PR31700 Processor
Issue Date: 01/02/08
Epson Research and Development
Vancouver Design Center
Page 3
Table of Contents
1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2
Interfacing to the PR31500/PR31700 . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3
S1D13506 Host Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.1 PR31500/PR31700 Host Bus Interface Pin Mapping . . . . . . . . . . . . . . . . 9
3.2 PR31500/PR31700 Host Bus Interface Signals . . . . . . . . . . . . . . . . . 10
4
Direct Connection to the Philips PR31500/PR31700 .
4.1 Hardware Description . . . . . . . . . . . . .
4.2 S1D13506 Configuration . . . . . . . . . . . .
4.3 Memory Mapping and Aliasing . . . . . . . . .
5
System Design Using the IT8368E PC Card Buffer
5.1 Hardware Description . . . . . . . . . . . .
5.2 IT8368E Configuration . . . . . . . . . . . .
5.3 S1D13506 Configuration . . . . . . . . . . .
6
Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
7
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
7.1 Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
7.2 Document Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
8
Technical Support . . . . . . . . . . . . . .
8.1 EPSON LCD/CRT Controllers (S1D13506)
8.2 Philips MIPS PR31500/PR31700 Processor .
8.3 ITE IT8368E . . . . . . . . . . . . .
Interfacing to the Philips MIPS PR31500/PR31700 Processor
Issue Date: 01/02/08
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
. .
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
. .
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
11
11
12
13
. . .
. .
. .
. .
.
.
.
.
.
.
.
.
.
.
.
.
. . .
. .
. .
. .
.
.
.
.
.
.
.
.
.
.
.
.
. . .
. .
. .
. .
.
.
.
.
.
.
.
.
.
.
.
.
14
14
15
15
. . .
. .
. .
. .
.
.
.
.
.
.
.
.
.
.
.
.
. . .
. .
. .
. .
.
.
.
.
.
.
.
.
.
.
.
.
. . .
. .
. .
. .
.
.
.
.
.
.
.
.
.
.
.
.
. 18
. 18
. 18
. 18
S1D13506
X25B-G-009-02
Page 4
Epson Research and Development
Vancouver Design Center
THIS PAGE LEFT BLANK
S1D13506
X25B-G-009-02
Interfacing to the Philips MIPS PR31500/PR31700 Processor
Issue Date: 01/02/08
Epson Research and Development
Vancouver Design Center
Page 5
List of Tables
Table 3-1: PR31500/PR31700 Host Bus Interface Pin Mapping . . . . . . . . . . . . . . . . . . . . 9
Table 4-1: S1D13506 Configuration for Direct Connection. . . . . . . . . . . . . . . . . . . . . . 12
Table 4-2: PR31500/PR31700 to PC Card Slots Address Remapping for Direct Connection . . . . 13
List of Figures
Figure 4-1: Typical Implementation of Direct Connection . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 5-1: IT8368E Implementation Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . 14
Interfacing to the Philips MIPS PR31500/PR31700 Processor
Issue Date: 01/02/08
S1D13506
X25B-G-009-02
Page 6
Epson Research and Development
Vancouver Design Center
THIS PAGE LEFT BLANK
S1D13506
X25B-G-009-02
Interfacing to the Philips MIPS PR31500/PR31700 Processor
Issue Date: 01/02/08
Epson Research and Development
Vancouver Design Center
Page 7
1 Introduction
This application note describes the hardware and software environment necessary to
provide an interface between the S1D13506 Color LCD/CRT Controller and the Philips
MIPS PR31500/PR31700 Processor.
The designs described in this document are presented only as examples of how such
interfaces might be implemented. This application note will be updated as appropriate.
Please check the Epson Electronics America website at http://www.eea.epson.com for the
latest revision of this document before beginning any development.
We appreciate your comments on our documentation. Please contact us via email at
[email protected]
Interfacing to the Philips MIPS PR31500/PR31700 Processor
Issue Date: 01/02/08
S1D13506
X25B-G-009-02
Page 8
Epson Research and Development
Vancouver Design Center
2 Interfacing to the PR31500/PR31700
The Philips MIPS PR31500/PR31700 processor supports up to two PC Card (PCMCIA)
slots. It is through this Host Bus Interface that the S1D13506 connects to the
PR31500/PR31700 processor.
The S1D13506 can be successfully interfaced using one of the following configurations:
• Direct connection to the PR31500/PR31700 (see Section 4, “Direct Connection to the
Philips PR31500/PR31700” on page 11).
• System design using the ITE IT8368E PC Card/GPIO buffer chip (see Section 5,
“System Design Using the IT8368E PC Card Buffer” on page 14).
S1D13506
X25B-G-009-02
Interfacing to the Philips MIPS PR31500/PR31700 Processor
Issue Date: 01/02/08
Epson Research and Development
Vancouver Design Center
Page 9
3 S1D13506 Host Bus Interface
The S1D13506 implements a 16-bit Host Bus Interface specifically for interfacing to the
PR31500/PR31700 microprocessor.
The PR31500/PR31700 Host Bus Interface is selected by the S1D13506 on the rising edge
of RESET#. After releasing reset, the bus interface signals assume their selected
configuration. For details on S1D13506 configuration, see Section 4.2, “S1D13506 Configuration” on page 12.
Note
At reset, the Register/Memory Select bit in the Miscellaneous Register (REG[001h] bit
7) is set to 1. This means that only REG[000h] (read-only) and REG[001h] are
accessible until a write to REG[001h] sets bit 7 to 0 making all registers accessible.
When debugging a new hardware design, this can sometimes give the appearance that
the interface is not working, so it is important to remember to clear this bit before
proceeding with debugging.
3.1 PR31500/PR31700 Host Bus Interface Pin Mapping
The following table shows the function of each Host Bus Interface signal.
Table 3-1: PR31500/PR31700 Host Bus Interface Pin Mapping
S1D13506 Pin Name
AB20
AB19
AB18
AB17
AB[16:13]
AB[12:0]
DB[15:8]
DB[7:0]
WE1#
M/R#
CS#
BUSCLK
BS#
RD/WR#
RD#
WE0#
WAIT#
RESET#
Interfacing to the Philips MIPS PR31500/PR31700 Processor
Issue Date: 01/02/08
Philips PR31500/PR31700
ALE
/CARDREG
/CARDIORD
/CARDIOWR
VDD
A[12:0]
D[23:16]
D[31:24]
/CARDxCSH
VDD
VDD
DCLKOUT
VDD
/CARDxCSL
/RD
/WE
/CARDxWAIT
RESET#
S1D13506
X25B-G-009-02
Page 10
Epson Research and Development
Vancouver Design Center
3.2 PR31500/PR31700 Host Bus Interface Signals
When the S1D13506 is configured to operate with the PR31500/PR31700, the Host Bus
Interface requires the following signals:
• BUSCLK is a clock input required by the S1D13506 Host Bus Interface. It is separate
from the input clock (CLKI) and should be driven by the PR31500/PR31700 bus clock
output DCLKOUT.
• Address input AB20 corresponds to the PR31500/PR31700 signal ALE (address latch
enable) whose falling edge indicates that the most significant bits of the address are
present on the multiplexed address bus (AB[12:0]).
• Address input AB19 should be connected to the PR31500/PR31700 signal /CARDREG.
This signal is active when either IO or configuration space of the PR31500/PR31700
PC Card slot is being accessed.
• Address input AB18 should be connected to the PR31500/PR31700 signal
/CARDIORD. Either AB18 or the RD# input must be asserted for a read operation to
take place.
• Address input AB17 should be connected to the PR31500/PR31700 signal
/CARDIOWR. Either AB17 or the WE0# input must be asserted for a write operation to
take place.
• Address inputs AB[16:13] and control inputs M/R#, CS# and BS# must be tied to VDD
as they are not used in this interface mode.
• Address inputs AB[12:0], and the data bus DB[15:0], connect directly to the
PR31500/PR31700 address and data bus, respectively. MD4 must be set to select the
proper endian mode on reset (see Section 4.2, “S1D13506 Configuration” on page 12).
Because of the PR31500/PR31700 data bus naming convention and endian mode,
S1D13506 DB[15:8] must be connected to PR31500/PR31700 D[23:16], and
S1D13506 DB[7:0] must be connected to PR31500/PR31700 D[31:24].
• Control inputs WE1# and RD/WR# should be connected to the PR31500/PR31700
signals /CARDxCSH and /CARDxCSL respectively for byte steering.
• Input RD# should be connected to the PR31500/PR31700 signal /RD. Either RD# or the
AB18 input (/CARDIORD) must be asserted for a read operation to take place.
• Input WE0# should be connected to the PR31500/PR31700 signal /WR. Either WE0# or
the AB17 input (/CARDIOWR) must be asserted for a write operation to take place.
• WAIT# is a signal output from the S1D13506 that indicates the host CPU must wait
until data is ready (read cycle) or accepted (write cycle) on the host bus. Since the host
CPU accesses to the S1D13506 may occur asynchronously to the display update, it is
possible that contention may occur in accessing the S1D13506 internal registers and/or
display buffer. The WAIT# line resolves these contentions by forcing the host to wait
until the resource arbitration is complete.
S1D13506
X25B-G-009-02
Interfacing to the Philips MIPS PR31500/PR31700 Processor
Issue Date: 01/02/08
Epson Research and Development
Vancouver Design Center
Page 11
4 Direct Connection to the Philips PR31500/PR31700
The S1D13506 was specifically designed to support the Philips MIPS PR31500/PR31700
processor. When configured, the S1D13506 will utilize one of the PC Card slots supported
by the processor.
4.1 Hardware Description
In this example implementation, the S1D13506 occupies one PC Card slot and resides in
the Attribute and IO address range. The processor provides address bits A[12:0], with
A[23:13] being multiplexed and available on the falling edge of ALE. Peripherals requiring
more than 8K bytes of address space would require an external latch for these multiplexed
bits. However, the S1D13506 has an internal latch specifically designed for this processor
making additional logic unnecessary. To further reduce the need for external components,
the S1D13506 has an optional BUSCLK divide-by-2 feature, allowing the high speed
DCLKOUT from the processor to be directly connected to the BUSCLK input of the
S1D13506. An optional external oscillator may be used for BUSCLK since the S1D13506
will accept host bus control signals asynchronously with respect to BUSCLK.
The following diagram shows a typical implementation of the interface.
VDD (+3.3V)
PR31500/PR31700
S1D13506
M/R#
CS#
BS#
AB[16:13]
AB[12:0]
DB[15:8]
DB[7:0]
A[12:0]
D[23:16]
D[31:24]
ALE
/CARDREG
AB20
/CARDIORD
AB18
/CARDIOWR
AB17
/CARDxCSH
WE1#
RD/WR#
RD#
WE0#
WAIT#
/CARDxCSL
/RD
/WE
/CARDxWAIT
AB19
VDD
pull-up
System RESET
RESET#
ENDIAN
DCLKOUT
...or...
Oscillator
See text
BUSCLK
CLKI
Note: When connecting the S1D13506 RESET# pin, the system designer should be aware of all
conditions that may reset the S1D13506 (e.g. CPU reset can be asserted during wake-up
from power-down modes, or during debug states).
Figure 4-1: Typical Implementation of Direct Connection
Interfacing to the Philips MIPS PR31500/PR31700 Processor
Issue Date: 01/02/08
S1D13506
X25B-G-009-02
Page 12
Epson Research and Development
Vancouver Design Center
The host interface control signals of the S1D13506 are asynchronous with respect to the
S1D13506 bus clock. This gives the system designer full flexibility to choose the
appropriate source (or sources) for CLKI and BUSCLK. The choice of whether both clocks
should be the same, whether to use DCLKOUT as clock source, and whether an external or
internal clock divider is needed, should be based on the desired:
• pixel and frame rates.
• power budget.
• part count.
• maximum S1D13506 clock frequencies.
The S1D13506 also has internal CLKI dividers providing additional flexibility.
4.2 S1D13506 Configuration
The S1D13506 latches MD15 through MD0 to allow selection of the bus mode and other
configuration data on the rising edge of RESET#. For details on configuration, refer to the
S1D13506 Hardware Functional Specification, document number X25B-A-001-xx.
The table below shows those configuration settings relevant to the Philips
PR31500/PR31700 Host Bus Interface.
Table 4-1: S1D13506 Configuration for Direct Connection
S1D13506
Pin Name
MD[3:1]
MD4
MD5
Value on this pin at rising edge of RESET# is used to configure:
1 (VDD)
0 (VSS)
111 = Philips PR31500/PR31700 Host Bus Interface when MD11 = 1
Little Endian
Big Endian
WAIT# is active high (1 = insert wait state)
WAIT# is active low (0 = insert wait state)
MD11
MD12
Alternate Host Bus Interface selected
BUSCLK input divided by two: use with DCLKOUT
Primary Host Bus Interface selected
BUSCLK input not divided: use with external oscillator
MD15
WAIT# is always driven
WAIT# is floating if S1D13506 is not selected
= configuration for Philips PR31500/PR31700 Host Bus Interface
S1D13506
X25B-G-009-02
Interfacing to the Philips MIPS PR31500/PR31700 Processor
Issue Date: 01/02/08
Epson Research and Development
Vancouver Design Center
Page 13
4.3 Memory Mapping and Aliasing
The PR31500/PR31700 uses a portion of the PC Card Attribute and IO space to access the
S1D13506. The S1D13506 responds to both PC Card Attribute and IO bus accesses, thus
freeing the programmer from having to set the PR31500/PR31700 Memory Configuration
Register 3 bit CARD1IOEN (or CARD2IOEN if slot 2 is used). As a result, the
PR31500/PR31700 sees the S1D13506 on its PC Card slot as described in the table below.
Table 4-2: PR31500/PR31700 to PC Card Slots Address Remapping for Direct Connection
S1D13506 Uses PC Card Slot #
1
2
Philips Address
Size
Function
0800 0000h
16M byte
Card 1 IO or Attribute
0900 0000h
8M byte
0980 0000h
8M byte
S1D13506 registers,
aliased 4 times at 2M byte intervals
S1D13506 display buffer,
aliased 4 times at 2M byte intervals
0A00 0000h
32M byte
Card 1 IO or Attribute
6400 0000h
64M byte
Card 1 Memory
0C00 0000h
16M byte
Card 2 IO or Attribute
0D00 0000h
8M byte
0D80 0000h
8M byte
0E00 0000h
32M byte
Card 2 IO or Attribute
6800 0000h
64M byte
Card 2 Memory
Interfacing to the Philips MIPS PR31500/PR31700 Processor
Issue Date: 01/02/08
S1D13506 registers,
aliased 4 times at 2M byte intervals
S1D13506 display buffer,
aliased 4 times at 2M byte intervals
S1D13506
X25B-G-009-02
Page 14
Epson Research and Development
Vancouver Design Center
5 System Design Using the IT8368E PC Card Buffer
In a system design using one or two ITE IT8368E PC Card and multiple-function IO
buffers, the S1D13506 can be interfaced so as to share one of the PC Card slots.
5.1 Hardware Description
The IT8368E can be programmed to allocate the same portion of the PC Card Attribute and
IO space to the S1D13506 as in the direct connection implementation described in Section
4, “Direct Connection to the Philips PR31500/PR31700” on page 11.
Following is a block diagram showing an implementation using the IT8368E PC Card
buffer.
PR31500/
PR31700
S1D13506
IT8368E
PC Card
Device
IT8368E
PC Card
Device
Figure 5-1: IT8368E Implementation Block Diagram
S1D13506
X25B-G-009-02
Interfacing to the Philips MIPS PR31500/PR31700 Processor
Issue Date: 01/02/08
Epson Research and Development
Vancouver Design Center
Page 15
5.2 IT8368E Configuration
The ITE IT8368E has been specifically designed to support EPSON LCD/CRT controllers.
Older EPSON Controllers not supporting a direct interface to the Philips processor can
utilize the IT8368E MFIO pins to provide the necessary control signals, however when
using the S1D13506 this is not necessary as the Direct Connection described in Section 4,
“Direct Connection to the Philips PR31500/PR31700” on page 11 can be used.
The IT8368E must have both “Fix Attribute/IO” and “VGA” modes enabled. When both
these modes are enabled a 16M byte portion of the system PC Card attribute and IO space
is allocated to address the S1D13506.
When the IT8368E senses that the S1D13506 is being accessed, it does not propagate the
PC Card signals to its PC Card device. This makes S1D13506 accesses transparent to any
PC Card device connected to the same slot.
For mapping details, refer to Section 4.3, “Memory Mapping and Aliasing” on page 13. For
further information on configuring the IT8368E, refer to the IT8368E PC Card/GPIO
Buffer Chip Specification.
5.3 S1D13506 Configuration
For S1D13506 configuration, refer to Section 4.2, “S1D13506 Configuration” on page 12.
Interfacing to the Philips MIPS PR31500/PR31700 Processor
Issue Date: 01/02/08
S1D13506
X25B-G-009-02
Page 16
Epson Research and Development
Vancouver Design Center
6 Software
Test utilities and Windows® CE v2.0 display drivers are available for the S1D13506. Full
source code is available for both the test utilities and the drivers.
The test utilities are configurable for different panel types using a program called
13506CFG, or by directly modifying the source. The Windows CE v2.0 display drivers can
be customized by the OEM for different panel types, resolutions and color depths only by
modifying the source.
The S1D13506 test utilities and Windows CE v2.0 display drivers are available from your
sales support contact or on the internet at http://www.eea.epson.com.
S1D13506
X25B-G-009-02
Interfacing to the Philips MIPS PR31500/PR31700 Processor
Issue Date: 01/02/08
Epson Research and Development
Vancouver Design Center
Page 17
7 References
7.1 Documents
• Philips Electronics, PR31500/PR31700 Preliminary Specifications.
• Epson Research and Development, Inc., S1D13506 Hardware Functional Specification,
Document Number X25B-A-001-xx.
• Epson Research and Development, Inc., S5U13506B00C Rev. 1.0 ISA Bus Evaluation
Board User Manual, Document Number X25B-G-004-xx.
• Epson Research and Development, Inc., S1D13506 Programming Notes and Examples,
Document Number X25B-G-003-xx.
7.2 Document Sources
• Philips Electronics Website: http://www-us2.semiconductors.philips.com.
• Epson Electronics America Website: http://www.eea.epson.com.
Interfacing to the Philips MIPS PR31500/PR31700 Processor
Issue Date: 01/02/08
S1D13506
X25B-G-009-02
Page 18
Epson Research and Development
Vancouver Design Center
8 Technical Support
8.1 EPSON LCD/CRT Controllers (S1D13506)
Japan
Seiko Epson Corporation
Electronic Devices Marketing Division
421-8, Hino, Hino-shi
Tokyo 191-8501, Japan
Tel: 042-587-5812
Fax: 042-587-5564
http://www.epson.co.jp
North America
Epson Electronics America, Inc.
150 River Oaks Parkway
San Jose, CA 95134, USA
Tel: (408) 922-0200
Fax: (408) 922-0238
http://www.eea.epson.com
Taiwan, R.O.C.
Epson Taiwan Technology
& Trading Ltd.
10F, No. 287
Nanking East Road
Sec. 3, Taipei, Taiwan, R.O.C.
Tel: 02-2717-7360
Fax: 02-2712-9164
Europe
Epson Europe Electronics GmbH
Riesstrasse 15
80992 Munich, Germany
Tel: 089-14005-0
Fax: 089-14005-110
Hong Kong
Epson Hong Kong Ltd.
20/F., Harbour Centre
25 Harbour Road
Wanchai, Hong Kong
Tel: 2585-4600
Fax: 2827-4346
Singapore
Epson Singapore Pte., Ltd.
No. 1
Temasek Avenue #36-00
Millenia Tower
Singapore, 039192
Tel: 337-7911
Fax: 334-2716
8.2 Philips MIPS PR31500/PR31700 Processor
Philips Semiconductors
Handheld Computing Group
4811 E. Arques Avenue
M/S 42, P.O. Box 3409
Sunnyvale, CA 94088-3409
Tel: (408) 991-2313
http://www.philips.com
8.3 ITE IT8368E
Integrated Technology Express, Inc.
Sales & Marketing Division
2710 Walsh Avenue
Santa Clara, CA 95051, USA
Tel: (408) 980-8168
Fax: (408) 980-9232
http://www.iteusa.com
S1D13506
X25B-G-009-02
Interfacing to the Philips MIPS PR31500/PR31700 Processor
Issue Date: 01/02/08
S1D13506 Color LCD/CRT/TV Controller
Interfacing to the Toshiba MIPS
TX3912 Processor
Document Number: X25B-G-010-02
Copyright © 2001 Epson Research and Development, Inc. All Rights Reserved.
Information in this document is subject to change without notice.You may download and use this document, but only for your own use in
evaluating Seiko Epson/EPSON products. You may not modify the document. Epson Research and Development, Inc. disclaims any
representation that the contents of this document are accurate or current. The Programs/Technologies described in this document may contain
material protected under U.S. and/or International Patent laws.
EPSON is a registered trademark of Seiko Epson Corporation. All other trademarks are the property of their respective owners.
Page 2
Epson Research and Development
Vancouver Design Center
THIS PAGE LEFT BLANK
S1D13506
X25B-G-010-02
Interfacing to the Toshiba MIPS TX3912 Processor
Issue Date: 01/02/08
Epson Research and Development
Vancouver Design Center
Page 3
Table of Contents
1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2
Interfacing to the TX3912
3
S1D13506 Host Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.1 TX3912 Host Bus Interface Pin Mapping . . . . . . . . . . . . . . . . . . . . . 9
3.2 TX3912 Host Bus Interface Signals . . . . . . . . . . . . . . . . . . . . . . 10
4
Direct Connection to the Toshiba TX3912
4.1 Hardware Description . . . . . . . .
4.2 S1D13506 Configuration . . . . . . .
4.3 Memory Mapping and Aliasing . . . .
5
System Design Using the IT8368E PC Card Buffer
5.1 Hardware Description . . . . . . . . . . . .
5.2 IT8368E Configuration . . . . . . . . . . . .
5.3 S1D13506 Configuration . . . . . . . . . . .
6
Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
7
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
7.1 Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
7.2 Document Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
8
Technical Support . . . . . . . . . . . . . .
8.1 EPSON LCD/CRT Controllers (S1D13506)
8.2 Toshiba MIPS TX3912 Processor . . . . .
8.3 ITE IT8368E . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Interfacing to the Toshiba MIPS TX3912 Processor
Issue Date: 01/02/08
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
. . .
. .
. .
. .
.
.
.
.
.
.
.
.
.
.
.
.
. . .
. .
. .
. .
. . .
. .
. .
. .
.
.
.
.
.
.
.
.
.
.
.
.
. . .
. .
. .
. .
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
. . .
. .
. .
. .
. . .
. .
. .
. .
.
.
.
.
.
.
.
.
.
.
.
.
. . .
. .
. .
. .
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
. 11
. 11
. 12
. 13
. . .
. .
. .
. .
.
.
.
.
.
.
.
.
.
.
.
.
. . .
. .
. .
. .
.
.
.
.
.
.
.
.
.
.
.
.
14
14
15
15
. 18
. 18
. 18
. 18
S1D13506
X25B-G-010-02
Page 4
Epson Research and Development
Vancouver Design Center
THIS PAGE LEFT BLANK
S1D13506
X25B-G-010-02
Interfacing to the Toshiba MIPS TX3912 Processor
Issue Date: 01/02/08
Epson Research and Development
Vancouver Design Center
Page 5
List of Tables
Table 3-1: TX3912 Host Bus Interface Pin Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 4-1: S1D13506 Configuration for Direct Connection. . . . . . . . . . . . . . . . . . . . . . 12
Table 4-2: TX3912 to PC Card Slots Address Remapping for Direct Connection . . . . . . . . . . 13
List of Figures
Figure 4-1: Typical Implementation of Direct Connection . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 5-1: IT8368E Implementation Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . 14
Interfacing to the Toshiba MIPS TX3912 Processor
Issue Date: 01/02/08
S1D13506
X25B-G-010-02
Page 6
Epson Research and Development
Vancouver Design Center
THIS PAGE LEFT BLANK
S1D13506
X25B-G-010-02
Interfacing to the Toshiba MIPS TX3912 Processor
Issue Date: 01/02/08
Epson Research and Development
Vancouver Design Center
Page 7
1 Introduction
This application note describes the hardware and software environment necessary to
provide an interface between the S1D13506 Color LCD/CRT/TV Controller and the
Toshiba MIPS TX3912 Processor.
The designs described in this document are presented only as examples of how such
interfaces might be implemented. This application note will be updated as appropriate.
Please check the Epson Electronics America website at http://www.eea.epson.com for the
latest revision of this document before beginning any development.
We appreciate your comments on our documentation. Please contact us via email at
[email protected]
Interfacing to the Toshiba MIPS TX3912 Processor
Issue Date: 01/02/08
S1D13506
X25B-G-010-02
Page 8
Epson Research and Development
Vancouver Design Center
2 Interfacing to the TX3912
The Toshiba MIPS TX3912 processor supports up to two PC Card (PCMCIA) slots. It is
through this Host Bus Interface that the S1D13506 connects to the TX3912 processor.
The S1D13506 can be successfully interfaced using one of the following configurations:
• Direct connection to the TX3912 (see Section 4, “Direct Connection to the Toshiba
TX3912” on page 11).
• System design using the ITE IT8368E PC Card/GPIO buffer chip (see Section 5,
“System Design Using the IT8368E PC Card Buffer” on page 14).
S1D13506
X25B-G-010-02
Interfacing to the Toshiba MIPS TX3912 Processor
Issue Date: 01/02/08
Epson Research and Development
Vancouver Design Center
Page 9
3 S1D13506 Host Bus Interface
The S1D13506 implements a 16-bit Host Bus Interface specifically for interfacing to the
TX3912 microprocessor.
The TX3912 Host Bus Interface is selected by the S1D13506 on the rising edge of
RESET#. After releasing reset, the bus interface signals assume their selected configuration. For details on S1D13506 configuration, see Section 4.2, “S1D13506 Configuration” on page 12.
Note
At reset, the Register/Memory Select bit in the Miscellaneous Register (REG[001h] bit
7) is set to 1. This means that only REG[000h] (read-only) and REG[001h] are
accessible until a write to REG[001h] sets bit 7 to 0 making all registers accessible.
When debugging a new hardware design, this can sometimes give the appearance that
the interface is not working, so it is important to remember to clear this bit before
proceeding with debugging.
3.1 TX3912 Host Bus Interface Pin Mapping
The following table shows the function of each Host Bus Interface signal.
Table 3-1: TX3912 Host Bus Interface Pin Mapping
S1D13506
Pin Names
AB20
AB19
AB18
AB17
AB[16:13]
AB[12:0]
DB[15:8]
DB[7:0]
WE1#
M/R#
CS#
BUSCLK
BS#
RD/WR#
RD#
WE0#
WAIT#
RESET#
Interfacing to the Toshiba MIPS TX3912 Processor
Issue Date: 01/02/08
Toshiba TX3912
ALE
CARDREG*
CARDIORD*
CARDIOWR*
VDD
A[12:0]
D[23:16]
D[31:24]
CARDxCSH*
VDD
VDD
DCLKOUT
VDD
CARDxCSL*
RD*
WE*
CARDxWAIT*
PON*
S1D13506
X25B-G-010-02
Page 10
Epson Research and Development
Vancouver Design Center
3.2 TX3912 Host Bus Interface Signals
When the S1D13506 is configured to operate with the TX3912, the Host Bus Interface
requires the following signals:
• BUSCLK is a clock input required by the S1D13506 Host Bus Interface. It is separate
from the input clock (CLKI) and should be driven by the TX3912 bus clock output
DCLKOUT.
• Address input AB20 corresponds to the TX3912 signal ALE (address latch enable)
whose falling edge indicates that the most significant bits of the address are present on
the multiplexed address bus (AB[12:0]).
• Address input AB19 should be connected to the TX3912 signal CARDREG*. This
signal is active when either IO or configuration space of the TX3912 PC Card slot is
being accessed.
• Address input AB18 should be connected to the TX3912 signal CARDIORD*. Either
AB18 or the RD# input must be asserted for a read operation to take place.
• Address input AB17 should be connected to the TX3912 signal CARDIOWR*. Either
AB17 or the WE0# input must be asserted for a write operation to take place.
• Address inputs AB[16:13] and control inputs M/R#, CS# and BS# must be tied to VDD
as they are not used in this interface mode.
• Address inputs AB[12:0], and the data bus DB[15:0], connect directly to the TX3912
address and data bus, respectively. MD4 must be set to select the proper endian mode on
reset (see Section 4.2, “S1D13506 Configuration” on page 12). Because of the TX3912
data bus naming convention and endian mode, S1D13506 DB[15:8] must be
connected to TX3912 D[23:16], and S1D13506 DB[7:0] must be connected to
TX3912 D[31:24].
• Control inputs WE1# and RD/WR# should be connected to the TX3912 signals
CARDxCSH* and CARDxCSL* respectively for byte steering.
• Input RD# should be connected to the TX3912 signal RD*. Either RD# or the AB18
input (CARDIORD*) must be asserted for a read operation to take place.
• Input WE0# should be connected to the TX3912 signal WR*. Either WE0# or the AB17
input (CARDIOWR*) must be asserted for a write operation to take place.
• WAIT# is a signal output from the S1D13506 that indicates the TX3912 must wait until
data is ready (read cycle) or accepted (write cycle) on the host bus. Since the TX3912
accesses to the S1D13506 may occur asynchronously to the display update, it is possible
that contention may occur in accessing the S1D13506 internal registers and/or display
buffer. The WAIT# line resolves these contentions by forcing the host to wait until the
resource arbitration is complete.
S1D13506
X25B-G-010-02
Interfacing to the Toshiba MIPS TX3912 Processor
Issue Date: 01/02/08
Epson Research and Development
Vancouver Design Center
Page 11
4 Direct Connection to the Toshiba TX3912
The S1D13506 was specifically designed to support the Toshiba MIPS TX3912 processor.
When configured, the S1D13506 will utilize one of the PC Card slots supported by the
processor.
4.1 Hardware Description
In this example implementation, the S1D13506 occupies one PC Card slot and resides in
the Attribute and IO address range. The processor provides address bits A[12:0], with
A[23:13] being multiplexed and available on the falling edge of ALE. Peripherals requiring
more than 8K bytes of address space would require an external latch for these multiplexed
bits. However, the S1D13506 has an internal latch specifically designed for this processor
making additional logic unnecessary. To further reduce the need for external components,
the S1D13506 has an optional BUSCLK divide-by-2 feature, allowing the high speed
DCLKOUT from the processor to be directly connected to the BUSCLK input of the
S1D13506. An optional external oscillator may be used for BUSCLK since the S1D13506
will accept host bus control signals asynchronously with respect to BUSCLK.
The following diagram shows a typical implementation of the interface.
VDD (+3.3V)
TX3912
S1D13506
M/R#
CS#
BS#
AB[16:13]
AB[12:0]
DB[15:8]
DB[7:0]
A[12:0]
D[23:16]
D[31:24]
ALE
CARDREG*
AB20
CARDIORD*
AB18
CARDIOWR*
AB17
CARDxCSH*
WE1#
RD/WR#
RD#
WE0#
WAIT#
CARDxCSL*
RD*
WE*
CARDxWAIT*
AB19
VDD
pull-up
System RESET
RESET#
ENDIAN
DCLKOUT
...or...
Oscillator
See text
BUSCLK
CLKI
Note: When connecting the S1D13506 RESET# pin, the system designer should be aware of all
conditions that may reset the S1D13506 (e.g. CPU reset can be asserted during wake-up
from power-down modes, or during debug states).
Figure 4-1: Typical Implementation of Direct Connection
Interfacing to the Toshiba MIPS TX3912 Processor
Issue Date: 01/02/08
S1D13506
X25B-G-010-02
Page 12
Epson Research and Development
Vancouver Design Center
The host interface control signals of the S1D13506 are asynchronous with respect to the
S1D13506 bus clock. This gives the system designer full flexibility to choose the
appropriate source (or sources) for CLKI and BUSCLK. The choice of whether both clocks
should be the same, whether to use DCLKOUT as clock source, and whether an external or
internal clock divider is needed, should be based on the desired:
• pixel and frame rates.
• power budget.
• part count.
• maximum S1D13506 clock frequencies.
The S1D13506 also has internal CLKI dividers providing additional flexibility.
4.2 S1D13506 Configuration
The S1D13506 latches MD15 through MD0 to allow selection of the bus mode and other
configuration data on the rising edge of RESET#. For details on configuration, refer to the
S1D13506 Hardware Functional Specification, document number X25B-A-001-xx.
The table below shows those configuration settings relevant to the Toshiba TX3912 Host
Bus Interface.
Table 4-1: S1D13506 Configuration for Direct Connection
S1D13506
Pin Name
MD[3:1]
MD4
MD5
Value on this pin at rising edge of RESET# is used to configure:
1 (VDD)
0 (VSS)
111 = Toshiba TX3912 Host Bus Interface if MD11 = 1
Little Endian
Big Endian
WAIT# is active high (1 = insert wait state)
WAIT# is active low (0 = insert wait state)
MD11
MD12
Alternate Host Bus Interface selected
BUSCLK input divided by two: use with DCLKOUT
Primary Host Bus Interface selected
BUSCLK input not divided: use with external oscillator
MD15
WAIT# is always driven
WAIT# is floating if S1D13506 is not selected
= configuration for Toshiba TX3912 Host Bus Interface
S1D13506
X25B-G-010-02
Interfacing to the Toshiba MIPS TX3912 Processor
Issue Date: 01/02/08
Epson Research and Development
Vancouver Design Center
Page 13
4.3 Memory Mapping and Aliasing
The TX3912 uses a portion of the PC Card Attribute and IO space to access the S1D13506.
The S1D13506 responds to both PC Card Attribute and IO bus accesses, thus freeing the
programmer from having to set the TX3912 Memory Configuration Register 3 bit
CARD1IOEN (or CARD2IOEN if slot 2 is used). As a result, the TX3912 sees the
S1D13506 on its PC Card slot as described in the table below.
Table 4-2: TX3912 to PC Card Slots Address Remapping for Direct Connection
S1D13506 Uses PC Card Slot #
1
2
Toshiba Address
Size
Function
0800 0000h
16M byte
Card 1 IO or Attribute
0900 0000h
8M byte
0980 0000h
8M byte
S1D13506 registers,
aliased 4 times at 2M byte intervals
S1D13506 display buffer,
aliased 4 times at 2M byte intervals
0A00 0000h
32M byte
Card 1 IO or Attribute
6400 0000h
64M byte
Card 1 Memory
0C00 0000h
16M byte
Card 2 IO or Attribute
0D00 0000h
8M byte
0D80 0000h
8M byte
0E00 0000h
32M byte
Card 2 IO or Attribute
6800 0000h
64M byte
Card 2 Memory
Interfacing to the Toshiba MIPS TX3912 Processor
Issue Date: 01/02/08
S1D13506 registers,
aliased 4 times at 2M byte intervals
S1D13506 display buffer,
aliased 4 times at 2M byte intervals
S1D13506
X25B-G-010-02
Page 14
Epson Research and Development
Vancouver Design Center
5 System Design Using the IT8368E PC Card Buffer
In a system design using one or two ITE IT8368E PC Card and multiple-function IO
buffers, the S1D13506 can be interfaced so as to share one of the PC Card slots.
5.1 Hardware Description
The IT8368E can be programmed to allocate the same portion of the PC Card Attribute and
IO space to the S1D13506 as in the direct connection implementation described in Section
4, “Direct Connection to the Toshiba TX3912” on page 11.
Following is a block diagram showing an implementation using the IT8368E PC Card
buffer.
TX3912
S1D13506
IT8368E
PC Card
Device
IT8368E
PC Card
Device
Figure 5-1: IT8368E Implementation Block Diagram
S1D13506
X25B-G-010-02
Interfacing to the Toshiba MIPS TX3912 Processor
Issue Date: 01/02/08
Epson Research and Development
Vancouver Design Center
Page 15
5.2 IT8368E Configuration
The ITE IT8368E has been specifically designed to support EPSON LCD/CRT controllers.
Older EPSON Controllers not supporting a direct interface to the Toshiba processor can
utilize the IT8368E MFIO pins to provide the necessary control signals, however when
using the S1D13506 this is not necessary as the Direct Connection described in Section 4,
“Direct Connection to the Toshiba TX3912” on page 11 can be used.
The IT8368E must have both “Fix Attribute/IO” and “VGA” modes enabled. When both
these modes are enabled a 16M byte portion of the system PC Card attribute and IO space
is allocated to address the S1D13506.
When the IT8368E senses that the S1D13506 is being accessed, it does not propagate the
PC Card signals to its PC Card device. This makes S1D13506 accesses transparent to any
PC Card device connected to the same slot.
For mapping details, refer to Section 4.3, “Memory Mapping and Aliasing” on page 13. For
further information on configuring the IT8368E, refer to the IT8368E PC Card/GPIO
Buffer Chip Specification.
5.3 S1D13506 Configuration
For S1D13506 configuration, refer to Section 4.2, “S1D13506 Configuration” on page 12.
Interfacing to the Toshiba MIPS TX3912 Processor
Issue Date: 01/02/08
S1D13506
X25B-G-010-02
Page 16
Epson Research and Development
Vancouver Design Center
6 Software
Test utilities and Windows® CE v2.0 display drivers are available for the S1D13506. Full
source code is available for both the test utilities and the drivers.
The test utilities are configurable for different panel types using a program called
13506CFG, or by directly modifying the source. The Windows CE v2.0 display drivers can
be customized by the OEM for different panel types, resolutions and color depths only by
modifying the source.
The S1D13506 test utilities and Windows CE v2.0 display drivers are available from your
sales support contact or on the internet at http://www.eea.epson.com.
S1D13506
X25B-G-010-02
Interfacing to the Toshiba MIPS TX3912 Processor
Issue Date: 01/02/08
Epson Research and Development
Vancouver Design Center
Page 17
7 References
7.1 Documents
• Toshiba America Electrical Components, Inc., TX3905/12 Specification.
• Epson Research and Development, Inc., S1D13506 Hardware Functional Specification,
Document Number X25B-A-001-xx.
• Epson Research and Development, Inc., S5U13506B00C Rev. 1.0 ISA Bus Evaluation
Board User Manual, Document Number X25B-G-004-xx.
• Epson Research and Development, Inc., S1D13506 Programming Notes and Examples,
Document Number X25B-G-003-xx.
7.2 Document Sources
• Toshiba America Electrical Components Website: http://www.toshiba.com/taec.
• Epson Electronics America Website: http://www.eea.epson.com.
Interfacing to the Toshiba MIPS TX3912 Processor
Issue Date: 01/02/08
S1D13506
X25B-G-010-02
Page 18
Epson Research and Development
Vancouver Design Center
8 Technical Support
8.1 EPSON LCD/CRT Controllers (S1D13506)
Japan
Seiko Epson Corporation
Electronic Devices Marketing Division
421-8, Hino, Hino-shi
Tokyo 191-8501, Japan
Tel: 042-587-5812
Fax: 042-587-5564
http://www.epson.co.jp
North America
Epson Electronics America, Inc.
150 River Oaks Parkway
San Jose, CA 95134, USA
Tel: (408) 922-0200
Fax: (408) 922-0238
http://www.eea.epson.com
Taiwan, R.O.C.
Epson Taiwan Technology
& Trading Ltd.
10F, No. 287
Nanking East Road
Sec. 3, Taipei, Taiwan, R.O.C.
Tel: 02-2717-7360
Fax: 02-2712-9164
Europe
Epson Europe Electronics GmbH
Riesstrasse 15
80992 Munich, Germany
Tel: 089-14005-0
Fax: 089-14005-110
Hong Kong
Epson Hong Kong Ltd.
20/F., Harbour Centre
25 Harbour Road
Wanchai, Hong Kong
Tel: 2585-4600
Fax: 2827-4346
Singapore
Epson Singapore Pte., Ltd.
No. 1
Temasek Avenue #36-00
Millenia Tower
Singapore, 039192
Tel: 337-7911
Fax: 334-2716
8.2 Toshiba MIPS TX3912 Processor
http://www.toshiba.com/taec/nonflash/indexproducts.html
8.3 ITE IT8368E
Integrated Technology Express, Inc.
Sales & Marketing Division
2710 Walsh Avenue
Santa Clara, CA 95051, USA
Tel: (408) 980-8168
Fax: (408) 980-9232
http://www.iteusa.com
S1D13506
X25B-G-010-02
Interfacing to the Toshiba MIPS TX3912 Processor
Issue Date: 01/02/08
S1D13506 Color LCD/CRT/TV Controller
Interfacing to the NEC VR4121™
Microprocessor
Document Number: X25B-G-011-02
Copyright © 2001 Epson Research and Development, Inc. All Rights Reserved.
Information in this document is subject to change without notice.You may download and use this document, but only for your own use in
evaluating Seiko Epson/EPSON products. You may not modify the document. Epson Research and Development, Inc. disclaims any
representation that the contents of this document are accurate or current. The Programs/Technologies described in this document may contain
material protected under U.S. and/or International Patent laws.
EPSON is a registered trademark of Seiko Epson Corporation. All other trademarks are the property of their respective owners.
Microsoft and Windows are registered trademarks of Microsoft Corporation.
Page 2
Epson Research and Development
Vancouver Design Center
THIS PAGE LEFT BLANK
S1D13506
X25B-G-011-02
Interfacing to the NEC VR4121™ Microprocessor
Issue Date: 01/02/08
Epson Research and Development
Vancouver Design Center
Page 3
Table of Contents
1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2
Interfacing to the NEC VR4121 . .
2.1 The NEC VR4121 System Bus . .
2.1.1 Overview . . . . . . . . . .
2.1.2 LCD Memory Access Cycles
3
S1D13506 Host Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.1 Host Bus Interface Pin Mapping . . . . . . . . . . . . . . . . . . . . . . . 10
3.2 Host Bus Interface Signal Descriptions . . . . . . . . . . . . . . . . . . . . 11
4
VR4121 to S1D13506 Interface . .
4.1 Hardware Description . . . .
4.2 S1D13506 Configuration . . .
4.3 NEC VR4121 Configuration . .
4.4 Memory Mapping and Aliasing
5
Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
6
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
6.1 Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
6.2 Document Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
7
Technical Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
7.1 Epson LCD/CRT Controllers (S1D13506) . . . . . . . . . . . . . . . . . . . 17
7.2 NEC Electronics Inc. (VR4121). . . . . . . . . . . . . . . . . . . . . . . . 17
Interfacing to the NEC VR4121™ Microprocessor
Issue Date: 01/02/08
.
.
.
.
.
.
.
.
.
.
.
.
.
.
. . .
. .
. . .
. . .
. . .
. .
. .
. .
. .
.
.
.
.
.
.
.
.
.
. . . . . .
. . . . .
. . . . . . .
. . . . . . .
.
.
.
.
.
.
.
.
.
.
. . .
. .
. .
. .
. .
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
. . . . . . . . .
. . . . . . .
. . . . . . . . . .
. . . . . . . . . .
. . .
. .
. .
. .
. .
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
. . .
. .
. .
. .
. .
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
. . . 8
. . .8
. . . .8
. . . .9
.
.
.
.
.
. 12
. 12
. 13
. 13
. 14
S1D13506
X25B-G-011-02
Page 4
Epson Research and Development
Vancouver Design Center
THIS PAGE LEFT BLANK
S1D13506
X25B-G-011-02
Interfacing to the NEC VR4121™ Microprocessor
Issue Date: 01/02/08
Epson Research and Development
Vancouver Design Center
Page 5
List of Tables
Table 3-1: Host Bus Interface Pin Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 4-1: Summary of Power-On/Reset Options . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
List of Figures
Figure 2-1: NEC VR4121 Read/Write Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 4-1: NEC VR4121 to S1D13506 Configuration Schematic . . . . . . . . . . . . . . . . . . . 12
Interfacing to the NEC VR4121™ Microprocessor
Issue Date: 01/02/08
S1D13506
X25B-G-011-02
Page 6
Epson Research and Development
Vancouver Design Center
THIS PAGE LEFT BLANK
S1D13506
X25B-G-011-02
Interfacing to the NEC VR4121™ Microprocessor
Issue Date: 01/02/08
Epson Research and Development
Vancouver Design Center
Page 7
1 Introduction
This application note describes the hardware and software environment necessary to
provide an interface between the S1D13506 Color LCD/CRT/TV Controller and the NEC
VR4121TM (µPD30121) microprocessor.
The designs described in this document are presented only as examples of how such
interfaces might be implemented. This application note will be updated as appropriate.
Please check the Epson Electronics America website at http://www.eea.epson.com for the
latest revision of this document before beginning any development.
We appreciate your comments on our documentation. Please contact us via email at
[email protected]
Interfacing to the NEC VR4121™ Microprocessor
Issue Date: 01/02/08
S1D13506
X25B-G-011-02
Page 8
Epson Research and Development
Vancouver Design Center
2 Interfacing to the NEC V R 4121
2.1 The NEC VR4121 System Bus
The VR-Series family of microprocessors features a high-speed synchronous system bus
typical of modern microprocessors. Designed with external LCD controller support and
Windows CE based embedded consumer applications in mind, the VR4121 offers a highly
integrated solution for portable systems. This section provides an overview of the operation
of the CPU bus in order to establish interface requirements.
2.1.1 Overview
The NEC VR4121 is designed around the RISC architecture developed by MIPS. This
microprocessor is based on the 166MHz VR4120 CPU core which supports 64-bit
processing. The CPU communicates with the Bus Control Unit (BCU) using its internal
SysAD bus. The BCU in turn communicates with external devices using its ADD and
DATA buses which can be dynamically sized to 16 or 32-bit operation.
The NEC VR4121 has direct support for an external LCD controller. Specific control
signals are assigned for an external LCD controller providing an easy interface to the CPU.
A 16M byte block of memory is assigned for the LCD controller and its own chip select
and ready signals are available. Word or byte accesses are controlled by the system high
byte signal (SHB#).
S1D13506
X25B-G-011-02
Interfacing to the NEC VR4121™ Microprocessor
Issue Date: 01/02/08
Epson Research and Development
Vancouver Design Center
Page 9
2.1.2 LCD Memory Access Cycles
Once an address in the LCD block of memory is placed on the external address bus
(ADD[25:0]), the LCD chip select (LCDCS#) is driven low. The read or write enable
signals (RD# or WR#) are driven low for the appropriate cycle and LCDRDY is driven low
to insert wait states into the cycle. The high byte enable (SHB#) in conjunction with address
bit 0 allows for byte steering.
The following figure illustrates typical NEC VR4121 memory read and write cycles to the
LCD controller interface.
TCLK
ADD[25:0]
VALID
SHB#
LCDCS#
WR#,RD#
D[15:0]
(write)
VALID
Hi-Z
D[15:0]
(read)
VALID
Hi-Z
LCDRDY
Figure 2-1: NEC VR4121 Read/Write Cycles
Interfacing to the NEC VR4121™ Microprocessor
Issue Date: 01/02/08
S1D13506
X25B-G-011-02
Page 10
Epson Research and Development
Vancouver Design Center
3 S1D13506 Host Bus Interface
The S1D13506 directly supports multiple processors. The S1D13506 implements a 16-bit
MIPS/ISA Host Bus Interface which is most suitable for direct connection to the VR4121
microprocessor.
The MIPS/ISA Host Bus Interface is selected by the S1D13506 on the rising edge of
RESET#. After releasing reset the bus interface signals assume their selected configuration.
For details on S1D13506 configuration, see Section 4.2, “S1D13506 Configuration” on
page 13.
Note
At reset, the Register/Memory Select bit in the Miscellaneous Register (REG[001h] bit
7) is set to 1. This means that only REG[000h] (read-only) and REG[001h] are
accessible until a write to REG[001h] sets bit 7 to 0 making all registers accessible.
When debugging a new hardware design, this can sometimes give the appearance that
the interface is not working, so it is important to remember to clear this bit before
proceeding with debugging.
3.1 Host Bus Interface Pin Mapping
The following table shows the functions of each Host Bus Interface signal.
Table 3-1: Host Bus Interface Pin Mapping
S1D13506 Pin Name
AB20
AB[19:0]
DB[15:0]
WE1#
M/R#
CS#
BUSCLK
BS#
RD/WR#
RD#
WE0#
WAIT#
RESET#
S1D13506
X25B-G-011-02
NEC VR4121 Pin Name
ADD20
ADD[19:0]
DAT[15:0]
SHB#
ADD21
LCDCS#
BUSCLK
VDD
VDD
RD#
WR#
LCDRDY
connected to system reset
Interfacing to the NEC VR4121™ Microprocessor
Issue Date: 01/02/08
Epson Research and Development
Vancouver Design Center
Page 11
3.2 Host Bus Interface Signal Descriptions
The S1D13506 MIPS/ISA Host Bus Interface requires the following signals.
• BUSCLK is a clock input which is required by the S1D13506 Host Bus Interface. It is
separate from the input clock (CLKI) and is typically driven by the host CPU system
clock.
• The address inputs AB[20:0], and the data bus DB[15:0], connect directly to the
VR4121 address (ADD[20:0]) and data bus (DAT[15:0]), respectively. MD4 must be
set to select the proper endian mode upon reset.
• M/R# (memory/register) selects between memory or register access. It may be
connected to an address line, allowing system address ADD21 to be connected to the
M/R# line.
• Chip Select (CS#) must be driven low by LCDCS# whenever the S1D13506 is accessed
by the VR4121.
• WE1# connects to SHB# (the high byte enable signal from the VR4121) which in
conjunction with address bit 0 allows byte steering of read and write operations.
• WE0# connects to WR# (the write enable signal from the VR4121) and must be driven
low when the VR4121 bus is writing data to the S1D13506.
• RD# connects to RD# (the read enable signal from the VR4121) and must be driven low
when the VR4121 bus is reading data from the S1D13506.
• WAIT# connects to LCDRDY and is a signal output from the S1D13506 that indicates
the VR4121 bus must wait until data is ready (read cycle) or accepted (write cycle) on
the host bus. Since VR4121 bus accesses to the S1D13506 may occur asynchronously to
the display update, it is possible that contention may occur in accessing the S1D13506
internal registers and/or display buffer. The WAIT# line resolves these contentions by
forcing the host to wait until the resource arbitration is complete.
• The BS# and RD/WR# signals are not used for the MIPS/ISA Host Bus Interface and
should be tied high (connected to VDD).
Interfacing to the NEC VR4121™ Microprocessor
Issue Date: 01/02/08
S1D13506
X25B-G-011-02
Page 12
Epson Research and Development
Vancouver Design Center
4 V R 4121 to S1D13506 Interface
4.1 Hardware Description
The NEC VR4121 microprocessor is specifically designed to support an external LCD
controller. It provides all the necessary internal address decoding and control signals
required by the S1D13506.
The diagram below shows a typical implementation utilizing the S1D13506.
NEC VR4121
S1D13506
WR#
WE0#
SHB#
WE1#
RD#
RD#
LCDCS#
CS#
Pull-up
LCDRDY
WAIT#
System RESET
RESET#
M/R#
ADD21
ADD[25:0]
AB[20:0]
DAT[15:0]
DB[15:0]
BUSCLK
BUSCLK
VDD(+3.3V)
BS#
VDD3
VDD2
+3.3V
RD/WR#
+2.5V
VDD
Note:
When connecting the S1D13506 RESET# pin, the system designer should be aware of all
conditions that may reset the S1D13506 (e.g. CPU reset can be asserted during wake-up
from power-down modes, or during debug states).
Figure 4-1: NEC VR4121 to S1D13506 Configuration Schematic
Note
For pin mapping see Table 3-1:, “Host Bus Interface Pin Mapping,” on page 10.
S1D13506
X25B-G-011-02
Interfacing to the NEC VR4121™ Microprocessor
Issue Date: 01/02/08
Epson Research and Development
Vancouver Design Center
Page 13
4.2 S1D13506 Configuration
The S1D13506 latches MD15 through MD0 to allow selection of the bus mode and other
configuration data on the rising edge of RESET#. For details on configuration, refer to the
S1D13506 Hardware Functional Specification, document number X25B-A-001-xx.
The table below shows those configuration settings relevant to the MIPS/ISA Host Bus
Interface used by the NEC VR4121 microprocessor.
Table 4-1: Summary of Power-On/Reset Options
S1D13506
Pin Name
MD[3:1]
MD4
MD5
value on this pin at rising edge of RESET# is used to configure:(1/0)
1
0
101 = MIPS/ISA Host Bus Interface
Little Endian
Big Endian
WAIT# is active high (1 = insert wait state)
WAIT# is active low (0 = insert wait state)
MD11
Alternate Host Bus Interface Selected
Primary Host Bus Interface Selected
MD12
BUSCLK input divided by 2
BUSCLK input not divided
MD15
WAIT# is always driven
WAIT# is floating if S1D13506 is not selected
= configuration for NEC VR4121 microprocessor
4.3 NEC VR4121 Configuration
The NEC VR4121 register BCUCNTREG1 bit ISAM/LCD must be set to 0. A 0 indicates
that the reserved address space is for the LCD controller, and not for the high-speed ISA
memory. The register BCUCNTREG2 bit GMODE must be set to 1 to indicate that a
non-inverting data bus is used for LCD controller accesses.
The LCD interface must be set to operate using a 16-bit data bus. This is accomplished by
setting the NEC VR4121 register BCUCNTREG3 bit LCD32/ISA32 to 0.
Note
Setting the register BCUCNTREG3 bit LCD32/ISA32 to 0 affects both the LCD controller and high-speed ISA memory access.
The frequency of BUSCLK output is programmed from the state of pins TxD/CLKSEL2,
RTS#/CLKSEL1 and DTR#/CLKSEL0 during reset, and from the PMU (Power
Management Unit) configuration registers of the NEC VR4121. The S1D13506 works at
any of the frequencies provided by the NEC VR4121.
Interfacing to the NEC VR4121™ Microprocessor
Issue Date: 01/02/08
S1D13506
X25B-G-011-02
Page 14
Epson Research and Development
Vancouver Design Center
4.4 Memory Mapping and Aliasing
The NEC VR4121 provides the internal address decoding required by an external LCD
controller. The physical address range from 0A00 0000h to 0AFF FFFFh (16M bytes) is
reserved for use by an external LCD controller (e.g. S1D13506).
The S1D13506 supports up to 2M bytes of display buffer. The NEC VR4121 address line
ADD21 (connected to M/R#) is used to select between the S1D13506 display buffer
(ADD21=1) and the S1D13506 internal registers (ADD21=0). NEC VR4121 address lines
ADD[23:22] are ignored, thus the S1D13506 is aliased four times at 4M byte intervals over
the LCD controller address range. Address lines ADD[25:24] are set at 10b and never
change while the LCD controller is being addressed.
S1D13506
X25B-G-011-02
Interfacing to the NEC VR4121™ Microprocessor
Issue Date: 01/02/08
Epson Research and Development
Vancouver Design Center
Page 15
5 Software
Test utilities and Windows® CE v2.0 display drivers are available for the S1D13506. Full
source code is available for both the test utilities and the drivers.
The test utilities are configurable for different panel types using a program called
13506CFG, or by directly modifying the source. The Windows CE v2.0 display drivers can
be customized by the OEM for different panel types, resolutions and color depths only by
modifying the source.
The S1D13506 test utilities and Windows CE v2.0 display drivers are available from your
sales support contact or on the internet at http://www.eea.epson.com.
Interfacing to the NEC VR4121™ Microprocessor
Issue Date: 01/02/08
S1D13506
X25B-G-011-02
Page 16
Epson Research and Development
Vancouver Design Center
6 References
6.1 Documents
• NEC Electronics Inc., VR4121 Preliminary Users Manual, Document Number
U13569EJ1V0UM00.
• Epson Research and Development, Inc., S1D13506 Hardware Functional Specification,
Document Number X25B-A-001-xx.
• Epson Research and Development, Inc., S5U13506B00C Rev. 1.0 ISA Bus Evaluation
Board User Manual, Document Number X25B-G-004-xx.
• Epson Research and Development, Inc., S1D13506 Programming Notes and Examples,
Document Number X25B-G-003-xx.
6.2 Document Sources
• NEC Electronics Website: http://www.necel.com.
• Epson Electronics America Website: http://www.eea.epson.com.
S1D13506
X25B-G-011-02
Interfacing to the NEC VR4121™ Microprocessor
Issue Date: 01/02/08
Epson Research and Development
Vancouver Design Center
Page 17
7 Technical Support
7.1 Epson LCD/CRT Controllers (S1D13506)
Japan
Seiko Epson Corporation
Electronic Devices Marketing Division
421-8, Hino, Hino-shi
Tokyo 191-8501, Japan
Tel: 042-587-5812
Fax: 042-587-5564
http://www.epson.co.jp
Hong Kong
Epson Hong Kong Ltd.
20/F., Harbour Centre
25 Harbour Road
Wanchai, Hong Kong
Tel: 2585-4600
Fax: 2827-4346
North America
Epson Electronics America, Inc.
150 River Oaks Parkway
San Jose, CA 95134, USA
Tel: (408) 922-0200
Fax: (408) 922-0238
http://www.eea.epson.com
Taiwan, R.O.C.
Epson Taiwan Technology
& Trading Ltd.
10F, No. 287
Nanking East Road
Sec. 3, Taipei, Taiwan, R.O.C.
Tel: 02-2717-7360
Fax: 02-2712-9164
Europe
Epson Europe Electronics GmbH
Riesstrasse 15
80992 Munich, Germany
Tel: 089-14005-0
Fax: 089-14005-110
Singapore
Epson Singapore Pte., Ltd.
No. 1
Temasek Avenue #36-00
Millenia Tower
Singapore, 039192
Tel: 337-7911
Fax: 334-2716
7.2 NEC Electronics Inc. (VR4121).
NEC Electronics Inc. (U.S.A.)
Corporate Headquarters
2880 Scott Blvd.
Santa Clara, CA 95050-8062, USA
Tel: (800) 366-9782
Fax: (800) 729-9288
http://www.nec.com
http://www.vrseries.com
Interfacing to the NEC VR4121™ Microprocessor
Issue Date: 01/02/08
S1D13506
X25B-G-011-02
Page 18
Epson Research and Development
Vancouver Design Center
THIS PAGE LEFT BLANK
S1D13506
X25B-G-011-02
Interfacing to the NEC VR4121™ Microprocessor
Issue Date: 01/02/08
S1D13506 Color LCD/CRT/TV Controller
Interfacing to the NEC V832™
Microprocessor
Document Number: X25B-G-012-03
Copyright © 1999, 2001 Epson Research and Development, Inc. All Rights Reserved.
Information in this document is subject to change without notice.You may download and use this document, but only for your own use in
evaluating Seiko Epson/EPSON products. You may not modify the document. Epson Research and Development, Inc. disclaims any
representation that the contents of this document are accurate or current. The Programs/Technologies described in this document may contain
material protected under U.S. and/or International Patent laws.
EPSON is a registered trademark of Seiko Epson Corporation. All other trademarks are the property of their respective owners.
Microsoft and Windows are registered trademarks of Microsoft Corporation.
Page 2
Epson Research and Development
Vancouver Design Center
THIS PAGE LEFT BLANK
S1D13506
X25B-G-012-03
Interfacing to the NEC V832™ Microprocessor
Issue Date: 01/02/08
Epson Research and Development
Vancouver Design Center
Page 3
Table of Contents
1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2
Interfacing to the NEC V832 . . . .
2.1 The NEC V832 System Bus . . .
2.1.1 Overview . . . . . . . . . .
2.1.2 Access Cycles . . . . . . . .
3
S1D13506 Host Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.1 Host Bus Interface Pin Mapping . . . . . . . . . . . . . . . . . . . . . . . 10
3.2 Host Bus Interface Signal Descriptions . . . . . . . . . . . . . . . . . . . . 11
4
V832 to S1D13506 Interface . . . .
4.1 Hardware Description . . . . .
4.2 S1D13506 Hardware Configuration
4.3 NEC V832 Configuration . . . .
4.4 Memory Mapping and Aliasing .
5
Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
6
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
6.1 Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
6.2 Document Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
7
Technical Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
7.1 Epson LCD/CRT Controllers (S1D13506) . . . . . . . . . . . . . . . . . . . 18
7.2 NEC Electronics Inc. (V832). . . . . . . . . . . . . . . . . . . . . . . . . 18
Interfacing to the NEC V832™ Microprocessor
Issue Date: 01/02/08
.
.
.
.
.
.
.
.
.
. . .
. .
. . .
. . .
. . .
. .
. .
. .
. .
.
.
.
.
.
.
.
.
.
. . . . . .
. . . . .
. . . . . . .
. . . . . . .
.
.
.
.
.
.
.
.
.
.
. . .
. .
. .
. .
. .
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
. . . . . . . . .
. . . . . . .
. . . . . . . . . .
. . . . . . . . . .
. . .
. .
. .
. .
. .
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
. . .
. .
. .
. .
. .
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
. . . 8
. . .8
. . . .8
. . . .9
.
.
.
.
.
. 12
. 12
. 13
. 14
. 15
S1D13506
X25B-G-012-03
Page 4
Epson Research and Development
Vancouver Design Center
THIS PAGE LEFT BLANK
S1D13506
X25B-G-012-03
Interfacing to the NEC V832™ Microprocessor
Issue Date: 01/02/08
Epson Research and Development
Vancouver Design Center
Page 5
List of Tables
Table 3-1:
Table 4-1:
Table 4-2:
Table 4-3:
Host Bus Interface Pin Mapping . . . . . . . . . .
Summary of Power-On/Reset Options . . . . . . .
NEC V832 Wait States vs. Bus Clock Frequency .
NEC V832 IO Address Range For Each CSn Line
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
10
13
14
15
List of Figures
Figure 2-1: NEC V832 Read/Write Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 4-1: NEC V832 to S1D13506 Configuration Schematic . . . . . . . . . . . . . . . . . . . . 12
Interfacing to the NEC V832™ Microprocessor
Issue Date: 01/02/08
S1D13506
X25B-G-012-03
Page 6
Epson Research and Development
Vancouver Design Center
THIS PAGE LEFT BLANK
S1D13506
X25B-G-012-03
Interfacing to the NEC V832™ Microprocessor
Issue Date: 01/02/08
Epson Research and Development
Vancouver Design Center
Page 7
1 Introduction
This application note describes the hardware and software environment required to provide
an interface between the S1D13506 Color LCD/CRT/TV Controller and the NEC V832TM
microprocessor (µPD705102).
The designs described in this document are presented only as examples of how such
interfaces might be implemented. This application note is updated as appropriate. Please
check the Epson Electronics America Website at http://www.eea.epson.com for the latest
revision of this document before beginning any development.
We appreciate your comments on our documentation. Please contact us via email at
[email protected]
Interfacing to the NEC V832™ Microprocessor
Issue Date: 01/02/08
S1D13506
X25B-G-012-03
Page 8
Epson Research and Development
Vancouver Design Center
2 Interfacing to the NEC V832
2.1 The NEC V832 System Bus
This section provides an overview of the operation of the CPU bus in order to establish
interface requirements.
2.1.1 Overview
The NEC V832 is designed around the RISC architecture developed by MIPS. This
microprocessor is based on the 32-bit V830 CPU core. The CPU communicates with
external devices via the Bus Control Unit (BCU). The BCU in turn communicates using its
ADD and DATA buses which can be dynamically sized to 16 or 32-bit operation.
The NEC V832 features dedicated chip select pins which allow memory-mapped IO
operations. A 16M byte block of addressing space can be assigned for the LCD controller
and its own chip select and ready signals are available. Word or byte accesses are controlled
by system byte enable signals (LLBEN and LUBEN).
S1D13506
X25B-G-012-03
Interfacing to the NEC V832™ Microprocessor
Issue Date: 01/02/08
Epson Research and Development
Vancouver Design Center
Page 9
2.1.2 Access Cycles
Once an address in the appropriate range is placed on the external address bus (A[23:1]),
the corresponding chip select (CSn) is driven low. The read or write enable signals (IORD
or IOWR) are driven low and READY is driven low by the S1D13506 to insert wait states
into the cycle. The byte enable signals (LLBEN and LUBEN) allow byte steering.
The following figure illustrates typical NEC V832 memory-mapped IO access cycles.
SDCLKOUT
A[23:1]
VALID
LLBEN,
LUBEN
CSn
IORD,
IOWR
D[15:0]
(write)
VALID
Hi-Z
D[15:0]
(read)
VALID
Hi-Z
READY
Figure 2-1: NEC V832 Read/Write Cycles
Interfacing to the NEC V832™ Microprocessor
Issue Date: 01/02/08
S1D13506
X25B-G-012-03
Page 10
Epson Research and Development
Vancouver Design Center
3 S1D13506 Host Bus Interface
The S1D13506 directly supports multiple processors. The S1D13506 implements a 16-bit
PC Card (PCMCIA) Host Bus Interface which is most suitable for direct connection to the
V832 microprocessor.
The PC Card Host Bus Interface is selected by the S1D13506 on the rising edge of
RESET#. After releasing reset the bus interface signals assume their selected configuration.
For details on S1D13506 configuration, see Section 4.2, “S1D13506 Hardware Configuration” on page 13.
Note
At reset, the Register/Memory Select bit in the Miscellaneous Register (REG[001h] bit
7) is set to 1. This means that only REG[000h] (read-only) and REG[001h] are
accessible until a write to REG[001h] sets bit 7 to 0 making all registers accessible.
When debugging a new hardware design, this can sometimes give the appearance that
the interface is not working, so it is important to remember to clear this bit before
proceeding with debugging.
3.1 Host Bus Interface Pin Mapping
The following table shows the functions of each Host Bus Interface signal.
Table 3-1: Host Bus Interface Pin Mapping
S1D13506 Pin Name
NEC V832 Pin Name
AB[20:1]
A[20:1]
A0
GND1
DB[15:0]
D[15:0]
WE1#
LUBEN
M/R#
A21
CS#
CS3, CS4, CS5 or CS6
BUSCLK
SDCLKOUT
BS#
VDD (+3.3V)
RD/WR#
LLBEN
RD#
IORD
WE0#
IOWR
WAIT#
READY
RESET#
connected to system reset
Note
1
S1D13506
X25B-G-012-03
The bus signal A0 is not used by the S1D13506 internally.
Interfacing to the NEC V832™ Microprocessor
Issue Date: 01/02/08
Epson Research and Development
Vancouver Design Center
Page 11
3.2 Host Bus Interface Signal Descriptions
The S1D13506 PC Card Host Bus Interface requires the following signals.
• BUSCLK is a clock input which is required by the S1D13506 Host Bus Interface. It is
driven by the V832 signal SDCLKOUT.
• The address inputs AB[20:1], and the data bus DB[15:0], connect directly to the V832
address (A[20:1]) and data bus (D[15:0]), respectively. MD4 must be set to select little
endian mode upon reset.
• M/R# (memory/register) selects between memory or register access. It may be
connected to an address line, allowing system address A21 to be connected to the M/R#
line.
• Chip Select (CS#) must be driven low by CSx (where x is the V832 chip select used)
whenever the S1D13506 is accessed by the V832.
• WE1# and RD/WR# connect to LUBEN and LLBEN (the byte enables for the highorder and low-order bytes). They are driven low when the V832 is accessing the
S1D13506.
• RD# connects to IORD (the read enable signal from the V832).
• WE0# connects to IOWR (the write enable signal from the V832).
• WAIT# is a signal output from the S1D13506 that indicates the V832 must wait until
data is ready (read cycle) or accepted (write cycle) on the host bus. Since V832 accesses
to the S1D13506 may occur asynchronously to the display update, it is possible that
contention may occur in accessing the S1D13506 internal registers and/or display
buffer. The WAIT# line resolves these contentions by forcing the host to wait until the
resource arbitration is complete. For V832 applications, this signal should be set active
low using the MD5 configuration input.
• The Bus Start (BS#) signal is not used for the PC Card Host Bus Interface and should be
tied high (connected to V DD).
• The RESET# (active low) input of the S1D13506 may be connected to the system
RESET.
Interfacing to the NEC V832™ Microprocessor
Issue Date: 01/02/08
S1D13506
X25B-G-012-03
Page 12
Epson Research and Development
Vancouver Design Center
4 V832 to S1D13506 Interface
4.1 Hardware Description
The NEC V832 microprocessor features configurable chip select lines which can easily be
used for an external LCD controller. It provides all the necessary internal address decoding
and control signals required by the S1D13506.
The diagram below shows a typical implementation utilizing the S1D13506.
S1D13506
NEC V832
LLBEN
RD/WR#
LUBEN
WE1#
IORD
IOWR
RD#
WE0#
CS#
CSn
Pull-up
READY
WAIT#
System RESET
RESET#
A21
M/R#
A[20:1]
AB[20:1]
D[15:0]
DB[15:0]
SDCLKOUT
BUSCLK
VDD(+3.3V)
BS#
VDD_O
VDD_I
+3.3V
VDD
+2.5V
AB0
Note: When connecting the S1D13506 RESET# pin, the system designer should be aware of all
conditions that may reset the S1D13506 (e.g. CPU reset can be asserted during wake-up
from power-down modes, or during debug states).
Figure 4-1: NEC V832 to S1D13506 Configuration Schematic
Note
For pin mapping see Table 3-1:, “Host Bus Interface Pin Mapping,” on page 10.
S1D13506
X25B-G-012-03
Interfacing to the NEC V832™ Microprocessor
Issue Date: 01/02/08
Epson Research and Development
Vancouver Design Center
Page 13
4.2 S1D13506 Hardware Configuration
The S1D13506 latches MD15 through MD0 to allow selection of the bus mode and other
configuration data on the rising edge of RESET#. For details on configuration, refer to the
S1D13506 Hardware Functional Specification, document number X25B-A-001-xx.
The table below shows those configuration settings relevant to the PC Card Host Bus
Interface used by the NEC V832 microprocessor.
Table 4-1: Summary of Power-On/Reset Options
S1D13506
Pin Name
MD[3:1]
MD4
MD5
MD11
Value on this pin at rising edge of RESET# is used to configure: (1/0)
1
0
111 = PC Card Host Bus Interface
Little Endian
Big Endian
WAIT# is active high (1 = insert wait state)
WAIT# is active low (0 = insert wait state)
MD12
Alternate Host Bus Interface Selected
BUSCLK input divided by two
Primary Host Bus Interface Selected
BUSCLK input not divided by two
MD15
WAIT# is always driven
WAIT# is floating if S1D13506 is not
selected
= configuration for NEC V832 microprocessor
Interfacing to the NEC V832™ Microprocessor
Issue Date: 01/02/08
S1D13506
X25B-G-012-03
Page 14
Epson Research and Development
Vancouver Design Center
4.3 NEC V832 Configuration
The NEC V832 should access the S1D13506 in non-burst mode only. This is ensured by
using any one of the CS3 to CS6 lines to control the S1D13506 and setting that line to
respond to IO operations using the NEC V832 BCTC register. For example, if line CS5 is
used then bit 5 (CT5) of the BCTC register should be set to 1 (IO cycle).
The NEC V832 data bus should be programmed to use 16 bits as the maximum width for
S1D13506 bus transactions. This does not affect the width of other NEC V832 data bus
transactions. Data bus width is set in the NEC V832 DBC register. For example, if line CS4
is used then bit 4 (BW4) of the DBC register should be set to 1 (16-bit bus width).
Depending on bus clock frequencies, a different number of wait states may be required.
These need to be programmed into the NEC V832 PWC0 and PWC1 registers in the bit
field corresponding to the CSn line chosen for the S1D13506. For example, if CS3 is used
and one wait state is required, then bits 14-12 of the NEC V832 PWC0 register (WS3) must
be set to 001b (one wait state). If CS6 is used and no wait state is needed, then bits 11-8 of
the NEC V832 PWC1 register (WS6) must be set to 0000b (zero wait state).
The table below shows the recommended wait states depending on the bus clock frequency.
Table 4-2: NEC V832 Wait States vs. Bus Clock Frequency
Wait States
Maximum Frequency (SDCLKOUT)
0
10.8MHz
1
32.6MHz
2
No limit
No idle state needs to be added. The NEC V832 PIC0 and PIC1 register bit field
corresponding to the CSn line chosen for the S1D13506 must be set to zero. For example,
if CS3 is used then bits 14-12 of the NEC V832 PIC0 register (IS3) must be set to 000b (no
idle state).
S1D13506
X25B-G-012-03
Interfacing to the NEC V832™ Microprocessor
Issue Date: 01/02/08
Epson Research and Development
Vancouver Design Center
Page 15
4.4 Memory Mapping and Aliasing
The CSn line selected determines the address range to be reserved for the S1D13506. The
table below summarizes the S1D13506 address mapping.
Table 4-3: NEC V832 IO Address Range For Each CSn Line
CSn Line
CS3
CS4
CS5
CS6
NEC V832 IO Address
S1D13506 Function
0300 0000h
to
03FF FFFFh
0300 0000h
Registers
0320 0000h
Display buffer (2M bytes)
0400 0000h
to
04FF FFFFh
0400 0000h
Registers
0420 0000h
Display buffer (2M bytes)
0500 0000h
to
05FF FFFFh
0500 0000h
Registers
0520 0000h
Display buffer (2M bytes)
0600 0000h
to
06FF FFFFh
0600 0000h
Registers
0620 0000h
Display buffer (2M bytes)
Each address range is 16M bytes, therefore, the S1D13506 is aliased four times over the
address range.
Interfacing to the NEC V832™ Microprocessor
Issue Date: 01/02/08
S1D13506
X25B-G-012-03
Page 16
Epson Research and Development
Vancouver Design Center
5 Software
Test utilities and Windows® CE display drivers are available for the S1D13506. Full
source code is available for both the test utilities and the drivers.
The test utilities are configurable for different panel types using a program called
13506CFG, or by directly modifying the source. The Windows CE display drivers can be
customized by the OEM for different panel types, resolutions and color depths only by
modifying the source.
The S1D13506 test utilities and Windows CE display drivers are available from your sales
support contact or www.eea.epson.com.
S1D13506
X25B-G-012-03
Interfacing to the NEC V832™ Microprocessor
Issue Date: 01/02/08
Epson Research and Development
Vancouver Design Center
Page 17
6 References
6.1 Documents
• NEC Electronics Inc., V832 Preliminary Users Manual, Document Number
U13577EJ1V0UM00.
• Epson Research and Development, Inc., S1D13506 Hardware Functional Specification,
Document Number X25B-A-001-xx.
• Epson Research and Development, Inc., S5U13506B00C Rev. 1.0 ISA Bus Evaluation
Board User Manual, Document Number X25B-G-004-xx.
• Epson Research and Development, Inc., S1D13506 Programming Notes and Examples,
Document Number X25B-G-003-xx.
6.2 Document Sources
• NEC Electronics Website: http://www.necel.com.
• Epson Electronics America Website: http://www.eea.epson.com.
Interfacing to the NEC V832™ Microprocessor
Issue Date: 01/02/08
S1D13506
X25B-G-012-03
Page 18
Epson Research and Development
Vancouver Design Center
7 Technical Support
7.1 Epson LCD/CRT Controllers (S1D13506)
Japan
Seiko Epson Corporation
Electronic Devices Marketing Division
421-8, Hino, Hino-shi
Tokyo 191-8501, Japan
Tel: 042-587-5812
Fax: 042-587-5564
http://www.epson.co.jp
Hong Kong
Epson Hong Kong Ltd.
20/F., Harbour Centre
25 Harbour Road
Wanchai, Hong Kong
Tel: 2585-4600
Fax: 2827-4346
North America
Epson Electronics America, Inc.
150 River Oaks Parkway
San Jose, CA 95134, USA
Tel: (408) 922-0200
Fax: (408) 922-0238
http://www.eea.epson.com
Taiwan, R.O.C.
Epson Taiwan Technology
& Trading Ltd.
10F, No. 287
Nanking East Road
Sec. 3, Taipei, Taiwan, R.O.C.
Tel: 02-2717-7360
Fax: 02-2712-9164
Europe
Epson Europe Electronics GmbH
Riesstrasse 15
80992 Munich, Germany
Tel: 089-14005-0
Fax: 089-14005-110
Singapore
Epson Singapore Pte., Ltd.
No. 1
Temasek Avenue #36-00
Millenia Tower
Singapore, 039192
Tel: 337-7911
Fax: 334-2716
7.2 NEC Electronics Inc. (V832).
NEC Electronics Inc. (U.S.A.)
Corporate Headquarters
2880 Scott Blvd.
Santa Clara, CA 95050-8062, USA
Tel: (800) 366-9782
Fax: (800) 729-9288
http://www.necel.com
S1D13506
X25B-G-012-03
Interfacing to the NEC V832™ Microprocessor
Issue Date: 01/02/08
S1D13506 Color LCD/CRT/TV Controller
Interfacing to the StrongARM SA-1110
Processor
Document Number: X25B-G-013-03
Copyright © 1999, 2001 Epson Research and Development, Inc. All Rights Reserved.
Information in this document is subject to change without notice.You may download and use this document, but only for your own use in
evaluating Seiko Epson/EPSON products. You may not modify the document. Epson Research and Development, Inc. disclaims any
representation that the contents of this document are accurate or current. The Programs/Technologies described in this document may contain
material protected under U.S. and/or International Patent laws.
EPSON is a registered trademark of Seiko Epson Corporation. All other trademarks are the property of their respective owners.
Page 2
Epson Research and Development
Vancouver Design Center
THIS PAGE LEFT BLANK
S1D13506
X25B-G-013-03
Interfacing to the StrongARM SA-1110 Processor
Issue Date: 01/02/08
Epson Research and Development
Vancouver Design Center
Page 3
Table of Contents
1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2
Interfacing to the StrongARM SA-1110 Bus
2.1 The StrongARM SA-1110 System Bus . .
2.1.1 StrongARM SA-1110 Overview . . .
2.1.2 Variable-Latency IO Access Overview
2.1.3 Variable-Latency IO Access Cycles .
3
S1D13506 Host Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.1 Host Bus Interface Pin Mapping . . . . . . . . . . . . . . . . . . . . . . . 11
3.2 Host Bus Interface Signal Descriptions . . . . . . . . . . . . . . . . . . . . 12
4
StrongARM SA-1110 to S1D13506 Interface
4.1 Hardware Description . . . . . . . . .
4.2 S1D13506 Hardware Configuration . . . .
4.3 Performance . . . . . . . . . . . . .
4.4 Register/Memory Mapping . . . . . . .
4.5 StrongARM SA-1110 Register Configuration
5
Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
6
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.1 Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.2 Document Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
7
Technical Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
7.1 EPSON LCD/CRT Controllers (S1D13506) . . . . . . . . . . . . . . . . . . 19
7.2 Intel StrongARM SA-1110 Micro-processor . . . . . . . . . . . . . . . . . . 19
Interfacing to the StrongARM SA-1110 Processor
Issue Date: 01/02/08
. . . . . .
. . . . .
. . . . . . .
. . . . . . .
. . . . . . .
.
.
.
.
.
.
.
.
.
.
.
.
. . .
. .
. .
. .
. .
. .
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
. . . . . . .
. . . . . .
. . . . . . . .
. . . . . . . .
. . . . . . . .
.
.
.
.
.
.
. . .
. .
. .
. .
. .
. .
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
. . .
. .
. . .
. . .
. . .
. . .
. .
. .
. .
. .
. .
.
.
.
.
.
.
.
.
.
.
.
. . . . 8
. . . .8
. . . . .8
. . . . .8
. . . . .9
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
13
13
14
14
15
16
S1D13506
X25B-G-013-03
Page 4
Epson Research and Development
Vancouver Design Center
THIS PAGE LEFT BLANK
S1D13506
X25B-G-013-03
Interfacing to the StrongARM SA-1110 Processor
Issue Date: 01/02/08
Epson Research and Development
Vancouver Design Center
Page 5
List of Tables
Table 3-1:
Table 4-1:
Table 4-2:
Table 4-3:
Host Bus Interface Pin Mapping . . . . . . . . . . . . . .
Summary of Power-On/Reset Options . . . . . . . . . . .
Register/Memory Mapping for Typical Implementation .
RDFx Parameter Value versus CPU Maximum Frequency
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
11
14
15
16
List of Figures
Figure 2-1: SA-1110 Variable-Latency IO Read Cycle. . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 2-2: SA-1110 Variable-Latency IO Write Cycle . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 4-1: Typical Implementation of SA-1110 to S1D13506 Interface . . . . . . . . . . . . . . . 13
Interfacing to the StrongARM SA-1110 Processor
Issue Date: 01/02/08
S1D13506
X25B-G-013-03
Page 6
Epson Research and Development
Vancouver Design Center
THIS PAGE LEFT BLANK
S1D13506
X25B-G-013-03
Interfacing to the StrongARM SA-1110 Processor
Issue Date: 01/02/08
Epson Research and Development
Vancouver Design Center
Page 7
1 Introduction
This application note describes the hardware and software environment required to provide
an interface between the S1D13506 Color LCD/CRT/TV Controller and the Intel
StrongARM SA-1110.
The designs described in this document are presented only as examples of how such
interfaces might be implemented. This application note is updated as appropriate. Please
check the Epson Electronics America website at http://www.eea.epson.com for the latest
revision of this document before beginning any development.
We appreciate your comments on our documentation. Please contact us via email at
[email protected]
Interfacing to the StrongARM SA-1110 Processor
Issue Date: 01/02/08
S1D13506
X25B-G-013-03
Page 8
Epson Research and Development
Vancouver Design Center
2 Interfacing to the StrongARM SA-1110 Bus
2.1 The StrongARM SA-1110 System Bus
The StrongARM SA-1110 microprocessor is a highly integrated communications microcontroller that incorporates a 32-bit StrongARM RISC processor core. The SA-1110 is
ideally suited to interface to the S1D13506 LCD controller and provides a high performance, power efficient solution for embedded systems.
2.1.1 StrongARM SA-1110 Overview
The SA-1110 system bus can access both variable-latency IO and memory devices. The
SA-1110 uses a 26-bit address bus and a 32-bit data bus which can be used to access 16-bit
devices. A chip select module with six chip select signals (each accessing 64M bytes of
memory) allows selection of external devices. Only chip selects 3 through 5 (nCS[5:3])
may be used to select variable-latency devices which use RDY to extend access cycles.
These chip selects are individually programmed in the SA-1110 memory configuration
registers and can be configured for either a 16 or 32-bit data bus.
Byte steering is implemented using the four signals nCAS[3:0]. Each signal selects a byte
on the 32-bit data bus. For example, nCAS0 selects bits D[7:0] and nCAS3 selects bits
D[31:24]. For a 16-bit data bus, only nCAS[1:0] are used with nCAS0 selecting the low
byte and nCAS1 selecting the high byte. The SA-1110 can be configured to support little
or big endian mode.
2.1.2 Variable-Latency IO Access Overview
A data transfer is initiated when a memory address is placed on the SA-1110 system bus
and a chip select signal (nCS[5:3]) is driven low. If all byte enable signals (nCAS[3:0]) are
driven low, then a 32-bit transfer takes place. If only nCAS[1:0] are driven low, then a word
transfer takes place over a 16-bit bus interface. If only one byte enable is driven low, then
a byte transfer takes place on the respective data lines.
During a read cycle, the output enable signal (nOE) is driven low. A write cycle is specified
by driving nOE high and driving the write enable signal (nWE) low. The cycle can be
lengthened by driving RDY high for the time needed to complete the cycle.
S1D13506
X25B-G-013-03
Interfacing to the StrongARM SA-1110 Processor
Issue Date: 01/02/08
Epson Research and Development
Vancouver Design Center
Page 9
2.1.3 Variable-Latency IO Access Cycles
The first nOE assertion occurs two memory cycles after the assertion of chip select (nCS3,
nCS4, or nCS5). Two memory cycles prior to the end of minimum nOE or nWE assertion
(RDF+1 memory cycles), the SA-1110 starts sampling the data ready input (RDY).
Samples are taken every half memory cycle until three consecutive samples (at the rising
edge, falling edge, and following rising edge of the memory clock) indicate that the IO
device is ready for data transfer. Read data is latched one-half memory cycle after the third
successful sample (on falling edge). Then nOE or nWE is deasserted on the next rising edge
and the address may change on the subsequent falling edge. Prior to a subsequent data
cycle, nOE or nWE will remain deasserted for RDN+1 memory cycles. The chip select and
byte selects (nCAS/DQM[1:0] for 16-bit data transfers), remain asserted for one memory
cycle after the final nOE or nWE deassertion of the burst.
The SA-1110 is capable of burst cycles during which the chip select remains low while the
read or write command is asserted, precharged and reasserted repeatedly.
Figure 2-1: illustrates a typical variable-latency IO access read cycle on the SA-1110 bus.
A[25:0]
ADDRESS VALID
nCS4
nOE
nWE
RDY
D[31:0]
DATA VALID
nCAS[3:0]
Figure 2-1: SA-1110 Variable-Latency IO Read Cycle
Interfacing to the StrongARM SA-1110 Processor
Issue Date: 01/02/08
S1D13506
X25B-G-013-03
Page 10
Epson Research and Development
Vancouver Design Center
Figure 2-2: illustrates a typical variable-latency IO access write cycle on the SA-1110 bus.
A[25:0]
ADDRESS VALID
nCS4
nWE
nOE
RDY
D[31:0]
DATA VALID
nCAS[3:0]
Figure 2-2: SA-1110 Variable-Latency IO Write Cycle
S1D13506
X25B-G-013-03
Interfacing to the StrongARM SA-1110 Processor
Issue Date: 01/02/08
Epson Research and Development
Vancouver Design Center
Page 11
3 S1D13506 Host Bus Interface
The S1D13506 directly supports multiple processors. The S1D13506 implements a 16-bit
PC Card (PCMCIA) Host Bus Interface which is most suitable for direct connection to the
SA-1110.
The PC Card Host Bus Interface is selected by the S1D13506 on the rising edge of
RESET#. After releasing reset the bus interface signals assume their selected configuration.
For details on S1D13506 configuration, see Section 4.2, “S1D13506 Hardware Configuration” on page 14.
Note
At reset, the Register/Memory Select bit in the Miscellaneous Register (REG[001h] bit
7) is set to 1. This means that only REG[000h] (read-only) and REG[001h] are
accessible until a write to REG[001h] sets bit 7 to 0 making all registers accessible.
When debugging a new hardware design, this can sometimes give the appearance that
the interface is not working, so it is important to remember to clear this bit before
proceeding with debugging.
3.1 Host Bus Interface Pin Mapping
The following table shows the functions of each Host Bus Interface signal.
Table 3-1: Host Bus Interface Pin Mapping
S1D13506 Pin Name
AB[20:1]1
DB[15:0]
WE1#
M/R#
CS#
BUSCLK
BS#
RD/WR#
RD#
WE0#
WAIT#
RESET#
SA-1110
A[20:1]1
D[15:0]
nCAS1
A21
nCS4
SDCLK2
VDD
nCAS0
nOE
nWE
RDY
system RESET
Note
1
The bus signal A0 is not used by the S1D13506 internally.
Interfacing to the StrongARM SA-1110 Processor
Issue Date: 01/02/08
S1D13506
X25B-G-013-03
Page 12
Epson Research and Development
Vancouver Design Center
3.2 Host Bus Interface Signal Descriptions
The S1D13506 PC Card Host Bus Interface requires the following signals.
• BUSCLK is a clock input which is required by the S1D13506 Host Bus Interface. It is
driven by one of the SA-1110 signals SDCLK1 or SDCLK2 (the example implementation in this document uses SDCLK2). For further information, see Section 4.3, “Performance” on page 14.
• The address inputs AB[20:1], and the data bus DB[15:0], connect directly to the
SA-1110 address (A[20:1]) and data bus (D[15:0]), respectively. MD4 must be set to
select little endian mode upon reset.
• M/R# (memory/register) selects between memory or register access. It may be
connected to an address line, allowing system address A21 to be connected to the M/R#
line.
• Chip Select (CS#) must be driven low by nCSx (where x is the SA-1110 chip select
used) whenever the S1D13506 is accessed by the SA-1110.
• WE1# and RD/WR# connect to nCAS1 and nCAS0 (the byte enables for the high-order
and low-order bytes). They are driven low when the SA-1110 is accessing the
S1D13506.
• RD# connects to nOE (the read enable signal from the SA-1110).
• WE0# connects to nWE (the write enable signal from the SA-1110).
• WAIT# is a signal output from the S1D13506 that indicates the SA-1110 must wait until
data is ready (read cycle) or accepted (write cycle) on the host bus. Since SA-1110
accesses to the S1D13506 may occur asynchronously to the display update, it is possible
that contention may occur in accessing the S1D13506 internal registers and/or display
buffer. The WAIT# line resolves these contentions by forcing the host to wait until the
resource arbitration is complete. For the SA-1110, this signal should be set active low
using the MD5 configuration input.
• The Bus Start (BS#) signal is not used for this Host Bus Interface and should be tied
high (connected to VDD).
• The RESET# (active low) input of the S1D13506 may be connected to the system
RESET.
S1D13506
X25B-G-013-03
Interfacing to the StrongARM SA-1110 Processor
Issue Date: 01/02/08
Epson Research and Development
Vancouver Design Center
Page 13
4 StrongARM SA-1110 to S1D13506 Interface
4.1 Hardware Description
The S1D13506 is designed to directly support a variety of CPUs, providing an interface to
each processor’s unique “local bus”. Using the S1D13506’s PC Card Host Bus Interface
provides a “glueless” interface to the SA-1110.
In this implementation, the address inputs (AB[20:1]) and data bus (DB[15:0]) connect
directly to the CPU address (A[20:1]) and data bus (D[15:0]). M/R# is treated as an address
line so that it can be controlled using system address A21.
BS# (Bus Start) is not used and should be tied high (connected to VDD).
The following diagram shows a typical implementation of the SA-1110 to S1D13506
interface.
S1D13506
SA-1110
VDDX
nOE
nWE
+3.3V
+3.3V
VDD
RD#
WE0#
nCAS0
nCAS1
RD/WR#
WE1#
System RESET
+3.3V
nCS4
A21
RESET#
BS#
CS#
M/R#
A[20:1]
AB[20:1]
D[15:0]
DB[15:0]
WAIT#
RDY
SDCLK2
BUSCLK
Oscillator
CLKI
Note:
When connecting the S1D13506 RESET# pin, the system designer should be aware of all
conditions that may reset the S1D13506 (e.g. CPU reset can be asserted during wake-up
from power-down modes, or during debug states).
Figure 4-1: Typical Implementation of SA-1110 to S1D13506 Interface
Interfacing to the StrongARM SA-1110 Processor
Issue Date: 01/02/08
S1D13506
X25B-G-013-03
Page 14
Epson Research and Development
Vancouver Design Center
4.2 S1D13506 Hardware Configuration
The S1D13506 latches MD15 through MD0 to allow selection of the bus mode and other
configuration data on the rising edge of RESET#. For details on configuration, refer to the
S1D13506 Hardware Functional Specification, document number X25B-A-001-xx.
The table below shows only those configuration settings important to the PC Card Host Bus
Interface.
Table 4-1: Summary of Power-On/Reset Options
MD[3:1]
MD4
MD5
value on this pin at rising edge of RESET# is used to configure:(1/0)
1
0
111 = PC Card Host Bus Interface selected
Little Endian
Big Endian
WAIT# is active high (1 = insert wait state)
WAIT# is active low (0 = insert wait state)
MD11
MD12
Alternate Host Bus Interface Selected
BUSCLK input divided by two
Primary Host Bus Interface Selected
BUSCLK input not divided by two
MD15
WAIT# is always driven
WAIT# is tristated when the chip is not accessed by
the host
S1D13506
Pin Name
= configuration for PC Card Host Bus Interface
4.3 Performance
The S1D13506 PC Card Interface specification supports a BUSCLK up to 50MHz, and
therefore provides a high performance display solution.
The BUSCLK signal input to the S1D13506 (from one of the SDCLK[2:1] pins) is a
derivative of the SA-1110 internal processor speed. Since the PC Card Host Bus Interface
on the S1D13506 has a maximum BUSCLK of 50MHz, the output clock from the SA-1110
must be a divided down from the processor clock. The DRAM Refresh Control Register
(MDREFR) determines the output of this signal.
• If SDCLK2 is used, bit 26 should be set to 1 to divide the CPU clock by 4.
• If SDCLK1 is used, bit 22 should be set to 1 to divide the CPU clock by 4.
S1D13506
X25B-G-013-03
Interfacing to the StrongARM SA-1110 Processor
Issue Date: 01/02/08
Epson Research and Development
Vancouver Design Center
Page 15
4.4 Register/Memory Mapping
The S1D13506 is a memory mapped device. The SA-1110 will use the memory assigned
to a chip select (nCS4 in this example) to map the S1D13506 internal registers and display
buffer. The internal registers require 2M bytes of memory and are mapped to the lower
memory address space starting at zero. The display buffer also requires 2M bytes and is
mapped in the third and fourth megabytes (ranging from 200000h to 3FFFFFh).
This implementation decodes as shown in the following table.
Table 4-2: Register/Memory Mapping for Typical Implementation
M/R# (A21)
Address Range
Function
0
0 - 1F FFFFh
Internal Registers
1
20 0000h - 3F FFFFh
Display Buffer
Each chip select on the SA-1110 provides 64M bytes of address space. Without further
resolution of the decoding logic (M/R# connected to A21), the entire register set and
display buffer are aliased for every 4M byte boundary within the specified address range of
the chip select. Since address bits A[25:22] are ignored, the S1D13506 registers and display
buffer are aliased 16 times.
Note
If aliasing is not desirable, the upper addresses must be fully decoded.
Interfacing to the StrongARM SA-1110 Processor
Issue Date: 01/02/08
S1D13506
X25B-G-013-03
Page 16
Epson Research and Development
Vancouver Design Center
4.5 StrongARM SA-1110 Register Configuration
The SA-1110 requires configuration of several of its internal registers to interface to the
S1D13506 PC Card Host Bus Interface.
• The Static Memory Control Registers (MSC[2:0]) are read/write registers containing
control bits for configuring static memory or variable-latency IO devices. These registers correspond to chip select pairs nCS[5:4], nCS[3:2], and nCS[1:0] respectively. Each
of the three registers contains two identical CNFG fields, one for each chip select within
the pair. Since only nCS[5:3] controls variable-latency IO devices, MSC2 and MSC1
should be programmed based on the chip select used.
Parameter RTx<1:0> should be set to 01b (selects variable-latency IO mode).
Parameter RBWx should be set to 1 (selects 16-bit bus width).
Parameter RDFx<4:0> should be set according to the maximum desired CPU
frequency as indicated in the table below.
Table 4-3: RDFx Parameter Value versus CPU Maximum Frequency
CPU Frequency
147.5MHz
206.4MHz
Up to SA-1110 maximum
RDFx
2
3
4
Parameter RDNx<4:0> should be set to 0 (minimum command precharge time).
Parameter RRRx<2:0> should be set to 0 (minimum nCSx precharge time).
• The S1D13506 endian mode is set to little endian. To program the SA-1110 for little
endian as well use the control register (register 1).
• Bit 7 must be set to 0.
• The BUSCLK signal input to the S1D13506 (from one of the SDCLK[2:1] pins) is a
derivative of the SA-1110 internal processor speed. Since the PC Card Host Bus Interface on the S1D13506 has a maximum BUSCLK of 50MHz, the output clock from the
SA-1110 must be a divided down from the processor clock. The DRAM Refresh
Control Register (MDREFR) determines the output of this signal.
• If SDCLK2 is used, bit 26 should be set to 1 to divide the CPU clock by 4.
• If SDCLK1 is used, bit 22 should be set to 1 to divide the CPU clock by 4.
S1D13506
X25B-G-013-03
Interfacing to the StrongARM SA-1110 Processor
Issue Date: 01/02/08
Epson Research and Development
Vancouver Design Center
Page 17
5 Software
Test utilities and Windows® CE display drivers are available for the S1D13506. Full
source code is available for both the test utilities and the drivers.
The test utilities are configurable for different panel types using a program called
13506CFG, or by directly modifying the source. The Windows CE display drivers can be
customized by the OEM for different panel types, resolutions and color depths only by
modifying the source.
The S1D13506 test utilities and Windows CE display drivers are available from your sales
support contact or on the internet at http://www.eea.epson.com.
Interfacing to the StrongARM SA-1110 Processor
Issue Date: 01/02/08
S1D13506
X25B-G-013-03
Page 18
Epson Research and Development
Vancouver Design Center
6 References
6.1 Documents
• Intel Corporation, StrongARM® SA-1110 Microprocessor Advanced Developer’s
Manual, Order Number 278240-001.
• Epson Research and Development, Inc., S1D13506 Hardware Functional Specification,
Document Number X25B-A-001-xx.
• Epson Research and Development, Inc., S1D13506 Programming Notes and Examples,
Document Number X25B-G-003-xx.
• Epson Research and Development, Inc., S5U13506B00C Rev. 1.0 ISA Bus Evaluation
Board User Manual, Document Number X25B-G-004-xx.
6.2 Document Sources
• Intel Developers Website: http://developer.intel.com.
• Intel Literature contact: 1(800) 548-4725.
• Epson Electronics America Website: http://www.eea.epson.com.
S1D13506
X25B-G-013-03
Interfacing to the StrongARM SA-1110 Processor
Issue Date: 01/02/08
Epson Research and Development
Vancouver Design Center
Page 19
7 Technical Support
7.1 EPSON LCD/CRT Controllers (S1D13506)
Japan
Seiko Epson Corporation
Electronic Devices Marketing Division
421-8, Hino, Hino-shi
Tokyo 191-8501, Japan
Tel: 042-587-5812
Fax: 042-587-5564
http://www.epson.co.jp
North America
Epson Electronics America, Inc.
150 River Oaks Parkway
San Jose, CA 95134, USA
Tel: (408) 922-0200
Fax: (408) 922-0238
http://www.eea.epson.com
Taiwan, R.O.C.
Epson Taiwan Technology
& Trading Ltd.
10F, No. 287
Nanking East Road
Sec. 3, Taipei, Taiwan, R.O.C.
Tel: 02-2717-7360
Fax: 02-2712-9164
Hong Kong
Epson Hong Kong Ltd.
20/F., Harbour Centre
25 Harbour Road
Wanchai, Hong Kong
Tel: 2585-4600
Fax: 2827-4346
Europe
Epson Europe Electronics GmbH
Riesstrasse 15
80992 Munich, Germany
Tel: 089-14005-0
Fax: 089-14005-110
Singapore
Epson Singapore Pte., Ltd.
No. 1
Temasek Avenue #36-00
Millenia Tower
Singapore, 039192
Tel: 337-7911
Fax: 334-2716
7.2 Intel StrongARM SA-1110 Micro-processor
INTEL
Intel Customer Support (ICS) for StrongARM: (800) 628-8686
Website for StrongARM Processor http://developer.intel.com/design/strong/
Interfacing to the StrongARM SA-1110 Processor
Issue Date: 01/02/08
S1D13506
X25B-G-013-03
Page 20
Epson Research and Development
Vancouver Design Center
THIS PAGE LEFT BLANK
S1D13506
X25B-G-013-03
Interfacing to the StrongARM SA-1110 Processor
Issue Date: 01/02/08