PF836-02 SED1670 SED1670 Dot Matrix High Duty LCD Driver ● 100 Output ● 1/64 to 1/300 in display duty ● CMOS High Voltage Resistant Process ■ OVERVIEW The SED1670 is a 100 output low-power resistance common (row) driver which is suitable for driving a very high capacity dotmatrix LCD panels upto a duty ratio of 1/300. It is intended to be used in conjunction with the SED1640D or SED1606D as a pair. Since the SED1670 is so designed to drive LCDs over a wide range of voltages, and also the maximum potential V0 of its LCD drive bias voltages is isolated from VDD to allow the LCD driving bias voltages to be externally generated optionally with a high accuracy, it can cope with a wide range of LCD panels. Owing to its pad layout which can minimize its PC boards mounting space in addition to its selectable bidirectional driver output sequence and as many as 100 LCD output segments of high pressure resistance and low output impedance, it is possible to obtain the highest driver working efficiency for the 1/200 duty panel. And the SED1670 can display 65 x 132 panel when used as a common driver of RAM buit-in driver, SED1531. ■ FEATURES ● ● ● ● ● ● ● ● ● ● ● Number of LCD drive output segments: 100 Common output ON resistance: 700Ω (Typ.) Display duty ratio: 1/64 to 1/300 (Reference) Display capacity: Possible to display 640 x 480 dots when used in combination with SED 1640D or SED1606D. Selectable pin output shift direction No-bias display OFF function (*1*) Instantaneous display blanking enabled by inhibit function (*0*) Adjustable offset bias of LCD power to VDD level Wide range of LCD drive voltages: –7 V to –28 V (Absolute maximum rated voltage: –30 V) Logic system power supply: –2.7 V to –5.5 V Chip packaging SED1670D0A (Al-pad die form) SED1670D1A SED1670D0B (Au bump die form) SED1670D1B SED1670T0A (TCP die form) * Under Planning SED1670T1A * Under Planning ● No radial rays countermeasure taken in designing 1 SED1670 ■ BLOCK DIAGRAM COM0 COM1COM2 ············ COM99 VDD ············ VSS V1 V4 LCD driver 100 bit V0 V5 Voltage control circuit FR shift register 100 bit DIO1 DIO2 shift register 100 bit YSCL SHL DOFF INH INH in SED16700* DOFF in SED16701* 2 SED1670 • PAD LAYOUT AND COORDINATES 57 92 56 93 Y X (0,0) 37 112 1 36 Chip size .............................. 5.49mm x 3.03mm 1) Au bump specification reference values Bump specific : High Quarity Au bump Bump size : 100µm x 113µm Bump height : 17µm - 28µm 2) Al Pad specification reference values Pad Opening : 100µm x 100µm 3 SED1670 NO. PAD NAME Actual dimensions X Y NO. PAD NAME 1 COM5 -2187 2 6 -2058 NO. PAD NAME 41 COM45 42 46 -711 81 COM85 -803 -581 82 86 -932 3 7 4 8 -1929 43 47 -1799 44 48 -452 83 87 -1062 -323 84 88 5 9 -1670 45 -1191 49 -194 85 89 6 10 -1541 -1320 46 50 -65 89 90 7 11 -1449 -1412 47 51 65 87 91 8 -1578 12 -1283 48 52 194 88 92 -1708 9 13 -1153 49 53 323 89 93 -1837 10 14 -1024 50 54 452 90 94 -1966 11 15 -895 51 55 581 91 95 -2095 12 16 -766 52 56 711 92 96 -2224 1357 13 17 -637 53 57 840 93 97 -2473 1334 14 18 -507 54 58 969 94 98 1201 15 19 -378 55 59 1098 95 99 1071 16 20 -249 56 60 2584 1231 96 DIO2 941 17 21 -120 57 61 2298 1357 97 DOFF 715 (INH) -1357 Actual dimensions X Y 2584 Actual dimensions X Y 1357 18 22 10 58 62 2168 (97) 19 23 139 59 63 2039 98 FR 20 24 268 60 64 1910 99 YSCL 455 21 25 397 61 65 1781 100 SHL 325 22 26 526 62 66 1652 101 VDD 185 23 27 656 63 67 1522 102 VSS 46 24 28 785 64 68 1393 103 V0 -112 25 29 914 65 69 1264 104 V1 -252 26 30 1043 66 70 1135 105 V4 -391 27 31 1172 67 71 1006 106 V5 -531 28 32 1302 68 72 876 107 DIO1 -671 29 33 1431 69 73 747 108 COM0 -810 30 34 1560 70 74 618 109 1 -941 31 35 1689 71 75 489 110 2 -1071 32 36 1818 72 76 360 111 3 33 37 1948 73 77 230 112 4 34 38 2077 74 78 101 35 39 2206 75 79 -28 36 40 2335 -1357 76 80 -157 37 41 2584 -1231 77 81 -286 38 42 2584 -1094 78 82 -416 39 43 2584 -969 79 83 -545 40 44 2584 -840 80 84 -674 585 -1201 -2473 -1334 1357 PAD No. 97: INH for SED1670 0* * DOFF for SED1670 1* * 4 SED1670 • ABSOLUTE MAXIMUM RATINGS VDD=0V Parameter Symbol Rating Unit Supply voltage (1) VSS –7.0 to +0.3 V Supply voltage (2) V5 –30.0 to +0.3 V Supply voltage (3) V0, V1, V4 V5–0.3 to +0.3 V VSS–0.3 to +0.3 V VSS–0.3 to +0.3 V Input voltageVI Output voltage VO Output current (1) IO 20 mA Output current (2) IOCOM 20 mA Operating temperature Topr –40 to + 85 °C Storing temperature 1 Tstg –65 to +150 °C > V0 = > V1 = > V4 = > V5. Notes: 1. The voltage of V0, V1 and V4 must always satisfy the condition of VDD = 2. Floating of the logic system power during while the LCD drive system power is applied, or exceeding VSS = –2.6 V or more can cause permanent damage to the LSI. Functional operation under these conditions is not implied. Care should be taken to the power supply sequence especially in the system power ON or OFF. 5 SED1670 • ELECTRICAL CHARACTERISTICS ● DC characteristics (Unless otherwise specified, VDD = V0 = 0V, VSS = –5.0V±10%, Ta = –40 to 85°C.) Parameter Supply voltage (1) Recommended operating voltage Operation enable voltage Supply voltage (2) Supply voltage (3) Supply voltage (4) “H” input voltage (1) “L” input voltage (1) “H” input voltage (2) “L” input voltage (2) “H” output voltage “L” output voltage Input leakage current Input/output leakage current Static current Symbol VSS Condition – Min. –5.5 Typ. –5.0 Max. –2.7 Unit V Applicable pin VSS V5 – –28.0 – –7.0 V V5 V5 V0 V1 V4 VIH VIL VIHT VILT Functional operation Recommended value Recommended value Recommended value – –2.5 2/9·V5 V5 0.2VSS VSS 0.2VSS VSS – – – – – – – – –7.0 0 VDD 7/9·V5 0 0.8VSS 0 0.85VSS V V V V V V V V V5 V0 V1 V4 –0.4 – 0 V VOH VOL IOH=–0.3mA IOH=–0.2mA (VSS=–2.7 to –4.5V) IOL=+0.3mA IOL=+0.2mA (VSS=–2.7 to –4.5V) DIO1, DIO2 VSS – VSS+0.4 V – – 2.0 µA YSCL, SHL, DOFF, INH, FR ILI/O VSS ≤ VIN ≤ 0V – – 5.0 µA DIO1, DIO2 – – 25 µA VDD – 0.70 1.40 KΩ COM0~COM99 µA VSS µA V5 RCOM ISS1 Average operating current consumption (2) ISS2 V5=–7.0 to –28.0V VIH=VDD, VIL=VSS When the V1, V4, V0 or ∆VON V5= =0.5V –20.0V V5 level is output VSS=–5.0V, VIH=VDD, VIL=VSS, fYSCL=12KHz, Frame frequency=60Hz – 7 15 Input data; “H” at no load every 1/200 duty ------------------------------------------------------Other conditions are the same – 5 10 as VSS = –3.0 V VSS=–5.0, V,=–2.0V, V4=–18.0V, V5=–20.0V – 7 15 Other conditions are the same as in the item of ISS1. CI – – 8 pF YSCL, SHL, DOFF, INH, FR – – 15 pF DIO1, DIO2 Ta=25°C Input/output pin capacitance 6 DOFF, INH VSS ≤ VIN ≤ 0V Average operating current consumption (1) Input pin capacitance VSS=–2.7V to –5.5V DIO1, DIO2, YSCL, SHL, FR ILI IDDS Output resistance VSS=–2.7V to –5.5V CI/O SED1670 • DIFFERENT POINTS FROM REPLACEMENT PRODUCT SED1670*0* SED1631*** Function Bidirectional shift register INH 100 output segments Bidirectional shift register INH 100 output segments Output Tr configuration Fig. 1 Fig. 2 PAD layout Identical to the equivalent product – PAD coordinates Different from the equivalent product – SED1670*1* SED1635*** Function Bidirectional shift register DOFF 100 output segments Bidirectional shift register DOFF 100 output segments Output Tr configuration Fig. 1 Fig. 2 PAD layout Identical to the equivalent product – PAD coordinates Different from the equivalent product – COM COM V0 V0 V1 V4 V5 V1 V5 V4 Fig. 1 FIg. 2 @ 7 SED1670 NOTICE: No part of this material may be reproduced or duplicated in any form or by any means without the written permission of Seiko Epson. Seiko Epson reserves the right to make changes to this material without notice. Seiko Epson does not assume any liability of any kind arising out of any inaccuracies contained in this material or due to its application or use in any product or circuit and, further, there is no representation that this material is applicable to products requiring high level reliability, such as, medical products. Morever, no license to any intellectual property rights is granted by implication or otherwise, and there is no representation or warranty that anything made in accordance with this material will be free from any patent or copyright infringement of a third party. This material or portions thereof may contain techonology or the subject relating to strategic products under the control of the Foreign Exchange and Foreign Trade Control Law of Japan and may require an export license from the Ministry of International Trade and Industry or other approval from another government agency. © Seiko Epson Corporation 1996 All right reserved. ELECTRONIC DEVICE MARKETING DEPARTMENT IC Marketing & Engineering Group 421-8 Hino, Hino-shi, Tokyo 191, JAPAN Phone: 0425-87-5816 FAX: 0425-87-5624 International Marketing Department I (Europe, U.S.A.) 421-8 Hino, Hino-shi, Tokyo 191, JAPAN Phone: 0425-87-5812 FAX: 0425-87-5564 International Marketing Department II (Asia) 421-8 Hino, Hino-shi, Tokyo 191, JAPAN Phone: 0425-87-5814 FAX: 0425-87-5110 8 Issue Nov. 1996, printed in Japan H