EtronTech EM562161 128K x 16 Low Power SRAM Preliminary, Rev 1.0 07/2001 Features • Single power supply voltage of 2.7V to 3.6V • Power down features using CE1# and CE2 • Low operating current : 30mA(max for 55 ns) • Maximum Standby current : 10µA at 3.6 V • Data retention supply voltage: 1.5V to 3.6V • Direct TTL compatibility for all input and output • Wide operating temperature range: -40°C to 85°C • Package type: 48-ball TFBGA, 6x8mm circuit technology provides both high speed and low power. It is automatically placed in low-power mode when chip enable (CE1#) is asserted high or (CE2) is asserted low. There are three control inputs. CE1# and CE2 are used to select the device and for data retention control, and output enable (OE#) provides fast memory access. Data byte control pin (LB#,UB#) provides lower and upper byte access. This device is well suited to various microprocessor system applications where high speed, low power and battery backup are required. And, with a guaranteed operating range from -40°C to 85°C, the EM562161 can be used in environments exhibiting extreme temperature conditions. Ordering Information Part Number Speed IDDS2 Package EM562161BC-55 55 ns 10 µA 6x8 BGA EM562161BC-70 70 ns 10 µA 6x8 BGA Pin Configuration 48-Ball BGA (CSP), Top View 1 2 3 4 5 6 A LB # O E# A0 A1 A2 CE 2 B DQ 8 UB # A3 A4 CE1 # DQ 0 C DQ 9 DQ 1 0 A5 A6 DQ 1 DQ 2 D GN D DQ 1 1 NC A7 DQ 3 VD D E V DD DQ 1 2 NC A 16 DQ 4 G ND F DQ 1 4 DQ 1 3 A 14 A 15 DQ 5 DQ 6 G DQ 1 5 NC A 12 A 13 WE# DQ 7 H NC A8 A9 A 10 A1 1 NC Pin Description Symbol Function A0 - A16 Address Inputs DQ0 - DQ15 Data Inputs / Outputs CE1#, CE2 Chip Enable Inputs OE# Output Enable WE# Read / Write Control Input LB#, UB# Data Byte Control Inputs GND Ground VDD Power Supply NC No Connection Overview The EM562161 is a 2,097,152-bit SRAM organized as 131,072 words by 16 bits. It is designed with advanced CMOS technology. This Device operates from a single 2.7V to 3.6V power supply. Advanced Etron Technology, Inc. No. 6, Technology Rd. V, Science-Based Industrial Park, Hsinchu, Taiwan 30077, R.O.C. TEL: (886)-3-5782345 FAX: (886)-3-5778671 Etron Technology, Inc., reserves the right to make changes to its products and specifications without notice. EtronTech EM562161 Block Diagram A0 VDD MEMORY CELL ARRAY 2,048X64X16 (2,097,152) GND A16 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 SENSE AMP DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 COLUMN ADDRESS DECODER WE# UB# LB# OE# CE1# CE2 POWER DOWN CIRCUIT Preliminary 2 Rev 1.0 July 2001 EtronTech EM562161 Operating Mode Mode CE1# CE2 Read L Write H L Output Deselect Standby OE# H L X WE# LB# UB# DQ0~DQ7 DQ8~DQ15 Power L L DOUT DOUT Active H L High-Z DOUT Active L H DOUT High-Z Active L L DIN DIN Active H L High-Z DIN Active L H DIN High-Z Active High-Z High-Z Active High-Z High-Z Standby H L L H H H X X H X X X X X X L X X X X L H X X H H Note: X = don't care. H=logic high. L=logic low. Absolute Maximum Ratings Supply voltage, VDD -0.3 to +4.6V Input voltages, VIN -0.3 to +4.6V Input and output voltages, VI/O -0.5 to VDD +0.5V Operating temperature, TOPR -40 to +85°C Storage temperature, TSTRG -55 to +150°C Soldering Temperature (10s), TSOLDER 240°C Power dissipation, PD 0.6 W DC Recommended Operating Conditions (Ta=-40° C to 85° C) Symbol Parameter Min Typ Max VDD Power Supply Voltage 2.7 − 3.6 VIH Input High Voltage VIL Input Low Voltage VDR Data Retention Supply Voltage 2.2 (2) -0.3 1.5 − Unit V (1) VDD + 0.3 V − 0.6 V − 3.6 V Note: (1) Overshoot : VDD +2.0V in case of pulse width ≤ 20ns (2) Undershoot : -2.0V in case of pulse width ≤ 20ns Preliminary 3 Rev 1.0 July 2001 EtronTech EM562161 DC Characteristics (Ta = -40° C to 85° C, VDD = 2.7V to 3.6V) Parameter Symbol Input low current Test Conditions IIL IIN = 0V to VDD Min Typ* Max Unit -1 − 1 µA Output low voltage VOL IOL = 2.1 mA - − 0.4 V Output high voltage VOH IOH = -1.0 mA 2.2 − − V 55 ns − 15 30 70 ns − 10 25 − − 4 − − 0.5 mA − 1 10 µA VDD = 3.6 V , IDD1 CE1# = VIL and Operating current CE2 = VIH and IOUT = 0mA IDD2 CE1# = VIH or CE2 = VIL CE1# ≥ VDD – 0.2V or CE2 ≤ 0.2V, IDDS2** (Note) Cycle time = 1µs Other Input = VIH / VIL IDDS1 Standby current Cycle time = min or LB# = UB# ≥ VDD – 0.2V mA Notes: * Typical value are measured at Ta = 25°C, and not 100% tested. ** In standby mode with CE1# ≥ VDD - 0.2V, these limits are assured for the condition CE2 ≥ VDD - 0.2V or CE2 ≤ 0.2V. Capacitance (Ta = 25° C; f = 1 MHz) Parameter Input capacitance Symbol Min Typ Max Unit CIN − − 10 pF Test Conditions VIN = GND COUT − − 10 pF VOUT = GND Notes: This parameter is periodically sampled and is not 100% tested. Output capacitance Preliminary 4 Rev 1.0 July 2001 EtronTech EM562161 AC Characteristics and Operating Conditions (Ta = -40° C to 85° C, V DD = 2.7V to 3.6V) Read Cycle Symbol EM562161 -55 -70 Parameter Unit Min Max Min Max tRC Read cycle time 55 − 70 − tAA Address access time − 55 − 70 tCO1 Chip Enable (CE1#) Access Time − 55 − 70 tCO2 Chip Enable (CE2) Access Time − 55 − 70 tOE Output enable access time − 25 − 35 tBA Data Byte Control Access Time − 55 − 70 tLZ Chip Enable Low to Output in Low-Z 10 − 10 − tOLZ Output enable Low to Output in Low-Z 3 − 3 − tBLZ Data Byte Control Low to Output in Low-Z 5 − 5 − Chip Enable High to Output in High-Z − 20 − 25 tOHZ Output Enable High to Output in High-Z − 20 − 25 tBHZ Data Byte Control High to Output in High-Z − 20 − 25 tOH Output Data Hold Time 10 − 10 − tHZ ns Write Cycle Symbol EM562161 -55 -70 Parameter Unit Min Max Min Max tWC Write cycle time 55 − 70 − tWP Write pulse width 40 − 55 − tCW Chip Enable to end of write 45 − 60 − tBW Data Byte Control to end of Write 45 − 60 − tAS Address setup time 0 − 0 − tWR Write Recovery time 0 − 0 − tWHZ WE# Low to Output in High-Z − 25 − 30 tOW WE# High to Output in Low-Z 5 − 5 − tDS Data Setup Time 25 − 30 − tDH Data Hold Time 0 − 0 − ns AC Test Condition • Output load : 50pF + one TTL gate • Input pulse level : 0.4V, 2.4V • Timing measurements : 0.5 x VDD • tR, tF : 5ns Preliminary 5 Rev 1.0 July 2001 EtronTech EM562161 Read Cycle (See Note 1) t RC A ddr es s tO H tA A t CO 1 C E 1# CE 2 t CO 2 t HZ t OE O E# t OH Z t BA U B # , LB # t B LZ t BHZ t O LZ t LZ D O UT Preliminary V AL ID DA TA OUT 6 Rev 1.0 July 2001 EtronTech EM562161 Write Cycle1 (WE# Controlled)(See Note 4) tWC A d d r es s t AS tW P tW R W E# tC W C E1# C E2 tC W tB W U B# , LB# tW H Z D O UT tO W ( Se e No te 2 ) (S e e N ot e 3) t DS D IN Preliminary ( Se e Not e 5 ) tD H V A LI D D A TA I N 7 Rev 1.0 (S e e N ot e 5 ) July 2001 EtronTech EM562161 Write Cycle 2 (CE1# Controlled)(See Note 4) tW C A d d r e ss tA S tWP tWR W E# t CW C E1# C E2 t CW tB W U B# , LB# t B LZ D t W HZ O UT tL Z t DS D IN Preliminary (S e e No te 5) t DH V AL I D DA T A IN 8 Rev 1.0 July 2001 EtronTech EM562161 Write Cycle 3 (CE2 Controlled)(See Note 4) tW C A d d r e ss tA S tWP tWR W E# t CW C E1# C E2 t CW t W HZ D O UT tL Z t DS D IN Preliminary (S e e No te 5) t DH V AL I D DA T A IN 9 Rev 1.0 July 2001 EtronTech EM562161 Write Cycle4 (UB#, LB# Controlled)(See Note 4) tW C A d d r e ss tA S tWP tWR W E# t CW C E1# C E2 t CW tB W U B# , LB# t B LZ D t W HZ O UT tL Z t DS D IN (S e e No te 5) t DH V AL I D DA T A IN Note: 1. WE# remains HIGH for the read cycle. 2. If CE1# goes LOW (or CE2 goes HIGH) with or after WE# goes LOW, the outputs will remain at high impedance. 3. If CE1# goes HIGH (or CE2 goes LOW) coincident with or before WE# goes HIGH, the outputs will remain at high impedance. 4. If OE# is HIGH during the write cycle, the outputs will remain at high impedance. 5. Because I/O signals may be in the output state at this time, input signals of reverse polarity must not be applied. Preliminary 10 Rev 1.0 July 2001 EtronTech EM562161 Data Retention Characteristics (Ta = -40° C to 85° C) Symbol Parameter VDR Data Retention Supply Voltage IDR Data Retention Current CE1# ≥ VDD - 0.2V, CE2 ≤ 0.2V, VIN ≥ VDD - 0.2V or VIN ≤ 0.2V VDD = 1.5V, CE1# ≥ VDD - 0.2V, CE2 ≤ 0.2V, VIN ≥ VDD - 0.2V or VIN ≤ 0.2V tSDR Chip Deselect to Data Retention Mode Time tRDR Recovery Time Min Typ Max Unit 1.5 − 3.6 V − 0.5 3.0 µA 0 − − ns tRC − − ns CE1# Controlled Data Retention Mode tS D R D a ta R e t e n t io n M o d e tR D R V DD 2. 7V 2. 2V V DR N o te 1 C E1 # G ND CE2 Controlled Data Retention Mode Dat a Ret ent ion M ode V DD 2.7V t CE 2 V t S DR RDR DR 0 .4 V N o te 2 G ND Note: 1. CE1# ≥ VDD – 0.2V or UB# = LB# ≥ VDD – 0.2V 2. CE2 ≤ 0.2V Preliminary 11 Rev 1.0 July 2001 EtronTech EM562161 Package Diagrams 48-Ball (6mm x 8mm) BGA Units in mm TOP VIEW BOTTOM VIEW 2 C PIN 1 C O R N E R 0.25 S C A 0.30 PIN 1 C O R N E R 1 0.10 S 3 4 5 6 6 5 4 B 0.05(48X) 3 2 1 -B0.75 3.75 - A0.20(4X) 0.10 -C- Preliminary SEATING PL ANE 12 Rev 1.0 July 2001