MP8798 CMOS Very Low Power, 1 MSPS 10-Bit Analog-to-Digital Converter with 4-Channel Mux FEATURES BENEFITS • • • • • • • • • • • • • • • • 10-Bit Resolution 4-Channel Mux Sampling Rates from <1 kHz to 1 MHz Very Low Power CMOS - 30 mW (typ) Power Down; Lower Consumption – 3 mW (typ) Input Range between GND and VDD No S/H Required for Analog Signals less than 100 kHz No S/H Required for CCD Signals less than 1 MHz Single Power Supply (4 to 6 Volts) Latch-Up Free High ESD Protection: 4000 Volts Minimum 3 V Version: MP87L98 Reduced Board Space (Small Package) Reduced External Parts, No Sample/Hold Needed Suitable for Battery & Power Critical Applications Designer can Adapt Input Range & Scaling APPLICATIONS • • • • µP/DSP Interface and Control Applications High Resolution Imaging – Scanners & Copiers Wireless Digital Communications Multiplexed Data Acquisition GENERAL DESCRIPTION The MP8798 is a flexible, easy to use, precision 10-bit Analog-to-Digital Converter with 4-channel mux that operates over a wide range of input and sampling conditions. The MP8798 can operate with pulsed “on demand” conversion operation or continuous “pipeline” operation for sampling rates up to 1 MHz. The elimination of the S/H, requirements, very low power, and small package size offer the designer a low cost solution. No sample and hold is required for charge couple device applications, up to 1 MHz, or multiplexed input applications when the signal source bandwidth is limited to 100 kHz. The input architecture of the MP8798 allows direct interface to any analog input range between AGND and AVDD (0 to 2 V, 1 to 4 V, 0 to 5 V, etc.). The user simply sets VREF(+) and VREF(–) to encompass the desired input range. the transfer curve as well as providing a 1/2 span reference voltage. Digital outputs are CMOS and TTL compatible. The MP8798 uses a two-step flash technique. The first segment converts the 4 MSBs and consists of 15 autobalanced comparators, latches, an encoder, and buffer storage registers. The second segment converts the remaining 6 LSBs. When the power down input is “high”, the data outputs DB9 to DB0 hold the current values and VREF(–) is disconnected from VREF1(–). The power consumption during the power down mode is approximately 3mW. Specified for operation over the commercial / industrial (–40 to +85°C) temperature range, the MP8798 is available in plastic dual-in-line (PDIP), surface mount (SOIC), and shrink small outline (SSOP) packages. Scaled reference resistor tap 1/2 R allows for customizing ORDERING INFORMATION Package Type Temperature Range Part No. DNL (LSB) INL (LSB) SOIC –40 to +85°C MP8798AS 1 2 PDIP –40 to +85°C MP8798AN 1 2 SSOP –40 to +85°C MP8798AQ 1 2 Rev. 3.00 1 MP8798 SIMPLIFIED BLOCK AND TIMING DIAGRAM AVDD DVDD Coarse Comparators Adder 4 φS 5 φB CLK OFW VREF(+) Fine Resolution Comparators 1/2 R VREF(–) VREF1(–) PD DB9-DB0 DFF N DB9-DB0 N-1 N OFW N-1 N 10 6 Ladder CLK AIN1 AIN2 AIN3 AIN4 φS 1 or 4 MUX WR 4 2 to 4 Decoder Latch A1 A0 AGND DGND PIN CONFIGURATIONS See Packaging Section for Package Dimensions DB3 DB4 DB5 DB6 DB7 DGND DVDD WR A1 A0 CLK DB8 DB9 OFW 1 28 2 27 3 26 4 25 5 24 6 23 7 22 8 21 9 20 10 19 11 18 12 17 13 16 14 15 DB2 DB1 DB0 PD AVDD AGND AIN4 AIN3 AIN2 AIN1 1/2 R VREF1(–) VREF(–) VREF(+) DB3 DB4 DB5 DB6 DB7 DGND DVDD WR A1 A0 CLK DB8 DB9 OFW 28 Pin PDIP (0.300”) NN28 1 28 2 27 3 26 4 25 5 24 6 23 7 22 8 21 9 20 10 19 11 18 12 17 13 16 14 15 DB2 DB1 DB0 PD AVDD AGND AIN4 AIN3 AIN2 AIN1 1/2 R VREF1(–) VREF(–) VREF(+) 28 Pin SOIC (Jedec, 0.300”) – S28 28 Pin SSOP – A28 Rev. 3.00 2 φB MP8798 PIN OUT DEFINITIONS PIN NO. NAME DESCRIPTION PIN NO. NAME DESCRIPTION 1 DB3 Data Output Bit 3 15 VREF(+) Upper Reference Voltage 2 DB4 Data Output Bit 4 16 VREF(–) Lower Reference Voltage 3 DB5 Data Output Bit 5 17 VREF1(–) Lower Reference Voltage 4 DB6 Data Output Bit 6 18 1/2 R Reference Ladder Tap 5 DB7 Data Output Bit 7 19 AIN1 Analog Signal Input 1 6 DGND Digital Ground 20 AIN2 Analog Signal Input 2 7 DVDD Digital VDD 21 AIN3 Analog Signal Input 3 AIN4 Analog Signal Input 4 8 WR Write (Active Low) 22 9 A1 Address 1 Input 23 AGND Analog Ground 10 A0 Address 0 Input 24 AVDD Analog VDD 11 CLK Clock Input 25 PD Power Down 12 DB8 Data Output Bit 8 26 DB0 Data Output Bit 0 (LSB) 13 DB9 Data Output Bit 9 (MSB) 27 DB1 Data Output Bit 1 14 OFW Overflow Output 28 DB2 Data Output Bit 2 TRUTH TABLE FOR INPUT CHANNEL SELECTION WR A1 A0 SELECTED ANALOG INPUT 0 0 0 AIN1 0 0 1 AIN2 0 1 0 AIN3 0 1 1 AIN4 1 X X Previous selection Note: WR, A1, A0 are internally connected to GND through 500kΩ resistance. Rev. 3.00 3 MP8798 ELECTRICAL CHARACTERISTICS TABLE Unless Otherwise Specified: AVDD = DVDD = 5 V, FS = 1 MHz (50% Duty Cycle), VREF(+) = 4.6, VREF(–) = AGND, TA = 25°C Parameter Symbol Min FS 10 .001 25°C Typ Max Units Test Conditions/Comments 1 Bits MHz For Rated Performance 1 2 LSB LSB KEY FEATURES Resolution Sampling Rate ACCURACY2 Differential Non-Linearity Integral Non-Linearity DNL INL 3/4 Zero Scale Error Full Scale Error EZS EFS +0.50 –2.5 LSB LSB Best Fit Line (Max INL – Min INL)/2 Reference from VREF(+) to VREF(–) REFERENCE VOLTAGES Positive Ref. Voltage Negative Ref. Voltage Differential Ref. Voltage5 Ladder Resistance Ladder Temp. Coefficient1 Ladder Switch Resistance1 Ladder Switch Off Leakage1 VREF(+) VREF(–) VREF RL RTCO AVDD AGND 0.5 525 ILKG-SW 675 2000 12 50 AVDD 900 V V V Ω ppm/°C Ω nA ANALOG INPUT1 Input Bandwidth Input Voltage Range7 Input Capacitance3 Aperture Delay 100 VIN CIN tAP VREF(–) VIH VIL IIN 2.0 45 kHz V pF ns 0.8 V V VREF(+) 60 35 DIGITAL INPUTS Logical “1” Voltage Logical “0” Voltage Leakage Currents CLK PD, (Internal Res to DGND) Input Capacitance Clock Timing (See NO TAG)1 Clock Period Rise & Fall Time4 “High” Time6 “Low” Time6 100 30 –5 5 TS tR, tF tB tS 1000 10 500,000 500,000 250 150 Rev. 3.00 4 µA µA pF ns ns ns ns VIN=DGND to DVDD MP8798 ELECTRICAL CHARACTERISTICS TABLE (CONT’D) Parameter Symbol Min 25°C Typ Max Units DIGITAL OUTPUTS Logical “1” Voltage Logical “0” Voltage Tristate Leakage Data Hold Time (See NO TAG)1 Data Valid Delay1 Write Pulse Width1 Multiplexer Address Setup Time1 Multiplexer Address Hold Time1 Delay from WR to Multiplexer1 Enable Power Down Time1 Power Up Time1 Test Conditions/Comments COUT=15 pF VOH VOL IOZ tHLD tDL tWR tAS tAH DVDD-0.5 0 30 35 0.4 5 35 45 40 80 0 tMUXEN1 tPD tPU V V µA ns ns ns ns ns 80 300 200 ns ns ns 1.2 6.5 10 mA V mA ILOAD = 2 mA ILOAD = 4 mA VOUT = 0 to DVDD POWER SUPPLIES8 Power Down (IDD) Operating Voltage (AVDD, DVDD) Current (AVDD + DVDD) IPD-DD VDD IDD 4 0.6 5 6 VIN = 2 V NOTES: Guaranteed. Not tested. Tester measures code transition voltages by dithering the voltage of the analog input (VIN). The difference between the measured code width and the ideal value (VREF/1024) is the DNL error (see NO TAG). The INL error is the maximum distance (in LSBs) from the best fit line to any transition voltage (See Figure 7.). 3 See VIN input equivalent circuit (see Figure 9.). 4 Clock specification to meet aperture specification (tAP). Actual rise/fall time can be less stringent with no loss of accuracy. 5 Specified values guarantee functional device. Refer to other parameters for accuracy. 6 System can clock MP8798 with any duty cycle as long as all timing conditions are met. 7 Input range where input is converted correctly into binary code. Input voltage outside specified range converts to zero or full scale output. 8 DVDD and AVDD are connected through the silicon substrate. Connect together at the package. 1 2 Specifications are subject to change without notice ABSOLUTE MAXIMUM RATINGS (TA = +25°C unless otherwise noted)1, 2 Storage Temperature . . . . . . . . . . . . . . . . . . . –65 to +150°C VDD (to GND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7 V VREF(+) & VREF(–) . . . . . . . . . . . . . . GND –0.5 to VDD +0.5 V VIN . . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 to VDD +0.5 V All Inputs . . . . . . . . . . . . . . . . . . . . . GND –0.5 to VDD +0.5 V All Outputs . . . . . . . . . . . . . . . . . . . GND –0.5 to VDD +0.5 V Lead Temperature (Soldering 10 seconds) . . . . . . . +300°C Package Power Dissipation Rating to 75°C SOIC, PDIP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000mW Derates above 75°C . . . . . . . . . . . . . . . . . . . . . 14mW/°C NOTES: 1 Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation at or above this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. 2 Any input pin which can see a value outside the absolute maximum ratings should be protected by Schottky diode clamps (HP5082-2835) from input pin to the supplies. All inputs have protection diodes which will protect the device from short transients outside the supplies of less than 100mA for less than 100µs. 3 VDD refers to AVDD and DVDD. GND refers to AGND and DGND. Rev. 3.00 5 MP8798 tR tS when φS disconnects the latches from the comparators. This delay is called aperture delay (tAP). tF tB VIH CLOCK The coarse comparators make the first pass conversion and selects a ladder range for the fine comparators. The fine comparators are connected to the selected range during the next φB phase. VIL SAMPLE N–1 AUTO BALANCE SAMPLE N AUTO BALANCE SAMPLE N+1 φB φS TS ANALOG INPUT φS VIN Latch VOH VTAP DATA N-1 Ref Ladder VOL tDL COARSE COMPARATOR φB φS φS tHLD φB VIN Figure 1. MP8798 Timing Diagram Latch VTAP THEORY OF OPERATION Selected Range Analog-to-Digital Conversion Figure 2. MP8798 Comparators The MP8798 converts analog voltages into 1024 digital codes by encoding the outputs of 15 coarse and 67 fine comparators. Digital logic is used to generate the overflow bit. The conversion is synchronous with the clock and it is accomplished in 2 clock periods. AIN Sampling, Ladder Sampling, and Conversion Timing Figure 3. shows this relationship as a timing chart. AIN sampling, ladder sampling and output data relationships are shown for the general case where the levels which drive the ladder need to change for each sampled AIN time point. The ladder is referenced for both last AIN sample and next AIN sample at the same time. If the ladder’s levels change by more than 1 LSB, one of the samples must be discarded. Also note that the clock low period for the discarded AIN can be reduced to the minimum tS time of 150 ns. The reference resistance ladder is a series of 1025 resistors. The first and the last resistor of the ladder are half the value of the others so that the following relations apply: RREF = 1024 ∗ R FINE COMPARATOR φB VREF = VREF(+) – VREF(–) = 1024 ∗ LSB The clock signal generates the two internal phases, φB (CLK high) and φS (CLK low = sample) (See Figure 2.). The rising edge of the CLK input marks the end of the sampling phase (φS). Internal delay of the clock circuitry will delay the actual instant Hold Reference Value Past Clock Change for tAP Time Short Cycle Sample will be discarded tS External Settle by Clock Update Time Reference Stable Time – For Sample AIN2 Update References Reference Stable Time – For Sample AIN1 Clock Internal AIN Sample Window Ladder Sample Window (MSB Bank) Ladder Compare (LSB Bank) External DATA AINX1 Sample AIN1 FS FB AINX0 Sample AIN2 Not Used FB Sample AIN1 FS FS FB AINX1 Sample AIN2 Sample Ladder for AIN1 Sample Ladder for AINX1 Sample Ladder for AIN2 Sample Ladder for AINX2 Compare Ladder V/S AINX0 Compare Ladder V/S AIN1 Compare Ladder V/S AINX1 Compare Ladder V/S AIN2 DATA AIN0 DATA AINX0 DATA AIN1 Not Used Figure 3. AIN Sampling, Ladder Sampling & Conversion Timing Rev. 3.00 6 DATA AINX1 Not Used MP8798 Accuracy of Conversion: DNL and INL DNL LSB V(N+1) The transfer function for an ideal A/D converter is shown in Figure 4. Analog Input V(N) DIGITAL CODES 0.5 ∗ LSB N+1 Output Codes 0.5 ∗ LSB N N–1 OFW = 0 1 LSB (N+1) Code Width = V(N+1) – V(N) LSB = [ VREF(+) – VREF(–) ] / 1024 OFW = 1 3FF 3FE 001 000 002 DNL(N) = [ V(N+1) – V(N) ] – LSB 3FD LSB Figure 5. DNL Measurement On Production Tester V VREF(–) V001 V002 V3FE V3FF V0FW VREF(+) Figure 4. Ideal A/D Transfer Function The formulas for Differential Non-linearity (DNL), Integral Non-Linearity (INL) and zero and full scale errors (EZS, EFS) are: The overflow transition (VOFW) takes place at: DNL (001) = V002 – V001 – LSB VIN = VOFW = VREF(+) – 0.5 ∗ LSB : : : The first and the last transitions for the data bits take place at: DNL (3FE) = V3FF – V3FE – LSB VIN = V001 = VREF(–) + 0.5 ∗ LSB EFS (full scale error) = V3FF – [VREF(+) –1.5 ∗ LSB] VIN = V3FF = VREF(+) – 1.5 ∗ LSB EZS (zero scale error) = V001 – [VREF(–) + 0.5 ∗ LSB] LSB = VREF / 1024 = (V3FF – V001) / 1022 DIGITAL CODES 0.5 ∗ LSB Note that the overflow transition is a flag and has no impact on the data bits. In a “real” converter the code-to-code transitions don’t fall exactly every VREF/1024 volts. 1.5 ∗ LSB EZS EFS 3FF A positive DNL (Differential Non-Linearity) error means that the real width of a particular code is larger than 1 LSB. This error is measured in fractions of LSBs. 002 3FE 001 000 A Max DNL specification guarantees that ALL code widths (DNL errors) are within the stated value. A specification of Max DNL = + 0.5 LSB means that all code widths are within 0.5 and 1.5 LSB. If VREF = 4.608 V then 1 LSB = 4.5 mV and every code width is within 2.25 and 6.75 mV. VREF(–) V001 V002 V3FE V V3FF VREF(+) Figure 6. Real A/D Transfer Curve Figure 6. shows the zero scale and full scale error terms. Rev. 3.00 7 MP8798 Figure 7. gives a visual definition of the INL error. The chart shows a 3-bit converter transfer curve with greatly exaggerated DNL errors to show the deviation of the real transfer curve from the ideal one. A system will clock the MP8798 continuously or it will give clock pulses intermittently when a conversion is desired. The timing of Figure 8a shows normal operation, while the timing of Figure 8b keeps the MP8798 in balance and ready to sample the analog input. After a tester has measured all the transition voltages, the computer draws a line parallel to the ideal transfer line. By definition the best fit line makes equal the positive and the negative INL errors. For example, an INL error of –1 to +2 LSB’s relative to the Ideal Line would be +1.5 LSB’s relative to the best fit line. CLOCK N N+1 DATA N N+1 a. Continuous sampling Output Codes Best Fit Line 7 CLOCK N BALANCE Real Transfer Line 6 DATA 5 N b. Single sampling EFS INL 4 Figure 8. Relationship of Data to Clock Ideal Transfer Line 3 Analog Input 2 The MP8798 has very flexible input range characteristics. The user may set VREF(+) and VREF(–) to two fixed voltages and then vary the input DC and AC levels to match the VREF range. Another method is to first design the analog input circuitry and then adjust the reference voltages for the analog input range. One advantage is that this approach may eliminate the need for external gain and offset adjust circuitry which may be required by fixed input range A/Ds. LSB 1 Analog Input (Volt) EZS Figure 7. INL Error Calculation The MP8798’s performance is optimized by using analog input circuitry that is capable of driving the AIN input. Figure 9. shows the equivalent circuit for AIN. Clock and Conversion Timing 40 Ω VDD R Series 40Ω 87 pF φS R MUX 500Ω 60 pF 160 Ω 4 AIN 15 pF 1 pF φS 10 pF 4 Control 87 pF 300 Ω Channel Selection Figure 9. Analog Input Equivalent Circuit Rev. 3.00 8 φB + 4 pF 1/2 [ VREF(+) + VREF(–) ] MP8798 Analog Input Multiplexer Digital Interfaces The MP8798 includes a 4-channel analog input multiplexer. The relationship between the clock, the multiplexer address, the WR and the output data is shown in Figure 10. The logic encodes the outputs of the comparators into a binary code and latches the data in a D-type flip-flop for output. Clock Sample N Old Address Sample M New Address tCLKS2 tWR The functional equivalent of the MP8798 (Figure 12.) is com- Sample M+1 posed of: tCLKH2 WR tAS Delay stage (tAP) from the clock to the sampling phase 2) An ideal analog switch which samples VIN. 3) An ideal A/D which tracks and converts VIN with no (φS). tAH ÉÉ ÉÉÉÉÉÉÉÉÉÉ ÉÉ ÉÉÉÉÉÉÉÉÉÉ Address DB0-DB9 1) N-2 Valid N-1 Valid Old Address N Valid Old Address delay. A series of two DFF’s with specified hold (tHLD) and 4) M Valid New Address delay (tDL) times. tCLKS2 = tCLKH2 = 0 tAP, tHLD and tDL are specified in the Electrical Characteristics Figure 10. MUX Address Timing table. tAS tAH φS A1, A0 VIN tWR WR A/D tMUXEN1 D Q D Q DB9-DB0 tAP CLK MP8798 MUXEN (Internal Signal) CLK Figure 11. Analog MUX Timing N VIN N+1 tHLD tDL Reference Voltages DB9-DB0 N-1 N The input/output relationship is a function of VREF: AIN = VIN – VREF(–) VREF = VREF(+) – VREF(–) DATA = 1023 ∗ (AIN/VREF) Figure 12. MP8798 Functional Equivalent Circuit and Interface Timing A system can increase total gain by reducing VREF. Rev. 3.00 9 MP8798 Power Down Figure 13. shows the relationship between the clock, sampled AIN to output data relationship and the effect of power down. CLK SAMPLE N SAMPLE M VIN DB0-DB9 N-2 Valid N-1 Valid N Valid tCLKS1 SAMPLE M+1 ÇÇÇÇÇÇ ÇÇÇÇÇÇ M Valid tCLKH1 PD tPD tPU IDD, IVREF(+) Figure 13. Power Down Timing Diagram Rev. 3.00 10 MP8798 APPLICATION NOTES C1 = 4.7 or 10µF Tantalum C2 = 0.1µF Chip Cap or low inductance capacitor RT = Clock Transmission Line Termination +5 V C1A, C2A AVDD 1 of 4 AIN C1D, C2D DVDD Z 100W Buffer Resistive Isolation of 50 to 100W AIN1 (Substrate) OFW AIN4 DB9 - DB0 MP8798 WR A0 A1 Reference Voltage Source VREF(+) + C1 C2 C1 CLK 1/2 R C2 – RT VREF(–) VREF1(–) AGND DGND Figure 14. Typical Circuit Connections The following information will be useful in maximizing the performance of the MP8798. shield for parasitics and not a return path for signals. To reduce noise levels, use separate low impedance ground paths. DGND should not be shared with other digital circuitry. If separate low impedance paths cannot be provided, DGND should be connected to AGND next to the MP8798. 1. All signals should not exceed AVDD +0.5 V or AGND –0.5 V or DVDD +0.5 V or DGND –0.5 V. 2. Any input pin which can see a value outside the absolute maximum ratings (AVDD or DVDD+0.5 V or AGND –0.5 V) should be protected by diode clamps (HP5082-2835) from input pin to the supplies. All MP8798 inputs have input protection diodes which will protect the device from short transients outside the supply ranges. 7. DVDD should not be shared with other digital circuitry to avoid conversion errors caused by digital supply transients. DVDD for the MP8798 should be connected to AVDD next to the MP8798. 8. DVDD and AVDD are connected inside the MP8798 through the N – doped silicon substrate. Any DC voltage difference between DVDD and AVDD will cause undesirable internal currents. 3. The design of a PC board will affect the accuracy of MP8798. Use of wire wrap is not recommended. 4. The analog input signal (VIN) is quite sensitive and should be properly routed and terminated. It should be shielded from the clock and digital outputs so as to minimize cross coupling and noise pickup. 9. Each power supply and reference voltage pin should be decoupled with a ceramic (0.1µF) and a tantalum (10µF) capacitor as close to the device as possible. 10. The digital output should not drive long wires. The capacitive coupling and reflection will contribute noise to the conversion. When driving distant loads, buffers should be used. 100Ω resistors in series with the digital outputs in some applications reduces the digital output disruption of AIN. 5. The analog input should be driven by a low impedance (less than 50Ω). 6. Analog and digital ground planes should be substantial and common at one point only. The ground plane should act as a Rev. 3.00 11 MP8798 +5 V 5k 0.1µF + MP5010 100k + – – Figure 15. Example of a Reference Voltage Source +5 V 1 of 4 5 V R +5 V R VREF(+) AVDD + VIN DB0 AIN1 – AIN4 VREF(–) AGND For R = 5k use Beckman Instruments #694-3-R10k resistor array or equivalent. NOTE: High R values affect the input BW of ADC due to the (R ∗ CIN of ADC) time constant. Therefore, for different applications the R value needs to be selected as a tradeoff between AIN settling time and power dissipation. Figure 16. 5 V Analog Input +5 V 1 of 4 10 V 2R +5 V R VREF(+) AVDD + VIN DB0 AIN1 – 2R AIN4 VREF(–) AGND For R = 5k use Beckman Instruments #694-3-R10k resistor array or equivalent. NOTE: High R values affect the input BW of ADC due to the (R ∗ CIN of ADC) time constant. Therefore, for different applications the R value needs to be selected as a tradeoff between AIN settling time and power dissipation. Figure 17. 10 V Analog Input Rev. 3.00 12 MP8798 MP8798 DAC7 AIN2 DAC6 AIN3 DAC5 AIN4 DAC4 VREF(+) DAC3 1/2 + – VIN AIN1 + – VIN DAC8 + – VIN + – VIN VREF(+) DAC1 DAC MP7641 VREF1(–) @ Power Down write values to DAC 3, 2, 1 = DAC 4 to minimize power consumption. Only AIN and Ladder detail shown. Figure 18. A/D Ladder and AIN with Programmed Control (of VREF(+), VREF(–), 1/2 TAP.) Rev. 3.00 13 MP8798 PERFORMANCE CHARACTERISTICS Graph 1. DNL vs. Sampling Frequency Graph 2. INL vs. Sampling Frequency Graph 3. Supply Current vs. Sampling Frequency Graph 4. Power Down Current vs. Sampling Frequency Graph 5. DNL vs. Reference Voltage Graph 6. DNL vs. Temperature Rev. 3.00 14 MP8798 Graph 7. Supply Current vs. Temperature Graph 8. Power Down Current vs. Temperature Graph 9. Reference Resistance vs. Temperature Rev. 3.00 15 MP8798 28 LEAD PLASTIC DUAL-IN-LINE (300 MIL PDIP) NN28 S 28 15 1 14 Q1 E1 E D A1 Seating Plane A L B e B1 α MILLIMETERS INCHES SYMBOL MIN MAX MIN MAX A 0.130 0.230 3.30 5.84 A1 0.015 –– 0.381 –– B 0.014 0.023 0.356 0.584 B1 (1) 0.038 0.065 0.965 1.65 C 0.008 0.015 0.203 0.381 D 1.340 1.485 34.04 37.72 E 0.290 0.325 7.37 8.26 E1 0.240 0.310 6.10 7.87 e 0.100 BSC L 0.115 α 0.150 2.54 BSC 2.92 3.81 0° 15° 0° 15° Q1 0.055 0.070 1.40 1.78 S 0.020 0.100 0.508 2.54 Note: (1) The minimum limit for dimensions B1 may be 0.023” (0.58 mm) for all four corner leads only. Rev. 3.00 16 C MP8798 28 LEAD SMALL OUTLINE (300 MIL JEDEC SOIC) S28 D 28 15 E H 14 h x 45° C A Seating Plane α B e A1 L INCHES SYMBOL MILLIMETERS MIN MAX MIN A 0.097 0.104 2.464 A1 0.0050 0.0115 0.127 0.292 B 0.014 0.019 0.356 0.483 C 0.0091 0.0125 0.231 0.318 D 0.701 0.711 17.81 18.06 E 0.292 0.299 7.42 7.59 e 0.050 BSC MAX 2.642 1.27 BSC H 0.400 0.410 10.16 10.41 h 0.010 0.016 0.254 0.406 L 0.016 0.035 0.406 0.889 α 0° 8° 0° 8° Rev. 3.00 17 MP8798 28 LEAD SHRINK SMALL OUTLINE PACKAGE (SSOP) A28 D 28 15 E 1 H 14 C A Seating Plane α B e A1 L MILLIMETERS SYMBOL INCHES MIN MAX MIN A 1.73 2.05 0.068 0.081 A1 0.05 0.21 0.002 0.008 B 0.20 0.40 0.008 0.016 C 0.13 0.25 0.005 0.010 D 10.07 10.40 0.397 0.409 E 5.20 5.38 0.205 0.212 e 0.65 BSC MAX 0.0256 BSC H 7.65 8.1 0.301 0.319 L 0.45 0.95 0.018 0.037 α 0° 8° 0° 8° Rev. 3.00 18 MP8798 Notes Rev. 3.00 19 MP8798 NOTICE EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contains here in are only for illustration purposes and may vary depending upon a user’s specific application. While the information in this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies. EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the circumstances. Copyright 1993 EXAR Corporation Datasheet April 1995 Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited. Rev. 3.00 20