XR-2212 ...the analog plus Precision Phase-Locked Loop company TM October 2006 FEATURES APPLICATIONS Quadrature VCO Outputs Frequency Synthesis Wide Frequency Range (0.01Hz to 300kHz) Data Synchronization Wide Supply Voltage Range (4.5V to 20V) FM Detection TTL/HCMOS Compatible (VCC = 5VDC) Tracking Filters Wide Dynamic Range (2mV to 3Vrms) FSK Demodulation Adjustable Tracking Range (1% to 80%) Excellent Temp. Stability 20ppm/°C, Typ. GENERAL DESCRIPTION The XR-2212 is an ultra-stable monolithic phase-locked loop (PLL) system especially designed for data communications and control system applications. Its on board reference and uncommitted operational amplifier, together with a typical temperature stability of better than 20ppm/°C, make it ideally suited for frequency synthesis, FM detection, and tracking filter applications. The wide input dynamic range, large operating voltage range, large frequency range, and HCMOS and TTL compatibility contribute to the usefulness and wide applicability of this device. ORDERING INFORMATION Part No. Package Operating Temperature Range XR-2212M 16 Lead 300 Mil CDIP -55°C to +125°C XR-2212CP 16 Lead 300 Mil PDIP 0°C to +70°C BLOCK DIAGRAM Pre Amplifier INP 2 VCC GND 1 4 Phase Detector 10 0-DET O 15 VCOQO 3 VCOOC 5 VCOOV 11 VREF 8 OUT 6 COMP 0-DET I 16 TIM C1 14 VCO Amp TIM C2 13 TIM R 12 PINP 9 NINP 7 VREF Op Amp Figure 1. XR-2212 Block Diagram Rev. 2.10 1979-2006 EXAR Corporation, 48720 Kato Road, Fremont, CA 94538 (510) 668-7000 FAX (510) 668-7017 1 XR-2212 PIN CONFIGURATION VCC INP VCOOC GND VCOOV COMP NINP OUT 1 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 0-DET I VCOQO TIM C1 TIM C2 TIM R VREF 0-DET O PINP 16 Lead PDIP, CDIP (0.300”) PIN DESCRIPTION Pin # Symbol Type Description 1 VCC 2 INP I Receive Analog Input. 3 VCOOC O VCO Current Output. Positive Power Supply. 4 GND 5 VCOOV O Ground Pin. VCO Voltage Source Output. 6 COMP I Uncommitted Amplifier, Frequency Compensation Input. 7 NINP I Inverted Input. Uncommitted amplifier. 8 OUT O Uncommitted Amplifier Output. 9 PINP I Positive Input. Uncommitted amplifier. 10 0-DET O O Phase Detector Output. 11 VREF O Internal Voltage Reference. The value of VREF is VCC /2 -650mV. 12 TIM R I Timing Resistor Input. This pin connects to the timing resistor of the VCO. 13 TIM C2 I Timing Capacitor Input. The timing capacitor connects between this pin and pin 14. 14 TIM C1 I Timing Capacitor Input. The timing capacitor connects between this pin and pin 13. 15 VCOQO O VCO Quadrature Output. 16 0-DET I I Phase Detector Input. Rev. 2.10 2 XR-2212 ELECTRICAL CHARACTERISTICS Test Conditions: VCC = +12V, TA = + 25°C, R0 = 30k, C0 = 0.033F, unless otherwise specified. See Figure 3 for component designation. XR-2212M P Parameter t Min. Typ. XR-2212CP Max. Min. 15 4.5 Typ. Max. U it Units C diti Conditions General Characteristics Supply Voltage 4.5 Supply Current 6 10 6 +1 +3 +1 15 V 12 mA R0 > 10k., See Figure 5 % Deviation from f0 = 1/R0C0 Oscillator Section Frequency Accuracy R1 = R Frequency Stability See Figure 9 Temperature +20 +50 +20 ppm/°C Power Supply 0.05 0.5 0.05 %/V VCC = 12 + 1V, See Figure 8 0.2 0.2 %/V VCC = 5 + 0.5V, See Figure 8 300 300 kHz R0 = 8.2k, C0 = 400pF 0.01 Hz R0 = 2M, C0 = 50F Upper Frequency Limit 100 Lowest Practical Operating F Frequency 0.01 See Figure 5 Timing Resistor, R0 Operating Range 5 2000 5 2000 k Recommended Range 15 100 15 100 k See Figure 8 and Figure 9 Oscillator Outputs Voltage Output Measured at Pin 5 Positive Swing, VOH 11 Negative Swing, VOL 0.4 Current Sink Capability 11 0.8 1 V 0.5 V 1 mA Current Output Measured at Pin 3 150 150 A 1 1 M Output Swing 0.6 0.6 V DC Level 0.3 0.3 V 3 3 k Peak Current Swing 100 Output Impedance Quadrature Output Measured at Pin 15 Output Impedance Loop Phase Detector Section Peak Output Current Measured at Pin 10 +150 +200 +300 +100 +200 +300 A Output Offset Current +1 +2 A Output Impedance 1 1 M +5 V Maximum Swing Referenced to Pin 11 +4 +5 +4 Referenced to Pin 11 Note Bold face parameters are covered by production test and guaranteed over operating temperature range. Rev. 2.10 3 XR-2212 ELECTRICAL CHARACTERISTICS (CONT’D) XR-2212M Parameter Min. Typ. XR-2212CP Max. Min. Typ. Max. Units Input Preamp Section Conditions Measured at Pin 2 Input Impedance 20 Input Signal to Cause Limiting 2 10 20 k 2 mV rms 70 dB Op Amp Section Voltage Gain 55 70 55 Input Bias Current 0.1 1 0.1 1 Offset Voltage +5 +20 +5 +20 Slew Rate 2 2 A mV V/sec Internal Reference Voltage Level RL = 5.1k, RF = R Measured at Pin 11 4.9 5.3 5.7 4.75 5.3 5.85 V Output Impedance 100 100 Maximum Source Current 80 80 A AC Small Signal Note Bold face parameters are covered by production test and guaranteed over operating temperature range. Specifications are subject to change without notice ABSOLUTE MAXIMUM RATINGS Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18V Power Dissipation: Ceramic Package: . . . . . . . . . . . . . . . . . . . . . . . Derate Above TA = + 25°C . . . . . . . . Plastic Package: . . . . . . . . . . . . . . . . . . . . . . . . Derate Above TA = + 25°C . . . . . . . . Input Signal Level . . . . . . . . . . . . . . . . . . . . . . . . 3V rms 750mW 6mW/°C 625mW 5mW/°C SYSTEM DESCRIPTION external components. The PLL output is directly compatible with CMOS, HCMOS and TTL logic families as well as microprocessor peripheral systems. The XR-2212 is a complete PLL system with buffered inputs and outputs, an internal reference, and an uncommitted op amp. Two VCO outputs are pinned out; one sources current, the other sources voltage. This enables operation as a frequency synthesizer using an external programmable divider. The op amp section can be used as an audio preamplifier for FM detection or as a high speed sense amplifier (comparator) for FSK demodulation. The center frequency, bandwidth, and tracking range of the PLL are controlled independently by The precision PLL system operates over a supply voltage range of 4.5V to 20V, a frequency range of 0.01Hz to 300kHz, and accepts input signals in the range of 2mV to 3V rms. Temperature stability of the VCO is typically better than 20 ppm/°C with the optimum timing resistor value. Rev. 2.10 4 XR-2212 Loop Filter Pre Amp Signal Input + Phase Detector Op Amp 0-DET Input AMP VCO Voltage Output VCO Phase Quadrature VCO Current Output Output Figure 2. Functional Block Diagram of XR-2212 Precision PLL System VCC RL 6 2 Input Signal Phase Detector 10 ÁÁ ÁÁ 9 0.1F 8 5.6K CO Demod Output 7 C1 RF 16 RC R3 0.1F 11 Internal Reference 0.1F 5 12 %N External Divider (Optional) R1 VCO 14 R0 13 CO Figure 3. Generalized Circuit Connection for FM Detection, Signal Tracking or Frequency Synthesis Rev. 2.10 5 XR-2212 Phase Detector Input 1 Vcc Loop Phase Detector Output 16 10 11 Signal Input 2 30K Reference Output Voltage 30K Input Preamplifier Phase Detector 2K 2K VCO Out A Timing Capacitor C0 13 14 5K Internal Voltage Reference A A1 5 3 5K A1 VCO Quad Out 15 Non Inv Inp VCO Current Output 9 Amp Out 8 Inv Inp 7 6 Comp 5K 5K Op Amp 12 Timing Resistor RO Figure 4. Simplified Circuit Schematic of XR-2212 Rev. 2.10 6 4 GND XR-2212 TYPICAL CHARACTERISTICS 20 10 15 R0=10k RL = 5K RL = 10K 10 C 0 ( F ) Supply Current (mA) R0=5k RL > 100K R0=20k 0.1 R0=40k 5 R0=80k 0 4 6 8 10 12 14 16 18 20 22 R0=160k 0.01 100 24 Supply Voltage VCC (V) 1000 10,000 f0 (Hz) Figure 5. Typical Supply Current vs. VCC (Logic Outputs Open Circuited) Figure 6. VCO Frequency vs. Timing Resistor 1000 1.02 C0=0.001F f0 = 1kHz Normalized Frequency 5 R0 (k ) C0=0.0033F C0=0.01F 100 C0=0.033F C0=0.1F 4 2 3 1.00 4 3 CURVE 0.99 1 2 3 4 5 2 0.98 1 C0=0.33F R0 5K 10K 30K 100K 300K 0.97 10 0 1.01 5 1 R > 10R0 1000 f0 (Hz) 4 10,000 Figure 7. VCO Frequency vs. Timing Capacitor 6 8 10 12 14 VCC (V) 16 18 20 Figure 8. Typical f0 vs. Power Supply Characteristics Rev. 2.10 7 22 24 Normalized Frequency Drift (% of f o ) XR-2212 +1.0 1MΩ R0=10K +0.5 500K R0=50K 0 50K R0=500K -0.5 -1.0 -50 -25 10K VCC=12V R1=12R0 f0=1kHz R0=1MΩ 0 25 50 75 100 125 Temperature (C) Figure 9. Typical Center Frequency Drift vs. Temperature DESCRIPTION OF CIRCUIT CONTROLS Signal Input (Pin 2): Signal is AC coupled to this terminal. The internal impedance at Pin 2 is 20k. Recommended input signal level is in the range of 10mV to 5V peak-to-peak. Op Amp Output (Pin 8): The op amp output is an opencollector type gain stage and requires a pull-up resistor, RL, to VCC for proper operation. For most applications, the recommended value of RL is in 5k to 10k range. VCO Current Output (Pin 3): This is a high impedance (M) current output terminal which can provide +100A drive capability with a voltage swing equal to VCC. This output can directly interface with CMOS or NMOS logic families. Phase Detector Output (Pin 10): This terminal provides a high-impedance output for the loop phase-detector. The PLL loop filter is formed by R1 and C1 connected to Pin 10 (see Figure 3). With no input signal, or with no phase-error within the PLL, the DC level at Pin 10 is very nearly equal to VREF. The peak voltage swing available at the phase detector output is equal to $VREF. VCO Voltage Output (Pin 5): This terminal provides a low- impedance ( 50) buffered output for the VCO. It can directly interface with low-power Schottley TTL. For interfacing with standard TTL circuits, a 750 pull-down resistor from Pin 5 to ground is required. For operation of the PLL without an external divider, Pin 5 can be DC coupled to Pin 16. Reference Voltage, VREF (Pin 11): This pin is internally biased at the reference voltage level. VREF:VREF = VCC/2 - 650mV. The DC voltage level at this pin forms an internal reference for the voltage levels at Pins 10, 12 and 16. Pin 1 must be bypassed to ground with a 0.1F capacitor, for proper operation of the circuit. VCO Control Input (Pin 12): VCO free-running frequencies determined by external timing resistor, R0, connected from this terminal to ground. For optimum temperature stability, R0 must be in the range of 10K to 100k (see Figure 9). Op Amp Compensation (Pin 6): The op amp section is frequency compensated by connecting an external capacitor from Pin 6 to the amplifier output (Pin 8). For unity-gain compensation a 20pF capacitor is recommended. VCO Frequency Adjustment: VCO can be fine-tuned by connecting a potentiometer, RX, in series with R0 at Pin 12 (see Figure 11). Op Amp Inputs (Pins 7 and 9): These are the inverting and the non-inverting inputs for the op amp section. The common-mode range of the op amp inputs is from +1V to (VCC - 1.5) volts. This terminal is a low-impedance point, and is internally biased at a DC level equal to VREF. The maximum timing Rev. 2.10 8 XR-2212 is connected to this pin. The DC level of the sensing threshold for the phase detector is referenced to VREF. If the signal is capacitively coupled to Pin 16, then this pin must be biased from Pin 11, through an external resistor, RB (RB [ 10kW). The peak voltage swing applied to Pin 16 must not exceed (VCC - 1.5) volts. current drawn from Pin 12 must be limited to <3 mA for proper operation of the circuit. VCO Timing Capacitor (Pins 13 and 14): VCO frequency is inversely proportional to the external timing capacitor, C0, connected across these terminals (see Figure 6). C0 must be nonpolar, and in the range of 200pF to 10mF. VCO Quadrature Output (Pin 15): The low-level ([ 0.6Vpp) output at this pin is at quadrature phase (i.e. 90° phase-offset) with the other VCO outputs at Pins 3 and 5. The DC level at Pin 15 is approximately 300mV above VREF. The quadrature output can be used with an external multiplier as a “lock detect” circuit. In order not to degrade oscillator performance, the output at Pin 15 must be buffered with an external high impedance low capacitance amplifier. When not in use, Pin 15 should be left open-circuited. PHASE-LOCKED LOOP PARAMETERS Transfer Characteristics Figure 10 shows the basic frequency to voltage characteristics of XR-2212. With no input signal present, filtered phase detector output voltage is approximately equal to the internal reference voltage, VREF at Pin 11. The PLL can track an input signal over its tracking bandwidth, shown in the figure. The frequencies fTL and fTH represent the lower and the upper edge of the tracking range, f0 represents the VCO center frequency. Phase Detector Input (Pin 16): Voltage output of the VCO (Pin 5) or the output of an external frequency divider Tracking Bandwidth 2VR Phase Detector Output (Pin 10) Df Df VR 0 fTL fO fTH Frequency Input Signal Frequency Figure 10. Phase Detector Output Voltage (Pin 10) as a Function of Input Signal Frequency Note Output Voltage is Referenced to Internal Reference Voltage VREF at Pin 11 Rev. 2.10 9 XR-2212 8. Total Loop Gain, KT KT = 2pKO K0 = 4/C0R1 rad/sec/volt Design Equations (See Figure 3 and Figure 10 for definition of components.) 9. Peak Phase-Detector Current, IA; available at Pin 10. IA = VREF (volts)/25mA 1. VCO Center Frequency, f0: f0 = 1/R0C0 Hz 2. Internal Reference Voltage, VREF (measured at Pin 11) VREF = VCC/2 - 650mV APPLICATION INFORMATION 3. Loop Low-Pass Filter Time Constant, t : t = R1C1 4. Loop Damping, j: + 0.25 FM Demodulation Ǹ XR-2212 can be used as a linear FM demodulator for both narrow-band and wide-band FM signals. The generalized circuit connection for this application is shown in Figure 11, where the VCO output (Pin 5) is directly connected to the phase detector input (Pin 16). The demodulated signal is obtained at phase detector output (Pin 10). In the circuit connection of Figure 10, the op amp section of XR-2212 is used as a buffer amplifier to provide both additional voltage amplification as well as current drive capability. Thus, the demodulated output signal available at the op amp output (Pin 8) is fully buffered from the rest of the circuit. NC 0 C1 where N is the external frequency divider modular (See 2). If no divider is used, N = 1. 5. Loop Tracking Bandwidth, $Df/f0: Df/f0 = R0/R1 6. Phase Detector Conversion Gain, KO: (KO is the differential DC voltage across Pins 10 and 11, per unit of phase error at phase-detector input) KO = -2VREF/p volts/radian 7. VCO Conversion Gain, K0: (K0 is the amount of change in VCO frequency, per unit of DC voltage change at Pin 10. It is the reciprocal of the slope of conversion characteristics shown in Figure 10). K0 = -1/VREFC0R1 Hz/V In the circuit of Figure 11, R0C0 set the VCO center frequency, R1 sets the tracking bandwidth, C1 sets the low-pass filter time constant. Op amp feedback resistors RF and RC set the voltage gain of the amplifier section. Rev. 2.10 10 XR-2212 VCC VCC 1 2 Phase Detector 0.1mF FM Input 6 10 9 0.1mF 30pF 8 7 C1 RL 5K Demod Output RF 16 4 RC 11 Internal Reference 0.1mF R1 5 12 VCO 14 13 R0 CO Rx Fine Tune Figure 11. Circuit Connection for FM Demodulation d) Choose R1 to determine the tracking bandwidth, Df (see design equation 5). The tracking bandwidth, Df, should be set significantly wider than the maximum input FM signal deviation, DfSM. Assuming the tracking bandwidth to be “N” times larger than DfSM, one can re-unite design equation 5 as: Design Instructions The circuit of Figure 11 can be tailored to any FM demodulation application by a choice of the external components R0, R1, RC, RF, C0 and C1. For a given FM center frequency and frequency deviation, the choice of these components can be calculated as follows, using the design equations and definitions given on page 10. Df + R 0 + N Df SM R1 f0 f0 a) Choose VCO center frequency f0 to be the same as FM carrier frequency. b) Choose value of timing resistor R0, to be in the range of 10kW to 100kW. This choice is arbitrary. The recommended value is R0 + 20kW. The final value of R0 is normally fine-tuned with the series potentiometer, RX. Table 2. lists recommended values of N, for various values of the maximum deviation of the input FM signal. c) Calculate value of C0 from design equation (1) or from Figure 7: e) Calculate C1 to set loop damping (see design equation 4). Normally, ς = 1/2 is recommended. Then, C1 = C0/4 for ς = 1/2. C0 = 1/R0f0 Rev. 2.10 11 XR-2212 R0 /R1 = (3)(0.0746) = 0.224 or: R1 = 89.3kW. % Deviation of FM Signal (DfSM/f0) Recommended Value of Bandwidth Ratio, N (N = Df/DfSM) 1% or less 10 Step e): Calculate C1 = (C0 /4) = 186pF. 1% to 3% 5 Step f): 1% to 5% 4 Calculate RC and RF to get $4V peak output swing: Let RF = 100kW. Then, 5% to 10% 3 RC = 80.6kW. 10% to 30% 2 30% to 50% 1.5 Note: All values except R0 can be rounded-off to nearest standard value. FREQUENCY SYNTHESIS Table 2. Figure 12 shows the generalized circuit connection for frequency synthesis. In this application an external frequency divider is connected between the VCO output (Pin 5) and the phase-detector input (Pin 16). When the circuit is in lock, the two signals going into the phase-detector are at the same frequency, or fS = f1/N where N is the modulus of the external frequency divider. Conversely, the VCO output frequency, f1 is equal to NfS. Recommended values of bandwidth ratio, N, for various values of FM signal frequency deviation. (Note: N is the ratio of tracking bandwidth Df to max. signal frequency deviation, DfSM). f) Calculate RC and RF to set peak output signal amplitude. Output signal amplitude, VOUT, is given as: VOUT In the circuit configuration of Figure 12, the external timing components, R0 and C0, set the VCO free running frequency; R1 sets the tracking bandwidth and C1 sets the loop damping, i.e., the low-pass filter time constant (see design equations). + ǒDf Ǔ( V )ǒR ǓǒR ) R Ǔ R R f SM REF 0 1 0 C F C In most applications, RF = 100kW is recommended; then RC, can be calculated from the above equation to give desired output swing. The output amplifier can also be used as a unity-gain voltage follower, by open circuiting RC (i.e., RC = ∞). The total tracking range of the PLL (see Figure 10), should be chosen to accommodate the lowest and the highest frequency, fmax and fmin, to be synthesized. A recommended choice for most applications is to choose a tracking half-bandwidth Df, such that: Note: All calculated component values except R0 can be rounded-off to the nearest standard value, and R0 can be varied to fine-tune center frequency, through a series potentiometer, RX , (See Figure 11). Df fmax - fmin If a variable input frequency and a variable counter modulus N is used, then the maximum and the minimum values of output frequency will be: Design Example fmax = Nmax (fS )max and fmin = Nmin (fS )min Demodulator for FM signal with 67kHz carrier frequency with $5kHz frequency deviation. Supply voltage is +12V and required peak output swing is $4V. If a fixed output frequency is desired, i.e. N and fS are fixed, then a $10% tracking bandwidth is recommended. Excessively large tracking bandwidth may cause the PLL to lock on the harmonics of the input signals; and the small tracking range increases the “lock-up” or acquisition time. Step a) f0 is chosen as 67kHz. Step b) Choose R0 = 20kW (18kW fixed resistor in series with 5kW potentiometer). Step c) Calculate C0; from design equation (1). Design Instructions C0 = 746pF For a given performance requirement, the circuit of Figure 12 can be optimized as follows: Step d) Calculate R1. For given FM deviation, DfSM/f0 = 0.0746, and N = 3 from Table 2. Then: a) Choose center frequency, f0, to be equal to the output frequency to be synthesized. If a range of output Rev. 2.10 12 XR-2212 frequencies is desired, set f0 to be at mid-point of the desired range. If a single fixed output frequency is desired, set R1 to get: b) Choose timing resistor R0 to be in the range of 15k to 100k. This choice is arbitrary. R0 can be fine tuned with a series potentiometer, RX. Df = 0.1 f0 e) Calculate C1 to obtain desired loop damping. (See design equation 4). For most applications, ς = 1/2 is recommended, thus: c) Choose timing capacitor, C0 from Figure 7 or Equation 1. C0 = NC0 /4 d) Calculate R1 to set tracking bandwidth (see Figure 10 and design equation 5). If a range of output frequencies are desired, set R1 to get: Note All component values except R0 can be rounded off to the nearest standard value. Df = fmax - fmin VCC 0.1F 1 2 Input Signal Phase Detector 0.1F 6 VCC 10 9 8 7 C1 16 4 74LS90 or Similar %N 11 0.1F FO= F1/N Output 5 12 R1 VCO F1 = Nfs 1K 14 13 R0 CO Figure 12. Circuit Connection for Frequency Synthesizer Rev. 2.10 13 Internal Reference XR-2212 INPUT SENSITIVITY V IN minimum (peak) + V a–V b + The input to the XR-2212 may sometimes be too sensitive to noise conditions on the input line. Figure 13 illustrates a method of de-sensitizing the XR-2212 from such noisy line conditions by the use of a resistor, Rx, connected from pin 2 to ground. The value of Rx is chosen by the equation and the desired minimum signal threshold level. DV " 2.8V offset + VREF + ǒ RX + 20, 000 VREF * 1 DV VIN minimum (peak) input voltage must exceed this value to be detected (equivalent to adjusting V threshold). Vcc Input ÎÎ To Phase Detector Va Vb 2 20K Rx 20K ÎÎ ÎÎ VREF 11 Figure 13. Desensitizing Input Stage Rev. 2.10 14 Ǔ 20, 000 or (20, 000 ) RX) XR-2212 16 LEAD CERAMIC DUAL-IN-LINE (300 MIL CDIP) Rev. 1.00 16 9 1 8 E E1 D A1 Base Plane Seating Plane A L e c B α B1 INCHES SYMBOL MILLIMETERS MIN MAX MIN MAX A 0.100 0.200 2.54 5.08 A1 0.015 0.060 0.38 1.52 B 0.014 0.026 0.36 0.66 B1 0.045 0.065 1.14 1.65 c 0.008 0.018 0.20 0.46 D 0.740 0.840 18.80 21.34 E1 0.250 0.310 6.35 7.87 E 0.300 BSC 7.62 BSC e 0.100 BSC 2.54 BSC L 0.125 0.200 3.18 5.08 α 0° 15° 0° 15° Note: The control dimension is the inch column Rev. 2.10 15 XR-2212 16 LEAD PLASTIC DUAL-IN-LINE (300 MIL PDIP) Rev. 1.00 16 9 1 8 E1 E D A2 Seating Plane A L α A1 B INCHES SYMBOL eA eB B1 e MILLIMETERS MIN MAX MIN MAX A 0.145 0.210 3.68 5.33 A1 0.015 0.070 0.38 1.78 A2 0.115 0.195 2.92 4.95 B 0.014 0.024 0.36 0.56 B1 0.030 0.070 0.76 1.78 C 0.008 0.014 0.20 0.38 D 0.745 0.840 18.92 21.34 E 0.300 0.325 7.62 8.26 E1 0.240 0.280 6.10 7.11 e eA 0.100 BSC 2.54 BSC 0.300 BSC 7.62 BSC eB 0.310 0.430 7.87 10.92 L 0.115 0.160 2.92 4.06 α 0° 15° 0° 15° Note: The control dimension is the inch column Rev. 2.10 16 C XR-2212 Notes Rev. 2.10 17 XR-2212 Notes Rev. 2.10 18 XR-2212 Notes Rev. 2.10 19 XR-2212 NOTICE EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained herein are only for illustration purposes and may vary depending upon a user’s specific application. While the information in this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies. EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the circumstances. Copyright 1979-2006 EXAR Corporation Datasheet October 2006 Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited. Rev. 2.10 20