EXAR XR68C681

XR68C681
FEATURES
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ORDERING INFORMATION
Part No.
Pin
Package
Operating
Temperature
Range
Part No.
Pin
Package
Operating
Temperature
Range
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XR68C681
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Figure 1. Block Diagram of the XR68C681 DUART Device
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PIN CONFIGURATION
44 Pin PLCC
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XR68C681
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40 Pin PDIP, CDIP
(0.600”)
PIN DESCRIPTION
Pin Number
Pin Number
(44 pin PLCC)
(40 pin DIP)
Symbol
Type
8
Description
No Connect.
#
LSB of Address Input. (% (
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XR68C681
PIN DESCRIPTION (CONT’D)
Pin Number
Pin Number
(44 pin PLCC)
(40 pin DIP)
<
@
Symbol
Type
Description
#,
#
Input Port 0. 0
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Read/Write Input. #+ (% (
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XR68C681
PIN DESCRIPTION (CONT’D)
Pin Number
Pin Number
(44 pin PLCC)
(40 pin DIP)
@
6
Symbol
Type
Description
,@
Output 7. -
% (% (
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Three State Data Bus.
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Three State Data Bus.
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Three State Data Bus.
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XR68C681
PIN DESCRIPTION (CONT’D)
Pin Number
Pin Number
(44 pin PLCC)
(40 pin DIP)
11
1
1=
Symbol
Type
5
Description
Transmitter Serial Data Output. % %(-
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16
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Receiver Serial Data Input. % %(-
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XR68C681
PIN DESCRIPTION (CONT’D)
Pin Number
Pin Number
(44 pin PLCC)
(40 pin DIP)
=
1<
Symbol
Type
Description
#,6
#
Input 5. 0
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Input 4. 0
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XR68C681
DC ELECTRICAL CHARACTERISTICS 1, 2, 3
Test Conditions: TA = 0 - 70C, VCC = 5V +5% unless otherwise specified.
Symbol
Parameter
Min
Typ
Max
Unit
;#:
#
: ;-
6
<
;
;#9
#
9(- ;-
;
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;#9
#
9(- ;- ((&
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#
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=
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Conditions
J 66 6
;
;
=
;
#: J = ;
#9 J =
;:
: ;-
;9
9(- ;-
=
#
:3- 6
6
;#8 J ;
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:3- 1
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#5:
5 #
: #5:
5 #
: @
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5 #
9(- ;#8 J ;
#59
5 #
9(- ;#8 J ;
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#
(
:3- ; J ;
#
, & =
/
6
'( $
#
=
1
$& $
, &
Notes
1. Parameters are valid over the specified temperature and operating supply ranges. Typical values are 25C, V
CC = 5V and typical
processing parameters.
2. All voltages are referenced to ground (GND). For testing, input signal levels are 0.4V and 2.4V with a transition time of 20ns
maximum. All time measurements are referenced at input voltages of 0.8V and 2.0V as appropriate. See Figure 31.
3. For prime grade N, P, J, L, M, ML, V
CC = 5V + 10%
4. Measured operating with a 3.6864MHz crystal and with all outputs open.
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XR68C681
AC ELECTRICAL CHARACTERISTICS 1, 2, 3
Test Conditions: TA = 0 - 70C, VCC = 5.0V +5% unless otherwise specified.
Symbol
Parameter
Min
Typ
Max
Unit
Rest Timing (See Figure 32)
2
22 ,% A($
%
Read, Write and Interrupt Cycle Timing (Figure 33, Figure 34, Figure 35 )
= ( :
%
9
= 9$ ( + 9(-
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A
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%
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A($ =" 6
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9
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6
%
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7 : + $ ;($
%
9
7 9(- + #7 9(-
%
7 9(- #$
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6
%
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<
%
%
Port Timing (Figure 36)
,
, #
( : .A 9(-
,9
, #
9$ ( + 9(-
,
, ;($ + .A" 9(-
%
=
%
1
%
1
%
Interrupt Output Timing (Figure 37)
#
#8 ,1,@ %$ % #
% 9(- +4
+ #
% % *(% (
# #,
+ #
%3 (
#
Clock Timing (Figure 38)
:7
5.:7 2!
9(- : (
:7
5.:7 &% 2!
C
'&
.( 2!
'3 9(- : ( #,
.( 2!
'3
C
'&
%
1/<=
@1@
9G
%
@1@
9G
Conditions
XR68C681
AC ELECTRICAL CHARACTERISTICS 1, 2, 3 (CONT’D)
Test Conditions: TA = 0 - 70C, VCC = 5.0V +5% unless otherwise specified.
Symbol
Parameter
Min
Typ
Max
Unit
Conditions
Clock Timing (Figure 38)
5
+5
5
$ 5
2!
9(- : ( <
5
$ 5
2!
C
'&
/5
5
%
/
9G
9G
16
%
6
%
Transmitter Timing (Figure 39)
5
5 & 5 2!
:
5 & 5 #
:
Receiver Timing (Figure 40)
5
59
5 ( 5
2!
9(-
5 9$ ( + 5
2!
9(-
=
%
%
Notes
1. Parameters are valid over the specified temperature and operating supply ranges. Typical values are 25C, V
CC = 5V and typical
processing parameters.
2. All voltages are referenced to ground (GND). For testing, input signal levels are 0.4V and 2.4V with a transition time of 20ns
maximum. All time measurements are referenced at input voltages of 0.8V and 2.0V as appropriate. See Figure 31.
3. AC test conditions for outputs: CL = 50pF, RL = 2.7k• to V .
CC
4. Consecutive write operations to the same register require at least three edges of the X1 clock between writes.
5. This specification imposes a 6 MHz maximum 68000 clock frequency if a read or write cycle follows immediately after the previous
read or write cycle. A higher 68000 clock can be used if this is not the case.
6. This specification imposes a lower bound on CS and IACK low, guaranteeing that they will be low for at least one CLK period.
7. This parameter is specified only to insure DTACK is asserted with respect to the rising edge of X1/CLK as shown in the timing diagram, not to guarantee operation of the part. If the specified setup time is violated, DTACK may be asserted as shown or may be
asserted one clock cycle later.
8. The minimum high time must be at least 1.5 times the X1/CLK period and the minimum low time must be at least equal to the X1/CLK
period if either channel’s Receiver is operating in external 1X clock mode.
Specifications are subject to change without notice
ABSOLUTE MAXIMUM RATINGS1
& ;- @;
- /6 6
;-% ( %' 0
$ 6; ?@;
1. Stresses above those listed under the Absolute Maximum Ratings may cause permanent damage to the device.
This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the “Electrical Characteristics” section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
2. This product includes circuitry specifically designed for the protection of its internal devices from damaging effects of excessive static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying any voltage larger than the rated
maximum.
XR68C681
A. DATA BUS BUFFER
SYSTEM DESCRIPTION
5/</< '
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PRINCIPLES OF OPERATION
Figure 1 %
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B.1 DUART REGISTER ADDRESSING
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XR68C681
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XR68C681
Read Mode Registers
Write Mode Registers
Address
(HEX)
Register Name
Symbol
Register Name
Symbol
$ -(%" '
" $ -(%"
'
" % -(%" '
'3 ' -(%"
'
%3$ #
%
-(%
#
$ -(%"
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1
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- -(%"
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9
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9
=
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6
#
% -(%
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$ -(%" '
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$ -(%" '
*
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% -(%" '
*
*
'3 ' -(%"
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*
*
22;2
$ -(%"
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*
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- -(%"
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*
9*
! 9$(
- -(%"
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*
9*
#
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#;
#
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#
,
#,
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,
2
.(
$
, *(%
$
,*
.(
$
, *(% $
,*
Table 1. DUART Port And Register Addressing
Note:
The shaded blocks are not Read/Write registers but rather, “Address-Triggered” Commands.
1
XR68C681
Table 1 (
$('% ' '
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Bit 7
Bit 6
Bit 5
Bit 4
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$ -(% +" $
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Section G.3
B.2 COMMAND DECODING
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Bit 2
Bit 1
Bit 0
Miscellaneous Commands
Enable/Disable Transmitter
Enable/Disable Receiver
(
- !
J 8 -
J 2
!
J (% !
J 8 ;($
%
J 8 -
J 2
!
J (% !
J 8 ($
$ %
Table 2. Command Register - CRA, CRB
+
'(
+ ( + '
$ -(%% (% +(& %(-+$ (% ( (% %$ ( $(% %( $. '(
( + '
$ -(% (% %$ (
3 %(% + (%'
% '
$% Table 3
$+(
% '
$% %%'($ ( ( + '
$ -(%% ,% (
'
$% / - */ ++'% & +
' + '
$ -(%F% '
9" '
$% /
- / ++'% %&% '( (
=
XR68C681
Bit 7
Bit 6
Bit 5
Bit 4
Description
Null Command:
Reset MRn Pointer: %% '
F% (
(
Reset Receiver: %% (
$(($ '
'( % (+ $ % %
($ '( (% $(%$ $ # (% +%$
Reset Transmitte4 %% (
$(($ '
%( % (+ $ %
$ ($ 5
(% +'$ (- Reset Error Status: % '($ *3 *" ,(& 2 ,2" (
2 2 $ 2 2 %% (%" M@41N
'(+('&" (+ $" + (' '
(% % H*'3I $"
(% '
$ ( % + '( (
$('% (
%% -(%
#
'3 $" ' ( ,2" 2" 2 * ''%" (% ( '
(
+--$ (
'
%% -(%" ( (% '
$ (% (%%$
#+ 2 $" + (' '
(% % H'I 2 $" '
% + % -(% + ,2" 2 $ * +'$ '' &
'' %(' #
H'I 2 $" % + % (
$('% (%
%$ & '' (% + 9
2 (
$(' (% &% +--$ % H*'3I 2 $ (
$('" $ C(%
(% '
$ %
Reset Break Change Interrupt: % '
F% 3 '
- (
%%
(
Start Break: '% 5
%( % $ %
3 #+ %( (% &" % + 3 & $&$ ( (% #+ %( (% '(" 3 -(
% %(%%(
+
% ''% (
9 (% '$" (G" 52, % + 3 ( -(
Stop Break: 5
(
( - (- ((
( (% 5
( (
(-
+ ( ( + ! ''" (+ &" (% %($
Set Rx BRG Select Extend Bit: % '
F% H'( *0 ' 2!
$
*(I HI - !J
Clear Rx BRG Select Extend Bit: % '
F% H'( *0 '
2!
$ *(I - !J
Set Tx BRG Select Extend Bit: % '
F% H
%( *0 ' 2!
$ *(I HI
Clear Tx BRG Select Extend Bit: % '
F% H
%( *0 ' 2!
$ *(I HI
Set Standby Mode (Channel A): A
(% '
$ (% (
3$ ( '
'
$ -(%" (% $ + ' + %(%" '(%"
.( $ $$((
'('(% ' (
%
$& $ ,% (% '
$ ++'% (
+ (
'( 8 (
(% %$ & $ % & (
3(
- H2 #;2 2I '
$
Set Active Mode (Channel A): A
(% '
$ (% (
3$ ( '
'
$ -(%" (% $ + %
$& $ $ %%
(
Reserved
Reserved
Table 3. Miscellaneous Commands, Upper Nibble of all Command Registers, Unless Otherwise Specified.
6
XR68C681
#
$$((
'
$% (' ( -
'
$ -(%%" % ++%
H$$%%(--$I '
$% % '
$% (%$ (
Table 1" , 8 20#2
2#80IK $ + ($
(+($ & (
H%$$I (
'(+('&" % '
$% 4
82.#2 8
% + (
% '
% + (
$(($ (% ((
, 9
'" (+ ,MN (% % HI" % + '%
$(
- (
" ," (%
% -(' HI %C
&" '
(
3 + H2 , , *#I '
$ % H:2
, , ,#8I '
$ $($
$(%'%%(
(
(
+ %" %
% Section F
, 82.#2 8
2 , , *# 8
C. INTERRUPT CONTROL BLOCK
:2 , , *# 8
(
'
'3 % % & (
H#
(
I (
(
'$% #
C% %(-
#8 (% ($$ (' & -$ %%$ ''
' + & + +(
%4
2' + % '
$% (
3$ & ( $(
- ((
- $ ( '%
$(
- $$%%% %
%'(+($ (
Table 1
!" 82.#2 8
(% (
3$ & '$ + $(
- $$%%
2/ ,% (% H$ (
I ( % (
'(
- '
% + -(% $ % & (
- ( " (
%
% (% '$K (% .( ( (
((
'
(
- $($ $(%'%%(
(
(
+
.(%" % % Section D.2
! + H$$%%(--$I '
$%
(% H2 , , *# I $ (%
'
$ (% (
3$ & +(
- ( + $ $$%% 2/ A
% (
3% (%
'
$ " .% (% %(
- '(
(% HI ((
, , -(% (%" ((
,
%'(+($ %" '
-$
Register
%( 9$ -(% * $&
'( 9$ -(% * $&
'( # * 2
$ + '($ *3 (
% *
2
$ + .( '$
- + (
(
%" #," #," #," #,1
(
'
'3 '
%(%% + #
%
-(% #" #
%3 -(% #" %3$ #
% -(% # $ #
;' -(% #; Table 4 (%% % -(%%" $
( $$%% '(
((
Address Location
(in DUART Address Space)
Description
#
#
% -(%
6/ $ &
#
#
%3 -(%
6/A( &
%3$ #
% -(%
/$ &
#
#;
#
;' -(%
/
Table 4. Listing and Brief Description of Interrupt Control Block Registers
$ % + ' + % -(%% $+(
$ % +%4
C.1 Interrupt Status Registers (ISR)
'
% + # (
$('% %% + (
/
(
'
$((
% #+ & (% ((
% -(%% --$ H(-I" '%
$(
- '
$((
% (%
''(
- #
-
" '
% + # ( (
$('
'%%" %' %
+ (
C% + (+ + #
-(% (% %
$ % +%
XR68C681
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Input Port
Change
Delta Break
B
RXRDY/
FFULLB
TXRDYB
Counter
Ready
Delta Break
A
RXRDY/
FFULLA
TXRDYA
J 8
J 8
J 8
J 8
J 8
J 8
J 8
J 8
J E%
J E%
J E%
J E%
J E%
J E%
J E%
J E%
Table 5. Interrupt Status Register - (ISR) Bit Format
(
- (
$ ' + % (% (% $+(
$ ISR[7]: Input Port Change of State:
#+ (% ( (% -(' HI" H'
- + %I %
$'$ #, #,1 (
% % $ %(' (%
(
& $(
- #, (+ #M@N J #M@N (%
'$ , % $ #, *& $(
- #," % ( $(
4
(
$(($ #
, (
'
-$ %
+(
% + ($ (
%" +(
- + $($ $%'((
+ #," % %
Section E
,% (
$ (% (
'
$((
"
% % $ (
-%4
A( ( $ ( + !((& -(%" M14N #
(% %" % (% %'(+&(
- (' (
(
% %$ (-- H#
, -I (
C%
ISR[5] RXRDYB/FFULLB - Channel B Receiver
Ready or FIFO Full
+
'(
+ (% ( (% %'$ & -(
*M/N #+ -$ % '( $&
(
$(' 5E*" ( (
$('% % '' + $ (% (
9* $ (% $& $ &
, (% ( (% % '' (% %+$
+ '($ %(+ -(% 9* $ (% '$
, $% 9* #+ %( ''% (
9* + $ (
" ( ( % -(
+ 9* (% H$I
#+ (% ( (% -$ % # (
$(' ::*"
( (% % '' (% %+$ + 9* $ %+ '%% 9* ' + (%
( (% '$ , $% 9*K $ &
H(
-I # " 3(
- + ! '' #+
'' (% ((
- (
'% 9* (% +"
(% ( ( % -(
+ $ (
" '' (% $$ (
9*
ISR[4] TXRDYB - Channel B Transmitter Ready
A( -(' HI #M@N
ISR[6] Delta Break Indicator - Channel B:
A
(% ( (% %" ( (
$('% '
* '(
% $'$ -(
(
- $ + '($ 3
(% ( (% '$ % , (
3% '
* H22 *27 9802 #82,I
'
$
(
+(
(
F%
%
% *27 '
$((
" % % Section G.2
@
(% (" %" (
$('% 9* (% & $ (%
$& '' '' + , ( (%
'$ , (% '' 9*K
$ (% % -(
" '' (% %+$ 5E (% % %( (% (
((&
$ $ (% '$ %( (% $(%$
'% $$ (
9* ( %( (%
$(%$ ( %($
XR68C681
ISR[3] Counter Ready
#
#2 $" . .( ( %
#M1N ' ' '&' + %
%C ( ,1 (
#M1N ( '$ &
(
3(
- H, 82I '
$ * (
(
$"
(
#2 $" H, 82I
'
$ ( % .
#
82 $" (% ( (% % .
'% (
'
/ $ (% '$ . (% %$ & H, 82I '
$
A
.( (% (
82 $" (%
'
$ ( % '
ISR[2]: Delta Break Indicator - Channel A
%%(
+ (% ( (
$('% '
'(
% $'$ -(
(
- $ + '($ *3
* (% ( (% '$ , (
3% '
H22 *27 9802 #82,I '
$
(
+(
(
F% %
% *27 '
$((
" % % Section G.2
(
9 + $ (
" ( ( % -(
+ 9 (% H$I
#+ (% ( (% -$ % # 9 + (
$('
::" ( (% % '' (% %+$ +
9 $ & %+$ ''
'%% 9 ' + # (% '$ ,
$% 9 #+ '' (% ((
- (
'%
9 (% +" (% ( ( % -(
+ $
(
" '' (% $$ (
9
ISR[0]: Channel A Transmitter Ready
(% (" %" (
$('% 9 (% & $ (%
$& '' '' + , ( (%
'$ , (% '' 9K
$ (% % -(
" '' (% %+$ 5E (% % %( (% (
((&
$ $ (% '$ %( (% $(%$
'% $$ (
9 ( %( (%
$(%$ ( %($
C.2 Interrupt Mask Register (IMR)
ISR[1] RXRDYA/FFULLA - Channel A Receiver
Ready or FIFO Full
+
'(
+ (% ( (% %'$ & -(
M/N
#+ -$ % '( $&
(
$(' 5E" (% ( (
$('% (% %
'' + $ (
9" $ (% $& $ &
, (% ( (% % '' (% %+$
+ 9 $ (% '$ ,
$% H%I 9 #+ %( ''%
(
%3 -(% (% HA( &I -(%
(' % % %' '
$((
% (
'% (%% (
C% '%% #
$%" % % (
+
%3(
- '3(
- '(
'
$((
% + '%(
- (%% (
C% +" (+ + # (% %%
(& % % #
9" + '
%%" ( + + # (%
%
$ (
+(
- Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Input Port
Change
Delta Break
B
RXRDY/
FFULLB
TXRDYB
Counter
Ready
Delta Break
A
RXRDY/
FFULLA
TXRDYA
J ++
J ++
J ++
J ++
J ++
J ++
J ++
J ++
J J J J J J J J Table 6. IMR Bit Format
<
XR68C681
#+ % (%% '(
(
" .%
%$ ( HI (" ((
#" '%
$(
(
'
$((
:(3(%" $(% %3
'(
'
$((
'%(
- (
" %
%$ ( HI ( '(
'%
$(
- '
$((
(
% % $ (
HI% (% -(%
,% # (% H(
&I -(%" $
+" '
$ & '%%
C.3 Masked Interrupt Status Register (MISR)
'
% + # -(% (% %('& %%
+ 8(
- # $ # -
# J M# %N M# %N
(((
+ (
(
% & $(
- # (% (% ((
# '
-- H(-I $ ( '%
$(
- '
$((
% & $ & # +" %" +(
$(
- (
%% -(%" ( 3
(%(
% +K $ !' H(&(I 8 + #
$ # '
% (
' # (% HA( &I -(%
$ '
$ & '%%" '
% + # ( %$ (% %&% &" + ' $$((
$ $ %+ $
C($ % (% '((& '
((
$ ( % +
#
C.4 Interrupt Vector Register, IVR
/< +(& + (''%%% %%
'$(
'%%(
-
'(+('&" $(
(
%('(
-" ( %
$ (
'3
$- %(-
" + ," & '(
'
% + #; $ %" $ & , (
- (
" '
% + #; (%
$ '(
(
&" (
(
%(' (
+ (
(
- %($%
+" (
'$ (
('(
%" '
%
+ #; ''(% (
-%4
#$
(+& ( '
% C%(
- (
, $(
'(
+K $
' - '
'(
" (
-
&" '
(
% ( (
%(' (
+ (
(
- %C
&" $(
- (
(((G(
+ " %
( $ #; ( !$'( % +
/ 66"
% =/ /= -
(
'%(& (% (% - + %" (
/<!F%
!'(
' " %$ + H%
#
;'I & '(
+ HI
(
%(' (
'
+
$ & (&(
- '
% + #; & = 9
'" % %$ 3
' 3 % (
%(' (
%%
M
% + #;N = (
- &
5/</<" (3 & /<%(% (
$('% $%(-
$ %' $+ '
% +
( #; +(
- 22 '
$((
(% /
%C
&" (+" $(
- H(
'3
$-I '&'
% ! %'(
, $% / +
K $ H
(
(((G$ #
;'I !'(
( -
$
C.5 Limitations of the DUART Interrupt Structure
(
%' ++$ & % % - -
(
% (
%
% '(
9 $ 9 # '
$((
%K H
.( $&I '
$((
" $ '
-% (
3 '
$((
'( 9" %($ +
H *3 $((
I" F% (
%' $% + (
C%% $ '( % %' % ,(& 2 ,2" '(
2 2" (
- 2 2 % $% ++ % ((& '
+(- +
% & ''
' + & + %
'
$((
% % (%" +" '
$$ H($I '( $ & +C
& $(
- %% -(%K $ ''3(
- + & G ( % (% (% %'(& '% (+ % %
% $ H'I M6N J C.6 Servicing DUART Interrupts
/< +(& + (''%%% %%
'$(
'%%(
-
#
'$(
'%%(
-" ( $('" %
%( +
C%(
- (
" ( ($
(+& (%+ (''%%" $(
- H#
'3
$-I
'&' ' (''%% 3
% (' (
$(' (% C%(
- (
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$(
'(
+ ( (
%('
(
(
&" $ ' - '
'(
$
- + %(
- H;'$#
I '%%(
H,$#
I '%%(
- (% %(-
(+('
(
XR68C681
('((' ('(
% %(
- & (% $('%
#
H,$#
I '%%(
-" $'(
+ (
C%" (''%% ( -
- $ ' $ & ( $(' (
$ $(
$(' '%(
- (
&
+ (% (
- '$ (% '$ '
(''%% ' - '
#8
#7
#
,((&
2
'$
'(
$
'$
( (
%(' (
( C($ ' + % ( $('% $$% (
'& ($ $ (' $ ''
$(
- '$(
'%%(
-
Figure 2 %
% %( (%(
+ (
+'
/< '%% + (
%('
'
%($(
%
#,:
#,:
#,:
@
@
7
7
MC68000 Processor
XR68C681
Figure 2. Simple Illustration Depicting the Interfacing of the
XR68C681 DUART to a 68000 Processor
XR68C681
Figure 3 %
% $($ %'(' + 5/</< $(' (
+'(
- /< (''%%
(% +(- %% & (
'%%(
- (
+
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%(%% + H#
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2
'$I 8@=:=<" $ 1(
<(
$'$% 8@=:1< $(%'%%(
%%" +
% 8@=:1< $('% $ H#7 '$I
$ (% $ H#. ( ' '$I #
(%
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((& + =
+
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$%'((
+ (% '('( +% #+ C(% %(' + ," ( ( %% '(" $(
" %(-
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(%
%(-
--% HI (
((& '$
8@=:=< ( -
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((& $ %
(% ((& , #
(% '%" (
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%
% ((& = (
C%" , ( ''3 (
%3 (% + (%
(
%% -(% (
$ $(
%
(
((& #+ %
(
((& (% = %%K , ( '3
$- $
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C% #+ %
(
((& (% 6 -" F%
(
C% ( %('$ ( '(
+ (- ((& (
% ' (''%%
$'($% %(' (% (' (
C%" ( (
$ % & %%(
- + '(
$ % J
" J " J " (
$ (
$(' (% ! %
'&' ( (
'3
$- '&' $$((
&"
/< , (% (
$" ( ( $$%% (% " " $ 1" (
((& "
( $$%% (% = 1 % -(' +" , ( '3
$- (% (
C% & %(
- J " J " 1 J " $
= 1 J ' + '(
$ % %" 88 - @=: ( %% + (
% + H#7 '$I $$((
&" $$%%
( %
%%$ (
$ %
! % '&' ' ( (% %%$" (
+ #7 $'$ ( % %%$ A
(
% %%$" #7 $'$ (
%% $ H#7=" & %%(
- #7 (
+ #
( #7=
%(-
(
- %%$" $$%% (%" < 1" $ - $$%% $'$ %
9" (+ + % $$%% (% -(' HI "
H#. ( ' '$I ( % $ #
(%
+(-" $ ( %%$" &
%%(
- (
+ ,% $% C( (F% (
%%$ (
$ %
$ H#
'3
$-I '&'
& C(% (% H#7I (
%%$
#
%
% %%(
+ #7 (
" ( ' '
% + #; #
;'
-(% $ % @" ( '
$
& , ' % '$ '
% +
#; $ %" ( ( %% 7 (
$ (
+ , $ (% $& $ +
$ % , ( !' (% H$I (
($
(' ( & $ '&' ' (%
H$I '&' (% '$" , ( - & -(
- #7 (
+ K $ (" (
" - 7 ,
' 7 % -$" (
'&' (% '$" $ ! % $ $ (
'&'% ( (3& $$('$ %('(
- (
#+ % $ & (
(((G$ #;" ( %
-(
- /= =/ $ 66 /" , (
(& (% & =" (
$ $(
'(
"
(
&" + (
%(' (
+$% (% $$%% '(
( $$ (
- '
+ , $ , ( '
- '
(% '(
(%&" % %
% ( (
%(' (
!(%% '(
(
%&% & #+ %
% +($ (
(((G #;" (% '
% ( &
$+ / 5/</< $('" (3 & /< %(% (% $%(-
$ $+
+ ( (
' -(%% / #+"
$(
- (
'&'" , $% / + #;" , ( (& (% & =" $ (
' - '
H
(
(((G$ #
;'I !'(
%(' (
" '$ 1/ (
&
A
, % & %('$ (
$ '
$((
% '%(
- (
C%% + ((
$" #8 + ( -$
XR68C681
.A
.A
7
7
@
#,:
@
/
#,:
#,:
=
#)@
1
1
#)/
8@=:=<
#)6
#)1
@
;''
#)=
#7=
#)
#)
1
=
@=:
@
1
< 1
/<
#7
1
=
=
#8
6
@
#7
'$ 1
=
1
6
8@=:1<
$$%%
'$(
- ('(&
#7@
#7/
#76
5/</<
#
=
#71
#7
#7
8
$$%%
'$(
- ('(&
6
/
@
6
@
#. (
'
'$ 1
1
=
6
8@=:1<
@
/
6
=
1
Figure 3. Detailed Schematics of the XR68C681 Interfacing to the 68000 Processor
XR68C681
Figure 4 %
% ((
- $(- $('(
- %C
' + % ( '' ., (
+'" $(
(
% '&'
#8
#,: #,:
1
= 1
#7
@
;2
7
Figure 4. XR68C681/68000 CPU Interrupt Cycle Timing
Interrupt Service Routine
D. TIMING CONTROL BLOCK
L'(% + (
%(' (
4
((
- '
'3 % % %'(+& (
% .% (%% %( $ '( $ ' '
((
- '
'3 '
%(%% + +(
- %4
)('3& ($
(+& '
$((
'%(
- (
C%
)('3& %(' (
& ((
(
- '
$((
'%(
- #
%'( ('(
#
$ ($
(+& '% + (
" ,
% $ (
%% -(% %3$
#
% % -(% + '
% +
# ($
(+(% '
$((
% '%(
- (
C% Section C.1 $+(
% ( + + # $
$(%'%%% ' ' + (% ((
#
/ ( .(
1
*( 0
= 2!
#
,(
% ''3 %(%
$ '(%" $('&
'3 ' -(%% 14 5%
XR68C681
#,=
!
#,1
!
,% -(%%
" :
14
5
!
14
5
!
14
5
!*
14
5
!*
5
5*
#,
M=/N
(($ & /
.
(
(
(($ & /
5.:7
5
%'(
('(
*( 0
#,6
5*
#,
5*
M@N
Figure 5. Block Diagram of DUART Timing Control Block
Figure 5 %
% '3 $(- + ((
- '
'3 + 5/</< $('
2' + ((
- '
'3 (% $(%'%%$ (
+(
- %'(
D.1 Oscillator Circuit:
'&% %'( (% &('& '
'$ !
&
'%% 5.:7 $ 5 (
% %'( '('(
((
'( +
'(
% % $ + %
'&% %'(" $ ++% %(
- %'((
-
=
%(-
" + % & ( -
" $
.( '&% : %(-
+C
'& +
9G $ = 9G (% C($ + (
+ 9" '&% : %(-
+C
'& + 1/</= 9G (% C($ + -
(
+
%
$$ ( % & ( -
Table 3
Figure 6 %
% '
$$ %'(' + 5: %'( '('(& #+ % $%(% % % + %(
- '&% %'("
Figure 7 %
% ' $ '%%&
'('(& ''(% (% L'(
XR68C681
4 ? & O 6 4 ? & O 6 4 •
4 •
5
XR68C681
5
1/</=9G
, %
&%
Figure 6. A Recommended Schematic for the XTAL Oscillator Circuitry
Note:
The user also has an option to drive the oscillator circuit with a TTL input signal, in lieu of using a crystal oscillator. If this approach is
used, the TTL must be driven into the X1/CLK pin, and the X2 pin must be left floating.
#+ % $%(% % % + %(
- '&% %'(" Figure 7 %
% ' $ '%%& '('(& ''(% (% L'(
XR68C681
5
5
1/<=9G
E
@=9=
5 (
% +
%
Figure 7. A Recommended Schematic to Drive Multiple DUARTs From the Same Crystal Oscillator
6
XR68C681
D.2 Bit Rate Generator
*0 *( 0
''% ((
- + %'( '('( $ -
''3 %(-
+ 1
'
& %$ $ '
('(
( % -(
+ 6 % 6 7% ,% *0
( & -
% %
$$ ( % (+ %'(
'('( (% (
- 1/</= 9G $$((
&" '
''3 +C
'(% + *0 / (%
% %
% '
%' + $(++
%% + ( %" -
$ + *0 (% %'(
(% $ &
%(
- '(
- M@N (%(
- + % %% + (
%" + *0" (% %
$ (
$(%'%%(
+ '3 ' -(%% % (
Section D.5 '3
$(- + *0 '('(& (% %
$ (
Figure 8
M@4=N
14 5
M@N
M14N
14 5
5.:7
5
%'(
('(
!
!
*( 0
'
% $ *
*M@4=N
14 5
!*
*M14N
14 5
Figure 8. Block Diagram of the Bit Rate Generator
Portion of the Timing Control Block
/
!*
XR68C681
D.3 Counter/Timer
((
- '
'3 % '
(
% / (
.( . . (% - / (
$
'
(' '
% + % ((
%'% % (% (
Figure 9 %
% '3 $(- +
'('(& %
$(
- . %'(
+ %
((
- %'% + .( '
$ &
((
- ( $ M/4=N !((& %'(
('(
-(% (% / - = ,% % Table 7 + (
%( .( $" $ ((
- %' '
% + (% M/4=N . (% ( ''3 %' -(%% + % % - ( -
+ %(% $
'(%
,% -(%%
" :
(($ & /
$ *
14 5%
#,
(($ & /
.(
5
.DE
,1
5*
M=/N
Figure 9. A Block Diagram of the Circuitry
Associated with the Counter/Timer
Bit 6
Bit 5
Bit 4
C/T Mode
Timing Source
2!
#
#,
5 5 '3 + '
%(
5* 5 '3 + '
* %(
5.:7 #
(($$ & /
(
2!
#
#,
(
2!
#
#," (($$ & /
(
5.:7 #
(
5.:7 #
(($$ & /
Table 7. ACR[6:4] Bit Field Definition - C/T
@
XR68C681
D.3.1 Timer Mode:
,% + . $%" ( $ (%
& $ (' (% +
'(
+ ( %'(
9" + '
%%" '
$
(% % $(%'%%$ ! + '&' + %C . -(
%
(
%(
- % (
.: '( +
$$%%(-- H 82I '
$ Table 1
#
( $" . '% % - $(($
$ -
% %C % ($ (% (' (
''3 ($% + '
% + .( -(%%" $ : . '
%$ % - ( -
(
$ $' /5 ''3 + & ( ($$ & *0 %C" (-(
(
- + . (% (
" ,1
. % '
(
%& %%C
H
82I '
$ '%% . (
'
((
- '&' $ -(
((
- '&' %(
'
% %$ (
$ : 82 2E %% (" (
#
%
-(% #M1N" (% % ' ' '&' + %C
(% % % + . % ($('
(
-
" (+ '
$((
(% -$ -
(
( #
%3 -(%
#
#1@ '
'$ & (%%(
- $$%%(--$ H, 82I '
$ Table 1 #
#2 $" " '
$
$% '& % .
#+ . (% -$ (
( $" +C
'& + %(
- . %C '
!%%$ % +%4
C/T Output Frequency =
fsts
• MCTURN • < +
MCTLRN
D.3.2 COUNTER MODE
where:
fSTS = The frequency of the selected timing source (See
Table 7)
[CTUR] = the contents of the CTUR register in decimal
form
[CTLR] = the contents of the CTLR register in decimal
form
(
' . (% $$ % /5 ''3 %(-
&
'('(&" %(
- ( (% ./ +C
'& + . %(-
+" ( "
$($ + . '
!%%$ % +%4
Bit Rate =
fsts
1 • MCTURN • < +
MCTLRN
'
% + $ : -(%% & '
-$ & (" ( & -(
3 ++' <
#
'
$" . '
% $
+
%% (
(
.:" -(
(
- '(
+ H 82I '
$
82.2E %% ( #M1N (% % '(
- '
+ / . ( '
(
'
% / $ $+ ( ! '
(
/ ( ( (% %$ & , ( H,
82I '
$ #+ ,1 (% -$ + ." ( (
(- ( (
'
(% '$" (' ( -%
# % (- % $ #M1N (% '$
. (% %$ ( H, 82I
'
$ H 82I '
$ ( '
(% (
- %% '
( % (
.: , & '
- '
% +
: & ( '
3% ++'
& + %%C
82 '
$
#+ % -$ (% %
%$ $ %$ + ! '&'
XR68C681
D.4 External Inputs
D.5 Clock Select Registers, CSRA and CSRB
% + % + #
, (
% #, #,6 %$ % $(' !
(
% ((
'
'3 % ((
- %'% + %(% $
'(% + '
% ,% % '
%'(+& ''3 %(-
" ($ + %
!
(
%" (% 5 /5 ''3 %(-
K ( ''3
%' -(%% % $($
$(%'%%(
(
(
% $ ( +
'(
" %
% Section E
#
Figure 5" '3 ' -(%% % 14 5F% ''3 %' -(%% % % '
%' (' ''3 %(-
% ( $( %(% $ '(% + '
% %
% %' 1 $(++
%
$$ ( %
+ *0" .( " % !
(
% ((
- %' + %(%
$ '(%
Table 8 $ Table 9 %
(
%( '
% + % $ ''3 %' $((
- %(% $ '(%
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
'( '3 '
%( '3 '
Table 9
Bit 0
Table 8. Bit Format of the Clock Select Registers, CSRA and CSRB
Field
Bit Rate
CSR[7:4]
ACR[7] = 0 (Bit Rate Set #1)
ACR[7] = 1 (Bit Rate Set #2)
CSR[3:0]
X=0
X=1
X=0
X=1
6
@6
@6
6
1=6
1=6
1=6
1=6
6
6
1
1/
1
1/
/
==7
/
==7
<<7
<<7
6
6@/7
6@/7
=
67
=
67
=<
=<
=<
=<
@
<
<
@
/
/
/
/
1<=7
7
7
1<=7
(
(
(
(
2!
/5
2!
/5
2!
/5
2!
/5
2!
5
2!
5
2!
5
2!
5
Table 9. Bit Format of the Clock Select Registers CSR[3:0] and CSR[7:4]
XR68C681
,% Table 6 '% + % %'(+& +(
- %4
(Note: the b suffix denotes a binary expression. x = don’t care
value).
M@N % %(-
(+('
( * + !(
(& -(%
5 ' 2!
$ (
5 2!
$ (
M@N (% * + !((& '
-(%" $
'
%(& -$ & ((
- !!!!!!! !!!!!!! " (
$ % '"
%'(&
2' %( $ '(" ((
% !
$ ( '
% '$ & ((
- ( $ '
F% '
$ -(%
- (% (
+(
'
+
$ (
Table 1
Table 10 %(G% % '
$%" $ ( ++'
!
$ (%
Register
Contents
Resulting Action
$ -(% " </
! *0 ' 2!
$ *( 5 J $ -(% " /
! *0 ' 2!
$ *( 5 J $ -(% *" *
/
! *0 ' 2!
$ *( 5 J $ -(% *" *
*/
! *0 ' 2!
$ *( 5 J Table 10. Command Register Control Over the Extend Bit
Note: if the user programs either nibble of the Clock
Select Register (CSRn[7:4] or CSRn[3:0]) with values
ranging from 0 16 to C 16, then the user is using the BRG as
a source for timing. However, these standard bit rates
(presented in Table 9) apply only if the X1/CLK pin is
driven with a 3.6864 MHz signal. If a signal with a different
frequency (fo) is applied to the X1/CLK pin, then the
DUART channel is running at the following baud rate:
Actual Baud Rate =
MTable Baud Rate ValueN • fo
1/</= MHz
provided that fo is between 2.0 MHz and 4.0 MHz.
$$((
&" % (
'% + %
$$ $ %" ' +C
'& + ''3 %(-
( / (% %
%
1X vs 16X Clock Signals
% H5 '3I $ H/5 '3I ($
- (% ! +" ( (% (
$(%'%%
( (
- $ %(-
(+('
'
H/5 '3I
%% '($ %( $ & +' + /
1
A% H5 '3I & %% %(-
% ' ( ($ (%" %$ ''& '
'$ - '''& ( % '($ (
% + /5 ''3 (
( + 5 ''3 +(
- -% ( '(+& %
%
'( (
+ '
% (% ''3$ & ' ((
- %' + ((
- '
'3 #+ (%
'( (% '( $ (% '((
- $ + %( %(" %( (% % ''3$ & (%
' ((
- %' 9
'" (% -
''3 +C
'& + '( (% !'& % % + %( (% (% ''(%('
+
%&
'
%
%(
$
'
('(
- '( $ %( -$ '( $
%( $ !'& % $ " %++('(
$(++
'% (
+C
'(% + ''3 %'%
' '( $ %( '
'
( ( % (
'((
- '%%" % %
$ (
+(
- $(%'%%(
% %( $ %(%%(
%&%
% $('$ (
Figure 10 (% %&% '
%(%% + %( 5" $ ' '( 5
XR68C681
Transmitter
TX
Receiver
RX
TX Clock
RX Clock
Figure 10. Example of a Serial Data Transmission System
: % + %% '( (% ''3$ & %' (% %(-& +% + %("
$ '( (% & %(
- %( $ '
( ($
Figure 11 %
% %% + (%
Figure 11. Receiver (1X) Sampling, if the RX clock is slightly faster
than the TX clock.
Figure 11 %% % (
%( '(F% %(
- (
$ ' %( $ ( (%
'
-(
- #
(% '%" '( (% %(
- '
%( $ (" ( $ ( (
( ($" (
' %''%%( $ ( (% (% 3
%
1
'( $(+ #+ (% ''(
+ '( $(+"
( & % (
%(%%(
$
'(
+ (% %( $" % $('$ (
Figure 12.
XR68C681
Received Data
0
Actual Data
0
1
1
0
1
0
0
1
0
0
1
1
0
0
1
1
Figure 12. Illustration of an Error Due to Receiver Drift.
Figure 12 %% '( %(
- (- ( %(
+ $ ( ( # (% (
%(
- " (
(% +(-" '( %$ #
%$ $ '( $(+ '
% (+
' '( (% % %(
''3
#
-
(" + (% H
''$I %&%
(% +
'(
+ ((
- $(++
'% 5 $
5 ' ''3 %(-
% 9" (
$ '' +
'( $(+ $ (
((G *2 $(
- %( $
%(%%(
" & % (
3 '" &
'( %(
- + ( A
(%
+ (% &$" '(" $'(
+ (" ( -(
%(
- (% ( &
% (
- +' &('&" + % %
$&
%" (% % +' (% / 5/</<
1
$(' % ''$% /5 '( %(
- +
( +" (
% $('%" '( $'% ''
' + (" ( '( ( -(
%(
- (% ( & +' + / 9" + %
/5 ''3 ($% %
%$" '( ( %% (% (
((
( ($ (
+ ( ($" $ (
'% %(
- + (" $ + %%C
$ (% (
" - $ + ''" '( ( % %( $ %
5 $ &" ' '( %
'$ ( (% ($(
+ (" '( (" + (
" -(
%(
- %( $ ( ($ (
% % Figure 13 +
'( % '($ , (" ( ( ( ''
' + ( ' ( %
$'$" (% %(
- '$ (% $
XR68C681
%
%
($(
+ *(
*( ,($
@ /5 ''3
($%
Figure 13. The Typical Sampling Pattern of each Receiver
within the XR68C681 Device.
%(
- '
(C ((-% & + %(
$ ( % & (
- $L% '(
%(
- (
" ($(
+ ( ($%" '' '' %(% (% ' (% %''%%+
+ %
%4
D.7 Application Examples using the Timing Control
Block
# ++% ($(' ''(
'( %(
(
Example A: Using the BRG
# ((% '( $(+ %(
- (
$L%
% &('& % (% < ( '' ? (& $ , (%
+" (+ % %'% '( $ $ + / $K $'(
+ (" '( ( -(
%(
- $ / ! / J
61"/ 9G
9" ' '( %
%$ @ 61/ 39G ''3 %" ( (
3 (% '(
% ($(
+ ( (% (
" 61/ 39G ''3 %(-
(% $(($$ & / -
% ''3 / 9G + (
(
$ $ $ (% + ''
5/</< $(' -(% % (
$' !
(
''3 %(-
% ( 5 /5 ''3 %(-
A
% (% -(
'(' % ( 5 /5 ''3 %(-
'3 '
-(%%" % (% $(%$ &% % /5
''3" (
$ ((- ++'% + '( $(+ % (% + $(%$ % 5 ''3 +%
+ " %% (
'(
- %( $ % (%
%&
'
% ( '( 5 ''3
11
#
$ '(+& % + %%% ((
((
'
'3" !% (
'$$
% % (%% '( $ %( $
+ 63% ( '
% % $ +(
-
% 1/</= 9G '&% %'( '%% 5.:7 $ 5 (
%K $((
- 1/</= 9G :
%(-
(
5.:7 (
( 5 (
+(
-
A( / $ -(% (% % ( % %( *0 ' 2!
$
( 5 J 1 A( </ $ -(% (% % ( % '( *0 ' 2!
$ (
5 J = A( !!!!!!! (% % %'% H*( I P Table 9 + (%
$ %
A %++(! $
% (
& !%%(
" $ !
$
% H$
F 'I + (
& !%%(
6 A( <</ (% % %% '( $ %( ( +
'
63% Table 8 $ Table 9
XR68C681
Example B: Programming the Bit Rate via the
Counter/Timer
Example C: Using the External Input Ports
% % (%% %( $ '( $ /63% ( '
* ,% (% ('
( (% ++$ & *0 #
(% '% % '
$ +(
-
% " (
$$((
(
- '
* /63% % 2! *" .% % %( $
'( $ % ( '
% $% + + %% %
$ (
2! *" - ( +(
-4
( = 9G : %(-
(
5.:7 (
" (
5 (
(% + +(
-
A( !!!!!! +(-(
-(%
A( / $ / :
(% % % 9G %C + . ,1
(% %% %% (
. -
(
- %C + +C
'& J = 9G.MN J 9G
1 A( M/4=N
(% ( % . (
( $" $ %' ((
- %' + . 5.:7 (
= A( / *
(% ( %'(+& ((
- %' + '(
$ %( + '
* ( $($ + .
,% (%
-$ (
(% '
+(-(
" . %
% /5 % + %($ $
'($ $ +" '( '('(& ( $(($
9G %C & /" L% (3 + ''3 %(-
%
(-(
(
- + *0
%4 *( J 9G./ J /63%
1=
,
,
2!
& '
' ,1 (
#,1 $ #,= (
%
& &(
- 9G %C (
%
(
(
%
1 A(
/
(% % ( %'(+& ((
- %' + %( $ '( + '
( $($
+ (
(
% #,1 $ #,=" %'(& $$((
&"
(% % $ % % (
%(-
5 %(-
% 9
'" (% $((%(
&/ + (% %(-
+" ( +
'
(% %
,% (+ % & (% !"
.% $ %
%( + %(
- (
'(
- %( $ % (% %&
'
% ( 9G 5 ''3 %(-
K (
$ (
((G ( %
XR68C681
D.8 Explanation of Clock Timing Signals
% + (% %'(
(% !(
%'(+('(
((
- *'3 % #
%" (% %L' % %' + '
%($ '
+%(
& % %%
Limits
Symbol
Parameter
Min.
:7
5.:7 2!
9(- : (
+:7
5.:7 &% 2!
C
'&
.( 2!
'3 9(- : ( #, #
+
.( 2!
'3 C
'& #,
#
5
5 $ 5 2!
9(- : ( (
#," #,1" #,= $ #,6
+5
5 $ 5 2!
C
'& ( #,"
#,1" #,=" $ #,6
Typ.
Max.
Units
%
1/</=
=
9G
%
=
9G
%
+5 /5
/5
9G
+5 5
5
9G
Table 11. The XR68C681 Data Sheet presents the following parameter specifications, in the
“AC ELECTRICAL CHARACTERISTICS”
tCLK - X1/CLK (External) High or Low Time
&% $&
(' -(' - ' +
(% '('(& +" '3" ''" $ +' ((% $$ (
$ % $(' ( +
'(
& (%
'% (( + ( %(-
($ 5.:7 (
% %($ (- $ %%
fCLK - X1/CLK Crystal High or Low Time
(% %'(+(% - + +C
'(%
(%%( 5.:7 (
" ( ( '&%
%'( ($ : (
%(-
+" %
'
& & $ = 9G (% (
fCTC - Counter/Timer External Clock Frequency - IP2
Input
(% '% (( (
+C
'& (
- ($ #, (
" + % & .( %' %('& %% %(-
( +C
'& = 9G '
($ #,
(
" $ %( & $$ & .(
(% %' (% $ 5" (' %
%'(+(% ((% %(-
% ($ #, (
(
%" + % !
''3 %' + %(
$ '(%
tRTX - RXC and TXC (External) High or Low Time via IP2, IP3, IP4 and IP5
tCTC - Counter/Timer External Clock High or Low
Time - IP2 Input
(% '% (( + (
%(-
" (
- ($ #, (
+ % & .(" '
%($ (- $ %%
,% (% (( % (
%( ( 5" (' (% %' %%'($ ( #, (
16
(% %' '% (( + ( %(-
" (
- ($ -
% (
(
%"
#, #,6" + % % %( $ '( ''3
%'" '
%($ (- % (% %' %
(
%( " - ( (% % (% (
(
#,
XR68C681
fRTX - RXC and TXC (External) Frequency - via IP2,
IP3, IP4, and IP5
E. INPUT PORT
(% %' '% ((% 5 $ /5 !
%(-
% %$ ''3 %(% $
'(% #+ % (%% % 5 ''3" .% '
& & %(-
( +C
'(% 9G (%
(
( %% (
( + % % 2! #+
% (%% % /5 ''3" .% '
& &
%(-
( +C
'(% 9G (
' (% 9G ''3 %(-
(% /5 %(-
" (% ( % (
!( ( + 63%
(
'
%$ % -
% (
'
-$ % % + %
(
% + %'( +
'(
% '
% + (
% (% '$ '
$ & , &
$(
- #, -(% + %% + #, #,6 (-
(
%(-
#,M
N (
%% (
-(' HI (
#,M
N ( %((
" ((
#, -(% :(3(%" HI
(
%(-
#,
(
%% (
-(' HI (
#,M
N
( %((
" ((
#, -(%
#
%&" ((
- '
'3 -(% % ((& -
(& & $ % $%(% ((
- '
'3 -(% %
''%% +(
- %'%4
1 $(++
%
$$ ( % ( *0
.(" (' '
'
+(-$ -
( % (' ( + *0
#
% ((
- *'3 ( % (
(
% (' % % + !
''3 %(-
% -
'% ( 1/
E.1 Alternate Functions for the Input Port
Table 12 $%'(% %% + #
,
(
%" %' % ''3 (
% $ $ + '
%(-
%"
$ (
'$% (+ %& - +
'(
$ + #, -(%% ( % -(' % (
" -$%% + (% -$
+
'(
XR68C681
Input
Port
#,
Alternate Function(s)
Approach to Program Alternate Functions
4 $ (
+ '
#, '
-$ +
'(
% (
& %(
- M=N J $($ $(%'%%(
(% +
'(
" % % Section G.3
84 (% (
(% '( :" + +
'(
#,
*4 $ (
+ '
*
#, '
-$ +
'(
% * (
& %(
- *M=N J $($ $(%'%%(
(% +
'(
" % % Section G.3
84 (% (
(% '( : + +
'(
#,
D254 .( 2!
'3 #
#, '
-$ +
'(
% !
''3 (
+ .( & %(
- M/4=N J
M" " N $($ $(%'%%(
(
++'
+ (% '(
% % Section D.2
5*4 2!
'3 (
+ '( '
*
#, '
% -$ +
'(
% !
''3 (
+ '( + '
* & %(
*M@4=N J M" " " N + /5 '3" *M@4=N
J M" " " N + 5 '3
#,1
54 2!
'3 (
+ %( '
#,1 '
-$ +
'(
% !
''3 (
+ %( + '
& %(
M14N J M" " " N + /5 '3" M14N
J M" " " N + 5 '3
#,=
54 2!
'3 (
+ '( '
#,= '
-$ +
'(
% !
''3 (
+ '( + '
& %(
M@4=N J M" " " N + /5 '3" M@4=N
J M" " " N + 5 '3
#,6
5*4 2!
'3 (
+ %( '
*
#,6 '
-$ +
'(
% !
''3 (
+ %( + '
* & %(
*M14N J M" " " N + /5 '3" *M14N
J M" " " N + 5 '3
Table 12. Listing of Alternate Function for the Input Port Pins
E.2 Input Port Configuration Registers (IPCR)
#
, +(-(
-(% (% H$
&I
-(% %% +(
- +
'(
%4
% 3
(' + + (
(
% 4
#, #,1" % '
-$ -(' %" %(
' % $
+ (% -(%
%C
&" #
, +(-(
-(% (%
+
'(
& $(($ (
%'(
%4
% 3
'
-(' % + %
+ (
(
%
( + + #
, +(-(
-(% (%
%
$ (
Table 13.
*(% @ =4 H
- (
:-(' I #$
(+('(
(%
*(% 1 4 '
% + #
,(
% #, #,1
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
#,1
#,
#,
#,
#,1
#,
#,
#,
J 8
J 8
J 8
J 8
J :
J :
J :
J :
J E%
J E%
J E%
J E%
J 9(-
J 9(-
J 9(-
J 9(-
Table 13. Bit Format of the Input Port Configuration Register (IPCR)
(+ $(%'%%(
+ ' (+($" ((
(% -(% +%
1@
XR68C681
Bits 7 - 4: “Change in Logic State” Identification Bits
% (+($% H% $I $ '
$ & H
- + '%I % H
- + '%I ($$ + (
(
% #, - #,1 #+ % H
- + '%I $' '
- (
-('
% (
& + % + (
(
%" & ( ($
(+& H--(
-I (
& %(
- '%
$(
- HI (+($
((
#, HI #+ H
- + '%I $ $' '
- + %" (' (
" &
( +' (% & 3(
- '%
$(
- (+($% % HI
#
$%" (+ (
(
#,1 !(
'% '
- (
-(' %" ( @ ( '
(
-(' HI
Bits 3 - 0: “The Current State of Input Pins IP0 - IP3”
% (+($% H$ &I $ +' '
-(' % #, - #,1 (
(
%
#
$ H#
, - + I (
" % $ +(
-
A( ( $ ( + ( +% + (% %
$ ,% (' (%" ((
-(%" %$$
( + #, ( (
$(' (' + + (
% (
% !(
'$ '
- + % ( + #, %
% %
% + % (
% +" $(
- #," (
%
% H
- + I (
" , ( $(
4
(
(
% --$
+(
% + '
-(
- (
(
(
- # M@N
Bit 7
Bit 6
Bit 5
Bit 4
Bit3
Bit 2
Bit 1
Bit 0
BRG Set
Select
Counter/Timer Mode and Source
Delta IP3
Interrupt
Delta IP2
Interrupt
Delta IP1
Interrupt
Delta IP0
Interrupt
J J Table 7
J
J 8
J
J 8
J
J 8
J
J 8
Table 14. ACR- Auxiliary Control Register
Note:
This “two-tiered” interrupt enabling/disabling approach, for the “Input Change of State” interrupt allows tremendous flexibility for the
user. Setting or clearing the bits in ACR[3:0] allows the user to specify exactly which Input Port pins to be enabled (or disabled) for
generating the “Input Port Change of State” interrupt. Setting or clearing IMR[7] allows the user to “globally” enable or disable this
interrupt.
1<
XR68C681
F. OUTPUT PORT
F.1 Writing Data to the OPR/Output Port Pins
'
%(%% + < ( '
%$ % -
% '
%$ + ((
- $ %% %(-
% &
(& -(
- + $ -(%% "
* $ " * $ % '
+(-(
-(%" , A
%$ %% %(-
% (
% $(
" (' % ( % (
( (
%'
% (
$ (" % + , $
'
%C
&" (
% (% '
$ & H$$%% (--$I '
$%
,-(
- (% ( $(++
+ '
(
(% &(' $
% '('(& '
%(%% + ,
-(% ," $ (
% %%
'
% + , '
% + '
% + (
% !" (+ ( ,M6N
(% % -(' HI" (% ( % (
,6 (
(
- -(' HI :(3(%" (+ ( ,M6N (% % -(' HI" (%
%% (
,6 (
(
- -(' HI (
3% -(
- ( $$ (% '$ % % ''(% (% +
A
((
- (% " % (
3
+ $$%% (--$ '
$%4 H2
, , *#I $ H:2 , ,
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(
3(
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, , *#I '
$" % (% %(
- (% -(' HI (
, 9" (% '(
%%
(
%(
- '%
$(
- (
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$ '
& (
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+ (
% $ (% (
, :(3(%"
H:2 , , *#I '
$ (%
(
3$" %'(+($ (%" ((
, H'$I -(' HI 9" '%
$(
- (
% % -(' HI %
% + ' ( ((
," +(
- ,
% ," (% HI +" % + ' (
" +(
- , (% -(' HI
(% + , '
% $ '$ (
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*#I '
$ % Table 1 ( ''
&(
$" $ %" %'(+&(
- (%" ((
,"
% J %" J '
- ( (% '$ & $$%% (--$ H:2 , , *#I
'
$ % Table 1 ( ''
&(
- $" $ %" %'(+&(
- (% % J '$" J '
-
1
, *(% $
, *(% $
'$ $ ++' + %(
- % '
$% $(%'%%$ (
+(
- %'(
F.1.1 SET OUTPUT PORT BITS COMMAND
' '$ %$ (
3 H2 ,
, *#I '
$ (% % % ((
- '
% $ % @ $$%%
2/ + ,@ , & HI !(%% ((
'$ '
% + $ %" '%
$(
- ("
((
, (% % -(' H(-I & HI (%
%
$ % $ (% (
$$%%
2/" % + '%
$(
- (" ((
, (%
'
-$
A '$ % (% & %4 & HI (%
%
$ %" $(
- % + H2
, , *#I '
$" '%
$(
(
(% % -(' HI $ + & HI (% %
$ %" $(
- (% '
$" %
+ '%
$(
- (
(% '
-$
!4
% '
+ , ,M@4N J M" "
" " " " " N 9
'" % + (
% % +%4
M,@" ,/" ,6" ,=" ,1" ," ," ,N J M" " " "
" " " N
#+ ( +(
- $$%% 2/K
M@""N J M" " " " " " " NK %(
- % + -(% (% +%4
,M@4N J M" " " " " " " N
%C
&" % + (
% %
+%4
M,@" ,/" ,6" ,=" ,1" ," ," ,N J M" " " "
" " " N
(% ! + H2 , , *#I
'
$ (% (%$ (
Figure 14.
XR68C681
State of Output Port Pins (OP7 - OP0)
#
(( ,M@4N
*%" @ (
,M@4N
$$%% 2
Figure 14. Illustration of the “SET OUTPUT PORT BIT” Command and its
Effect on the Output Port Register and the State of the Output Port Pins.
#
%&" + H2 , , *#I
'
$K
J K %% (
'
- + ,M
N" (
,
J K %% (
,M
N J HI" $ (
"
,
J HI
% + '%
$(
- , -(% (" $ (
% + (
(% '
-$
!4
% '
% + , -(%"
, J M" " " " " " " N %C
&" % + (
% 4
M,@" ,/" ,6" ,=" ,1" ," ," ,N J M" " " "
" " " N
F.1.2 CLEAR OUTPUT PORT BITS COMMAND
'$ + (
3(
- (% '
$ (% & %((
+ H2 , , *# 8IK
!' % (% $$%% /
+ M,@"",N
& HI (% H(
I (% $$%%" '%
$(
- ( (
, -(% (% % -(' HI
$ '%
$(
- (
" ,
(% % -(' H(-I & HI (% (
(% $$%%"
=
#+ ( M@""N J M" " " " " " " N $$%% /" %(
- '
% + -(% ( 4
,M@4N J M" " " " " " " N
" %(
- % + (
% ( 4
M,@" ,/" ,6" ,=" ,1" ," ," ,N J M" " " "
" " " N
(% ! + H2 , , *#
8I '
$ (% (%$ (
Figure 15.
XR68C681
State of Output Port Pins (OP7 - OP0)
#
(( ,M@4N
*%" @ (
,M@4N
$$%% Figure 15. Illustration of the “CLEAR OUTPUT PORT BIT” Command and its
Effect on the Output Port Register and the State of the Output Port Pins.
M,@" ,/" ,6" ,=" ,1" ," ," ,N J M" " " "
" " " N
#
%&" + H:2 , , *#I
'
$K
J " %% (
'
- + ,M
N $ '
- (
% + (
" ,
J " %% (
,M
N J " $ %% '%
$(
(
-(' HI
=
F.2 Output Port Configuration Register (OPCR)
(
% '
%$ % -
%
(
%" & '
'
+(-$ %$ (
+
'(
% Table 15 (%% +
'(
%
+ ' + (
%
XR68C681
Output Port
Alternate Function(s)
,
RTSA: C%
$ + '
84 (% (% '( : + +
'
(
,
RTSB: C%
$ + '
* 84 (% (% '( : + +
'
(
,
TXCA_16X Output: /5 %( '3 4
TXCA_1X Output: 5 %( '3 RXCA_1X: Output: 5 '( '3 ,1
TXCB_1X Output: * 5 %( '3 4
RXCB_1X Output: * 5 '( '3 C/T_1_RDY: .( $& + . P Note: This output is an Open-Drain output
when used as the Counter/Timer Ready Output.
,=
RXRDY/FFULL_A Output: '( $&. # #
$(' 84 (% (% (
+ 5E. ::D +
'(
,6
RXRDY/FFULL_B Output: * '( $&. # #
$(' 84 (% (% (
+ 5E. ::D* +
'(
,/
TXRDY_A Output: %( $& #
$(' (% (% (
+ 5ED +
'(
,@
TXRDY_B Output: * %( $& #
$(' (% (% (
+ 5ED* +
'(
Table 15. Listing of the Alternate Functions for the Output Port
& + '(
% + (% (
% %'$ & ((
- ( $ ,
( + + (% -(% +%
Bit 7
Bit 6
Bit 5
Bit 4
OP7
OP6
OP5
OP4
J ,M@N
J 5E*
J ,M/N
J 5E
J ,M6N
J 5E.
::*
Bit 3
Bit 2
OP3
J ,M=N
J 5E.
::
J ,M1N
J . P J 5*5
J 5* 5
Bit 1
Bit 0
OP2
J ,MN
J 5 /5
J 5 5
J 5 5
Table 16. Output Port Configuration Register - OPCR
Note:
OPCR only addresses the alternate functions for output port pins, OP7 - OP2. OP0 and OP1 assume their RTS roles if either
MR1n[7] = 1 or MR2n[5] = 1. Setting those mode register bits enables the RTS function. Otherwise, these two ports will only be
general purpose output ports.
G. SERIAL CHANNELS A and B
2' %( '
+ '(%% +$! %&
'
% '( $ %( '
% '
(
$
$
& %' ( (
+C
'& + *0" ." !
''3 %
% (
- $ *%($% $ (
=
(' '( $ %( + ' '
(
$
$
&" '
'
+(-$ (
(% (
- $%" (' %+ +
' $ $(-
%('%" % % (
3 $ %$ + ($ ('(
%
XR68C681
#
(% %'(
'(
%&% ( %$ $
'(
%'% + %( $ '( $+(
((
+ % + % %&% +%
5
%( ( + 5
%( '3 (-
+ 5
'( ( #
+ 5
'( '3 (-
+ '3 ' -(% Section D" ((
- *'3
G.1 Transmitter (TSR and THR)
(% %'(
+ $ % $(%'%%% %'%
( ' '
% %'% (%$ 4
%( %( 9$(
- -(% $ %(
(+ -(%
'( '( 9$(
- -(% $ '(
(+ -(%
% -(%
$ -(%
$ -(% Section B.2" $
'$(
-
%( ''% $ + , $
'
% ( %( ( % ( (% 5
(
" $$(
- %" % $ (
(& (% %
C($ & %&
'
% '
2' %( '
%(%% + %( (+ -(%
$ %( 9$(
- -(% 9 9
(% '& & # Figure 16 %
% %((+($
(%(
+ $ 9 , (
((% %(%%(
+ %( $ & ((
- '' $ 9 '' ( $$ (
$ '%%$
- # " ( ( '% (
- %((
+ 9 " '' $ (%
%((G$ $ (% %($ + '( ( 5
(
%( '3 + ((
- *'3
5
5
%( (+ -(%
-(
( $ %
, +
,
%( 9$(
-(%
Figure 16. A Simplified Drawing depicting the Transmit Shift Register and the Transmit Holding Register.
=1
XR68C681
A
%( (% ($ (
'(" 5
+ (' '
( '
(
%&
3(
- -(' H(-I 9" L% ( %(%%(
+ ''" %( % '( & -
(
- ( ( (%
%('& 5
--(
- HI + ( ($"
+(
- ($ ($ , ( + '$(
'' #$(& + %(%%(
+ (" % %(-
(+('
( + '' ( %
+(%
+$ & -%%(& %(-
(+('
(% #+ '
('(
' '% + (" %( (
%
$ H(&I ( % %(-
(+('
( + '' $ , ( Figure 17 %
% + + + %( 5
#
(% '%" %( (% %
$(
- 6*/" ( <8
' < (% ''" 8(&" *(
%( #$
*(
5
*(
*(
Figure 17. The Output Waveform of the Transmitter
while sending 5D16 (8-N-1 protocol).
'
-$ -
(
C% , & %(
- #MN $ #M=N +
'
% " $ *" %'(& #
(% '%" $ -
(
C% &( %(
9 $ & + ''% , '
%(' (% (
C% & ((
- '' & 9
%( '
$ $(%$ ( '
$ -(% % Table 2 (
Section B.2 #+ '
$ (% (%%$ $(% %(" ( %( ''% (
9 $ " %(
( '
(
%((
- + (
(
- $ ((
9 $ " ( & '& & +
''% 8 ''% '
(
9
' #*:2 8#2 '
$ % (%%$
==
G.2 Receiver (RSR and RHR)
+
'(
+ %( '( (% '( %( $
5
(
K '
( $" ( '
$ & , '( (% % %
%( +
'(
- $ ''3(
- (&" (+ (& (% (
- %$
'( '
%(%% + '( (+ -(% $ '( 9$(
- -(% 9 9 (%" (
%%
'" & # '( '(% $ 5
(
" ( (% '%%$ - +$%" $ (% '
$ +" $ (%
%+$ 9 (% '' (% '%%$
- 1 &% + # ' '($ ''
'% + # " ( '
H$I $ &
,K ( $% 9 Figure 18 $('% %((+($ $(
- + '(
XR68C681
'( '3 + ((
- *'3
#
'(
( 5
'( (+ -(%
5
$ %
$ & ,
'( 9$(
-(%
Figure 18. A Simplified Drawing of the Receiver Shift
Register and Receiver Holding Register
'( +
'(
% & %
%(
- - 5
(
A
+
$ %( (% ($" (% 5
$ '
%C
&" 5
(
(%
'
(
%& H3(
-I (
- (% ($ '( (%
(
'( $ (% '((
- '%%(
- & $
9" +
$ %( %
$% (" ( (% 5
--(
- HI" '( ''3"
(' (% / (% $ ( /! ''3" (
% %(
- (% ( #+ '( $(
%
(% 5
(
(% %( HI + (% @ %" '( $ '
%($% (% %(-
($
( #+ 5
(
(% II @
%" '( ( (-
(% $
$ % %
H
(%I (% @ % " '( ( %
' %''%%( ( (($ (
% .$
( ! ''3 % + (% /! ''3 (%
+$
=6
(+& $'$ HI (
5
(
(% (
$$ (
%(% % (
%( ! (
%(
- ''3" $ (
'(
- %( $ %
($ (% % ' $ ( (
($$ + (%
( ($
,% (+ /5 ''3 (% %'$ + '("
%(
- '$ ''% ( ' $ &
% (
'( ( '
(
% $ '( '
( + '' +% (" (
( (
% '(
+ ''F% * '( ( ''3 (& (+ -$ ( %
+ , ( #+ '( %% 3 '
$((
(% ( $ (& ''3 (+ & % ($K %''%%+ '(
+ '' (% %$K $
'( ( %
% $ % ''
' + ( + ! ''
XR68C681
Receiver Errors
#+ '( $% % H3I" %$
( + , (" (
- 2 2 (% +--$ &
%(
-" M/N J #+" ' '(
+ ''" %%C
(& ''3 (% (
''" ,(&
2 ,2 (% +--$ & %(
- M6N J #+ 9 %
+" $ '' !(%$ (
K $ (+ $ % ( '%
$(
- 5
(
K
'' (
( (
" $ H'( 2I 2 '
$((
( +--$ (
% -(% M=N J (% (%& %% (
%% + $
(
& (+ 5
(
(% $ %' '
$((
+
( '' ($" $ , ( % $'$
, ( %(
- %$ (
%'K '($
*3 '
$((
* (% %$ A
(% '
$((
(%
$'$ % (
-% H'($ *3I '
$((
(% +--$ (
% -(% M@N J H*3I '' (% $$ (
9
9" + $ (% '($ $$ (
9 ( 5
(
% H3I
'
$((
1 '%
$(
- H *3I (
(%
C%$ (+ -$ $ +--$ (
(
%% -(%
' 5
(
% H3I '
$((
"
%%C
''% ( $$ (
9" $
'%
$(
- H *3I (
'
$((
(
' -(
C%$ (+ -$ $ +--$ (
(
%% -(%
'
-$ -
(
C% , (+ 5E '( $& :: # '
$((
!(%% + ( '
5E '
$((
!(%% % '' +
$ !(%% ((
9" $ (% (& ((
- H$I $ $ & , :: '
$((
!(%% 9 (% '& + $ '
''
& ''% + ( , % $
H$I # % '
%' (
C% '' $ ( 5E :: '
$((
( '
$ -(%% %
(
% $ & %(
- #MN $ #M6N +
'
% $ *" %'(&
2' '
(% C($ ( % -(%%
%$ ($ '
$ ((
- + %
'
% + % -(%% $(%'%%$ (
( %'(
% + $ % 9" $($
$(%'%%(
+ (
$ + % -(%% %
$ (
+(
- %'(
G.3 Mode Registers, MR1n and MR2n
$ -(%%" % %'(+& '
% .% $ (3 '
% -(%% % % '
+(- '
% -- (
$ $%3(
'
(C% (% ((
' + % -(%% $(%'%%$ Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Rx RTS
Control
Rx Interrupt
Select
Error Mode
Select
Parity Mode
J 8
J E%
J!E
J ::
J'
J *'3
J A( ,(&
J ' ,(&
J 8 ,(&
J ( $
Bit 2
Number of Bits
per Character
J 2
J $$
J 6
J /
J @
J <
Table 17. The Bit Format for Mode Registers MR1A and MR1B
=/
Bit 0
Parity Type
Select
Bit 1
XR68C681
+ ' '
(% ''%%$ '
F%
(
(
% (
(% % & $ 22 & H22 ,#82I
Bit 7
Bit 6
Bit 5
Bit 4
Channel Mode
Tx RTS
Control
CTS Enable
Tx
J 8
J 2'
J :' :
J :
J 8
J E%
J 8
J E%
'
$ (
3$ ( '
F% '
$ -(%
+ & $ ( " (
(
('& (
Bit 3
Bit 2
Bit 1
Bit 0
Bit Length
J 6/1
J /6
J /<<
1 J @6
= J <1
6 J <@6
/ J 1<
@ J < J 6/1
J /6
J /<<
* J @6
J <1
J <@6
2 J 1<
J Table 18. The Bit Format for Mode Registers MR2A and MR2B
MR1n[7] - Receiver Request to Send Control
MR1n[5] - Error Mode Select
$(
(&" C% $ (% %%$ -$
& (
3(
- H2 , , *# 8I
H:2 , , *# 8I (
( 9" (+ M@N J (% %" '( ( '
-(
+ '(+('&" %(
- (% ( ( '( - (+ (% 9 (% + (% H+
'
I '
(C (% %+ (
(
- '( %
(% ( '
% (
+ # %% (%
,2" 2" '($ *3 + #+ (% ( (% %
HI" (% (' '
( (
H'I $ #+ (% (% (% % HI" (%
(' '
( (
H*'3I $
Figure 24 %
% $(- (' (%% '('
$ C% %
$ '
+(-(
$
+
'(
MR1n[6] - Receiver Interrupt Select
(% ( %'% ( 5E %% ( ::
%% ( + '
%$ % '(( +
-
(
- (
C% ," #MN +
'
$ #M6N + '
*
=@
#
'' $ % %% (% & & '' (% '
& + # #
'3 $" % (% %
'( -('
+ %% + ''% '(
- + # %(
' % H22 2 I '
$
+ '
% (%%$
MR1n[4:3] - Parity Mode Select
#+ HA#9 ,#EI H 2 ,#EI (
(%
-$" (& ( (% $$$ %($
''% $ '( +% (& ''3 '($ ''% Section H.2 + $%'((
+
( $ (
XR68C681
MR1n[2] - Parity Type Select
Mode Register 2 (Channels A and B)
(% ( %'% 2;28 (& (+ HA#9 ,#E
2I (% -$ $ % + +'$ (&
( (+ H 2 ,#EI $ (% -$ #
($ $ ( %'% % + . +- (
(% ( % ++' (+ H8 ,#EI (% %'$ (
M=41N
+ ' '
(% ''%%$ '
F%
,(
(
% " (' ''% + &
''%% '
F% -(% %C
$%
(% $% '
- '
% + (
MR2n[7:6] - Channel Mode Select
2' '
(
+ + $%
MR1n[1:0] - Bits per Character Select
'% + (% %($ $ '($
(
$ +($ + '' (% $% (
'$
" ,#E" $ , (%
(
- M@4/N J '
+(-% '
(
$ #
(% $" '( $ %( (
$
$
&
Figure 19 %
% $(- $('(
- $ (
5
5
#
'(
( 5
%( (+ -(%
'( (+ -(%
5
-(
- (
%( 9$(
-(%
'( 9$(
-(%
<
<
$ %
, $ + ,
$ %
$ & ,
Figure 19. A Block Diagram Depicting Normal Mode Operation
=<
XR68C681
(
- M@4/N J '% '
(
(' ' $" (' ('& %
(% '($ $ Figure 20 %
% $(
- $('(
- (' ' $ (
+(
- '
$((
% & ( (
(% $
'($ $ (% %($ '
F% 5
'( % $ %( $
$
5
5
#
'(
( 5
'( (+ -(%
%( (+ -(%
5
-(
- (
%( 9$(
-(%
'( 9$(
-(%
<
, % ''%% %(
$ %
$ & ,
Figure 20. A Block Diagram Depicting “Automatic Echo Mode” Operation
1 '
F% 5E $ 52 %% (% (
'(
@ , '( '
('(
% % &"
, %( (
3 (% $(%$
= '($ (& (% ''3$ (% -
$ +
%(%%(
%" %($ (& (% % '($
6 ' +(
- (% ''3$ % (% %($ % '($
/ '($ 3 (% '$ % '($ ( !
($ % ( (% $'$
=
2' '
'
'
+(-$ (
+
$(-
%(' $%
Local Loopback Mode
(% $ (% %'$ & %(
- M@4/N J Figure 21 (% $(- $('(
- ' '3 $
(
XR68C681
;
5
5
5
%( (+ -(%
'( (+ -(%
%( 9$(
-(%
'( 9$(
-(%
<
<
$ %
, + ,
$ %
$ & ,
Figure 21. A Block Diagram Depicting “Local Loopback Mode” Operation
#
(% $4
%( (% (
& '
'$ '( (
%( ''3 (% %$ + '(
= '
F% 5
(
(% (-
$
6 %( (% $" '($ $ $
/ , %( $ '( '
('(
%
'
(
&
1 '
F% 5
(% $ 3(
- (-
6
XR68C681
Remote Loopback Mode
(% $ (% %'$ & %(
- M@4/N J Figure 22 %
% $(- $('(
- '3 $
(
5
5
#
'(
( 5
'( (+ -(%
%( (+ -(%
5
-(
( %( 9$(
-(%
'( 9$(
-(%
Note: The CPU has no access to the Serial Data during Remote Loopback Mode.
Figure 22. A Block Diagram Depicting “Remote Loopback Mode” Operation
#
(% $4
'($ $ (% %($ '
F% 5
'($ $ (% %
, $ %% '
$((
% ''3$
8I (
( & %&%
%+ 9" %(
- M6N J % '
%( - ('&" (
( + ''% (
$ 9 %($ $ &
1 ,(& $ +(
- % (% %($ %
'($
Figure 26 %
% $(- (% %('
$ C% %
$ '
+(-(
$ +
'(
= '( % $
MR2n[4] - Clear to Send Control
6 '($ 3 (% '$ % '($ ( ! ($ % ( (% $'$
#+ (% ( (% " '
% (
#, + '
" #, + '
* % ++' %( #+
( (% HI" %( ( ''3 % + (%
(
' ( (% ( $& %
$ '' #+
(% HI" '' (% %($ #+
(% (- -$" 5
(
% (
3(
% $ %(%%(
+ ! '' (%
$&$ ( -% -% (
(
MR2n[5] - Transmitter Request-to-Send Control
$(
(&" C% $ (% %%$
-$ & (
3(
- H2 , , *#
8I H:2 , , *#
6
XR68C681
( '' (% (
- %((G$ $ ++'
%(%%(
+ '' (% (%
+ (%$ (
Figure 24 $ Figure 26
H3I H 2I 2 (% +--$ (
%
-(%
G.4 Status Register, SRn
MR2n[3:0] - Stop Bit Length
(% ( +($ -% $(
+ % (%
$$ ' %($ '' (
$(
+ ./ ( ( $ ./ ( (%" (
(
'
% + ./ (% '
-$ + ''
-% + /" @ $ < (% 6 ( ''" % (
$(
'
-$ + ./ ( (%
#+ !
! ''3 (% -$ + %(
''3 5
" M1N J %'% % ( $(
+
( ( $ M1N J %'% $(
+ (
(% + %(%%(
'( & ''3% + 3 '
$((
'
+ +(% % ( (%" ( ( + % $ (& ( (% %$ -$%% + -$
%($ % ( - #+ '( $% %
%% -(% ($% % ( %% 9 $ 9 '( $ %(
# %"
%'(&K $ %% ($ , ( % + C(& + '(
+ $ & '(
# %% (
$('% %+ (
$
%&%% $ % , ''3 $ % (+ %( (% & $. (% $& + $ + , # %% (
$('% % (
$(' 9 % ''" (' (% ((
- $
& ," (% + $ (
' + '((
- & ''% ( %( $
'( # %% (
$('% '$ (
( + %% -(%
( + %% -(% % % +
& $ '(
% (+ + %
-(% $ $(%'%%(
+ ' ( +%4
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Received
Break
Framing
Error
Parity Error
Overrun
Error
TXEMT
TXRDY
FFULL
RXRDY
J 8
J E%
J 8
J E%
J 8
J E%
J 8
J E%
J 8
J E%
J 8
J E%
J 8
J E%
J 8
J E%
Table 19. The Bit Format of the Status Register’s SRA and SRB
SRn[7] Received Break
(% ( (
$('% G '' + -$ '' - % '($ ( % ( & %(
- # %((
(% ''($ 3 (% '($ $$((
%+% (
# (
(($ ( 5 (
% 3(
- % +
% + ( ( (% (% $+(
$ % %''%%(
$-% + (
!
! ''3
#+ $ + '
% % H'I $" (% ( & (% '' + 9 (% ( ( '$ (+ 5
(
(% - -(' H(-I " (
!
''
#+ H2I $ % % H*'3I $" (%
(" ' % ( (
%%$ ( H22
2 I '
$ % (
3$ %
% Table 2
A
(% ( (% %" '
F% H9802 #8 *27
I ( (
# (% % ( (
# (% % %
$ + 3 '
$((
" % $+(
$ " (%
$'$
SRn[6] Framing Error
'(F% 3 $' -(' '
$' 3% -(
(
($$ + '' 9" 3 %
%(% ( $ + ! '' ( (
$ + (
$'$
(
- '(
+ '' (%" $ &
%%'($ (& (" '( ( ''3 + H3I
'
$((
(( +(
- % $ (& (
(% H3I '
$((
(% , ( #+ '( $%
6
XR68C681
$' H3I (% (" ( (% --$ H(-I
+--(
- ''
' + 2 2
#+ $ % % H'I $" (%
( & (% '' + 9 #+
(% ( (% % + -(
''" ( ( '$ (+ , ( (% & $'$ (
! ''
#+ H2I $ % % H*'3I $" (%
(" ' % ( (
%%$ ( H22
2 I '
$ % (
3$ %
% Table 2 ,% (+ $ (% H*'3I
(% (" (
%% -(% ( (
%" + %%C
''%" (
$
$
+ '
$((
+
% '($ ''%" ( H22 2
I '
$ % (
3$
SRn[5] Parity Error
(% ( (% % HA#9 ,#EI H 2
,#EI $% -$ $ (+ '%
$(
- '' (
$ # % '($
( (
'' (&
#+ $ % % H'I $" (%
( & (% '' + 9 #+
(% ( (% % + -(
''" ( ( '$ (+ '($ (& (% '' (
! ''
#+ H2I $ % % H*'3I $" (%
(" ' % ( (
%%$ ( H22
2 I '
$ % (
3$ %
% Table 2 ,% (+ $ (% H*'3I
(% (" (
%% -(% ( (
%" + %%C
''%" (
$
$
+ '
$((
+
% '($ ''%" ( H22 2
I '
$ % (
3$
SRn[4] Overrun Error
#+ %" (% ( (
$('% ''% (
'($ $ % # (% % '( + '' # (% + $ '' (%
$& (
((
- + & # %((
A
(% ''%" '' (
(% (
,% " (3 %% -(% (% + 2
(
- 2" ,2 ,(& 2 $ * '($
*3" 2 2 (
$(' (% &% +--$
H*'3I $ %(% 2 '
$((
(% +--$ '''' %(%" $ &
'$ H22 2 I '
$ (%
(
3$
61
SRn[3] Transmitter Empty (TXEMT)
(% ( (% % %( $
% # (% %
+ %(%%(
+ % % ( + '' $ (+
(% '' (
9 ((
%(%%(
(% ( (% '$ %( (%
$(%$" , (% '' 9
SRn[2] Transmitter Ready (TXRDY)
(% (" %" (
$('% 9 (% & $
$& '' '' + , ( (%
'$ , (% '' 9"
$ (% % '' (% %+$ 5E (% % %( (% (
((& $ $
(% % %( (% $(%$ '%
$$ (
9 ( %( (% $(%$ (
%($
SRn[1] FIFO Full (FFULL)
(% ( (% % '' (% %+$ + 9 $ %+ '%% ( ' +
(" # %((
% ''($ # (% %
, $% 9 #+ '' (% ((
- (
'% # (% +" :: ( %
, $% 9
SRn[0] Receiver Ready (RXRDY)
(% ( (
$('% % '' % '($ $ (% ((
- (
# $ & ,
# (% % '' (% %+$ + 9 $ (% '$ ( , $% %
'' '
& %$ (
# ,% % + '
$((
% +--$
& %% -(% '
% -$ -
(
C% , 9" % '
$((
% +--$ & %% -(%
'
-$ -
(
% '
$((
% (%$ 4
M/N (
- 2
M6N ,(& 2
M=N 2
+" (+ %&% ''3(
- (% &$"
% (% '
$$ ($ ' '' &
''3(
- %% -(%
XR68C681
H. SPECIAL MODES OF OPERATION
H.1.1 Receiver-Controlled RTS/CTS Handshaking
H.1 RTS/CTS Handshaking
'
-$ % .
$%3(
-" % % + $ + '
( $('% (% %'(
$%'(% (
% % % (
(
(
- .
9
$%3(
- '(+('&" % (
% 4
'(
$ . 9
$%3(
%(
$ . 9
$%3(
-
#
(% $" '( % ((& ('&
- %((
- $('
'(+('&" (% $ % '( - %(-
(+ (% 9 (% +K $" (% &" & ++'(
(
(
- '( % Figure 23 %
%
$(- + ! (%(
- (
+ '('
$ '
+(-(
Transmitting Device
Receiving Device
,
*
#,
5
5*
5
5*
#,
*
,
::
,=
,
::
5
Figure 23. Block Diagram and Timing Sequence of Two DUARTs
Connected in the Receiver-RTS Controlled Configuration.
6=
XR68C681
Figure 23 %% $('%" $
H'((
- ('I $ $ H
%((
('I
(% ! (-
% +' H'((
- ('I % %( $ H
%((
- ('I % '(
" (%
!" (% %(
- '
+ H'((
- ('I
$ '
* + H
%((
- ('I
! %% ( %%(
H'((
- ('I % -$ %' M@N J ''$(
- Section G.3" (% %% (
-(
- H'((
- ('I + '( '
$$((
&" H
%((
- ('I % -$ %' *M=N J ''$(
- Section G.3" %( + '
* + H
%((
- ('I % -$ $ * (
'
#
(% !" H'((
('I '
% %(-
(% %(-
(% +$ $('& (
* (
+ %((
$('
#+ 9 + H'((
- ('I (% + % $('$ &
:: (
- -(' H(-I" (
('& -$ & ( + '(
'
$ +% %C
&" '
*
%( + H
%((
- ('I ( (% *
(
-$ $ ( ($ %( &
$ 5 + H'((
- ('I
#+ , $% H%I 9 + '((
$('" 9 ( - +" $ ::
66
(
$(' ( -- +% #
(% '%" ::
(
$(' (% '
'$ % (
+ , #
%
% :: --(
- +%" , $
(
(% H
-($-I +
:: % (
C% , $ %(' (% H#
I &
H((
-I M@""N J M" " " " " " " N $$%% 2/ (% '(
!'% H2 ,
, 8I $ '%% ,MN -- H(-I
$ (
, -- HI
%C
&" (% %%$
A( + H'((
- ('I (
%%$ (
+ H
%((
- ('I (%
%%$ % " $ $ %(%%(
+ H
%((
- ('I H'((
- ('I (% ($
Figure 23 %% 5 (
'((
- $ +
% %%$ 9" (
(% !" (%
& '($ '' '%% 9 + H'((
- ('I + :: (
$('
%% (% %%$ $ + H'((
('I (% ('& -$ ( '(
'
%(-
+" %(%%(
+ '
* + %((
- $(' (%" ' -(
"
(
(($
Figure 24 %
% + $(- (%(
- -( '$ %$ (
(
(
- '('
$ . $%3(
- $
XR68C681
'((
- ('
M@N J %((
- ('
*M@N J 2 A( ) $$%% 2
(% (
3% H2 ,
, *# 8I $ %%
, (
" , -('
HI
8
#%
::
%%$Q
8
E2
(% ('&
8-$ & '(
$ '(
#%
E2
::
8-$Q
Figure 24. A Flow Diagram Depicting an Algorithm That Could be Used
to Apply the Receiver-Controlled RTS/CTS Handshaking Mode
H.1.2 Transmitter-Controlled RTS/CTS Handshaking
#
(% $" %( % ((& -
'((
- (' '(+('&"
6/
(% $ % %( - %(-
" ( ($ + &(
- (% 9 $ XR68C681
Transmitting Device
Receiving Device
RTSA
(OP0)
IP2
(RTS-in)
CTSA
(IP0)
OP3
(CTS-out)
TXDA
RXDB
TXRDY_A
(OP7)
To CPU
TXRDY_A
RTSA
CTSA
RXDA
Figure 25. Block Diagram and Timing Sequence of Two DUARTs Connected
in the Transmitter-RTS Controlled Configuration.
Figure 25 %% $('%" $
H
%((
- ('I $ " H'((
- ('I
(% ! %% ( %%(
H
%( ('I % -$ %' M6N J (' %% (
-(
- H
%((
- ('I + %( (%
! + %%% H
%((
- ('I
% -$ %' M=N J ''$(
Section G.3" %( + '
+ H
%((
- ('I % -$ $ (
'
#
'% + H'((
- ('I" #, (
%
-$ -
H#
, - +
I (
C% , +( + (
%(' (
% (% (
%' (+ #,
(
'
- $ #,MN J " , $
H(I M@"" N J M" " " " " " " N $$%% 2/ #
(% %" (
%(' (
$ (
3 H2 , , *#
8I" $ (
'%% -- ,M1N -('
H(-I $ (
" ,1" -('
HI (% $" (
" %% (
+ 6@
H
%((
- ('I $ ( %( $ H'((
- ('I
' '
%( % ($ (% 9 $
+ $" ( ( - " ( H
%( I + A
+ H
%((
- ('I (% --$ H(-I" #, (
(% % --$ H(-I" & -
(
H#
- + I (
C% , A( #,MN J " (3& (
%('
(
$ HA(I M@"" N J M" " " " " " "
N $$%% / #
(% %" #
%(' (
$ (
3 H:2 ,
, *# 8I" $ (
'%% -- ,1
H(-I (% $ (
- (
+ H
%((
- ('I $ (
(( %(%%(
+ $ + '
+ H
%((
- ('I
Figure 26 %
% (- (' $('% -( '$ %$ (
%('
. $%3(
- $ ,%
%$$ '3% (
''
'% ((
H'((
- ('I A% HA(I '3%
(
(
((
H
%((
- ('I
XR68C681
2 A( 9 $$%% 2
0
H#
, - + I
#
#, (
'((
- ('
8
#8, # 22
%(%%(
(% ($
#%
52
%%$
Q
00:2 ,1 D ,#8
H:AI
A( < $$%% 2
8
#%
#, J Q
E%
8
E%
(% ('& 8-$ &
'( $ '(
, --% H9(-I
#8, # 8202
%(%%(
(% $(%$
E%
#%
5E
8-$Q
00:2 ,1 D ,#8
H9#09I
A( < $$%% 8
Figure 26. A Flow Diagram Depicting an Algorithm That Could be Used to Realize
the Transmitter-Controlled RTS/CTS Handshaking Mode
H.2 Multi-drop (8051 9 bit) Mode
H.2.1 Concept of Multi-Drop Mode
2' %( '
+ '
'
+(-$ (
3 $ %+ + ($ ('%% ('(
% (% %'(
( +(% %
'
' + ($ $ $ &" +
'(
$ '$ + (
- (
($ $
(% $ (% '( ( %( H8(
( $I +
<6 +(& (''% #
(% $ + (
H% %(
I" '
'$ !( + 6/ %
%(
% (% %%(" % $('$ (
Figure 27
6<
XR68C681
% ('
5
5
5
5
5
('%
Figure 27. An Illustration Depicting the Concept of Multi-Drop Mode
:*
*
< *( '
.
$$%%. *(
Figure 28. Bit Format of Character Data Being Transmitted in
the Multi-Drop Mode
H% (
I '
('% H
(
%I & %((
- '' &('& & (
H$$%%.I ( +- $$ $ + '' (% &('& %% (
(
(% + $ (
%($ + & '' &" % %
$ (
Figure 28
A
H% (
I % %( '3 +
$ + % %%" ( +(% %
$% $$%%
& ($
(+(% H- I $$%% &
$(++% + $ & (
(
( (% HI (
$$%% & $ HI (
$ &
$$%% &" " (
% H%I % ' '
!(
'($ & % (+ ( (
$(($ % $(' (% (
- $$%%$ '(
+ $$%%$ % ( $ $ ( +
'(
+ $ &% +% %% $$%%$ ( % ( '(% $(%$"
$ ( '
(
(-
$ &% +%
6
& ( (
$ -(
! $$%% &
(% %($ & H% ('I
H.2.2 DUART Multi-Drop Operation
-(
'
((
(% -$ (
($ $ & %(
- M=41N J H" I #
(%
$" %($ '' '
%(%% + ("
-$ + $ (%" $$%%.
. +- (K $ -$ , ( - .
J (
$('% '' (% $" ( . J ($
(+(% ( % $$%%
Transmitter Operation During Multi-Drop Mode
%., '
% % + %($
'' & -(
- MN + '
(
$(
- $ (% (
9 (
- MN J
HI %% (
. J HI $ %(
- MN J HI %% (
. J HI Figure 29 %
% '$ + $(-
+ %((
- ''% $$%% " ( (
($ $
XR68C681
#
3 H22 ,#82I '
$
A( ! (
$ -(%
. *( HI
A( !!!!!!! -(%
%( '
('
A( ' 9
. *( HI
A( !!!!!!! -(%
%( $$%%
' ('
A( ' 9
'% A( '(
('Q
#
3 H22 ,#82I '
$
A( ! (
$ -(%
E%
8
Figure 29. A Flow Diagram Depicting a Procedure That Can be Used to
Transmit Characters in the Multi-Drop Mode.
Receiver Operation during Multi-Drop Mode
A
'
% -$ (
($ $" $ '( % $(%$ &(' '
+(-(
" '( ( $ ''
(
9 $ % 5E (
$(' $.
(
(+ . ( (% HI $$%% +- 9" '' ( $(%'$$ (+ (% . ( (% HI +-
+" (
%
% 5E (
$('" ,
%$ $ '($ '' $ $(
(+
$$%% ( %
% '% + , #+
$$%%% $ '" (
$('(
- ( (% H-
I" , %$ '(" (
/
(
+ %%C
'3% + $ ' '( % $ '( %( $ ( '%%$ % (
(
'($
''% ''%%( , & $(
- 9 % + . +- ( (% ( M6N"
%% -(% ( & %$ (
$(' H,(&
2I +" (
'
L
'(
( '( ' ''" , %$ '
(
( M6N (
$ (+& ( (% HI ''%
' H- ,I $'% $$%% ''" M6N
JHI" ( %$ ' (% $$%% ( (% #+ XR68C681
$$%%% $ '" (% , (% (
$$
'((
+ ! '3 + $" $ %$ $(%
'( Figure 30 %
% + $(- $('(
-
'
$$ '$ + $(
- '($
''% ( (
($ $
%
8& '($
$$%% '
, $$%%
Q
'( (% (%$
(% $$
(
( $
M=41N J M" N
L' '
8
'( (
% (%$
E%
2
'(
8
A( ! ( $ -(%
9%
5E #
$('
%%$
Q
$ (
'
+ 9
E%
'3 M6N
$ (
$$%%
' + 9
#% 8 ' '
M6N J Q
8
E%
Figure 30. A Flow Diagram Depicting a Procedure That Can
be Used to Receive Characters in the Multi-Drop Mode.
H.3 Standby Mode
& '$ (
%
$& $ '
% (% (
(% C($ %" ( (
H#;2 ,2#8I
$ H2 8*E 2I '
$ (%%$ (
'
'
$ -(% $(%% ''3% $(' !' + '&% %'(" (' %(-
(+('
&
$'% (
- '
#
%
$& $" & +
'(
% (' ( '
(
''& $(
- (
" ((
- $
(
3(
- H2 #;2 2I '
$ "
/
% (
3$ ( '
'
$ -(%"
%% $(' (
((
6• %
%(
- %(% $ '(% $ ((
- (
# #
%3 -(% + -(
- (
%
$& $" (% '
$$ &
%(% (
% + (
- -
$ '(
%$ -$ + H2 #;2 2I
'
$" %(
' -(% '
% -
$ (
% $(
- %
$& $ '( (
'
% %$ ( $ %
XR68C681
I. PROGRAMMING
(
+ (% -$ & ((
- '
$% (
( -(%%" ( (
+$'3 (% ($$ & %% -(%% (' '
$ & , -(% $$%%(
- (% %
(
Table 1 $ % '% '
% + "
#" #" ," $ , -(%% $ (
(((G% #; / (
- (
" ' %$ !'(%$ (+
'
% + '
-(%% '
-$" %(
'
'(
'
-% & % (
( (
!" '
-(
- + (% '' (
Bit 4
$ (% (
- '($ & % (
'(
+
% '' #
-
" '
-% -(%%
(' '
'( %( (
%$ $ & ( %( '( $(%$"
$ '(
'
-% %$ $ &
. (% %$
$" '
$" ''3 %'" $ %% -(%% $('$ + ' '
($ (
$
$
(
Table 10 %(G% ( %%(-
% +
' -(%
Bit 7
Bit 6
Bit 5
Bit 3
Bit 2
Bit 1
Bit 0
Rx RTS
Control
Rx Int Select
Error Mode
Parity Mode Select
Parity Select
Number of Bits/Char.
J 8
J E%
J5E
J ::
J J *'3
J A( ,(&
J ' ,(&
J 8 ,(&
J ( $
J 2
J $$
J 6
J /
J @
J <
Table 20. Mode Registers 1: MR1A, MR1B
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Channel Mode
Tx RTS
Control
CTS Enable
Tx
J 8
J 2'
J :' :
J :
J 8
J E%
J 8
J E%
Bit 2
Bit 1
Bit 0
Stop Bit Length
J 6/1
J /6
J /<<
1 J @6
= J <1
6 J <@6
/ J 1<
@ J < J 6/1
J /6
J /<<
* J @6
J <1
J <@6
2 J 1<
J Table 21. Mode Register 2: MR2A, MR2B
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
'( '3 '
%( '3 '
Table 6
Table 6
Table 22. Clock Select Registers: CSRA, CSRB
/
Bit 0
XR68C681
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Miscellaneous Commands
Enable / Disable
Transmitter
Enable / Disable
Receiver
! (
Section B.2
J 8 -
J 2
!
J (% !
J 8 ;($
8 %
J 8 -
J 2
!
J (% !
J 8 ;($
8 %
Table 23. Command Registers: CRA, CRB
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Received
Break
Framing
Error
Parity Error
Overrun
Error
TXEMT
TXRDY
FFULL
RXRDY
J 8
J E%
J 8
J E%
J 8
J E%
J 8
J E%
J 8
J E%
J 8
J E%
J 8
J E%
J 8
J E%
Bit 1
Bit 0
Table 24. Status Registers: SRA, SRB
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
OP7
OP6
OP5
OP4
J,M@N
J5E*
J,M/N
J5E
J,M6N
J5E.
::*
J,M=N
J5E.
::
Bit 2
OP3
OP2
J ,M1N
J . P J 5* 5
J 5* 5
J ,MN
J 5 /5
J 5 5
J 5 5
Table 25. Output Port Configuration Register: OPCR
Bit 3
Bit 2
Bit 1
Bit 0
BRG Set
Select
Bit 7
Counter/Timer #1 Mode and Source
Bit 6
Bit 5
Bit 4
Delta IP3
Interrupt
Delta IP2
Interrupt
Delta IP1
Interrupt
Delta IP0
Interrupt
J J Table 4
J
J 8
J
J 8
J
J 8
J
J 8
Table 26. Auxilliary Control Register: ACR
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Delta IP3
Delta IP2
Delta IP1
Delta IP0
IP3
IP2
IP1
IP0
J 8
J E%
J 8
J E%
J 8
J E%
J 8
J E%
J :
J 9(-
J :
J 9(-
J :
J 9(-
J :
J 9(-
Table 27. Input Port Configuration Register , IPCR
/1
XR68C681
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Input Port
Change
Delta Break
B
RXRDY/
FFULLB
TXRDYB
Counter #1
Ready
Delta Break
A
RXRDY/
FFULLA
TXRDYA
J 8
J E%
J 8
J E%
J 8
J E%
J 8
J E%
J 8
J E%
J 8
J E%
J 8
J E%
J 8
J E%
Table 28. Interrupt Status Register, ISR
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Input Port
Change
Delta Break
B
RXRDY/
FFULLB
TXRDYB
Counter #1
Ready
Delta Break
A
RXRDY/
FFULLA
TXRDYA
J ++
J J ++
J J ++
J J ++
J J ++
J J ++
J J ++
J J ++
J Table 29. Interrupt Mask Register, IMR
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
.6
.=
.1
.
.
.
.
.<
Table 30. Counter/Timer Upper Byte Register, CTUR
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
.@
./
.6
.=
.1
.
.
.
Bit 1
#;
Bit 0
#;
Table 31. Counter/Timer Lower Byte Register, CTLR
Bit 7
#;@
Bit 6
#;/
Bit 5
#;6
Bit 4
#;=
Bit 3
#;1
Bit 2
#;
Table 32. Interrupt Vector Register: IVR
/=
XR68C681
/6
XR68C681
J. Timing Diagrams
;
=;
;
% :%
<;
<;
Figure 31. Input and Output Levels for Timing Measurements
Note:
AC testing inputs are driven at 0.4V for a logic “0” and 2.4V for a logic “1” except for -40 to 85C and -55 to 125C, logic “1” shall be
2.6V. Timing measurements are made at 0.8V for a logic “0” and 2.0V for a logic “1”.
22
2
Figure 32. Reset Timing
//
XR68C681
5.:7
9
=
A
A9
.A
A
@
7
:
9
Figure 33. XR68C681 Read Cycle Timing
/@
XR68C681
5.:7
9
=
A
A9
.A
A
@
:
7
9
Figure 34. XR68C681 Write Cycle Timing
/<
XR68C681
5.:7
#8
#7
@
;2
:
7
9
Figure 35. XR68C681 Interrupt Cycle Timing
/
XR68C681
,
,9
#, #,6
.A , ,@
82A : ,
Figure 36. Port Timing
.A #
#8
Figure 37. Interrupt Timing
@
XR68C681
4 ? & O 6 4 ? & O 6 4 4 5
5/</<
5
1/</=9G
, %
&%
5.:7
:7
. :7
5
5
5
:7
5
Figure 38. Clock Timing
@
XR68C681
*( (
/ '3%
5
#
5
5
5
5 Figure 39. Transmitter Timing
5
5 #
5
59
5
Figure 40. Receiver Timing
@
XR68C681
44 LEAD PLASTIC LEADED CHIP CARRIER
(PLCC)
Rev. 1.00
C
D
D
(
- ,
45 x H1
45 x H2
A2
==
B1
D
D1
B D
2
D3
e
R
D3
A1
A
INCHES
SYMBOL
MIN
MAX
MILLIMETERS
MIN
MAX
/6
<
=
=6@
16
RRR
6
RRR
*
1
11
61
*
/
1
//
<
<
1
1
/<6
/6
@=
@/6
/6
/6/
/6
///
6
/1
=
/
1
6 &
6 *
@ &
@ *
9
=
6/
@
=
9
=
=<
@
6
=6
/=
=
Note: The control dimension is the inch column
@1
XR68C681
40 LEAD CERAMIC DUAL-IN-LINE
(600 MIL CDIP)
Rev. 1.00
=
E
E1
D
A1
Base
Plane
Seating
Plane
A
L
c
e
B
B1
INCHES
SYMBOL
MILLIMETERS
MIN
MAX
MIN
MAX
6
6=
6@
6
@6
1<
*
=
/
1/
//
*
=6
/6
=
/6
'
<
<
=/
666
61
2
66
/
1@
6=
2
/ *
6= *
*
6= *
:
6
1<
6<
6
6
Note: The control dimension is the inch column
@=
XR68C681
8#2
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