xr XRD8799 LOW POWER, 2 MSPS, 10-BIT, A/D CONVERTER WITH 8-CHANNEL MUX FEBRUARY 2001 REV. 1.00 FEATURES • 10-Bit Resolution APPLICATIONS • µP/DSP Interface and Control Application • 8-Channel Mux • High Resolution Imaging - Scanners & Copiers • Sampling Rate - < 1kHz - 2MHz • Wireless Digital Communications • Low Power CMOS - 35 mW (typ) • Multiplexed Data Acquisition • Power Down; Lower Consumption - 0.8 mW (typ) • Input Range between GND and VDD BENEFITS • Reduced Board Space (Small Package) • No S/H Required for Analog Signals less than 100kHz • Reduced External Parts, No Sample/Hold Needed • No S/H Required for CCD Signals less than 2MHz • Suitable for Battery & Power Critical Applications • Single Power Supply (4.5 to 5.5V) • Designer can Adapt Input Range & Scaling • Latch-Up Free • ESD Protection: 2000 Volts Minimum GENERAL DESCRIPTION The XRD8799 is a flexible, easy to use, precision 10bit analog-to-digital converter with 8-channel mux that operates over a wide range of input and sampling conditions. The XRD8799 can operate with pulsed "on demand" conversion operation or continuous "pipeline" operation for sampling rates up to 2MHz. The elimination of the S/H requirements, very low power, and small package size offer the designer a low cost solution. No sample and hold is required for CCD applications up to 2MHz, or multiplexed input applications when the signal source bandwidth is limited to 100kHz. The input architecture of the XRD8799 allows direct interface to any analog input range between AGND and AVDD (0 to 1V, 1 to 4V, 0 to 5V, etc.). The user simply sets VREF(+) and VREF(-) to encompass the desired input range. Scaled reference resistor taps @ 1/4 R, 1/2 R and 3/4 R allow for customizing the transfer curve as well as providing a 1/2 span reference voltage. Digital outputs are CMOS and TTL compatible. The XRD8799 uses a two-step flash technique. The first segment converts the 5 MSBs and consists of autobalanced comparators, latches, an encoder, and buffer storage registers. The second segment converts the remaining 5 LSBs. When the power down input is "high", the data outputs DB9 to DB0 hold the current values and VREF(-) is disconnected from VREF1(-). The power consumption during the power down mode is 0.1mW. ORDERING INFORMATION PART NUMBER PACKAGE O PERATING TEMPERATURE R ANGE XRD8799AIQ PQFP -40°C to +85°C Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com xr XRD8799 LOW POWER, 2 MSPS, 10-BIT, A/D CONVERTER WITH 8-CHANNEL MUX REV. 1.00 FIGURE 1. SIMPLIFIED B LOCK D IAGRAM AND TIMING AVDD Coarse Comparators Adder 5 AV DD DVDD φS 6 φB CLK OFW VREF(+) R3 Fine Resolution Comparators R2 R1 VREF(-) DB9-DB0 DB9-DB0 DFF 5 OFW OE Ladder VREF1(-) CLK φS CLR WR 1 or 8 MUX AIN8 Latch 8 N-1 N N-1 N 10 PD AIN1 φB N A2 3 to 8 Decoder A1 A0 AGND DGND FIGURE 2. PIN OUT OF THE XRD8799 33 PIN CONFIGURATIONS 23 See Packaging Section for Package Dimensions 22 34 Index 12 44 1 11 44-Pin PQFP (10mm x 10mm) 2 xr XRD8799 LOW POWER, 2 MSPS, 10-BIT, A/D CONVERTER WITH 8-CHANNEL MUX REV. 1.00 PIN DESCRIPTIONS PIN # NAME DESCRIPTION PIN # NAME 1 DB6 2 DB7 3 Data Output Bit 6 23 R3 Reference Ladder Tap Data Output Bit 7 24 N/C No Connect DGND Digital Ground 25 AIN1 Analog Signal Input 1 4 DGND Digital Ground 26 AIN2 Analog Signal Input 2 5 DVDD Digital V DD 27 AIN3 Analog Signal Input 3 6 CLR Clear (Active Low) 28 AIN4 Analog Signal Input 4 7 WR Write (Active Low) 29 AIN5 Analog Signal Input 5 8 A2 Address 2 30 AGND Analog Ground 9 A1 Address 1 31 AVDD Analog VDD 10 A0 Address 0 32 AVDD Analog VDD 11 CLK Clock Input 12 OE Output Enable (Active Low) 33 AIN6 Analog Signal Input 6 13 N/C No Connect 34 AGND 14 DB8 Data Output Bit 8 35 PD Power Down 15 DB9 Data Output Bit 9 (MSB) 36 AIN7 Analog Signal Input 7 16 OFW Overflow Output 37 DB0 Data Output Bit 0 (LSB) 17 VREF(+) Upper Reference Voltage 38 DB1 Data Output Bit 1 VREF(-) 39 DB2 Data Output Bit 2 18 Lower Reference Voltage 40 DB3 Data Output Bit 3 19 VREF1(-) Lower Reference Voltage 41 DB4 Data Output Bit 4 20 R1 Reference Ladder Tap 42 DB5 Data Output Bit 5 21 R2 Reference Ladder Tap 43 N/C No Connect 22 AIN8 Analog Signal Input 8 44 N/C No Connect 3 DESCRIPTION Analog Ground xr XRD8799 LOW POWER, 2 MSPS, 10-BIT, A/D CONVERTER WITH 8-CHANNEL MUX REV. 1.00 TABLE 1: TRUTH TABLE FOR INPUT CHANNEL SELECTION CLR WR A2 A1 A0 SELECTED ANALOG INPUT L X X X X AIN1 H L L L L AIN1 H L L L H AIN2 H L L H L AIN3 H L L H H AIN4 H L H L L AIN5 H L H L H AIN6 H L H H L AIN7 H L H H H AIN8 H H X X X Previous Selection NOTE: CLR, WR, A2, A1, A0 are internally connected to ground through 500kΩ resistance. 4 xr XRD8799 LOW POWER, 2 MSPS, 10-BIT, A/D CONVERTER WITH 8-CHANNEL MUX REV. 1.00 ELECTRICAL CHARACTERISTICS ELECTRICAL CHARACTERISTICS AVDD = DVDD = 5 V, FS = 2 MHZ (50% DUTY CYCLE), VREF(+) = 4.6, VREF(-) = AGND, TA = 25°C, UNLESS OTHERWISE SPECIFIED PARAMETER SYMBOL MIN TYP MAX UNITS TEST CONDITIONS/COMMENTS KEY FEATURES Resolution Sampling Rate 10 Bits 2.0 MHz +0.3 1 LSB 1 2 LSB FS .001 Differential Non-Linearity DNL -1 Integral Non-Linearity INL Zero Scale Error EZS 0 50 100 mV Full Scale Error EFS 0 30 60 mV Positive Ref. Voltage5 VREF(+) 1.0 4.0 AVDD V Negative Ref. Voltage5 VREF(-) AGND 1.0 AVDD -1 V VREF 1.0 3.0 AVDD V RL 500 1200 2000 W For Rated Performance ACCURACY (A GRADE)2 Best Fit Line (Max INL - Min INL)/2 REFERENCE VOLTAGES Differential Ref. Voltage5 Ladder Resistance ANALOG INPUT1 Input Bandwidth (-1dB) 1.0 4.0 MHz 1-Channel Input Bandwidth (-1dB) .125 0.5 MHz 8-Channel VREF(-) VREF(+) V Input Voltage Range7 VIN Input Capacitance3 CIN 20 pF Aperture Delay1 tAP 8 ns D IGITAL INPUTS Logical "1" Voltage VIH Logical "0" Voltage VIL Leakage Currents IIN 2.0 V 0.8 V VIN = DGND to DVDD CLK -1 1 µA CLR, WR, A2, A1, A0, PD, OE -5 30 µA Input Capacitance 5 5 pF These input pins have 500kΩ internal resistors to GND xr XRD8799 LOW POWER, 2 MSPS, 10-BIT, A/D CONVERTER WITH 8-CHANNEL MUX REV. 1.00 ELECTRICAL CHARACTERISTICS AVDD = DVDD = 5 V, FS = 2 MHZ (50% DUTY CYCLE), VREF(+) = 4.6, VREF(-) = AGND, TA = 25°C, UNLESS OTHERWISE SPECIFIED PARAMETER SYMBOL MIN TYP MAX UNITS TEST CONDITIONS/COMMENTS Clock Timing Clock Period Rise & Fall Time4 TS 500 tR, t F 1,000,000 ns 10 ns "High" Time tB 125 250 500,000 ns "Low" Time tS 125 250 500,000 ns DIGITAL OUTPUTS COUT=15 PF DVDD-0.5 V ILOAD = 4 mA 0.4 V ILOAD = 4 mA 1 µA VOUT = 0 to DVDD Logical "1" Voltage VOH Logical "0" Voltage VOL Tristate Leakage IOZ Data Hold Time1 tHLD 12 Data Valid Delay1 tDL 30 Write Pulse Width1 tWR 40 ns Multiplexer Address Setup tAS 80 ns tAH 0 ns -1 ns 35 ns Time1 Multiplexer Address Hold Time1 Delay from WR to Multiplexer1 Enable tMUXEN1 80 ns Clock to PD Setup Time tCLKS1 400 ns Clock to UR Setup Time tCLKS2 Clock to PD Hold Time tCLKH1 0 ns 600 6 ns xr XRD8799 LOW POWER, 2 MSPS, 10-BIT, A/D CONVERTER WITH 8-CHANNEL MUX REV. 1.00 ELECTRICAL CHARACTERISTICS AVDD = DVDD = 5 V, FS = 2 MHZ (50% DUTY CYCLE), VREF(+) = 4.6, VREF(-) = AGND, TA = 25°C, UNLESS OTHERWISE SPECIFIED PARAMETER SYMBOL Clock to WR Hold Time tCLKH2 MIN TYP MAX 0 UNITS ns Power Down Time1 tPD 300 ns Power Up Time1 tPU 200 ns Data Enable Delay tDEN 14 16 ns Data High Z Delay tDHZ 4 6 ns Pipeline Delay (Latency) TEST CONDITIONS/COMMENTS 1.5 cycles POWER S UPPLIES 8 Power Down (IDD) IPD-DD Operating Voltage (AVDD, DVDD) VDD Current (AVDD + DVDD) IDD 4.5 0.01 0.10 mA 5.0 5.5 V 7 10 mA PD=High, CLK High or Low PD=Low (Normal Mode) NOTES: 1 Guaranteed. Not tested. 2 Tester measures code transition voltages by dithering the voltage of the analog input (VIN). The difference between the measured code width and the ideal value (VREF/1024) is the DNL error. The INL error is the maximum distance (in LSBs) from the best fit line to any transition voltage. 3 See VIN input equivalent circuit. 4 Clock specification to meet aperture specification (tAP). Actual rise/fall time can be less stringent with no loss of accuracy. 5 Specified values guarantee functional device. Refer to other parameters for accuracy. 6 System can clock the XRD8799 with any duty cycle as long as all timing conditions are met. 7 Input range where input is converted correctly into binary code. Input voltage outside specified range converts to zero or full scale output. 8 DVDD and AVDD are connected through the silicon substrate. Connect together at the package. SPECIFICATIONS ARE SUBJECT TO CHANGE WITHOUT NOTICE 7 xr XRD8799 LOW POWER, 2 MSPS, 10-BIT, A/D CONVERTER WITH 8-CHANNEL MUX REV. 1.00 ABSOLUTE MAXIMUM RATINGS: (TA = +25°C UNLESS OTHERWISE NOTED)1, 2, 3 VDD (to GND) +7 V VREF(+), VREF(-), VREF(-) GND -0.5 to VDD +0.5 V All AINs GND -0.5 to VDD +0.5 V All Inputs GND -0.5 to VDD +0.5 V All Outputs GND -0.5 to VDD +0.5 V Storage Temperature -65 to +150 °C Lead Temperature (Soldering 10 seconds) +300 °C Package Power Dissipation Rating to 75°C PQFP 450mW Derates above 75°C 14mW/ °C NOTE: 1 Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation at or above this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. 2 Any input pin which can see a value outside the absolute maximum ratings should be protected by Schottky diode clamps(HP5082-2835) from input pin to the supplies. All inputs have protection diodes which will protect the device from short transients outside the supplies of less than 100mA for less than 100µs. 3 VDD refers to AVDD and DVDD. GND refers to AGND and DGND. 8 xr XRD8799 LOW POWER, 2 MSPS, 10-BIT, A/D CONVERTER WITH 8-CHANNEL MUX REV. 1.00 disconnects the latches from the comparators. This delay is called aperture delay (tAP). FIGURE 3. XRD8799 T IMING DIAGRAM The coarse comparators make the first pass conversion and selects a ladder range for the fine comparators. The fine comparators are connected to the selected range during the next φB phase. tAP tS tR tB tF FIGURE 4. XRD8799 COMPARATORS VIH CLOCK VIL Sample N-1 Auto Balance Sample N Auto Balance Sample N+1 φS TS Analog Input φB φS VIN Latch VTAP VOH Data Ref Ladder N-1 VOL φB φS tDL tHLD COARSE COMPARATOR φS φB VIN Latch VTAP THEORY OF OPERATION Selected Range 1.0 ANALOG-TO-DIGITAL CONVERSION The XRD8799 converts analog voltages into 1024 digital codes by encoding the outputs of coarse and fine comparators. Digital logic is used to generate the overflow bit. The conversion is synchronous with the clock and it is accomplished in 2 clock periods. φB FINE COMPARATOR AIN Sampling, Ladder Sampling, and Conversion Timing Figure 3 shows this relationship as a timing chart. AIN sampling, ladder sampling and output data relationships are shown for the general case where the levels which drive the ladder need to change for each sampled AIN time point. The ladder is referenced for both last AIN sample and next AIN sample at the same time. If the ladder's levels change by more than 1 LSB, one of the samples must be discarded. Also note that the clock low period for the discarded AIN can be reduced to the minimum t S time. The reference resistance ladder is a series of resistors. The fine comparators use a patented interpolation circuit to generate the equivalent of 1024 evenly spaced reference voltages between VREF(-) and VREF(+). The clock signal generates the two internal phases, φB (CLK high) and φS (CLK low = sample) (See Figure 1). The rising edge of the CLK input marks the end of the sampling phase (φS). Internal delay of the clock circuitry will delay the actual instant when φS 9 xr XRD8799 LOW POWER, 2 MSPS, 10-BIT, A/D CONVERTER WITH 8-CHANNEL MUX REV. 1.00 FIGURE 5. XRD8799 C OMPARATORS Hold Reference Value Past Clock Change for tAP Time Short Cycle Sample will be discarded tS External Settle by Clock Update Time Reference Stable Time - For Sample A Update References Reference Stable Time - For Sample A Clock AINX1 Sample A IN1 Internal AIN Sample Window ΦB ΦS A INX0 Ladder Sample Window (MSB Bank) Ladder Compare (LSB Bank) IN2 IN1 ΦB Not Used Sample A IN1 Sample A IN2 ΦS ΦB ΦS AINX1 Sample A IN2 Sample Ladder for A IN1 Sample Ladder for A INX1 Sample Ladder for AIN2 Sample Ladder for A INX2 Compare Ladder V/S A INX0 Compare Ladder V/S A IN1 Compare Ladder V/S A INX1 Compare Ladder V/S A IN2 External DATA DATA A IN0 DATA A INX0 DATA A IN1 Not Used 1.1 A CCURACY OF CONVERSION: DNL AND INL The transfer function for an ideal A/D converter is shown in Figure 6. DATA A INX1 Not Used The overflow transition (VOFW) takes place at: VIN = VOFW = VREF(+) The first and the last transitions for the data bits take place at: FIGURE 6. IDEAL A/D TRANSFER FUNCTION VIN = V001 = VREF(-) + 1.0 * LSB VIN = V3FF = VREF(-) - 1.0 * LSB VREF = VREF(+) - VREF(-) DIGITAL CODES LSB = VREF / 1024 = (V3FF - V001) / 1022 N OTE: The overflow transition is a flag and has no impact on the data bits. OFW=0 1 LSB In a "real" converter the code-to-code transitions don't fall exactly every VREF/1024 volts. OFW=1 3FF 3FE 002 A positive DNL (Differential Non-Linearity) error means that the real width of a particular code is larger than 1 LSB. This error is measured in fractions of LSBs. 3FD 001 000 LSB V VREF(-) V001 V002 V3FE V3FF V0FW = VREF(+) A Max DNL specification guarantees that ALL code widths (DNL errors) are within the stated value. A specification of Max DNL = + 0.5 LSB means that all code widths are within 0.5 and 1.5 LSB. If VREF = 4.608 V then 1 LSB = 4.5 mV and every code width is within 2.25 and 6.75 mV. 10 xr XRD8799 LOW POWER, 2 MSPS, 10-BIT, A/D CONVERTER WITH 8-CHANNEL MUX REV. 1.00 FIGURE 7. DNL MEASUREMENT ON PRODUCTION TESTER DNL Figure 8 shows the zero scale and full scale error terms. Figure 9 gives a visual definition of the INL error. The chart shows a 3-bit converter transfer curve with greatly exaggerated DNL errors to show the deviation of the real transfer curve from the ideal one. LSB V(N+1) After a tester has measured all the transition voltages, the computer draws a line parallel to the ideal transfer line. By definition the best fit line makes equal the positive and the negative INL errors. For example, an INL error of -1 to +2 LSB's relative to the Ideal Line would be +1.5 LSB's relative to the best fit line. Analog Input V(N) N+1 Output Codes N N-1 (N) Code Width = V(N+1) - V(N) LSB = [ VREF(+) - VREF(-) ] / 1024 FIGURE 9. INL ERROR CALCULATION DNL(N) = [ V(N+1) - V(N) ] - LSB Output Codes The formulas for Differential Non-Linearity (DNL), Integral Non-Linearity (INL) and zero and full scale errors (EZS, EFS) are: Best Fit Line 7 Real Transfer Line 6 DNL (001) = V002 - V001 - LSB ::: 5 EFS DNL (3FE) = V3FF - V3FE - LSB INL 4 EFS (full scale error) = V3FF - [VREF(+) -1.5 * LSB] EZS (zero scale error) = V001 - [VREF(-) + 0.5 * LSB] 3 Ideal Transfer Line 2 FIGURE 8. REAL A/D TRANSFER CURVE 1 EZS DIGITAL CODES 0.5 ∗ LSB 1.2 CLOCK AND CONVERSION TIMING A system will clock the XRD8799 continuously or it will give clock pulses intermittently when a conversion is desired. The timing of Figure 10a shows normal operation, while the timing of Figure 10b keeps the XRD8799 in balance and ready to sample the analog input. EFS 3FF 3FE 002 001 000 V V001 Analog Input (Volt) 1.5 ∗ LSB EZS VREF(-) LSB V002 V3FE V3FF VREF(+) 11 xr XRD8799 LOW POWER, 2 MSPS, 10-BIT, A/D CONVERTER WITH 8-CHANNEL MUX REV. 1.00 FIGURE 10. R ELATIONSHIP OF DATA TO CLOCK CLOCK N 1.3 ANALOG INPUT The XRD8799 has very flexible input range characteristics. The user may set VREF(+) and VREF(-) to two fixed voltages and then vary the input DC and AC levels to match the VREF range. Another method is to first design the analog input circuitry and then adjust the reference voltages for the analog input range. N+1 DATA N N+1 a. Continuous sampling CLOCK N One advantage is that this approach may eliminate the need for external gain and offset adjust circuitry which may be required by fixed input range A/Ds. BALANCE The XRD8799's performance is optimized by using analog input circuitry that is capable of driving the A IN input. Figure 11 shows the equivalent circuit for AIN. N DATA b. Single sampling FIGURE 11. A NALOG INPUT EQUIVALENT CIRCUIT 80 Ω 10 pF AVDD φS R MUX 200 Ω R Series 200 Ω 160 Ω 4 AIN 1 pF 10 pF φS 10 pF φB + 8 50 Ω 1/2 [ VREF(+) 1 pF Channel Selection Control + VREF(-) ] FIGURE 13. ANALOG MUX TIMING 1.4 A NALOG INPUT MULTIPLEXER The XRD8799 includes a 8-Channel analog input multiplexer. The relationship between the clock, the multiplexer address, the WR and the output data is shown in Figure 12. tAS tAH A2, A1, A0 FIGURE 12. MUX ADDRESS TIMING WR tWR tMUXEN1 MUXEN (Internal Signal) Clock Sample N Old Address tCLKS2 Sample M New Address tWR Sample M+1 tCLKH2 1.5 REFERENCE VOLTAGES The input/output relationship is a function of VREF: WR tAS tAH AIN = VIN - VREF(-) VREF = VREF(+) - VREF(-) Address DB0-DB9 DATA = 1024 * (AIN/VREF) N-2 Valid N-1 Valid Old Address N Valid Old Address A system can increase total gain by reducing VREF. M Valid New Address Note: tCLKS2 = tCLKH2 = 0 12 xr XRD8799 LOW POWER, 2 MSPS, 10-BIT, A/D CONVERTER WITH 8-CHANNEL MUX REV. 1.00 FIGURE 14. XRD8799 F UNCTIONAL EQUIVALENT CIRTIMING 1.6 D IGITAL INTERFACES The logic encodes the outputs of the comparators into a binary code and latches the data in a D-type flipflop for output. CUIT AND INTERFACE The functional equivalent of the XRD8799 (Figure 14) is composed of: φS D A/D VIN 1. Delay stage (tAP) from the clock to the sampling phase (fS). Q D tAP 2. An ideal analog switch which samples VIN. CLK XRD8799 3. An ideal A/D which tracks and converts VIN with no delay. 4. A series of two DFF's with specified hold (tHLD) and delay (tDL) times. N CLK N+1 tHLD VIN tAP, tHLD and tDL are specified in the Electrical Characteristics table. tDL DB9-DB0 N-1 1.7 POWER DOWN Figure 15 shows the relationship between the clock, sampled VIN to output data relationship and the effect of power down. FIGURE 15. POWER DOWN TIMING DIAGRAM CLK SAMPLE N SAMPLE M SAMPLE M+1 VIN DB0-DB9 N-2 Valid N-1 Valid N Valid M Valid tCLKH1 tCLKS1 PD DB9-DB0 Q tPD tPU IDD, IVREF(+) 13 N xr XRD8799 LOW POWER, 2 MSPS, 10-BIT, A/D CONVERTER WITH 8-CHANNEL MUX REV. 1.00 2.0 APPLICATION NOTES FIGURE 16. TYPICAL CIRCUIT CONNECTIONS +5 V C1 = 4.7 or 10µF Tantalum C2 = 0.1µ F Chip Cap or low inductance cap RT = Clock Transmission Line Termination C1A, C2A AVDD 1 of 8 C1D, C2D DVDD Z < 100Ω OFW AIN1 (Substrate) AIN Buffer DB9 - DB0 AIN8 Resistive Isolation of 50 to 100Ω OE XRD8799 WR CLK VREF(+) + Reference Voltage Source C1 C2 C1 CLK 3/4 R C2 RT 1/4 R C1 C2 - VREF(-) A2 A1 VREF1(-) AGND DGND A0 ground plane should act as a shield for parasitics and not a return path for signals. To reduce noise levels, use separate low impedance ground paths. DGND should not be shared with other digital circuitry. If separate low impedance paths cannot be provided, DGND should be connected to AGND next to the XRD8799. 7. DVDD should not be shared with other digital circuitry to avoid conversion errors caused by digital supply transients. DVDD for the XRD8799 should be connected to AVDD next to the XRD8799. The following information will be useful in maximizing the performance of the XRD8799. 1. All signals should not exceed AVDD +0.5 V or AGND -0.5 V or DVDD +0.5 V or DGND -0.5 V. 2. Any input pin which can see a value outside the absolute maximum ratings (AVDD or DVDD+0.5 V or AGND -0.5 V) should be protected by diode clamps (HP5082-2835) from input pin to the supplies. All XRD8799 inputs have input protection diodes which will protect the device from short transients outside the supply ranges. 3. The design of a PC board will affect the accuracy of XRD8799. Use of wire wrap is not recommended. 4. The analog input signal (VIN) is quite sensitive and should be properly routed and terminated. It should be shielded from the clock and digital outputs so as to minimize cross coupling and noise pickup. 5. The analog input should be driven by a low impedance (less than 50 Ω). 8. DVDD and AVDD are connected inside the XRD8799. DGND and AGND are connected internally. 9. Each power supply and reference voltage pin should be decoupled with a ceramic (0.1µF) and a tantalum (10µF) capacitor as close to the device as possible. 10. The digital output should not drive long wires. The capacitive coupling and reflection will contribute noise to the conversion. When driving distant loads, buffers should be used. 100Ω resistors in series with the digital outputs in some applications reduces the digital output disruption of AIN. 6. Analog and digital ground planes should be substantial and common at one point only. The 14 xr XRD8799 LOW POWER, 2 MSPS, 10-BIT, A/D CONVERTER WITH 8-CHANNEL MUX REV. 1.00 FIGURE 17. EXAMPLE OF A REFERENCE VOLTAGE SOURCE +5V 5k 0.1µ F + MP5010 100k + - - FIGURE 18. ±5V ANALOG INPUT +5V 1 of 8 +5V R +5V R VREF(+) AVDD + VIN DB0 AIN1 - AIN8 VREF(-) AGND For R = 5k use Beckman Instruments #694-3-R10k resistor array or equivalent. NOTE: High R values affect the input BW of ADC due to the (R * CIN of ADC) time constant. Therefore, for different applications the R value needs to be selected as a trade-off between AIN settling time and power dissipation. 15 xr XRD8799 LOW POWER, 2 MSPS, 10-BIT, A/D CONVERTER WITH 8-CHANNEL MUX REV. 1.00 FIGURE 19. ±10V ANALOG INPUT +5V 1 of 8 +10V 2R +5V R VREF(+) AVDD + VIN DB0 AIN1 2R AIN8 VREF(-) AGND For R = 5k use Beckman Instruments #694-3-R10k resistor array or equivalent. NOTE: High R values affect the input BW of ADC due to the (R * CIN of ADC) time constant. Therefore, for different applications the R value needs to be selected as a trade-off between AIN settling time and power dissipation. FIGURE 20. A/D LADDER AND AIN WITH PROGRAMMED C ONTROL (OF VREF(+), VREF(-), 1/4 AND 3/4 TAP.) XRD8799 MP7641 - VIN + DAC0 AIN1 - VIN + DAC7 AIN8 MP7226 DAC4 VREF(+) DAC3 3/4 DAC2 1/4 VREF(+) DAC1 VREF1(-) @ Power Down write values to DAC 3, 2, 1 = DAC 4 to minimize power consumption. Only AIN and Ladder detail shown. 16 xr XRD8799 LOW POWER, 2 MSPS, 10-BIT, A/D CONVERTER WITH 8-CHANNEL MUX REV. 1.00 FIGURE 21. DNL VS. SAMPLING FREQUENCY 2.0 V DD = 5V 1.5 V REF(+) = 4.6V DNL(LSB) 1.0 V REF(-) = 0V POS. DNL 0.5 0.0 -0.5 NEG. DNL -1.0 -1.5 -2.0 0.1 1.0 10.0 FS(MHz) FIGURE 22. INL VS. SAMPLING FREQUENCY 4 3 INL(LSB) 2 V DD = 5V V REF(+) = 4.6V V REF(-) = 0V POS. INL 1 0 -1 NEG. INL -2 -3 -4 0.10 1.00 FS(MHz) 17 10.00 xr XRD8799 LOW POWER, 2 MSPS, 10-BIT, A/D CONVERTER WITH 8-CHANNEL MUX REV. 1.00 FIGURE 23. SUPPLY CURRENT VS. SAMPLING FREQUENCY 9.5 9.0 8.5 IDD (mA) 8.0 VDD = 5V VREF(+) = 4.6V VREF(-) = 0V 7.5 7.0 6.5 6.0 5.5 5.0 0.0 2.0 4.0 6.0 8.0 10.0 Fs(MHZ) INL(LSB) FIGURE 24. B EST FIT INL VS. REFERENCE VOLTAGE 2 1.8 1.6 1.4 1.2 1 0.8 0.6 0.4 0.2 0 VDD = 5V Fs = 2MHz 0.5 1.0 1.5 2.0 2.5 3.0 V REF(V) 18 3.5 4.0 4.5 5.0 xr XRD8799 LOW POWER, 2 MSPS, 10-BIT, A/D CONVERTER WITH 8-CHANNEL MUX REV. 1.00 FIGURE 25. DNL VS. REFERENCE VOLTAGE 1.0 VDD = 5V 0.8 Fs = 2MHz 0.6 DNL(LSB) 0.4 POS. DNL 0.2 0.0 -0.2 NEG. DNL -0.4 -0.6 -0.8 -1.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 V REF(V) FIGURE 26. SUPPLY CURRENT VS. TEMPERATURE 10 V DD = 5V V REF(+) = 4.6V 8 V REF(-) = 0V F S = 2MHz I DD (mA) 6 4 2 0 -60 -40 -20 0 20 Temperature(C) 19 40 60 80 100 xr XRD8799 LOW POWER, 2 MSPS, 10-BIT, A/D CONVERTER WITH 8-CHANNEL MUX REV. 1.00 FIGURE 27. DNL VS. TEMPERATURE 1.0 V DD = 5V DNL(LSB) 0.8 V REF(+) = 4.6V 0.6 V REF(-) = 0V 0.4 FS = 2MHz POS. DNL 0.2 0.0 -0.2 NEG. DNL -0.4 -0.6 -0.8 -1.0 -60 -40 -20 0 20 40 60 80 100 Temperature(C) FIGURE 28. R EFERENCE RESISTANCE VS.TEMPERATURE 2.00 V DD = 5V 1.75 V REF(+) = 4.6V Ref. Resistance(Kohm) V REF(-) = 0V 1.50 FS = 2MHz 1.25 1.00 0.75 0.50 0.25 0.00 -60 -40 -20 0 20 Temperature(C) 20 40 60 80 100 xr XRD8799 LOW POWER, 2 MSPS, 10-BIT, A/D CONVERTER WITH 8-CHANNEL MUX REV. 1.00 FIGURE 29. INL @ 2MSPS 4.0 V DD = 5V V REF (+) = 4.6V 3.0 V REF(-) = 0V 2.0 LSB 1.0 0.0 -1.0 -2.0 -3.0 -4.0 0 128 256 384 512 Code 21 640 768 896 1024 xr XRD8799 LOW POWER, 2 MSPS, 10-BIT, A/D CONVERTER WITH 8-CHANNEL MUX REV. 1.00 44 LEAD PLASTIC QUAD FLAT PACK (10 mm x 10 mm QFP, 1.60 mm Form) REV. 2.00 D D1 33 23 22 34 D1 D 12 44 1 11 B e A2 C A α Seating Plane A1 L Note: The control dimension is the millimeter column INCHES MILLIMETERS SYMBOL MIN MAX MIN MAX A 0.072 0.093 1.82 2.45 A1 0.001 0.010 0.02 0.25 A2 0.071 0.087 1.80 2.20 B 0.011 0.018 0.29 0.45 C 0.004 0.009 0.11 0.23 D 0.510 0.530 12.95 13.45 D1 0.390 0.398 9.90 10.10 e 0.0315 BSC 0.80 BSC L 0.029 0.040 0.73 1.03 α 0° 7° 0° 7° 22 xr XRD8799 LOW POWER, 2 MSPS, 10-BIT, A/D CONVERTER WITH 8-CHANNEL MUX REV. 1.00 NOTICE EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration purposes and may vary depending upon a user’s specific application. While the information in this publication has been carefully checked; no responsibility, however, is assumed for in accuracies. EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the circumstances. Copyright 2001 EXAR Corporation Datasheet February 2001 Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited. 23