XRK32309 PRELIMINARY LOW-COST 3.3V ZERO DELAY BUFFER MAY 2006 REV. P1.0.1 GENERAL DESCRIPTION In this case, the skew between the outputs of two devices is guaranteed to be less than 700 ps. FUNCTIONAL DESCRIPTION Offered in both 16 pin SOIC and TSSOP packages, XRK32309 is a low cost 3.3V zero delay buffer. It is designed to distribute high speed clocks by taking one reference input and driving nine output clocks. The feedback of its on-chip PLL is internally connected to the FB output. XRK32309 devices operate over 10-100 MHz frequency range with 30 pF loads and up to 120MHz with lower loads (10 pF). The -1H version has higher drive strength than the base -1 version, featuring faster rise and fall time. The XRK32309 has two banks each with four outputs. These outputs are controlled by two select input lines according to the Table 2, “Select Input Decoding,” on page 3. In cases where not all outputs are needed, bank B can be tri-stated. The select lines also enable putting the device in a bypass mode where the input is directly applied to the outputs. This feature is useful for chip and testing purposes. Some applications may require distributing the clock to several destinations. In such situations, multiple XRK32309 devices can be connected to accept the same input clock and generate several clock signals. The available versions of XRK32309 are shown in Table 12, “Ordering Information,” on page 10. The XRK32309-1 is the base part. FEATURES • 10-MHz to 120-MHz operating range, compatible with CPU and PCI bus frequencies • Zero input-output propagation delay • Multiple low-skew outputs ■ ■ ■ Output-output skew less than 250 ps Device-device skew less than 700 ps One input drives nine outputs, grouped as 4 + 4+1 • Less than 200 ps cycle-cycle jitter, compatible with Pentium®-based systems • Test Mode to bypass phase-locked loop (PLL) (see “Select Input Decoding” on page 2) • Available in space-saving 16-pin 150-mil SOIC or 4.4-mm TSSOP packages • 3.3V operation • Industrial and commercial temperature available FIGURE 1. BLOCK DIAGRAM OF THE XRK32309 PLL FB MUX QA0 REF QA1 QA2 QA3 S2 S1 Select Input Decoding QB0 QB1 QB2 QB3 Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com PRELIMINARY XRK32309 LOW-COST 3.3V ZERO DELAY BUFFER REV. P1.0.1 FIGURE 2. PIN OUT OF THE XRK32309 16 SOIC/TSSOP REF 1 16 FB QA0 2 15 QA3 QA1 3 14 QA2 VDD 4 13 VDD GND 5 12 GND QB0 6 11 QB3 QB1 7 10 QB2 S2 8 9 S1 TABLE 1: PIN DESCRIPTION FOR XRK32309 PIN SIGNAL D ESCRIPTION 1 REF[1] Input reference frequency. 2 QA0[2] Buffered clock output, Bank A 3 QA1[2] Buffered clock output, Bank A 4 VDD 3.3V supply 5 GND Ground 6 QB0[2] Buffered clock output, Bank B 7 QB1[2] Buffered clock output, Bank B 8 S2[3] Select input, bit 2 9 S1[3] Select input, bit 1 10 QB2[2] Buffered clock output, Bank B 11 QB3[2] Buffered clock output, Bank B 12 GND Ground 13 VDD 3.3V supply 14 QA2[2] Buffered clock output, Bank A 15 QA3[2] Buffered clock output, Bank A 16 FB[2] Buffered output, internal feedback on this pin 2 PRELIMINARY XRK32309 LOW-COST 3.3V ZERO DELAY BUFFER REV. P1.0.1 TABLE 2: SELECT INPUT D ECODING S2 S1 QA0-QA3 QB0-QB3 FB[4] OUTPUT SOURCE 0 0 Tri-Stated Tri-Stated Driven PLL 0 1 Driven Tri-Stated Driven PLL 1 0 Driven Driven Driven Reference 1 1 Driven Driven Driven PLL NOTES: 1. Weak pull-down. 2. Weak pull-down on all outputs. 3. Weak pull-ups on these inputs. 4. This output has an internal feedback for the PLL. The load on this output can be adjusted to change the skew between the reference and output. FIGURE 3. REF. INPUT TO QAX/QBX DELAY VS. LOADING D IFFERENCE BETWEEN FB AND QAX/QBX PINS 1500 REF Input to QAx/QBx Delay (ps) 1000 500 0 -30 -25 -20 -15 -10 -5 0 5 10 15 20 25 30 -500 -1000 -1500 Output Load Difference: FB Load - QAx/QBx Load (pF) Note: Target only, actual characterization curve may be slightly different. ZERO DELAY AND SKEW CONTROL In order to achieve Zero Delay between the input reference and the output, all outputs, including FB, must be equally loaded even when the FB output is not being used. Being internally connected as the PLL feedback, the FB output's capacitive loading relative to the other outputs can adjust the input to output delay according to the characteristic shown in Figure 3. This figure provides a tool for mapping the required delay to the capacitive load difference required between the FB and the Clock output of interest. For zero output to output skew, the outputs have to be loaded equally as well. 3 PRELIMINARY XRK32309 LOW-COST 3.3V ZERO DELAY BUFFER REV. P1.0.1 TABLE 3: ABSOLUTE MAXIMUM RATINGS PARAMETER RANGE Supply Voltage to Ground Potential -0.5V to +7.0V DC Input Voltage (Except REF) -0.5V to VDD +0.5V DC Input Voltage REF -0.5 to 7V Storage Temperature -65°C to +150°C Junction Temperature 150°C Static Discharge Voltage (per MIL-STD-883, Method 3015) >2000V TABLE 4: OPERATING CONDITIONS FOR XRK32309SC-XX C OMMERCIAL TEMPERATURE DEVICES PARAMETER MIN MAX UNIT 3.0 3.6 V Operating Temperature (Ambient Temperature) 0 70 °C Load Capacitance, below 100MHz - 30 pF Load Capacitance, from 100MHz to 120MHz - 10 pF CIN Input Capacitance - 7 pF tPU Power-up time for all VDD’s to reach minimum specified voltage (power ramps must be monotonic) 0.05 50 ms VDD TA DESCRIPTION Supply Voltage CL TABLE 5: ELECTRICAL CHARACTERISTICS FOR XRK32309SC-XX COMMERCIAL TEMPERATURE DEVICES PARAMETER DESCRIPTION TEST CONDITIONS MIN M AX UNIT VIL Input Low Voltage[5] - 0.8 V VIH Input High Voltage[5] 2.0 - V IIL Input Low Current VIN=0V - 50.0 µA IIH Input High Current VIN=VDD - 100.0 µA VOL Output Low Voltage[6] IOL= 8mA (-1) - 0.4 V 2.4 - V - 32.0 mA IOL= 12mA (-1H) VOH Output High Voltage[6] IOH= -8mA (-1) IOH= -12mA (-1H) IDD Supply Current Unloaded outputs at 66.67MHz, SEL inputs at VDD 4 PRELIMINARY XRK32309 LOW-COST 3.3V ZERO DELAY BUFFER REV. P1.0.1 TABLE 6: SWITCHING CHARACTERISTICS FOR XRK32309SC-1 COMMERCIAL TEMPERATURE D EVICES[7] PARAMETER t1 NAME TEST CONDITIONS MIN TYP MAX UNIT 10 10 - 100 120 MHz MHz 40.0 50.0 60.0 % Output Frequency 30-pF load 10-pF load Duty Cycle[6] = t2 ÷ t1 Measured at 1.4V, FOUT=66.67MHz t3 Rise Time[6] Measured between 0.8V and 2.0V - - 2.50 ns t4 Fall Time[6] Measured between 0.8V and 2.0V - - 2.50 ns t5 Output to Output Skew[6] All outputs equally loaded - - 250 ps t6A Delay, REF Rising Edge to Measured at VDD/2 FB Rising Edge[6] - 0 ±350 ps t6B Delay, REF Rising Edge to Measured at VDD/2. Measured in PLL Bypass Mode FB Rising Edge[6] 1 5 8.7 ns t7 Device to Device Skew[6] Measured at VDD/2 on the FB pins of devices - 0 700 ps tJ Cycle to Cycle Jitter[6] Measured at 66.67MHz, loaded outputs - - 200 ps PLL Lock Time[6] Stable power suppy, valid clock presented on REF pin - - 1.0 ms DC tLOCK NOTES: 5. REF input has a threshold voltage of V DD/2. 6. Parameter is guaranteed by design and characterization. Not 100% tested in production. 7. All parameters specified with loaded outputs. 5 PRELIMINARY XRK32309 LOW-COST 3.3V ZERO DELAY BUFFER REV. P1.0.1 TABLE 7: SWITCHING CHARACTERISTICS FOR XRK32309SC-1H COMMERCIAL TEMPERATURE D EVICES[7] PARAMETER t1 DC NAME Output Frequency Duty Cycle[6] = t2 ÷ t1 TEST CONDITIONS MIN TYP MAX UNIT 10 10 - 100 120 MHz MHz Measured at 1.4V, FOUT=66.67MHz 40.0 50.0 60.0 % Measured at 1.4V, FOUT<50.0MHz 45.0 50.0 55.0 % 30-pF load 10-pF load t3 Rise Time[6] Measured between 0.8V and 2.0V - - 1.50 ns t4 Fall Time[6] Measured between 0.8V and 2.0V - - 1.50 ns t5 Output to Output Skew[6] All outputs equally loaded - - 250 ps t6A Delay, REF Rising Edge to Measured at VDD/2 - 0 ±350 ps FB Rising Edge[6] t6B Delay, REF Rising Edge to Measured at VDD/2. Measured in PLL Bypass Mode FB Rising Edge[6] 1 5 8.7 ns t7 Device to Device Skew[6] Measured at VDD/2 on the FB pins of devices - 0 700 ps t8 Output Slew Rate[6] Measured between 0.8V and 2.0V using Test Circuit #2 1 - - V/ns tJ Cycle to Cycle Jitter[6] Measured at 66.67MHz, loaded outputs - - 200 ps PLL Lock Time[6] Stable power suppy, valid clock presented on REF pin - - 1.0 ms tLOCK 6 PRELIMINARY XRK32309 LOW-COST 3.3V ZERO DELAY BUFFER REV. P1.0.1 TABLE 8: OPERATING CONDITIONS FOR XRK32309SI-XX INDUSTRIAL TEMPERATURE DEVICES PARAMETER MIN MAX UNIT Supply Voltage 3.0 3.6 V Operating Temperature (Ambient Temperature) -40 85 °C Load Capacitance, below 100MHz - 30 pF Load Capacitance, from 100MHz to 120MHz - 10 pF CIN Input Capacitance - 7 pF tPU Power-up time for all VDD’s to reach minimum specified voltage (power ramps must be monotonic) 0.05 50 ms VDD TA DESCRIPTION CL TABLE 9: ELECTRICAL CHARACTERISTICS FOR XRK32309SI-XX INDUSTRIAL TEMPERATURE DEVICES PARAMETER DESCRIPTION TEST CONDITIONS MIN M AX UNIT VIL Input Low Voltage[5] - 0.8 V VIH Input High Voltage[5] 2.0 - V IIL Input Low Current VIN=0V - 50.0 µA IIH Input High Current VIN=VDD - 100.0 µA VOL Output Low Voltage[6] IOL= 8mA (-1) - 0.4 V 2.4 - V - 35.0 mA IOL= 12mA (-1H) VOH Output High Voltage[6] IOH= -8mA (-1) IOH= -12mA (-1H) IDD Supply Current Unloaded outputs at 66.67MHz REF, SEL inputs at VDD 7 PRELIMINARY XRK32309 LOW-COST 3.3V ZERO DELAY BUFFER REV. P1.0.1 TABLE 10: SWITCHING CHARACTERISTICS FOR XRK32309SI-1 INDUSTRIAL TEMPERATURE DEVICES[7] PARAMETER t1 NAME TEST CONDITIONS MIN TYP MAX UNIT 10 10 - 100 120 MHz MHz 40.0 50.0 60.0 % Output Frequency 30-pF load 10-pF load Duty Cycle[6] = t2 ÷ t1 Measured at 1.4V, FOUT=66.67MHz t3 Rise Time[6] Measured between 0.8V and 2.0V - - 2.50 ns t4 Fall Time[6] Measured between 0.8V and 2.0V - - 2.50 ns t5 Output to Output Skew[6] All outputs equally loaded - - 250 ps t6A Delay, REF Rising Edge to Measured at VDD/2 FB Rising Edge[6] - 0 ±350 ps t6B Delay, REF Rising Edge to Measured at VDD/2. Measured in PLL Bypass Mode FB Rising Edge[6] 1 5 8.7 ns t7 Device to Device Skew[6] Measured at VDD/2 on the FB pins of devices - 0 700 ps tJ Cycle to Cycle Jitter[6] Measured at 66.67MHz, loaded outputs - - 200 ps PLL Lock Time[6] Stable power suppy, valid clock presented on REF pin - - 1.0 ms DC tLOCK TABLE 11: SWITCHING CHARACTERISTICS FOR XRK32309SI-1H INDUSTRIAL TEMPERATURE DEVICES[7] PARAMETER t1 DC NAME Output Frequency Duty Cycle[6] = t2 ÷ t1 TEST CONDITIONS MIN TYP MAX UNIT 10 10 - 100 120 MHz MHz Measured at 1.4V, FOUT=66.67MHz 40.0 50.0 60.0 % Measured at 1.4V, FOUT<50.0MHz 45.0 50.0 55.0 % 30-pF load 10-pF load t3 Rise Time[6] Measured between 0.8V and 2.0V - - 1.50 ns t4 Fall Time[6] Measured between 0.8V and 2.0V - - 1.50 ns t5 Output to Output Skew[6] All outputs equally loaded - - 250 ps t6A Delay, REF Rising Edge to Measured at VDD/2 - 0 ±350 ps FB Rising Edge[6] t6B Delay, REF Rising Edge to Measured at VDD/2. Measured in PLL Bypass Mode FB Rising Edge[6] 1 5 8.7 ns t7 Device to Device Skew[6] Measured at VDD/2 on the FB pins of devices - 0 700 ps t8 Output Slew Rate[6] Measured between 0.8V and 2.0V using Test Circuit #2 1 - - v/ns 8 PRELIMINARY XRK32309 LOW-COST 3.3V ZERO DELAY BUFFER REV. P1.0.1 TABLE 11: SWITCHING CHARACTERISTICS FOR XRK32309SI-1H INDUSTRIAL TEMPERATURE DEVICES[7] PARAMETER tJ tLOCK NAME TEST CONDITIONS MIN TYP MAX UNIT Cycle to Cycle Jitter[6] Measured at 66.67MHz, loaded outputs - - 200 ps PLL Lock Time[6] Stable power suppy, valid clock presented on REF pin - - 1.0 ms FIGURE 4. SWITCHING WAVEFORMS All Outputs Rise/Fall Time Duty Cycle Timing t1 t2 1.4V OUTPUT 1.4V 1.4V 2.0V 0.8V t3 Output-Output Skew OUTPUT 0V t4 Input-Output Propagation Delay 1.4V INPUT 1.4V OUTPUT 3.3V 2.0V 0.8V VDD/2 VDD/2 OUTPUT t6 t5 Device-Device Skew FB, Device 1 VDD/2 VDD/2 FB, Device 2 t7 FIGURE 5. TEST CIRCUIT Test Circuit #2 Test Circuit #1 VDD VDD Outputs 0.1µF QAx/QBx 1KΩ Outputs 0.1µF 1KΩ CLOAD VDD 10pF VDD 0.1µF 0.1µF GND GND GND GND For parameters t 8 (output slew rate) on -1H devices. 9 PRELIMINARY XRK32309 LOW-COST 3.3V ZERO DELAY BUFFER REV. P1.0.1 TABLE 12: ORDERING INFORMATION PART ORDERING N UMBER PACKAGE TYPE OPERATING TEMPERATURE RANGE XRK32309CD-1 16 PIN SOIC 0° TO +70° XRK32309CDTR-1 16 PIN SOIC 0° TO +70° XRK32309ID-1 16 Pin SOIC -40° to +85° XRK32309IDTR-1 16 Pin SOIC -40° to +85° XRK32309CD-1H 16 Pin SOIC 0° TO +70° XRK32309CDTR-1H 16 Pin SOIC 0° TO +70° XRK32309ID-1H 16 Pin SOIC -40° to +85° XRK32309IDTR-1H 16 Pin SOIC -40° to +85° XRK32309CG-1H 16 Pin TSSOP 0° TO +70° XRK32309CGTR-1H 16 Pin TSSOP 0° TO +70° XRK32309IG-1H 16 Pin TSSOP -40° to +85° XRK32309IGTR-1H 16 Pin TSSOP -40° to +85° 10 PRELIMINARY XRK32309 LOW-COST 3.3V ZERO DELAY BUFFER REV. P1.0.1 PACKAGE DRAWINGS AND DIMENSIONS FIGURE 6. XRK32309 PACKAGE DRAWING - 16 LEAD SMALL OUTLINE 16 LEAD SMALL OUTLINE (150 MIL JEDEC SOIC) D 16 9 E 1 H 8 C A Seating Plane α e B A1 L Note: The control dimension is the millimeter column INCHES MILLIMETERS SYMBOL MIN MAX MIN MAX A 0.053 0.069 1.35 1.75 A1 0.004 0.010 0.10 0.25 B 0.013 0.020 0.33 0.51 C 0.007 0.010 0.19 0.25 D 0.386 0.394 9.80 10.00 E 0.150 0.157 3.80 4.00 e 0.050 BSC 1.27 BSC H 0.228 0.244 5.80 6.20 L 0.016 0.050 0.40 1.27 α 0° 8° 0° 8° 11 PRELIMINARY XRK32309 LOW-COST 3.3V ZERO DELAY BUFFER REV. P1.0.1 FIGURE 7. XRK32309 PACKAGE DRAWING - 16 LEAD THIN SHRINK SMALL OUTLINE 16 LEAD TSSOP THIN SHRINK SMALL OUTLINE (4.4mm TSSOP) SYMBOL A A1 A2 B C D E E1 e L α INCHES MIN MAX 0.031 0.043 0.002 0.006 0.031 0.037 0.007 0.012 0.004 0.008 0.193 0.201 0.248 0.260 0.169 0.177 0.0256 BSC 0.018 0.030 0° 8° 12 MILLIMETERS MIN MAX 0.80 1.10 0.05 0.15 0.80 0.95 0.19 0.30 0.09 0.20 4.90 5.10 6.30 6.60 4.30 4.50 0.65 BSC 0.45 0.75 0° 8° PRELIMINARY XRK32309 LOW-COST 3.3V ZERO DELAY BUFFER REV. P1.0.1 REVISIONS REV. # DATE DESCRIPTION OF CHANGES P1.0.0 04/05/06 Initial release. P1.0.1 05/12/06 Operating range changed to 10MHz to 120MHz - edit all references of this. NOTICE EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration purposes and may vary depending upon a user’s specific application. While the information in this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies. EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the circumstances. Copyright 2006 EXAR Corporation Datasheet May 2006. Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited. 13