EXAR XRK39653IQ-F

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XRK39653
PRELIMINARY
3.3V, 8-OUTPUT ZERO DELAY BUFFER
FEBRUARY 2006
REV. P1.0.0
XRK39653 GENERAL DESCRIPTION
The XRK39653 is a low voltage high performance PLL
based zero delay buffer/clock generator designed for high
speed clock distribution applications. It provides 9 low
skew, low jitter outputs ideal for networking, computing and
telecom applications.
The PLL based design allows the 9 outputs (8 clock outputs
and 1 feedback output) to be phase aligned to the input reference clock. The outputs source LVCMOS compatible levels and can drive 50Ω transmission lines. If series
termination is used, each output can drive up to 2 lines providing effectively a fanout of 1:16. The XRK39653’s reference input accepts a LVPECL clock source.
For normal operation (PLL used to source the outputs), the
feedback output (QFB) is connected to the feedback input
(FB_IN). The VCO range of operation is 200 to 500MHz.
This means that the input/output ranges are determined by
the divider setting. If ÷4 is used, the input/output range is 50
to 125MHz (high range), if ÷8 is used the input/output range
is 25 to 62.5MHz (low range).
For testing purposes two PLL bypass modes are provided.
The first simply replaces the PLL output with the reference
clock (PLL_EN=0, BYPASS=1). The dividers are still in
use. The second is a full bypass mode that has the PLL
and divider operation removed (BYPASS=0). In this mode
the reference clock directly sources the outputs drivers.
FEATURES
•
•
•
•
8 LVCMOS Clock Outputs
1 Feedback Output
LVPECL reference clock input
25-200 MHz input/output frequency range
■ Input/Output range (÷4): 50-125MHz
■ Input/Output range (÷8): 25-62.5MHz
• 150ps max output to output skew
• Two bypass test mode options
•
•
•
•
•
Fully Integrated PLL
3.3V Operation
Pin compatible with MPC9353
Industrial temp range: -40°C to +85°C
32-Lead TQFP Packaging
FIGURE 1. BLOCK DIAGRAM OF THE XRK39653
VDD
PECL
PECL
QFB
Ref
PLL
FB_IN
VDD
FB
Q0
0
0
Q1
0
1
÷4
÷2
1
1
PLL_EN
Q2
Q3
Q4
VCO_SEL
Q5
BYPASS
Q6
Q7
OE
Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com
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PRELIMINARY
XRK39653
3.3V, 8-OUTPUT ZERO DELAY BUFFER
REV. P1.0.0
PRODUCT ORDERING INFORMATION
PRODUCT NUMBER
PACKAGE TYPE
OPERATING TEMPERATURE RANGE
XRK39653IQ
32-Lead TQFP
-40°C to +85°C
XRK39653IQ-F
32-Lead TQFP "Lead Free"
-40°C to +85°C
VCO_SEL
BYPASS
PLL_EN
GND
QFB
VDD
Q0
GND
FIGURE 2. PIN OUT OF THE XRK39653
32
31
30
29
28
27
26
25
AVDD
1
24
Q1
FB_IN
2
23
VDD
NC
3
22
Q2
NC
4
21
GND
NC
5
20
Q3
NC
6
19
VDD
AGND
7
18
Q4
PECL
8
17
GND
2
OE
VDD
Q7
13
14
15
16
Q5
12
VDD
11
Q6
10
GND
9
PECL
XRK39653
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PRELIMINARY
REV. P1.0.0
XRK39653
3.3V, 8-OUTPUT ZERO DELAY BUFFER
PIN DESCRIPTIONS
NUMBER
NAME
TYPE
DESCRIPTION
1
AVDD
Power
2
FB_IN
Input
3, 4, 5, 6
NC
7
AGND
Power
PLL ground
8
PECL
Input
LVPECL - pos differential reference clock
9
PECL
Input
LVPECL - neg differential reference clock
10
OE
Input
11,15, 19,
23, 27,
VDD
Power
Power supply
12, 14, 16,
18, 20, 22,
24, 26
Q[7:0]
Output
Clock outputs
13, 17, 21,
25, 29
GND
Power
Ground
28
QFB
Output
Feedback output for PLL
30
PLL_EN
Input
pull-up
PLL enable/disable select
31
BYPASS
Input
pull-up
PLL and output divider bypass select
32
VCO_SEL
Input
pull-up
VCO divider select
Power supply for PLL
pull-up
pull-down
External PLL feedback clock input
Output enable/disable and device reset
TABLE 1: CONTROL INPUT FUNCTION TABLE
Pin Name
0
1
Default
VCO_SEL
System Divide = 4 of VCO output
System Divide = 8 of VCO output
1
PLL_EN
PLL is bypassed and disabled. The PECL
clock reference source drives the outputs
through the divider blocks
PLL enabled. Normal operation. VCO output drives the outputs through the divider
blocks
1
BYPASS
Complete bypass of the PLL and divider
blocks. PECL reference clocks the outputs.
Normal operation. Dividers selected.
1
OE
Outputs enabled
Outputs tri-stated and device reset. VCO
running at minimum frequency
0
3
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PRELIMINARY
XRK39653
3.3V, 8-OUTPUT ZERO DELAY BUFFER
REV. P1.0.0
DC C HARACTERISTICS (VCC= 3.3 + 5%, TA= -40°C TO +85°C)
SYMBOL
CHARACTERISTICS
M IN
TYP
MAX
UNIT
CONDITION
PECL Clock inputs common mode range
1.0
VDD-0.6
V
LVPECL
VPP
PECL Clock peak-to-peak input voltage
300
1000
mV
LVPECL
VIH
Input voltage high
2.0
VDD+0.3
V
LVCMOS
VIL
Input voltage low
0.8
V
LVCMOS
VOH
Output High Voltagea
V
IOH=-24mA
VOL
Output Low Voltagea
V
V
IOL=24mA
VCMRa
ZOUT
IIN
ICC_PLL
2.4
0.55
0.30
Output Impedance
Ω
14-17
Input leakage current
Maximum PLL supply current
5.0
ICCQ
Maximum Quiescent supply current
VTT
Output Termination Voltage
IOL=12mA
+200
μΑ
VIN =V DD or VIN =GND
10.0
mA
AVDD pin
10.0
mA
All VDD pins, OE=1
VCC÷2
V
a. VCMR is the cross point of the differential input signal.
.
AC C HARACTERISTICS (VCC= 3.3 + 5%, TA= -40°C TO +85°C) a
SYMBOL
fVCO
fref
PARAMETER
MIN
VCO Frequency
TYP
MAX
UNIT
200
500
MHz
CONDITION
Input Reference Frequency
÷4 feedback
÷8 feedback
PLL Bypass
50
25
0
125
62.5
200
MHz
PLL locked
PLL locked
bypass mode
fMAX
Max Output Frequency
÷4 feedback
÷8 feedback
50
25
125
62.5
MHz
PLL locked
PLL locked
VPP
PECL Clock peak-to-peak input voltage
450
1000
mV
LVPECL
VCMR
PECL input Common Mode range
1.2
VDD-0.75
V
LVPECL
tPW Min
Input Reference Clock Minimum Pulse Width
tSPO
Propagation Delay - Static Phase Offset (PECL
to FB_IN)
tPD
Propagation Delay - PLL Bypassed
Bypass mode 1 (BYPASS = 0)
Bypass mode 2, (BYPASS = 1, PLL_EN = 0)
2
ns
-75
125
ps
1.2
3.0
3.3
7.0
ns
ns
tskew(O)
Output-to-Output Skew
150
ps
tskew(PP)
Part to Part Skew (bypass PLL & divider)
1.5
ns
tJIT(CC)
Cycle-to-Cycle Jitter
100
ps
4
PLL locked
BYPASS=0
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PRELIMINARY
REV. P1.0.0
XRK39653
3.3V, 8-OUTPUT ZERO DELAY BUFFER
AC C HARACTERISTICS (VCC= 3.3 + 5%, TA= -40°C TO +85°C) a
SYMBOL
PARAMETER
MIN
TYP
MAX
UNIT
tJIT(PER)
Period Jitter
100
ps
tJIT(I/O)
I/O Phase Jitter (RMS)
25
ps
0.8 - 4
0.5 - 1.3
MHz
MHz
55
%
10.0
ms
1000
ps
BW
PLL bandwidth
DC
Output duty cycle
÷4 feedback
÷8 feedback
45
50
tLOCK
Maximum PLL Lock Time
tor/tof
Output Rise/Fall time
tPLZ,HZ
Output Disable Time
7
ns
tPHZ,LZ
Output Enable Time
6
ns
100
CONDITION
PLL locked
0.55 to 2.4V
a. AC characteristics apply for parallel output termination of 50Ω to VTT.
MAXIMUM RATINGSa
SYMBOL
CHARACTERISTICS
MIN
M AX
UNIT
VDD
Supply Voltage
-0.3
3.9
V
VIN
DC Input Voltage
-0.3
VDD+0.3
V
DC Output Voltage
-0.3
VDD+0.3
V
DC Input Current
+20
mA
DC Output Current
+50
mA
125
°C
VOUT
IIN
IOUT
TS
Storage Temperature
-65
CONDITION
a. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur.
Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability.
GENERAL SPECIFICATIONS
SYMBOL
CHARACTERISTICS
MIN
TYP
VCC÷2
MAX
UNIT
VTT
Output termination voltage
MM
ESD Protection (Machine model)
200
V
HBM
ESD Protection (Human body model)
2000
V
LU
Latch-up immunity
200
mA
CIN
Input Capacitance
4.0
5
CONDITION
V
pF
Inputs
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PRELIMINARY
XRK39653
3.3V, 8-OUTPUT ZERO DELAY BUFFER
REV. P1.0.0
PACKAGE DIMENSIONS
32 LEAD THIN QUAD FLAT PACK
(7 x 7 x 1.4 mm TQFP)
rev. 2.00
D
D1
24
17
16
25
D1
32
D
9
1
8
B
e
A2
C
A
α
Seating Plane
A1
L
Note: The control dimension is the millimeter column
INCHES
MILLIMETERS
SYMBOL
MIN
MAX
MIN
MAX
A
0.055
0.063
1.40
1.60
A1
0.002
0.006
0.05
0.15
A2
0.053
0.057
1.35
1.45
B
0.012
0.018
0.30
0.45
C
0.004
0.008
0.09
0.20
D
0.346
0.362
8.80
9.20
D1
0.272
0.280
6.90
7.10
e
0.0315 BSC
0.80 BSC
L
0.018
0.030
0.45
0.75
α
0°
7°
0°
7°
6
xr
PRELIMINARY
REV. P1.0.0
XRK39653
3.3V, 8-OUTPUT ZERO DELAY BUFFER
REVISION HISTORY
REVISION #
P1.0.0
DATE
DESCRIPTION
February 2006 Initial release.
NOTICE
EXAR Corporation reserves the right to make changes to the products contained in this publication in order to
improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any
circuits described herein, conveys no license under any patent or other right, and makes no representation that
the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration
purposes and may vary depending upon a user’s specific application. While the information in this publication
has been carefully checked; no responsibility, however, is assumed for inaccuracies.
EXAR Corporation does not recommend the use of any of its products in life support applications where the
failure or malfunction of the product can reasonably be expected to cause failure of the life support system or
to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless
EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has
been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately
protected under the circumstances.
Copyright 2006 EXAR Corporation
Datasheet February 2006.
Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.
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