XRT83SL28 xr 8-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT APRIL 2005 REV. 1.0.0 GENERAL DESCRIPTION The XRT83SL28 is a fully integrated 8-channel E1 short-haul LIU which optimizes system cost and performance by offering key design features. The XRT83SL28 operates from a single 3.3V power supply. The LIU features are programmed through a standard serial microprocessor interface or hardware control. EXAR’s LIU has patented high impedance circuits that allow the transmitter outputs and receiver inputs to be high impedance when experiencing a power failure or when the LIU is powered off. Key design features within the LIU optimize 1:1 or 1+1 redundancy and non-intrusive monitoring applications to ensure reliability without using relays. Additional features include TAOS for transmit and receive, RLOS, LCV, AIS, DMO, and diagnostic loopback modes. APPLICATIONS • • • • • • • • ISDN Primary Rate Interface CSU/DSU E1 Interface E1 LAN/WAN Routers Public Switching Systems and PBX Interfaces E1 Multiplexer and Channel Banks Integrated Multi-Service Access Platforms (IMAPs) Integrated Access Devices (IADs) Inverse Multiplexing for ATM (IMA) Wireless Base Stations FIGURE 1. HOST MODE BLOCK DIAGRAM OF THE XRT83SL28 1 of 8 Channels Driver Monitor TCLK TPOS TNEG HDB3 Encoder Timing Control Remote Loopback RCLK RPOS RNEG/LCV Jitter Attenuator (Rx or Tx) HDB3 Decoder TTIP Line Driver TRING Analog Loopback Digital Loopback Clock & Data Recovery RLOS Peak Detector & Slicer Rx Equalizer RTIP RRING AIS & LOS Detector Test Clock Distribution Reset HW/Host SDI SDO CS SCLK INT Serial Microprocessor Interface TxOE MCLK ICT Tx Pulse Shaper DMO Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com xr XRT83SL28 8-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT REV. 1.0.0 FIGURE 2. HARDWARE MODE BLOCK DIAGRAM OF THE XRT83SL28 1 of 8 Channels Driver Monitor TCLK TPOS TNEG/CODE HDB3 Encoder Remote Loopback RCLK RPOS RNEG/LCV Timing Control Jitter Attenuator (Rx or Tx) HDB3 Decoder TTIP Line Driver TRING Analog Loopback Digital Loopback Clock & Data Recovery RLOS Peak Detector & Slicer Rx Equalizer RTIP RRING AIS & LOS Detector Test Clock Distribution MCLK Reset HW/Host LBM[1:0] JASEL[1:0] FIFOS CHLB[3:0] Hardware Configuration SR/DR TERSEL[1:0] TCLKinv RCLKinv ICT Tx Pulse Shaper DMO 2 TxOE xr REV. 1.0.0 XRT83SL28 8-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT FEATURES • Fully integrated 8-Channel short haul transceivers for E1 (2.048MHz) applications. • Internal Impedance matching on both receive and transmit for 75Ω (E1) or 120Ω (E1) applications. • Tri-State on a per channel basis for the transmit selection. • On-Chip transmit short-circuit protection and limiting protects line drivers from damage on a per channel basis. • Independent Crystal-Less digital jitter attenuators (JA) with 32-Bit or 64-Bit FIFO for the receive or transmit paths • Driver failure monitor output (DMO) alerts of possible system or external component problems. • Transmit outputs and receive inputs may be "High" impedance for protection or redundancy applications on a per channel basis. • Support for automatic protection switching. • 1:1 and 1+1 protection without relays. • RLOS/AIS according to ITU-T G.775 or ETSI-300-233. • On-Chip HDB3 encoder/decoder for each channel. • On-Chip digital clock recovery circuit for high input jitter tolerance. • Line code error and bipolar violation detection. • Transmit all ones (TAOS) for the Transmit and Receive Outputs. • Supports local analog, remote, and digital loopback modes. • Supports gapped clocks for mapper/multiplexer applications. • Low Power dissipation • Single 3.3V supply operation (3V to 5V I/O tolerant). • 144-Pin TQFP package • -40°C to +85°C Temperature Range PRODUCT ORDERING INFORMATION PRODUCT NUMBER PACKAGE TYPE OPERATING TEMPERATURE RANGE XRT83SL28IV 144 Lead TQFP -40°C to +85°C 3 xr XRT83SL28 8-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT REV. 1.0.0 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 DMO4 TCLKinv RTIP4 RRING4 TGND4 TTIP4 TVDD4 TRING4 INT TRING5 TVDD5 TTIP5 TGND5 RRING5 RTIP5 DVDDcore SDI/CHLB0 SDO/CHLB1 SCLK/CHLB2 CS/CHLB3 DGNDcore RTIP6 RRING6 TGND6 TTIP6 TVDD6 TRING6 HW/Host TRING7 TVDD7 TTIP7 TGND7 RRING7 RTIP7 RCLKinv DMO7 FIGURE 3. PIN OUT OF THE XRT83SL28 XRT83SL28 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 DMO0 SR/DR RTIP0 RRING0 TGND0 TTIP0 TVDD0 TRING0 TxOE TRING1 TVDD1 TTIP1 TGND1 RRING1 RTIP1 AVDD MCLK AGND FIFOS JASEL1 JASEL0 RTIP2 RRING2 TGND2 TTIP2 TVDD2 TRING2 RESET TRING3 TVDD3 TTIP3 TGND3 RRING3 RTIP3 ICT DMO3 DMO5 TNEG4/CODE4 TPOS4/TDATA4 TCLK4 TNEG5/CODE5 TPOS5/TDATA5 TCLK5 RLOS5 RNEG5/LCV5 RPOS5/RDATA5 RCLK5 RLOS4 RNEG4/LCV4 RPOS4/RDATA4 RCLK4 TERSEL0 TERSEL1 RGND2 RVDD2 DGND2 DVDD2 RCLK0 RPOS0/RDATA0 RNEG0/LCV0 RLOS0 RCLK1 RPOS1/RDATA1 RNEG1/LCV1 RLOS1 TCLK1 TPOS1/TDATA1 TNEG1/CODE1 TCLK0 TPOS0/TDATA0 TNEG0/CODE0 DMO1 4 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 DMO6 TNEG7/CODE7 TPOS7/TDATA7 TCLK7 TNEG6/CODE6 TPOS6/TDATA6 TCLK6 RLOS6 RNEG6/LCV6 RPOS6/RDATA6 RCLK6 RLOS7 RNEG7/LCV7 RPOS7/RDATA7 RCLK7 LBM0 LBM1 RGND1 RVDD1 DGND1 DVDD1 RCLK3 RPOS3/RDATA3 RNEG3/LCV3 RLOS3 RCLK2 RPOS2/RDATA2 RNEG2/LCV2 RLOS2 TCLK2 TPOS2/TDATA2 TNEG2/CODE2 TCLK3 TPOS3/TDATA3 TNEG3/CODE3 DMO2 xr REV. 1.0.0 XRT83SL28 8-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT TABLE OF CONTENTS GENERAL DESCRIPTION................................................................................................. 1 APPLICATIONS........................................................................................................................................... 1 FIGURE 1. HOST MODE BLOCK DIAGRAM OF THE XRT83SL28 ......................................................................................................... 1 FIGURE 2. HARDWARE MODE BLOCK DIAGRAM OF THE XRT83SL28 ................................................................................................ 2 FEATURES ..................................................................................................................................................... 3 PRODUCT ORDERING INFORMATION.................................................................................................. 3 FIGURE 3. PIN OUT OF THE XRT83SL28 ......................................................................................................................................... 4 TABLE OF CONTENTS ............................................................................................................ I PIN DESCRIPTIONS .......................................................................................................... 5 SERIAL MICROPROCESSOR INTERFACE ............................................................................................................ 5 RECEIVER SECTION ....................................................................................................................................... 6 TRANSMITTER SECTION.................................................................................................................................. 7 CONTROL FUNCTION ...................................................................................................................................... 8 POWER AND GROUND (HOST AND HARDWARE MODES).................................................................................... 9 HARDWARE MODE INTERFACE ....................................................................................................................... 10 1.0 RECEIVE PATH LINE INTERFACE .................................................................................................... 14 FIGURE 4. SIMPLIFIED BLOCK DIAGRAM OF THE RECEIVE PATH LINE TERMINATION (RTIP/RRING)................................................. 14 1.1 INTERNAL TERMINATION ............................................................................................................................ 14 TABLE 1: SELECTING THE INTERNAL IMPEDANCE ............................................................................................................................. 14 FIGURE 5. TYPICAL CONNECTION DIAGRAM USING INTERNAL TERMINATION .................................................................................... 14 1.2 PEAK DETECTOR/DATA SLICER ................................................................................................................. 15 1.3 CLOCK AND DATA RECOVERY ................................................................................................................... 15 FIGURE 6. RECEIVE DATA UPDATED ON THE RISING EDGE OF RCLK .............................................................................................. 15 FIGURE 7. RECEIVE DATA UPDATED ON THE FALLING EDGE OF RCLK ............................................................................................ 15 TABLE 2: TIMING SPECIFICATIONS FOR RCLK/RPOS/RNEG .......................................................................................................... 15 1.4 RECEIVE SENSITIVITY .................................................................................................................................. 16 FIGURE 8. TEST CONFIGURATION FOR MEASURING RECEIVE SENSITIVITY ........................................................................................ 16 1.5 GENERAL ALARM DETECTION AND INTERRUPT GENERATION ............................................................ 16 1.5.1 RLOS (RECEIVER LOSS OF SIGNAL)...................................................................................................................... 17 1.5.2 AIS (ALARM INDICATION SIGNAL) .......................................................................................................................... 17 1.5.3 LCV (LINE CODE VIOLATION DETECTION) ............................................................................................................ 17 1.6 RECEIVE JITTER ATTENUATOR .................................................................................................................. 17 1.7 HDB3 DECODER ............................................................................................................................................ 18 1.8 ARAOS (AUTOMATIC RECEIVE ALL ONES) ............................................................................................... 18 FIGURE 9. SIMPLIFIED BLOCK DIAGRAM OF THE ARAOS FUNCTION ................................................................................................ 18 1.9 RPOS/RNEG/RCLK ........................................................................................................................................ 18 FIGURE 10. SINGLE RAIL MODE WITH A FIXED REPEATING "0011" PATTERN ................................................................................... 18 FIGURE 11. DUAL RAIL MODE WITH A FIXED REPEATING "0011" PATTERN ...................................................................................... 19 2.0 TRANSMIT PATH LINE INTERFACE ................................................................................................. 20 FIGURE 12. SIMPLIFIED BLOCK DIAGRAM OF THE TRANSMIT PATH ................................................................................................... 20 2.1 TCLK/TPOS/TNEG DIGITAL INPUTS ............................................................................................................ 20 FIGURE 13. TRANSMIT DATA SAMPLED ON FALLING EDGE OF TCLK ............................................................................................... 20 FIGURE 14. TRANSMIT DATA SAMPLED ON RISING EDGE OF TCLK ................................................................................................. 20 TABLE 3: TIMING SPECIFICATIONS FOR TCLK/TPOS/TNEG ........................................................................................................... 21 2.2 HDB3 ENCODER ............................................................................................................................................ 21 TABLE 4: EXAMPLES OF HDB3 ENCODING ...................................................................................................................................... 21 2.3 TRANSMIT JITTER ATTENUATOR ............................................................................................................... 21 TABLE 5: MAXIMUM GAP WIDTH FOR MULTIPLEXER/MAPPER APPLICATIONS .................................................................................... 21 2.4 TAOS (TRANSMIT ALL ONES) ..................................................................................................................... 22 FIGURE 15. TAOS (TRANSMIT ALL ONES)ATAOS (AUTOMATIC TRANSMIT ALL ONES) .................................................................... 22 2.5 ATAOS (AUTOMATIC TRANSMIT ALL ONES) ............................................................................................ 22 FIGURE 16. SIMPLIFIED BLOCK DIAGRAM OF THE ATAOS FUNCTION............................................................................................... 22 2.6 TRANSMITTER POWER DOWN IN HARDWARE MODE ............................................................................. 22 2.7 DMO (DRIVER MONITOR OUTPUT) ............................................................................................................. 22 2.8 LINE TERMINATION (TTIP/TRING) ............................................................................................................... 23 FIGURE 17. TYPICAL CONNECTION DIAGRAM USING INTERNAL TERMINATION ................................................................................... 23 3.0 E1 APPLICATIONS ............................................................................................................................. 24 3.1 LOOPBACK DIAGNOSTICS .......................................................................................................................... 24 I XRT83SL28 8-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT xr REV. 1.0.0 3.1.1 LOCAL ANALOG LOOPBACK .................................................................................................................................. 24 FIGURE 18. SIMPLIFIED BLOCK DIAGRAM OF LOCAL ANALOG LOOPBACK ......................................................................................... 24 3.1.2 REMOTE LOOPBACK ................................................................................................................................................ 24 FIGURE 19. SIMPLIFIED BLOCK DIAGRAM OF REMOTE LOOPBACK .................................................................................................... 24 3.1.3 DIGITAL LOOPBACK ................................................................................................................................................. 25 FIGURE 20. SIMPLIFIED BLOCK DIAGRAM OF DIGITAL LOOPBACK ..................................................................................................... 25 3.2 LINE CARD REDUNDANCY ........................................................................................................................... 26 3.2.1 1:1 AND 1+1 REDUNDANCY WITHOUT RELAYS .................................................................................................... 26 3.2.2 TRANSMIT INTERFACE WITH 1:1 AND 1+1 REDUNDANCY .................................................................................. 26 FIGURE 21. SIMPLIFIED BLOCK DIAGRAM OF THE TRANSMIT INTERFACE FOR 1:1 AND 1+1 REDUNDANCY ......................................... 26 3.2.3 RECEIVE INTERFACE WITH 1:1 AND 1+1 REDUNDANCY..................................................................................... 27 FIGURE 22. SIMPLIFIED BLOCK DIAGRAM OF THE RECEIVE INTERFACE FOR 1:1 AND 1+1 REDUNDANCY ........................................... 27 3.2.4 N+1 REDUNDANCY USING EXTERNAL RELAYS ................................................................................................... 27 3.2.5 TRANSMIT INTERFACE WITH N+1 REDUNDANCY ................................................................................................ 28 FIGURE 23. SIMPLIFIED BLOCK DIAGRAM OF THE TRANSMIT INTERFACE FOR N+1 REDUNDANCY ...................................................... 28 3.2.6 RECEIVE INTERFACE WITH N+1 REDUNDANCY ................................................................................................... 29 FIGURE 24. SIMPLIFIED BLOCK DIAGRAM OF THE RECEIVE INTERFACE FOR N+1 REDUNDANCY ........................................................ 29 3.3 POWER FAILURE PROTECTION .................................................................................................................. 30 3.4 OVERVOLTAGE AND OVERCURRENT PROTECTION ............................................................................... 30 3.5 NON-INTRUSIVE MONITORING .................................................................................................................... 30 FIGURE 25. SIMPLIFIED BLOCK DIAGRAM OF A NON-INTRUSIVE MONITORING APPLICATION............................................................... 30 4.0 SERIAL MICROPROCESSOR INTERFACE BLOCK ..........................................................................31 FIGURE 26. SIMPLIFIED BLOCK DIAGRAM OF THE SERIAL MICROPROCESSOR INTERFACE ................................................................. 31 4.1 SERIAL TIMING INFORMATION .................................................................................................................... 31 FIGURE 27. TIMING DIAGRAM FOR THE SERIAL MICROPROCESSOR INTERFACE ................................................................................ 31 4.2 16-BIT SERIAL DATA INPUT DESCRIPTION ............................................................................................... 32 4.2.1 4.2.2 4.2.3 4.2.4 R/W (SCLK1)............................................................................................................................................................... A[5:0] (SCLK2 - SCLK7)............................................................................................................................................. X (DUMMY BIT SCLK8) .............................................................................................................................................. D[7:0] (SCLK9 - SCLK16)........................................................................................................................................... 32 32 32 32 4.3 8-BIT SERIAL DATA OUTPUT DESCRIPTION ............................................................................................. 32 TABLE 6: MICROPROCESSOR REGISTER DESCRIPTION .................................................................................................................... 33 TABLE 7: MICROPROCESSOR REGISTER 0X00H BIT DESCRIPTION ................................................................................................... 35 TABLE 8: MICROPROCESSOR REGISTER 0X01H BIT DESCRIPTION ................................................................................................... 36 TABLE 9: MICROPROCESSOR REGISTER 0X02H BIT DESCRIPTION ................................................................................................... 36 TABLE 10: MICROPROCESSOR REGISTER BIT DESCRIPTION ............................................................................................................ 36 TABLE 11: MICROPROCESSOR REGISTER BIT DESCRIPTION ............................................................................................................ 38 TABLE 12: MICROPROCESSOR REGISTER BIT DESCRIPTION ............................................................................................................ 38 TABLE 13: MICROPROCESSOR REGISTER BIT DESCRIPTION ............................................................................................................ 39 ELECTRICAL CHARACTERISTICS ................................................................................41 TABLE 14: TABLE 15: TABLE 16: TABLE 17: TABLE 18: TABLE 19: ABSOLUTE MAXIMUM RATINGS ....................................................................................................................................... 41 DC DIGITAL INPUT AND OUTPUT ELECTRICAL CHARACTERISTICS .................................................................................... 41 AC ELECTRICAL CHARACTERISTICS ............................................................................................................................... 41 POWER CONSUMPTION .................................................................................................................................................. 41 RECEIVER ELECTRICAL CHARACTERISTICS ..................................................................................................................... 42 E1 TRANSMITTER ELECTRICAL CHARACTERISTICS .......................................................................................................... 43 ORDERING INFORMATION.............................................................................................44 PACKAGE DIMENSIONS.................................................................................................44 REVISION HISTORY.......................................................................................................................................45 II xr XRT83SL28 8-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT REV. 1.0.0 PIN DESCRIPTIONS HOST MODE INTERFACE SERIAL MICROPROCESSOR INTERFACE NAME PIN TYPE DESCRIPTION CS 89 I Chip Select Input Active low signal. This signal enables the serial microprocessor interface by pulling chip select "Low". The serial interface is disabled when the chip select signal returns "High". SCLK 90 I Serial Clock Input The serial clock input samples SDI on the rising edge and updates SDO on the falling edge. See the Serial Microprocessor section of this datasheet for more details. SDI 92 I Serial Data Input The serial data input pin is used to supply an address and data string to program the internal registers within the device. See the Serial Microprocessor section of this datasheet for more details. SDO 91 O Serial Data Output The serial data output pin is used to retrieve the internal contents of a selected register in readback mode. See the Microprocessor section of this datasheet for more details. Reset 28 I Hardware Reset Input Active low signal. When this pin is pulled "Low" for more than 10µS, all internal registers and state machines are set to their default state. NOTE: This pin must be pulled "High" to VDD for normal operation. INT 100 O Interrupt Output Active low signal. This signal is asserted "Low" when a change in alarm status occurs. Once the status registers have been read, the interrupt pin will return "High". GIE (Global Interrupt Enable) must be set "High" in the appropriate global register to enable interrupt generation. NOTE: This pin is an open-drain output that requires an external 10KΩ pull-up resistor. HW/Host 81 I Hardware / Host Mode Select Input This pin is used to select the mode of operation. By default, the LIU is configured for Host mode. To select Hardware mode, this pin must be pulled "High". NOTE: Internally pulled "Low" with a 50kΩ resistor. 5 xr XRT83SL28 8-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT REV. 1.0.0 RECEIVER SECTION NAME PIN TYPE DESCRIPTION RLOS7 RLOS6 RLOS5 RLOS4 RLOS3 RLOS2 RLOS1 RLOS0 61 65 116 120 48 44 137 133 O Receive Loss of Signal When a receive loss of signal occurs, the RLOS pin will go "High" for a minimum of one RCLK cycle. RLOS will remain "High" until the loss of signal condition clears. See the Receive Loss of Signal section of this datasheet for more details. RCLK7 RCLK6 RCLK5 RCLK4 RCLK3 RCLK2 RCLK1 RCLK0 58 62 119 123 51 47 134 130 O Receive Clock Output RCLK is the recovered clock from the incoming data stream. If the incoming signal is absent, RCLK maintains its timing by using an internal master clock as its reference. RPOS/RNEG data can be updated on either edge of RCLK selected by RCLKinv in the appropriate global register. RPOS7 RPOS6 RPOS5 RPOS4 RPOS3 RPOS2 RPOS1 RPOS0 59 63 118 122 50 46 135 131 O RPOS/RDATA Output Receive digital output pin. In dual rail mode, this pin is the receive positive data output. In single rail mode, this pin is the receive non-return to zero (NRZ) data output. RNEG/LCV7 RNEG/LCV6 RNEG/LCV5 RNEG/LCV4 RNEG/LCV3 RNEG/LCV2 RNEG/LCV1 RNEG/LCV0 60 64 117 121 49 45 136 132 O RNEG/LCV Output In dual rail mode, this pin is the receive negative data output. In single rail mode, this pin is a Line Code Violation indicator. If a line code violation or a bipolar violation occur, the LCV pin will pull "High" for a minimum of one RCLK cycle. LCV will remain "High" until there are no more violations. NOTE: RCLKinv is a global setting that applies to all 8 channels. 6 xr XRT83SL28 8-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT REV. 1.0.0 RECEIVER SECTION NAME PIN TYPE DESCRIPTION RTIP7 RTIP6 RTIP5 RTIP4 RTIP3 RTIP2 RTIP1 RTIP0 75 87 94 106 34 22 15 3 I Receive Differential Tip Input RTIP is the positive differential input from the line interface. Along with the RRING signal, these pins should be coupled to a 1:1 transformer for proper operation. RRING7 RRING6 RRING5 RRING4 RRING3 RRING2 RRING1 RRING0 76 86 95 105 33 23 14 4 I Receive Differential Ring Input RRING is the negative differential input from the line interface. Along with the RTIP signal, these pins should be coupled to a 1:1 transformer for proper operation. TRANSMITTER SECTION NAME PIN TYPE DESCRIPTION TxOE 9 I Transmit Output Enable Upon power up, the transmitters are tri-stated. Enabling the transmitters is selected through the serial microprocessor interface by programming the appropriate channel register if this pin is pulled "High". If the TxOE pin is pulled "Low", all 8 transmitters are tri-stated. NOTE: TxOE is ideal for redundancy applications. See the Redundancy Applications Section of this datasheet for more details. Internally pulled "Low" with a 50KΩ resistor. DMO7 DMO6 DMO5 DMO4 DMO3 DMO2 DMO1 DMO0 73 72 109 108 36 37 144 1 O Driver Monitor Output When no transmit output pulse is detected for more than 128 TCLK cycles, the DMO pin will go "High" for a minimum of one TCLK cycle. DMO will remain "High" until the transmitter sends a valid pulse. TCLK7 TCLK6 TCLK5 TCLK4 TCLK3 TCLK2 TCLK1 TCLK0 69 66 115 112 40 43 138 141 I Transmit Clock Input TCLK is the input facility clock used to sample the incoming TPOS/TNEG data. TPOS/TNEG data can be sampled on either edge of TCLK selected by TCLKinv in the appropriate global register. NOTE: TCLKinv is a global setting that applies to all 8 channels. 7 xr XRT83SL28 8-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT REV. 1.0.0 TRANSMITTER SECTION NAME PIN TYPE DESCRIPTION TPOS7 TPOS6 TPOS5 TPOS4 TPOS3 TPOS2 TPOS1 TPOS0 70 67 114 111 39 42 139 142 I TPOS/TDATA Input Transmit digital input pin. In dual rail mode, this pin is the transmit positive data input. In single rail mode, this pin is the transmit non-return to zero (NRZ) data input. TNEG7 TNEG6 TNEG5 TNEG4 TNEG3 TNEG2 TNEG1 TNEG0 71 68 113 110 38 41 140 143 I Transmit Negative Data Input In dual rail mode, this pin is the transmit negative data input. In single rail mode, this pin can be tied to ground. TTIP7 TTIP6 TTIP5 TTIP4 TTIP3 TTIP2 TTIP1 TTIP0 78 84 97 103 31 25 12 6 O Transmit Differential Tip Output TTIP is the positive differential output to the line interface. Along with the TRING signal, these pins should be coupled to a 1:2 step up transformer for proper operation. TRING7 TRING6 TRING5 TRING4 TRING3 TRING2 TRING1 TRING0 80 82 99 101 29 27 10 8 O Transmit Differential Ring Output TRING is the negative differential output to the line interface. Along with the TTIP signal, these pins should be coupled to a 1:2 step up transformer for proper operation. CONTROL FUNCTION NAME PIN TYPE DESCRIPTION ICT 35 I In Circuit Testing When this pin is tied "Low", all output pins are forced to "High" impedance for in circuit testing. NOTE: Internally pulled "High" with a 50KΩ resistor. MCLK 17 I Master Clock Input This pin is used as the internal reference to the LIU. This clock must be 2.048MHz +/-50ppm. 8 xr XRT83SL28 8-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT REV. 1.0.0 POWER AND GROUND (HOST AND HARDWARE MODES) NAME PIN TYPE DESCRIPTION TVDD7 TVDD6 TVDD5 TVDD4 TVDD3 TVDD2 TVDD1 TVDD0 79 83 98 102 30 26 11 7 PWR Transmit Analog Power Supply (3.3V ±5%) TVDD can be shared with DVDD. However, it is recommended that TVDD be isolated from the analog power supply RVDD. For best results, use an internal power plane for isolation. If an internal power plane is not available, a ferrite bead can be used. Each power supply pin should be bypassed to ground through an external 0.1µF capacitor. RVDD2 RVDD1 127 54 PWR Receive Analog Power Supply (3.3V ±5%) RVDD should not be shared with other power supplies. It is recommended that RVDD be isolated from the digital power supply DVDD and the analog power supply TVDD. For best results, use an internal power plane for isolation. If an internal power plane is not available, a ferrite bead can be used. Each power supply pin should be bypassed to ground through an external 0.1µF capacitor. DVDD2 DVDD1 DVDDcore 129 52 93 PWR Digital Power Supply (3.3V ±5%) DVDD should be isolated from the analog power supplies except for TVDD. For best results, use an internal power plane for isolation. If an internal power plane is not available, a ferrite bead can be used. Every two DVDD power supply pins should be bypassed to ground through at least one 0.1µF capacitor. AVDD 16 PWR Analog Power Supply (3.3V ±5%) AVDD should be isolated from the digital power supplies. For best results, use an internal power plane for isolation. If an internal power plane is not available, a ferrite bead can be used. Each power supply pin should be bypassed to ground through at least one 0.1µF capacitor. TGND7 TGND6 TGND5 TGND4 TGND3 TGND2 TGND1 TGND0 77 85 96 104 32 24 13 5 GND Transmit Analog Ground It’s recommended that all ground pins of this device be tied together. RGND2 RGND1 126 55 GND Receive Analog Ground It’s recommended that all ground pins of this device be tied together. DGND2 DGND1 DGNDcore 128 53 88 GND Digital Ground It’s recommended that all ground pins of this device be tied together. AGND 18 GND Analog Ground It’s recommended that all ground pins of this device be tied together. 9 xr XRT83SL28 8-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT REV. 1.0.0 HARDWARE MODE INTERFACE NAME PIN TYPE DESCRIPTION SR/DR 2 I Single Rail / Dual Rail Select Input This pin is used to select Single Rail or Dual Rail data formats. By default, Dual Rail is selected. To select Single Rail mode, this pin must be pulled "High". Once this pin is pulled "High", TNEGn/CODEn can be used to select between AMI and HDB3 Encoding/Decoding. NOTE: Internally pulled "Low" with a 50kΩ resistor. TERSEL1 TERSEL0 125 124 I Termination Impedance Select TERSEL[1:0] are used to set the internal impedance of the LIU for the Receive and Transmit paths. "00" = 75Ω for Tx and "High-Z" for Rx "01" = 120Ω for Tx and "High-Z" for Rx "10" = 75Ω for Tx and Rx "11" = 120Ω for Tx and Rx TCLKinv 107 I Transmit Clock Data "Low" = TPOS/TNEG data is sampled on the falling edge of TCLK "High" = TPOS/TNEG data is sampled on the rising edge of TCLK NOTE: Internally pulled "Low" with a 50kΩ resistor. RCLKinv 74 I Receive Clock Data "Low" = RPOS/RNEG data is updated on the rising edge of RCLK "High" = RPOS/RNEG data is updated on the falling edge of RCLK NOTE: Internally pulled "Low" with a 50kΩ resistor. LBM1 LBM0 56 57 I Loop Back Mode Select LBM[1:0] are used to configure the LIU into diagnostic loopback modes. To select the channel number, see pins CHLB[3:0]. LBM1 LBM0 Loopback Mode 0 0 No Loopback 0 1 Analog Loopback 1 0 Remote Loopback 1 1 Digital Loopback NOTE: Internally pulled "Low" with a 50kΩ resistor. JASEL1 JASEL0 20 21 I Jitter Attenuator Select JASEL[1:0] are used to configure the jitter attenuator into the Receive or Transmit path for all eight channels. JASEL1 JASEL0 JA Select Mode 0 0 JA Disabled 0 1 Transmit Path 1 0 Receive Path 1 1 JA Disabled NOTE: Internally pulled "Low" with a 50kΩ resistor. 10 xr XRT83SL28 8-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT REV. 1.0.0 NAME PIN TYPE DESCRIPTION FIFOS 19 I FIFO Bit Depth Select Input This pin is used to select the depth of the FIFO. By default, the FIFO is set to 32-Bit. To select a 64-Bit FIFO depth, this pin must be pulled "High". To meet TBR12/13 applications, the FIFO size must be set to 64-bit. NOTE: Internally pulled "Low" with a 50kΩ resistor. HW/Host 81 I Same as Host Mode. Reset 28 I Same as Host Mode. CHLB3 CHLB2 CHLB1 CHLB0 89 90 91 92 I Channel Loop Back Select CHLB[3:0] are used to select a particular channel or all eight channels simultaneously for Loop Back mode. See pins LBM[1:0] for selecting various types of Loop Back diagnostics. "0000" = Channel 0 "0001" = Channel 1 "0010" = Channel 2 "0011" = Channel 3 "0100" = Channel 4 "0101" = Channel 5 "0110" = Channel 6 "0111" = Channel 7 "1111" = All Eight Channels NOTE: CHLB3 (Pin 89) is internally pulled "High" with a 50kΩ Resistor. RLOS7 RLOS6 RLOS5 RLOS4 RLOS3 RLOS2 RLOS1 RLOS0 61 65 116 120 48 44 137 133 O Same as Host Mode. RCLK7 RCLK6 RCLK5 RCLK4 RCLK3 RCLK2 RCLK1 RCLK0 58 62 119 123 51 47 134 130 O Same as Host Mode. RPOS7 RPOS6 RPOS5 RPOS4 RPOS3 RPOS2 RPOS1 RPOS0 59 63 118 122 50 46 135 131 O Same as Host Mode. 11 xr XRT83SL28 8-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT REV. 1.0.0 NAME PIN TYPE DESCRIPTION RNEG/LCV7 RNEG/LCV6 RNEG/LCV5 RNEG/LCV4 RNEG/LCV3 RNEG/LCV2 RNEG/LCV1 RNEG/LCV0 60 64 117 121 49 45 136 132 O Same as Host Mode. RTIP7 RTIP6 RTIP5 RTIP4 RTIP3 RTIP2 RTIP1 RTIP0 75 87 94 106 34 22 15 3 I Same as Host Mode. RRING7 RRING6 RRING5 RRING4 RRING3 RRING2 RRING1 RRING0 76 86 95 105 33 23 14 4 I Same as Host Mode. TXOE 9 I Transmit Output Enable (Global Pin for All 8 Channels) Upon power up, the transmitters are tri-stated. Enabling the transmitters is controlled by pulling the TXOE hardware pin "High". If the TxOE pin is pulled "Low", all 8 transmitters are tri-stated. NOTE: TxOE is ideal for redundancy applications. See the Redundancy Applications Section of this datasheet for more details. Internally pulled "Low" with a 50KΩ resistor. DMO7 DMO6 DMO5 DMO4 DMO3 DMO2 DMO1 DMO0 73 72 109 108 36 37 144 1 O Same as Host Mode. TCLK7 TCLK6 TCLK5 TCLK4 TCLK3 TCLK2 TCLK1 TCLK0 69 66 115 112 40 43 138 141 I Transmit Clock Input TCLK is the input facility clock used to sample the incoming TPOS/TNEG data. If TCLK is pulled "Low" for 16 MCLK cycles, the transmitter outputs at TTIP/ TRING are tri-stated. If TCLK is pulled "High" for 16 MCLK cycles, the transmitter outputs at TTIP/TRING will send an All Ones pattern. TPOS/TNEG data can be sampled on either edge of TCLK selected by the TCLKinv pin. NOTE: The TCLKinv pin is a global setting that applies to all 8 channels. 12 xr XRT83SL28 8-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT REV. 1.0.0 NAME PIN TYPE DESCRIPTION TPOS7 TPOS6 TPOS5 TPOS4 TPOS3 TPOS2 TPOS1 TPOS0 70 67 114 111 39 42 139 142 I Same as Host Mode. TNEG7/CODE7 TNEG6/CODE6 TNEG5/CODE5 TNEG4/CODE4 TNEG3/CODE3 TNEG2/CODE2 TNEG1/CODE1 TNEG0/CODE0 71 68 113 110 38 41 140 143 I Transmit Negative Data / CODE Select Input TTIP7 TTIP6 TTIP5 TTIP4 TTIP3 TTIP2 TTIP1 TTIP0 78 84 97 103 31 25 12 6 O Same as Host Mode. TRING7 TRING6 TRING5 TRING4 TRING3 TRING2 TRING1 TRING0 80 82 99 101 29 27 10 8 O Same as Host Mode. ICT 35 I Same as Host Mode. MCLK 17 I Same as Host Mode. TNEG has the same definition as Host Mode. However, in Hardware mode and Single Rail Data Format, this pin is used to select between AMI and HDB3 Encoder/Decoder. By default, HDB3 is selected. To select AMI, this pin must be pulled "High". NOTE: Internally pulled "Low" with a 50kΩ resistor. 13 xr XRT83SL28 8-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT REV. 1.0.0 1.0 RECEIVE PATH LINE INTERFACE The receive path of the XRT83SL28 LIU consists of 8 independent E1 receivers. The following section describes the complete receive path from RTIP/RRING inputs to RCLK/RPOS/RNEG outputs. A simplified block diagram of the receive path is shown in Figure 4. FIGURE 4. SIMPLIFIED BLOCK DIAGRAM OF THE RECEIVE PATH LINE TERMINATION (RTIP/RRING) RCLK RPOS RNEG 1.1 HDB3 Decoder Rx Jitter Attenuator Clock & Data Recovery Peak Detector & Slicer RTIP RRING Internal Termination The input stage of the receive path accepts standard E1 coaxial cable or E1 twisted pair inputs through RTIP and RRING. The physical interface is optimized by placing the terminating impedance inside the LIU. This allows one bill of materials for all modes of operation reducing the number of external components necessary in system design. The receive termination impedance is selected by programming TERSEL[1:0] to match the line impedance. The XRT83SL28 has the ability to switch the internal termination to "High" impedance for redundancy applications. See Redundancy in the Applications Section of this datasheet. Selecting the internal impedance is shown in Table 1. A typical connection diagram is shown in Figure 5. TABLE 1: SELECTING THE INTERNAL IMPEDANCE TERSEL[1:0] RECEIVE TERMINATION 0h (00) 75Ω for Tx and "High-Z" for Rx 1h (01) 120Ω for Tx and "High-Z" for Rx 2h (10) 75Ω for Tx and Rx 3h (11) 120Ω for Tx and Rx FIGURE 5. TYPICAL CONNECTION DIAGRAM USING INTERNAL TERMINATION XRT83SL28 LIU RTIP Receiver Input 1:1 Line Interface E1 RRING One Bill of Materials Internal Impedance 14 xr XRT83SL28 8-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT REV. 1.0.0 1.2 Peak Detector/Data Slicer In the receive path, the line signal is coupled into the RTIP and RRing pins via a 1:1 transformer and are converted into digital pulses by an adaptive data slicer. Clock and data signals are recovered from the output of the slicer with the help of a digital PLL that provides excellent jitter accommodation for high input jitter tolerance. 1.3 Clock and Data Recovery The receive clock (RCLK) is recovered by the clock and data recovery circuitry. An internal PLL locks on the incoming data stream and outputs a clock that’s in phase with the incoming signal. In the absence of an incoming signal, RCLK maintains its timing by using MCLK as its reference. The recovered data can be updated on either edge of RCLK. By default, data is updated on the rising edge of RCLK. To update data on the falling edge of RCLK, set RCLKinv to "1" in the appropriate global register. Figure 6 is a timing diagram of the receive data updated on the rising edge of RCLK. Figure 7 is a timing diagram of the receive data updated on the falling edge of RCLK. The timing specifications are shown in Table 2. FIGURE 6. RECEIVE DATA UPDATED ON THE RISING EDGE OF RCLK R C LK R R DY R C LK F R C LK RPOS or RNEG R OH FIGURE 7. RECEIVE DATA UPDATED ON THE FALLING EDGE OF RCLK RCLKF RDY RCLKR RCLK RPOS or RNEG ROH TABLE 2: TIMING SPECIFICATIONS FOR RCLK/RPOS/RNEG PARAMETER SYMBOL MIN TYP MAX UNITS RCLK Duty Cycle RCDU 45 50 55 % Receive Data Setup Time RSU 150 - - ns Receive Data Hold Time RHO 150 - - ns RCLK to Data Delay RDY - - 40 ns 15 xr XRT83SL28 8-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT REV. 1.0.0 TABLE 2: TIMING SPECIFICATIONS FOR RCLK/RPOS/RNEG PARAMETER SYMBOL MIN TYP MAX UNITS RCLK Rise Time (10% to 90%) with 25pF Loading RCLKR - - 40 ns RCLK Fall Time (90% to 10%) with 25pF Loading RCLKF - - 40 ns NOTE: VDD=3.3V ±5%, TA=25°C, Unless Otherwise Specified 1.4 Receive Sensitivity To meet short haul requirements, the XRT83SL28 can accept E1 signals that have been attenuated by 9dB of cable loss in E1 mode. The test configuration for measuring the receive sensitivity is shown in Figure 8. FIGURE 8. TEST CONFIGURATION FOR MEASURING RECEIVE SENSITIVITY W&G ANT20 Tx Network Analyzer Rx Cable Loss Rx Tx External Loopback XRT83SL28 8-Channel Short Haul LIU E1 = PRBS 215 - 1 1.5 General Alarm Detection and Interrupt Generation The receive path detects RLOS and AIS. These alarms can be individually masked to prevent the alarm from triggering an interrupt. To enable interrupt generation, the Global Interrupt Enable (GIE) bit must be set "High" in the appropriate global register. Any time a change in status occurs (if the alarms are enabled), the interrupt pin will pull "Low" to indicate an alarm has occurred. Once the status registers have been read, the INT pin will return "High". The status registers are Reset Upon Read (RUR). NOTE: The interrupt pin is an Open-Drain output that requires a 10kΩ pull-up resistor. 16 xr REV. 1.0.0 1.5.1 XRT83SL28 8-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT RLOS (Receiver Loss of Signal) The XRT83SL28 supports both G.775 or ETSI-300-233 RLOS detection scheme. In G.775 mode, RLOS is declared when the received signal is less than 320mV for 32 consecutive pulse periods (typical). The device clears RLOS when the receive signal achieves 12.5% ones density with no more than 15 consecutive zeros in a 32 bit sliding window and the signal level exceeds 550mV (typical). In ETSI-300-233 mode the device declares RLOS when the input level drops below 320mV (typical) for more than 2048 pulse periods (1msec). The device exits RLOS when the input signal exceeds 550mV (typical) and has transitions for more than 32 pulse periods with 12.5% ones density with no more than 15 consecutive zero’s in a 32 bit sliding window. ETSI-300-233 RLOSS detection method is only available in Host mode. 1.5.2 AIS (Alarm Indication Signal) The XRT83SL28 adheres to ITU-T G.775 or ETSI-300-233 specifications for an all ones pattern detection by programming the appropriate channel register. The alarm indication signal is set to "1" if an all ones pattern is detected. In G.775 mode, AIS is defined as 2 or less zeros in 2 consecutive double frame (512-bit window) periods. AIS will clear when the incoming signal has 3 or more zeros in the same time period. In ETSI-300-233 mode, AIS is defined as less than 3 zeros in a 512-bit window. AIS detection scheme per ESTI-300-233 is only available in Host mode. 1.5.3 LCV (Line Code Violation Detection) In HDB3 mode, the LCV pin will be set to "High" if the receiver detects excessive zero’s, bipolar violations or HDB3 code violations. If the device is configured in AMI mode, any bipolar violations will cause the LCV pin to go "High". 1.6 Receive Jitter Attenuator The jitter attenuator can be configured in the receive path to reduce phase and frequency jitter in the recovered clock. The jitter attenuator uses a data FIFO (First In First Out) with a programmable depth of 32-bit or 64-bit. If the LIU is used for line synchronization (loop timing systems), the JA should be enabled. When the Read and Write pointers of the FIFO are within 2-Bits of over-flowing or under-flowing, the bandwidth of the jitter attenuator is widened to track the short term input jitter, thereby avoiding data corruption. When this condition occurs, the jitter attenuator will not attenuate input jitter until the Read/Write pointer’s position is outside the 2Bit window. The bandwidth is set to 2Hz when the JA is configured in the Receive or Transmit path. The JA has a typical clock delay equal to ½ of the FIFO bit depth. NOTE: If the LIU is used in a multiplexer/mapper application where stuffing bits are typically removed, the JA can be configured in the transmit path to smooth out the gapped clock. See the Transmit Section of this datasheet. 17 xr XRT83SL28 8-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT 1.7 REV. 1.0.0 HDB3 Decoder In single rail mode, RPOS is the output of decoded AMI or HDB3 signals and RNEG is the LCV output. HDB3 data is defined as any block of 4 successive zeros replaced with OOOV or BOOV, so that two successive V pulses are of opposite polarity to acheive zero DC offsey. If the HDB3 decoder is selected, the receive path removes the V and B pulses so that the original data is output to RPOS. 1.8 ARAOS (Automatic Receive All Ones) The XRT83SL28 has the ability to send an All Ones signal to RPOS if ARAOS is enabled in the appropriate channel register. If ARAOS is enabled and an RLOS condition occurs, the Receiver outputs will generate a single rail All Ones pattern. When RLOS clears, the All Ones pattern ends and the Receive path returns to normal operation. For TAOS in the transmit direction, see the Transmit Section of this datasheet. A simplified block diagram of the ATAOS function is shown in Figure 9. FIGURE 9. SIMPLIFIED BLOCK DIAGRAM OF THE ARAOS FUNCTION RPOS Rx RNEG TAOS ARAOS RLOS 1.9 RPOS/RNEG/RCLK The digital output data can be programmed to either single rail or dual rail formats. Figure 10 is a timing diagram of a repeating "0011" pattern in single-rail mode. Figure 11 is a timing diagram of the same fixed pattern in dual rail mode. FIGURE 10. SINGLE RAIL MODE WITH A FIXED REPEATING "0011" PATTERN RCLK RPOS 0 0 1 18 1 0 xr XRT83SL28 8-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT REV. 1.0.0 FIGURE 11. DUAL RAIL MODE WITH A FIXED REPEATING "0011" PATTERN RCLK RPOS RNEG 0 0 1 0 1 19 xr XRT83SL28 8-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT REV. 1.0.0 2.0 TRANSMIT PATH LINE INTERFACE The transmit path of the XRT83SL28 LIU consists of 8 independent E1 transmitters. The following section describes the complete transmit path from TCLK/TPOS/TNEG inputs to TTIP/TRING outputs. A simplified block diagram of the transmit path is shown in Figure 12. FIGURE 12. SIMPLIFIED BLOCK DIAGRAM OF THE TRANSMIT PATH TCLK TPOS TNEG 2.1 HDB3 Encoder Tx Jitter Attenuator TTIP Timing Control Tx Pulse Shaper Line Driver TRING TCLK/TPOS/TNEG Digital Inputs In dual rail mode, TPOS and TNEG are the digital inputs for the transmit path. In single rail mode, TNEG can be tied to ground unless Hardware mode is selected (see the Hardware Pin Description). The XRT83SL28 can be programmed to sample the inputs on either edge of TCLK. By default, data is sampled on the falling edge of TCLK. To sample data on the rising edge of TCLK, set TCLKinv to "1" in the appropriate global register. Figure 13 is a timing diagram of the transmit input data sampled on the falling edge of TCLK. Figure 14 is a timing diagram of the transmit input data sampled on the rising edge of TCLK. The timing specifications are shown in Table 3. FIGURE 13. TRANSMIT DATA SAMPLED ON FALLING EDGE OF TCLK TCLKR TCLKF TCLK TPOS or TNEG TSU THO FIGURE 14. TRANSMIT DATA SAMPLED ON RISING EDGE OF TCLK TCLKF TCLK TPOS or TNEG TSU THO 20 TCLKR xr XRT83SL28 8-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT REV. 1.0.0 TABLE 3: TIMING SPECIFICATIONS FOR TCLK/TPOS/TNEG PARAMETER SYMBOL MIN TYP MAX UNITS TCLK Duty Cycle TCDU 30 50 70 % Transmit Data Setup Time TSU 50 - - ns Transmit Data Hold Time THO 30 - - ns TCLK Rise Time (10% to 90%) TCLKR - - 40 ns TCLK Fall Time (90% to 10%) TCLKF - - 40 ns NOTE: VDD=3.3V ±5%, TA=25°C, Unless Otherwise Specified 2.2 HDB3 Encoder In single rail mode, the LIU can encode the TPOS input signal to AMI or HDB3 data. If HDB3 encoding is selected, any sequence with four or more consecutive zeros in the input will be replaced with 000V or B00V, where "B" indicates a pulse conforming to the bipolar rule and "V" representing a pulse violating the rule. An example of HDB3 encoding is shown in Table 4. TABLE 4: EXAMPLES OF HDB3 ENCODING NUMBER OF PULSES BEFORE NEXT 4 ZEROS Input 2.3 0000 HDB3 (Case 1) Odd 000V HDB3 (Case 2) Even B00V Transmit Jitter Attenuator The XRT83SL28 LIU is ideal for multiplexer or mapper applications where the network data crosses multiple timing domains. As the higher data rates are de-multiplexed to E1 data, stuffing bits are typically removed which can leave gaps in the incoming data stream. The JA can be configured in the transmit path with a 32-Bit or 64-Bit FIFO that is used to smooth the gapped clock into a steady E1 output. The maximum gap width the JA in the Transmit path can tolerate is shown in Table 5. TABLE 5: MAXIMUM GAP WIDTH FOR MULTIPLEXER/MAPPER APPLICATIONS FIFO DEPTH MAXIMUM GAP WIDTH 32-Bit 20 UI 64-Bit 50 UI NOTE: If the LIU is used in a loop timing system, the JA should be configured in the receive path. See the Receive Section of this datasheet. 21 xr XRT83SL28 8-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT 2.4 REV. 1.0.0 TAOS (Transmit All Ones) The XRT83SL28 has the ability to transmit all ones on a per channel basis by programming the appropriate channel register. If TAOS is enabled, the Transmitter outputs will generate an All Ones pattern regardless of the Transmit Input data. The Remote Loop Back mode has priority over TAOS. Figure 15 is a diagram showing the all ones signal at TTIP and TRING. FIGURE 15. TAOS (TRANSMIT ALL ONES)ATAOS (AUTOMATIC TRANSMIT ALL ONES) 1 1 1 TAOS 2.5 ATAOS (Automatic Transmit All Ones) Unlike TAOS, ATAOS is used to generate an All Ones signal only when an RLOS condition occurs. If ATAOS is enabled, any channel that experiences an RLOS condition will automatically cause the transmitter on that channel to send an all ones pattern to the line. When RLOS clears, the All Ones pattern ends and the Transmit path returns to normal operation. For TAOS on the receive output pins, see ARAOS in the Receive Section of this datasheet. A simplified block diagram of the ATAOS function is shown in Figure 16. FIGURE 16. SIMPLIFIED BLOCK DIAGRAM OF THE ATAOS FUNCTION Tx TTIP TRING TAOS ATAOS RLOS 2.6 Transmitter Power down in Hardware mode In Hardware mode, if TCLK is pulled "Low" for 16 MCLK cycles the transmitter outputs at TTIP/TRING are tristated. If TCLK is pulled "High" for 16 MCLK cycles the transmitter will send an All Ones signal to the line, using MCLK as reference. 2.7 DMO (Driver Monitor Output) The driver monitor circuit is used to detect transmit driver failures by monitoring the activities at TTIP/TRING outputs. Driver failure may be caused by a short circuit in the primary transformer or system problems at the transmit inputs. If the transmitter of a channel has no output for more than 128 TCLK cycles, DMO goes "High" until a valid transmit pulse is detected. If the DMO interrupt is enabled, the change in status of DMO will cause the interrupt pin to go "Low". Once the status register is read, the interrupt pin will return "High" and the status register will be reset (RUR). 22 xr XRT83SL28 8-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT REV. 1.0.0 2.8 Line Termination (TTIP/TRING) The output stage of the transmit path generates standard bipolar signals to the line for both E1 (75 Ohm) coaxial cable and E1 (120 Ohm) twisted pair. The XRT83L28 has built-in output impedance matching for both 75 Ohm and 120 Ohm operations. This eliminates the need to change any external components while switching from 75 Ohm to 120 Ohm operation. The transmitter interface only requires one 0.68µF DC blocking capacitor with a 1:2 transformer as shown in Figure 17. FIGURE 17. TYPICAL CONNECTION DIAGRAM USING INTERNAL TERMINATION XRT83SL28 LIU TTIP Transmitter Output 1:2 C=0.68uF TRING One Bill of Materials Internal Impedance 23 Line Interface E1 xr XRT83SL28 8-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT REV. 1.0.0 3.0 E1 APPLICATIONS This applications section describes common E1 system considerations along with references to application notes available for reference where applicable. 3.1 Loopback Diagnostics The XRT83SL28 supports several loopback modes for diagnostic testing. The following section describes the local analog loopback, remote loopback, and digital loopback. 3.1.1 Local Analog Loopback With local analog loopback activated, the transmit output data at TTIP/TRING is internally looped back to the analog inputs at RTIP/RRING. External inputs at RTIP/RRING are ignored while valid transmit output data continues to be sent to the line. A simplified block diagram of local analog loopback is shown in Figure 18. FIGURE 18. SIMPLIFIED BLOCK DIAGRAM OF LOCAL ANALOG LOOPBACK TAOS TCLK TPOS TNEG Encoder JA Timing Control RCLK RPOS RNEG Decoder JA Data and Clock Recovery TTIP TRING Tx RTIP RRING Rx NOTE: TAOS takes priority over the transmit input data at TPOS/TNEG. 3.1.2 Remote Loopback With remote loopback activated, the receive input data at RTIP/RRING is internally looped back to the transmit output data at TTIP/TRING. The transmit input data at TCLK/TPOS/TNEG are ignored while valid receive output data continues to be sent to the system. A simplified block diagram of remote loopback is shown in Figure 19. FIGURE 19. SIMPLIFIED BLOCK DIAGRAM OF REMOTE LOOPBACK TAOS TCLK TPOS TNEG Encoder JA Timing Control RCLK RPOS RNEG Decoder JA Data and Clock Recovery NOTE: Remote Loop Back takes priority over TAOS. 24 TTIP TRING Tx Rx RTIP RRING xr XRT83SL28 8-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT REV. 1.0.0 3.1.3 Digital Loopback With digital loopback activated, the transmit input data at TCLK/TPOS/TNEG is looped back to the receive output data at RCLK/RPOS/RNEG. The receive input data at RTIP/RRING is ignored while valid transmit output data continues to be sent to the line. A simplified block diagram of digital loopback is shown in Figure 20. FIGURE 20. SIMPLIFIED BLOCK DIAGRAM OF DIGITAL LOOPBACK TAOS TCLK TPOS TNEG Encoder JA Timing Control RCLK RPOS RNEG Decoder JA Data and Clock Recovery 25 TTIP TRING Tx Rx RTIP RRING xr XRT83SL28 8-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT 3.2 REV. 1.0.0 Line Card Redundancy Telecommunication system design requires signal integrity and reliability. When an E1 primary line card has a failure, it must be swapped with a backup line card while maintaining connectivity to a backplane without losing data. System designers can achieve this by implementing common redundancy schemes with the XRT83SL28 LIU. EXAR offers features that are tailored to redundancy applications while reducing the number of components and providing system designers with solid reference designs. RLOS and DMO If an RLOS or DMO condition occurs, the XRT83SL28 reports the alarm to the individual status registers on a per channel basis. However, for redundancy applications, RLOS and DMO pins can be used to initiate an automatic switch to the back up card. Typical Redundancy Schemes • 1:1 One backup card for every primary card (Facility Protection) • 1+1 One backup card for every primary card (Line Protection) • ·N+1 One backup card for N primary cards 3.2.1 1:1 and 1+1 Redundancy Without Relays The 1:1 facility protection and 1+1 line protection have one backup card for every primary card. When using 1:1 or 1+1 redundancy, the backup card has its transmitters tri-stated and its receivers in high impedance. This eliminates the need for external relays and provides one bill of materials for all interface modes of operation. For 1+1 line protection, the receiver inputs on the backup card have the ability to monitor the line for bit errors while in high impedance. The transmit and receive sections of the LIU device are described separately. 3.2.2 Transmit Interface with 1:1 and 1+1 Redundancy The transmitters on the backup card should be tri-stated. Select the appropriate impedance for the desired mode of operation, E1 75Ω or 120Ω. A 0.68uF capacitor is used in series with TTIP for blocking DC bias. See Figure 21. for a simplified block diagram of the transmit section for a 1:1 and 1+1 redundancy. FIGURE 21. SIMPLIFIED BLOCK DIAGRAM OF THE TRANSMIT INTERFACE FOR 1:1 AND 1+1 REDUNDANCY Backplane Interface Primary Card XRT83SL28 1:2 Tx 0.68uF E1 Line Internal Impedance Backup Card XRT83SL28 1:2 Tx 0.68uF Internal Impedance 26 xr XRT83SL28 8-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT REV. 1.0.0 3.2.3 Receive Interface with 1:1 and 1+1 Redundancy The receivers on the backup card should be programmed for "High" impedance. Since there is no external resistor in the circuit, the receivers on the backup card will not load down the line interface. This key design feature eliminates the need for relays and provides one bill of materials for all interface modes of operation. Select the impedance for the desired mode of operation, E1 75Ω or 120Ω. To swap the primary card, set the backup card to internal impedance, then the primary card to "High" impedance. See Figure 22. for a simplified block diagram of the receive section for a 1:1 redundancy scheme. FIGURE 22. SIMPLIFIED BLOCK DIAGRAM OF THE RECEIVE INTERFACE FOR 1:1 AND 1+1 REDUNDANCY Backplane Interface Primary Card XRT83SL28 1:1 E1 Line Rx Internal Impedance Backup Card XRT83SL28 1:1 Rx "High" Impedance 3.2.4 N+1 Redundancy Using External Relays N+1 redundancy has one backup card for N primary cards. Due to impedance mismatch and signal contention, external relays are necessary when using this redundancy scheme. The relays create complete isolation between the primary cards and the backup card. This allows all transmitters and receivers on the primary cards to be configured in internal impedance, providing one bill of materials for all interface modes of operation. The transmit and receive sections of the LIU device are described separately. 27 xr XRT83SL28 8-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT 3.2.5 REV. 1.0.0 Transmit Interface with N+1 Redundancy For N+1 redundancy, the transmitters on all cards can be programmed for internal impedance. The transmitters on the backup card do not have to be tri-stated. To swap the primary card, close the desired relays. A 0.68uF capacitor is used in series with TTIP for blocking DC bias. See Figure 23 for a simplified block diagram of the transmit section for an N+1 redundancy scheme. FIGURE 23. SIMPLIFIED BLOCK DIAGRAM OF THE TRANSMIT INTERFACE FOR N+1 REDUNDANCY Backplane Interface Line Interface Card Primary Card XRT83SL28 1:2 Tx 0.68uF E1 Line Internal Impedance XRT83SL28 Primary Card 1:2 Tx 0.68uF E1 Line Internal Impedance Primary Card XRT83SL28 1:2 Tx 0.68uF E1 Line Internal Impedance Backup Card XRT83SL28 Tx 0.68uF Internal Impedance 28 xr XRT83SL28 8-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT REV. 1.0.0 3.2.6 Receive Interface with N+1 Redundancy For N+1 redundancy, the receivers on all cards can be programmed for internal impedance. The receivers on the backup card do not have to be tri-stated. To swap the primary card, close the desired relays. See Figure Figure 24 for a simplified block diagram of the receive section for an N+1 redundancy scheme. FIGURE 24. SIMPLIFIED BLOCK DIAGRAM OF THE RECEIVE INTERFACE FOR N+1 REDUNDANCY Backplane Interface Primary Card Line Interface Card XRT83SL28 1:1 Rx E1 Line Internal Impedance Primary Card XRT83SL28 1:1 Rx E1 Line Internal Impedance Primary Card XRT83SL28 1:1 Rx E1 Line Internal Impedance Backup Card XRT83SL28 Rx Internal Impedance 29 xr XRT83SL28 8-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT 3.3 REV. 1.0.0 Power Failure Protection For 1:1 or 1+1 line card redundancy in E1 applications, power failure could cause a line card to change the characteristics of the line impedance, causing a degradation in system performance. The XRT83SL28 is designed to ensure reliability during power failures. The LIU has patented high impedance circuits that allow the receiver inputs and the transmitter outputs to be in "High" impedance when the LIU experiences a power failure or when the LIU is powered off. NOTE: For power failure protection, a transformer must be used to couple to the line interface. See the TAN-56 application note for more details. 3.4 Overvoltage and Overcurrent Protection Physical layer devices such as LIUs that interface to telecommunications lines are exposed to overvoltage transients posed by environmental threats. An Overvoltage transient is a pulse of energy concentrated over a small period of time, usually under a few milliseconds. These pulses are random and exceed the operating conditions of CMOS transceiver ICs. Electronic equipment connecting to data lines are susceptible to many forms of overvoltage transients such as lightning, AC power faults and electrostatic discharge (ESD). There are three important standards when designing a telecommunications system to withstand overvoltage transients. • UL1950 and FCC Part 68 • Telcordia (Bellcore) GR-1089 • ITU-T K.20, K.21 and K.41 NOTE: For a reference design and performance, see the TAN-54 application note for more details. 3.5 Non-Intrusive Monitoring In non-intrusive monitoring applications, the transmitters are shut off by setting TxON "Low". The receivers must be actively receiving data without interfering with the line impedance. The XRT83SL28’s internal termination ensures that the line termination meets E1 specifications for 75Ω or 120Ω while monitoring the data stream. System integrity is maintained by placing the non-intrusive receiver in "High" impedance, equivalent to that of a 1+1 redundancy application. A simplified block diagram of non-intrusive monitoring is shown in Figure 25. FIGURE 25. SIMPLIFIED BLOCK DIAGRAM OF A NON-INTRUSIVE MONITORING APPLICATION XRT83SL28 Data Traffic Line Card Transceiver Node XRT83SL28 Non-Intrusive Receiver 30 xr XRT83SL28 8-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT REV. 1.0.0 4.0 SERIAL MICROPROCESSOR INTERFACE BLOCK The serial microprocessor uses a standard 3-pin serial port with CS, SCLK, and SDI for programming the LIU. Optional pins such as SDO, INT, and RESET allow the ability to read back contents of the registers, monitor the LIU via an interrupt pin, and reset the LIU to its default configuration by pulling reset "Low" for more than 10µS. A simplified block diagram of the Serial Microprocessor is shown in Figure 26. FIGURE 26. SIMPLIFIED BLOCK DIAGRAM OF THE SERIAL MICROPROCESSOR INTERFACE SDO CS SCLK INT SDI Serial Microprocessor Interface HW/Host RESET 4.1 Serial Timing Information The serial port requires 16 bits of data applied to the SDI (Serial Data Input) pin. The Serial Microprocessor samples SDI on the rising edge of SCLK (Serial Clock Input). The data is not latched into the device until all 16 bits of serial data have been sampled. A timing diagram of the Serial Microprocessor is shown in Figure 27. FIGURE 27. TIMING DIAGRAM FOR THE SERIAL MICROPROCESSOR INTERFACE CS 25nS 50nS SCLK 1 SDI R/W SDO 2 A0 3 A1 4 A2 5 A3 6 A4 7 A5 9 8 X High-Z 31 10 11 12 13 14 15 16 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 High-Z XRT83SL28 8-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT 4.2 xr REV. 1.0.0 16-Bit Serial Data Input Description The serial data input is sampled on the rising edge of SCLK. In read-back mode, the serial data output is updated on the falling edge of SCLK. The serial data must be applied to the LIU LSB first. The 16 bits of serial data are described below. 4.2.1 R/W (SCLK1) The first serial bit applied to the LIU informs the microprocessor that a Read or Write operation is desired. If the R/W bit is set to “0”, the microprocessor is configured for a Write operation. If the R/W bit is set to “1”, the microprocessor is configured for a Read operation. 4.2.2 A[5:0] (SCLK2 - SCLK7) The next 6 SCLK cycles are used to provide the address to which a Read or Write operation will occur. A0 (LSB) must be sent to the LIU first followed by A1 and so forth until all 6 address bits have been sampled by SCLK. 4.2.3 X (Dummy Bit SCLK8) The dummy bit sampled by SCLK8 is used to allow sufficient time for the serial data output pin to update data if the read-back mode is selected by setting R/W = “1”. Therefore, the state of this bit is ignored and can hold either “0” or “1” during both Read and Write operations. 4.2.4 D[7:0] (SCLK9 - SCLK16) The next 8 SCLK cycles are used to provide the data to be written into the internal register chosen by the address bits. D0 (LSB) must be sent to the LIU first followed by D1 and so forth until all 8 data bits have been sampled by SCLK. Once 16 SCLK cycles have been complete, the LIU holds the data until CS is pulled “High” whereby, the serial microprocessor latches the data into the selected internal register. 4.3 8-Bit Serial Data Output Description The serial data output is updated on the falling edge of SCLK9 - SCLK16 if R/W is set to “1”. D0 (LSB) is provided on SCLK9 to the SDO pin first followed by D1 and so forth until all 8 data bits have been updated. The SDO pin allows the user to read the contents stored in individual registers by providing the desired address on the SDI pin during the Read cycle. 32 xr XRT83SL28 8-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT REV. 1.0.0 TABLE 6: MICROPROCESSOR REGISTER DESCRIPTION REG ADDR TYPE D7 D6 D5 D4 D3 D2 D1 D0 RCLKinv TCLKinv FIFO JASEL1 JASEL0 Global Control Register for All 8 Channels (0x00h) 0 0x00 R/W GIE SR/DR CODE 1 0x01 RO Revision ID (See Bit Description) 2 0x02 RO Device ID (See Bit Description) 3 0x03 R/W For Internal Use Only TSTEN Channel 0 Control Register (0x04h - 0x07h) 4 0x04 R/W Reserved RLAM0 ARAOS0 ATAOS0 TAOS0 TXOE0 TERSEL1 TERSEL0 5 0x05 R/W Reserved SRESET0 AISIE0 DMOIE0 RLOSIE0 Reserved LB1 LB0 6 0x06 RUR Reserved Reserved AISI0 DMOI0 RLOSI0 Reserved Reserved Reserved 7 0x07 RO Reserved Reserved AISS0 DMOS0 RLOSS0 Reserved Reserved Reserved Channel 1 Control Register (0x08h - 0x0Bh) 8 0x08 RO Reserved RLAM1 ARAOS1 ATAOS1 TAOS1 TXOE1 TERSEL1 TERSEL0 9 0x09 R/W Reserved SRESET1 AISIE1 DMOIE1 RLOSIE1 Reserved LB1 LB0 10 0x0A RUR Reserved Reserved AISI1 DMOI1 RLOSI1 Reserved Reserved Reserved 11 0x0B RO Reserved Reserved AISS1 DMOS1 RLOSS1 Reserved Reserved Reserved Channel 2 Control Register (0x0Ch - 0x0Fh) 12 0x0C R/W Reserved RLAM2 ARAOS2 ATAOS2 TAOS2 TXOE2 TERSEL1 TERSEL0 13 0x0D R/W Reserved SRESET2 AISIE2 DMOIE2 RLOSIE2 Reserved LB1 LB0 14 0x0E RUR Reserved Reserved AISI2 DMOI2 RLOSI2 Reserved Reserved Reserved 15 0x0F RO Reserved Reserved AISS2 DMOS2 RLOSS2 Reserved Reserved Reserved Channel 3 Control Register (0x10h - 0x13h) 16 0x10 R/W Reserved RLAM3 ARAOS3 ATAOS3 TAOS3 TXOE3 TERSEL1 TERSEL0 17 0X11 R/W Reserved SRESET3 AISIE3 DMOIE3 RLOSIE3 Reserved LB1 LB0 18 0x12 RUR Reserved Reserved AISI3 DMOI3 RLOSI3 Reserved Reserved Reserved 19 0x13 RO Reserved Reserved AISS3 DMOS3 RLOSS3 Reserved Reserved Reserved Channel 4 Control Register (0x14h - 0x17h)\ 20 0x14 R/W Reserved RLAM4 ARAOS4 ATAOS4 TAOS4 TXOE4 TERSEL1 TERSEL0 21 0x15 R/W Reserved SRESET4 AISIE4 DMOIE4 RLOSIE4 Reserved LB1 LB0 22 0x16 RUR Reserved Reserved AISI4 DMOI4 RLOSI4 Reserved Reserved Reserved 23 0x17 RO Reserved Reserved AISS4 DMOS4 RLOSS4 Reserved Reserved Reserved Channel 5 Control Register (0x18h - 0x1Bh) 24 0x18 R/W Reserved RLAM3 ARAOS5 ATAOS5 TAOS5 TXOE5 TERSEL1 TERSEL0 25 0x19 R/W Reserved SRESET5 AISIE5 DMOIE5 RLOSIE5 Reserved LB1 LB0 26 0x1A RUR Reserved Reserved AISI5 DMOI5 RLOSI5 Reserved Reserved Reserved 27 0X1B RO Reserved Reserved AISS5 DMOS5 RLOSS5 Reserved Reserved Reserved 33 xr XRT83SL28 8-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT REV. 1.0.0 TABLE 6: MICROPROCESSOR REGISTER DESCRIPTION REG ADDR TYPE D7 D6 D5 D4 D3 D2 D1 D0 Channel 6 Control Register (0x1Ch - 0x1Fh) 28 0x1C R/W Reserved RLAM6 ARAOS6 ATAOS6 TAOS6 TXOE6 TERSEL1 TERSEL0 29 0x1D R/W Reserved SRESET6 AISIE6 DMOIE6 RLOSIE6 Reserved LB1 LB0 30 0x1E RUR Reserved Reserved AISI6 DMOI6 RLOSI6 Reserved Reserved Reserved 31 0X1F RO Reserved Reserved AISS6 DMOS6 RLOSS6 Reserved Reserved Reserved Channel 7 Control Register (0x20h - 0x23h) 32 0x20 R/W Reserved RLAM7 ARAOS7 ATAOS7 TAOS7 TXOE7 TERSEL1 TERSEL0 33 0x21 R/W Reserved SRESET7 AISIE7 DMOIE7 RLOSIE7 Reserved LB1 LB0 34 0x22 RUR Reserved Reserved AISI7 DMOI7 RLOSI7 Reserved Reserved Reserved 35 0X23 RO Reserved Reserved AISS7 DMOS7 RLOSS7 Reserved Reserved Reserved 34 xr XRT83SL28 8-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT REV. 1.0.0 TABLE 7: MICROPROCESSOR REGISTER 0X00H BIT DESCRIPTION GLOBAL CONTROL REGISTER FOR ALL 8 CHANNELS (0X00H) BIT NAME FUNCTION D7 GIE Global Interrupt Enable The global interrupt enable is used to enable/disable all interrupt activity for all 8 channels. This bit must be set "High" for the interrupt pin to operate. Register Type Default Value (HW reset) R/W 0 R/W 0 R/W 0 "0" = Disable all interrupt generation "1" = Enable interrupt generation to the individual channel registers D6 SR/DR Single Rail / Dual Rail Select This bit is used to configure the receive outputs and transmit inputs to single rail or dual rail data formats. "0" = Dual Rail "1" = Single Rail D5 CODE Encoding / Decoding Select (Single Rail Mode Only) This bit is used to select between AMI or HDB3. "0" = HDB3 "1" = AMI D4 RCLKinv Receiver Clock Data "0" = RPOS/RNEG data is updated on the rising edge of RCLK "1" = RPOS/RNEG data is updated on the falling edge of RCLK R/W 0 D3 TCLKinv Transmitter Clock Data "0" = TPOS/TNEG data is sampled on the falling edge of TCLK "1" = TPOS/TNEG data is sampled on the rising edge of TCLK R/W 0 D2 FIFOS FIFO Depth Select The FIFO depth select is used to configure the part for a 32-bit or 64-bit FIFO (Within the Jitter Attenuator Block). The delay of the FIFO is typically equal to ½ the FIFO depth. R/W 0 R/W 0 0 "0" = 32-bit FIFO "1" = 64-bit FIFO D1 D0 JASEL1 JASEL0 Jitter Attenuator Select These bits are used to configure the Jitter Attenuator into the Receive or Transmit path. "00" = Disabled "01" = Transmit Path "10" = Receive Path "11" = Disabled 35 xr XRT83SL28 8-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT REV. 1.0.0 TABLE 8: MICROPROCESSOR REGISTER 0X01H BIT DESCRIPTION REVISION "ID" REGISTER (0X01H) BIT NAME FUNCTION D7 D6 D5 D4 D3 D2 D1 D0 Revision "ID" The revision "ID" of the XRT83SL28 LIU is used to enable software to identify which revision of silicon is currently being tested. The revision "ID" for the first revision of silicon (Revision A) will be 0x01h. Register Type Default Value (HW reset) RO 0 0 0 0 0 0 0 1 Register Type Default Value (HW reset) RO 1 1 1 1 0 1 1 1 TABLE 9: MICROPROCESSOR REGISTER 0X02H BIT DESCRIPTION DEVICE "ID" REGISTER (0X02H) BIT D7 D6 D5 D4 D3 D2 D1 D0 NAME FUNCTION Device "ID" The device "ID" of the XRT83SL28 LIU is 0xF7h. Along with the revision "ID", the device "ID" is used to enable software to identify the silicon adding flexibility for system control and debug. TABLE 10: MICROPROCESSOR REGISTER BIT DESCRIPTION CHANNEL CONTROL REGISTER (0X04H, 0X08H, 0X0CH, 0X10H, 0X14H, 0X18H, 0X1CH, 0X20H) BIT NAME FUNCTION D7 Reserved This Register Bit is Not Used D6 RLAM_n RLOS/AIS Mode Select This bit is used to select the industry standard for declaring / clearing RLOS and AIS functionality. See the Receive Path Line Interface section of this datasheet. "0" = ITU G.775 "1" = ETSI300233 36 Register Type Default Value (HW reset) X X R/W 0 xr XRT83SL28 8-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT REV. 1.0.0 TABLE 10: MICROPROCESSOR REGISTER BIT DESCRIPTION CHANNEL CONTROL REGISTER (0X04H, 0X08H, 0X0CH, 0X10H, 0X14H, 0X18H, 0X1CH, 0X20H) BIT NAME FUNCTION D5 ARAOS_n Automatic Receive All Ones If ARAOS_n is selected, an all ones pattern will be sent to the RPOS/RNEG outputs if the channel experiences an RLOS condition. If RLOS does not occur, ARAOS_n will remain inactive. Register Type Default Value (HW reset) R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 0 "0" = Disabled "1" = Enabled D4 ATAOS_n Automatic Transmit All Ones If ATAOS_n is selected, an all ones pattern will be transmitted from TTIP/TRING if the channel experiences an RLOS condition. If RLOS does not occur, ATAOS_n will remain inactive. "0" = Disabled "1" = Enabled D3 TAOS_n Transmit All Ones If TAOS_n is selected, an all ones pattern will be transmitted from TTIP/TRING if the transmitter is turned on. Remote Loop Back has priority over TAOS. "0" = Disabled "1" = Enabled D2 TXOE_n Transmit Output Enable Upon power up, the tranmitters are tri-stated. This bit is used to enable the transmitter for this channel if the TxOE pin is pulled "High". If the TxOE pin is pulled "Low", all 8 transmitters are tristated. "0" = Transmitter is disabled "1" = Transmitter is enabled if TxOE pin is pulled "High" D1 D0 TERSEL1 TERSEL0 Receive Line Impedance Select TERSEL[1:0] are used to select the internal line impedance. "00" = 75Ω for Tx and "High-Z" for Rx "01" = 120Ω for Tx and "High-Z" for Rx "10" = 75Ω for Tx and Rx "11" = 120Ω for Tx and Rx 37 xr XRT83SL28 8-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT REV. 1.0.0 TABLE 11: MICROPROCESSOR REGISTER BIT DESCRIPTION CHANNEL CONTROL REGISTER (0X05H, 0X09H, 0X0DH, 0X11H, 0X15H, 0X19H, 0X1DH, 0X21H) BIT NAME D7 Reserved D6 FUNCTION This Register Bit is Not Used SRESET_n Software Reset By setting this bit to "1" for more than 10µS, the individual channel is reset to its default register configuration and all state machines are internally reset. Register Type Default Value (HW reset) X X R/W 0 "0" = ITU G.775 "1" = ETSI300233 D5 AISIE_n Alarm Indication Signal Interrupt Enable "0" = Masks the AIS interrupt generation "1" = Enables Interrupt generation R/W 0 D4 DMOIE_n Driver Monitor Output Interrupt Enable "0" = Masks the DMO interrupt generation "1" = Enables Interrupt generation R/W 0 D3 RLOSIE_n Receiver Loss of Signal Interrupt Enable "0" = Masks the RLOS interrupt generation "1" = Enables Interrupt generation R/W 0 D2 Reserved X X D1 D0 LB1 LB0 R/W 0 This Register Bit is Not Used Loop Back Select These bits are used to configure the channel in one of three loopback modes. For additional information on loopback modes, see the Application Section of this datasheet. LB1 LB0 Loopback Mode 0 0 No Loopback 0 1 Analog Loopback 1 0 Remote Loopback 1 1 Digital Loopback TABLE 12: MICROPROCESSOR REGISTER BIT DESCRIPTION CHANNEL CONTROL REGISTER (0X06H, 0X0AH, 0X0EH, 0X12H, 0X16H, 0X1AH, 0X1EH, 0X22H) BIT NAME D7 Reserved D6 Reserved Register Type Default Value (HW reset) This Register Bit is Not Used R/W X This Register Bit is Not Used R/W X FUNCTION 38 xr XRT83SL28 8-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT REV. 1.0.0 TABLE 12: MICROPROCESSOR REGISTER BIT DESCRIPTION CHANNEL CONTROL REGISTER (0X06H, 0X0AH, 0X0EH, 0X12H, 0X16H, 0X1AH, 0X1EH, 0X22H) Register Type Default Value (HW reset) Alarm Indication Signal Interrupt Status "0" = No Change "1" = Change in Status Occured RUR 0 DMOI_n Driver Monitor Output Interrupt Status "0" = No Change "1" = Change in Status Occured RUR 0 D3 RLOSI_n Receiver Loss of Signal Interrupt Status "0" = No Change "1" = Change in Status Occured RUR 0 D2 Reserved This Register Bit is Not Used R/W X D1 Reserved This Register Bit is Not Used R/W X D0 Reserved This Register Bit is Not Used R/W X BIT NAME D5 AISI_n D4 FUNCTION TABLE 13: MICROPROCESSOR REGISTER BIT DESCRIPTION CHANNEL CONTROL REGISTER (0X07H, 0X0BH, 0X0FH, 0X13H, 0X17H, 0X1BH, 0X1FH, 0X23H) BIT NAME D7 Reserved D6 Reserved D5 AISS_n Register Type Default Value (HW reset) This Register Bit is Not Used R/W X This Register Bit is Not Used R/W X Alarm Indication Signal Alarm Status The alarm indication signal detection is always active regardless if the interrupt generation is disabled. This bit indicates the AIS activity. An interrupt will not occur unless the AISIE is set to "1" in the channel register 0x04h and GIE is set to "1" in the global register 0xE0h. RO 0 RO 0 FUNCTION "0" = No Alarm "1" = An all ones signal is detected D4 DMOS_n Driver Monitor Output Alarm Status The Driver Monitor output is always active regardless if the interrupt generation is disabled. This bit indicates the DMO activity. An interrupt will not occur unless the DMOIE is set to "1" in the channel register 0x04h and GIE is set to "1" in the global register 0xE0h. "0" = No Alarm "1" = Transmit output driver has failures 39 XRT83SL28 8-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT xr REV. 1.0.0 CHANNEL CONTROL REGISTER (0X07H, 0X0BH, 0X0FH, 0X13H, 0X17H, 0X1BH, 0X1FH, 0X23H) BIT NAME FUNCTION D3 RLOSS_n Receiver Loss of Signal Alarm Status The receiver loss of signal detection is always active regardless if the interrupt generation is disabled. This bit indicates the RLOS activity. An interrupt will not occur unless the RLOSIE is set to "1" in the channel register 0x04h and GIE is set to "1" in the global register 0xE0h. Register Type Default Value (HW reset) RO 0 "0" = No Alarm "1" = An RLOS condition is present D2 Reserved This Register Bit is Not Used R/W X D1 Reserved This Register Bit is Not Used R/W X D0 Reserved This Register Bit is Not Used R/W X 40 xr XRT83SL28 8-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT REV. 1.0.0 ELECTRICAL CHARACTERISTICS TABLE 14: ABSOLUTE MAXIMUM RATINGS Storage Temperature -65°C to +150°C Operating Temperature -40°C to +85°C Supply Voltage -0.5V to +3.8V Vin -0.5V to +5.5V TABLE 15: DC DIGITAL INPUT AND OUTPUT ELECTRICAL CHARACTERISTICS VDD=3.3V ±5%, TA=25°C, UNLESS OTHERWISE SPECIFIED PARAMETER SYMBOL MIN TYP MAX UNITS VDD 3.13 3.3 3.46 V Input High Voltage VIH 2.0 - 5.0 V Input Low Voltage VIL -0.5 - 0.8 V Output High Voltage IOH=2.0mA VOH 2.4 - Output Low Voltage IOL=2.0mA VOL - - 0.4 V Input Leakage Current IL - - ±10 µA Input Capacitance CI - 5.0 Output Lead Capacitance CL - - Power Supply Voltage V pF 25 pF NOTE: Input leakage current excludes pins that are internally pulled "Low" or "High". TABLE 16: AC ELECTRICAL CHARACTERISTICS VDD=3.3V ±5%, TA=25°C, UNLESS OTHERWISE SPECIFIED PARAMETER SYMBOL MIN TYP MAX UNITS MCLK Clock Duty Cycle 40 - 60 % MCLK Clock Tolerance - ±50 - ppm TABLE 17: POWER CONSUMPTION VDD=3.3V ±5%, TA=25°C, UNLESS OTHERWISE SPECIFIED TEST CONDITION MODE IMPEDANCE RECEIVER TRANSMITTER TYP MAX UNIT E1 75Ω 1:1 1:2 1.0 1.30 1.1 1.4 W 50% ones 100% ones E1 120Ω 1:1 1:2 0.9 1.2 1.0 1.3 W 50% ones 100% ones E1 75Ω/120Ω 1.1 1.2 0.30 0.4 W Transmitter OFF 41 xr XRT83SL28 8-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT REV. 1.0.0 TABLE 18: RECEIVER ELECTRICAL CHARACTERISTICS VDD=3.3V ±5%, TA=25°C, UNLESS OTHERWISE SPECIFIED PARAMETER MIN TYP MAX UNIT TEST CONDITION - 32 - 15 24 - dB 12.5 - - % ones 9 11 - dB -18 -14 - 13 - kΩ 37 0.2 - - UIp-p - 36 - -0.5 kHz dB ITU-G.736 - 10 1.5 - Hz Hz ITU-G.736 14 20 16 - - dB dB dB ITU-G.703 Receiver Loss of Signal Number of consecutive zeros before RLOS is declared Input signal level at RLOS RLOS clear Receiver Sensitivity (short haul with cable loss) Interference Margin Input Impedance Input Jitter Tolerance 1Hz 10kHz - 100kHz Recovered Clock Jitter Transfer Corner Frequency Peaking Amplitude Jitter Attenuator Corner Frequency JABW = "0" JABW = "1" Return Loss 51kHz - 102kHz 102kHz - 2048kHz 2048kHz - 3072kHz 42 Cable attenuation @ 1024kHz ITU-G.775, ETSI 300 233 With nominal pulse amplitude of 3.0V for 120Ω and 2.37V for 75Ω with 6dB cable loss. ITU-G.823 UIp-p xr XRT83SL28 8-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT REV. 1.0.0 TABLE 19: E1 TRANSMITTER ELECTRICAL CHARACTERISTICS VDD=3.3V ±5%, TA=25°C, UNLESS OTHERWISE SPECIFIED PARAMETER MIN TYP MAX UNIT AMI Output Pulse Amplitude 75Ω 120Ω 2.13 2.70 2.37 3.00 2.60 3.30 V V Output Pulse Width 224 244 264 ns Output Pulse Width Ratio 0.95 - 1.05 ITU-G.703 Output Pulse Amplitude Ratio 0.95 - 1.05 ITU-G.703 - 0.025 0.05 UIp-p 8 8 8 - - dB dB dB Jitter Added by the Transmitter Output Output Return Loss 51kHz - 102kHz 102kHz - 2048kHz 2048kHz - 3072kHz 43 TEST CONDITION 1:2 Transformer Broad Band with jitter free TCLK applied to the input. ETSI 300 166 xr XRT83SL28 8-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT REV. 1.0.0 ORDERING INFORMATION PRODUCT NUMBER PACKAGE OPERATING TEMPERATURE RANGE XRT83SL28IV 144 LEAD TQFP -400C to +850C PACKAGE DIMENSIONS 144 LEAD THIN QUAD FLAT PACK (20 x 20 x 1.4 mm TQFP) rev. 1.00 D D1 108 73 109 72 D1 D 37 144 1 36 A2 e B C A Seating Plane α A1 L Note: The control dimension is the millimeter column SYMBOL INCHES MIN MAX MILLIMETERS MIN MAX A A1 A2 B C D D1 e L α β 0.055 0.063 0.002 0.006 0.053 0.057 0.007 0.011 0.004 0.008 0.858 0.874 0.783 0.791 0.020 BSC 0.018 0.03 7o 0o 0.510 0.490 1.4 1.6 0.05 0.15 1.35 1.45 0.17 0.27 0.20 0.09 21.8 22.2 19.9 20.1 0.50 BSC 0.45 0.75 7o 0o 12.45 12.96 44 xr XRT83SL28 8-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT REV. 1.0.0 REVISION HISTORY REVISION # DATE DESCRIPTION P1.0.0 06/02/03 First release of the 8-Channel LIU Preliminary Datasheet P1.0.1 09/23/03 Updated the Receive Sensitivity in the Electrical Specification. Removed the Copper Slug reference in the package drawing. P1.0.2 08/4/04 Modified definitions of Reset (28) and HW/Host (81) pins. P1.0.3 08/12/04 Edited descriptions in sections 1.2, 1.3,1.4, 1.5, 1.7, 2.4, 2.6 and 2.8 P1.0.4 08/30/04 Made edits to LBM[1:0] pin numbers were reversed, made minor word edits to Clock Data recovery and RLOS sections. Made edits to LB1 and LB0 in table 11, Analog and Remote were reversed P1.0.5 01/28/05 Added Power Consumption Numbers 1.0.0 04/12/05 Added Max power Consumption. Removed Preliminary. NOTICE EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration purposes and may vary depending upon a user’s specific application. While the information in this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies. EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the circumstances. Copyright 2005 EXAR Corporation Datasheet April 2005. Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited. 45