AGILENT HCPL-901J

Agilent HCPL-9000/-0900, -9030/-0930,
HCPL-9031/-0931, -900J/-090J,
HCPL-901J/-091J, -902J/-092J
High Speed Digital Isolators
Data Sheet
Features
• +3.3V and +5V TTL/CMOS
compatible
• 3 ns max. pulse width distortion
• 6 ns max. propagation delay skew
• 15 ns max. propagation delay
Description
The HCPL-90xx and HCPL-09xx
CMOS digital isolators feature
high speed performance and
excellent transient immunity
specifications. The symmetric
magnetic coupling barrier gives
these devices a typical pulse
width distortion of 2 ns, a typical
propagation delay skew of 4 ns
and 100 Mbaud data rate, making
them the industry’s fastest
digital isolators.
The single channel digital isolators (HCPL-9000/-0900) features
an active-low logic output enable.
The dual channel digital isolators
are configured as unidirectional
(HCPL-9030/-0930) and bidirectional (HCPL-9031/-0931),
operating in full duplex mode
making it ideal for digital
fieldbus applications.
The quad channel digital isolators are configured as unidirec-
tional (HCPL-900J/-090J), two
channels in one direction and
two channels in opposite direction (HCPL-901J/-091J), and one
channel in one direction and
three channels in opposite
direction (HCPL-902J/-092J).
These high channel density make
them ideally suited to isolating
data conversion devices, parallel
buses and peripheral interfaces.
They are available in 8-pin PDIP,
8-pin Gull Wing, 8-pin SOIC
packages, and 16–pin SOIC
narrow-body and wide-body
packages. They are specified over
the temperature range of -40° C
to +100° C.
• High speed: 100 MBd
• 15 kV/µs min. common mode
rejection
• Tri-state output
(HCPL-9000/-0900)
• 2500 V RMS isolation
• UL1577 and IEC 61010-1 approved
Applications
• Digital fieldbus isolation
• Multiplexed data transmission
• Computer peripheral interface
• High speed digital systems
• Isolated data interfaces
• Logic level shifting
CAUTION: It is advised that
normal static precautions be
taken in handling and assembly
of this component to prevent
damage and/or degradation,
which may be induced by ESD.
Selection Guide
Device Number
Channel Configuration
Package
HCPL-9000
Single
8-pin DIP (300 Mil)
HCPL-0900
Single
8-pin Small Outline
HCPL-9030
Dual
8-pin DIP (300 Mil)
HCPL-0930
Dual
8-pin Small Outline
HCPL-9031
Dual, Bi-Directional
8-pin DIP (300 Mil)
HCPL-0931
Dual, Bi-Directional
8-pin Small Outline
HCPL-900J
Quad
16-pin Small Outline, Wide Body
HCPL-090J
Quad
16-pin Small Outline, Narrow Body
HCPL-901J
Quad, 2/2, Bi-Directional
16-pin Small Outline, Wide Body
HCPL-091J
Quad, 2/2, Bi-Directional
16-pin Small Outline, Narrow Body
HCPL-902J
Quad, 1/3, Bi-Directional
16-pin Small Outline, Wide Body
HCPL-092J
Quad, 1/3, Bi-Directional
16-pin Small Outline, Narrow Body
Ordering Information
Specify Part Number followed by Option Number (if desired).
Examples:
HCPL-90xx-xxx
xxx:
No option = 300 Mil PDIP-8 package, 50 units per tube.
300 = Gull Wing Surface Mount Option, 50 units per tube.
500 = Tape and Reel Packaging Option, 1000 units per reel.
HCPL-09xx-xxx
xxx:
No option = SO-8 package, 100 units per tube.
500 = Tape and Reel Packaging Option, 1500 units per reel.
HCPL-90xJ-xxx
xxx:
No option = Wide Body SOIC-16 package, 50 units per tube.
500 = Tape and Reel Packaging Option, 1000 units per reel.
HCPL-09xJ-xxx
xxx:
No option = Narrow Body SOIC-16 package, 50 per tube.
500 = Tape and Reel Packaging Option, 1000 units per reel.
2
Functional Diagrams
Symbol
Description
Single Channel
VDD1
Power Supply 1
VDD2
Power Supply 2
INX
Logic Input Signal
OUTX
Logic Output Signal
GND1
Power Supply Ground 1
GND2
Power Supply Ground 2
VOE
Logic Output Enable
(Single Channel), Active Low
NC
Not Connected
VDD1
1
IN1
2
NC
3
GND1
4
Galvanic Isolation
Pin Description
8
VDD2
7
VOE
6
OUT1
5
GND2
Truth Table
IN1
VOE
OUT1
L
L
L
H
L
L
H
H
Z
H
H
Z
HCPL-9000/0900
1
IN1
2
IN2
3
GND1
4
8
VDD2
VDD1
1
7
OUT1
IN1
2
6
OUT2
OUT2
3
5
GND2
GND1
4
HCPL-9030/0930
Galvanic Isolation
VDD1
Galvanic Isolation
Dual Channel
8
VDD2
7
OUT1
6
IN2
5
GND2
HCPL-9031/0931
Quad Channel
VDD2
VDD1
1
16
VDD2
VDD1
1
16
VDD2
GND1
2
15
GND2
GND1
2
15
GND2
GND1
2
15
GND2
IN1
3
14
OUT1
IN1
3
14
OUT1
IN1
3
14
OUT1
IN2
4
13
OUT2
IN2
4
13
OUT2
IN2
4
13
OUT2
IN3
5
12
OUT3
OUT3
5
12
IN3
IN3
5
12
OUT3
IN4
6
11
OUT4
OUT4
6
11
IN4
OUT4
6
11
IN4
NC
7
10
NC
NC
7
10
NC
NC
7
10
NC
GND1
8
9
GND2
GND1
8
9
GND2
GND1
8
9
GND2
HCPL-900J/-090J
3
HCPL-901J/-091J
Galvanic Isolation
16
Galvanic Isolation
1
Galvanic Isolation
VDD1
HCPL-902J/-092J
Package Outline Drawings
HCPL-9000, HCPL-9030 and HCPL-9031 Standard DIP Packages
8
7
6
5
0.240 (6.096)
0.260 (6.604)
1
2
3
4
0.370 (9.398)
0.400 (10.160)
0.55 (1.397)
0.65 (1.651)
0.290 (7.366)
0.310 (7.874)
0.120 (3.048)
0.150 (3.810)
0.008 (0.203)
0.015 (0.381)
0.015 (0.381)
0.035 (0.889)
0.030 (0.762)
0.045 (1.143)
0.015 (0.380)
0.023 (0.584)
3°
8°
0.300 (7.620)
0.370 (9.398)
0.090 (2.286)
0.110 (2.794)
0.045 (1.143)
0.065 (1.651)
DIMENSIONS: INCHES (MILLIMETERS) MIN
MAX
HCPL-9000, HCPL-9030 and HCPL-9031 Gull Wing Surface Mount Option 300
PAD LOCATION (for reference only)
0.040 (1.016)
0.047 (1.194)
0.370 (9.400)
0.390 (9.900)
8
7
6
5
0.190 TYP.
(4.826)
0.240 (6.100)
0.260 (6.600)
1
2
3
0.370 (9.398)
0.390 (9.906)
4
0.047 (1.194)
0.070 (1.778)
0.045 (1.143)
0.065 (1.651)
0.030 (0.762)
0.045 (1.143)
0.370 (9.400)
0.390 (9.900)
0.290 (7.370)
0.310 (7.870)
0.008 (0.203)
0.013 (0.330)
0.120 (3.048)
0.150 (3.810)
0.030 (0.760)
0.056 (1.400)
0.015 (0.385)
0.035 (0.885)
0.100
(2.540)
BSC
0.025 (0.632)
0.035 (0.892)
MIN
MAX
LEAD COPLANARITY = 0.004 INCHES (0.10 mm)
DIMENSIONS INCHES (MILLIMETERS)
4
0.015 (0.381)
0.025 (0.635)
12° NOM.
HCPL-0900, HCPL-0930 and HCPL-0931 Small Outline SO-8 Package
0.189 (4.80)
0.197 (5.00)
8
7
6
5
0.228 (5.80)
0.244 (6.20)
0.150 (3.80)
0.157 (4.00)
1
2
3
4
0.013 (0.33)
0.020 (0.51)
0.010 (0.25)
0.020 (0.50)
x 45°
0.008 (0.19)
0.010 (0.25)
0.004 (0.10)
0.010 (0.25)
0.054 (1.37)
0.069 (1.75)
0°
8°
0.040 (1.016)
0.060 (1.524)
0.016 (0.40)
0.050 (1.27)
DIMENSIONS: INCHES (MILLIMETERS) MIN
MAX
HCPL-900J, HCPL-901J and HCPL-902J Wide Body SOIC-16 Package
0.397 (10.084)
0.413 (10.490)
8
Pin 1 indent
1
0.394 (10.007)
0.419 (10.643)
0.291 (7.391)
0.299 (7.595)
0.013 (0.330)
0.020 (0.508)
7° TYP
0.092 (2.337)
0.104 (2.642)
0.287 (7.290)
0.297 (7.544)
7° TYP
0.080 (2.032)
0.100 (2.54)
0° – 8° TYP
0.040 (1.016)
0.060 (1.524)
DIMENSIONS: INCHES (MILLIMETERS) MIN
MAX
5
0.010 (0.254)
x 45°
0.020 (0.508)
0.004 (0.1016)
0.011 (0.279)
0.009 (0.229)
0.012 (0.305)
0.016 (0.40)
0.050 (1.27)
HCPL-090J, HCPL-091J and HCPL-092J Narrow Body SOIC-16 Package
0.386 (9.802)
0.394 (9.999)
8
Pin 1 indent
1
0.228 (5.791)
0.244 (6.197)
0.152 (3.861)
0.157 (3.988)
0.013 (0.330)
0.020 (0.508)
0.054 (1.372)
0.068 (1.727)
0.010 (0.245)
x 45°
0.020 (0.508)
0.008 (0.191)
0.010 (0.249)
0.050 (1.270)
0.060 (1.524)
0° – 8° TYP
0.040 (1.016)
0.060 (1.524)
0.016 (0.406)
0.050 (1.270)
0.004 (0.102)
0.010 (0.249)
DIMENSIONS: INCHES (MILLIMETERS) MIN
MAX
Package Characteristics
Parameter
Capacitance (Input-Output)
Single Channel
Dual Channel
Quad Channel
Symbol
[1]
Min.
Typ.
Max.
CI-O
Units
Test Conditions
pF
f = 1 MHz
°C/W
Thermocouple located at
center underside of package
1.1
2.0
4.0
Thermal Resistance
8-Pin PDIP
8-Pin SOIC
θJCT
Package Power Dissipation
8-Pin PDIP
8-Pin SOIC
PPD
150
240
mW
150
150
Notes:
1. Single and dual channels device are considered two-terminal devices: pins 1-4 shorted and pins 5-8 shorted. Quad channel devices are considered
two-terminal devices: pins 1-8 shorted and pins 9-16 shorted.
This product has been tested for electrostatic sensitivity to the limits stated in the specifications. However, Agilent recommends that all integrated circuits
be handled with appropriate care to avoid damage. Damage caused by inappropriate handling or storage could range from performance degradation to
complete failure.
6
Insulation and Safety Related Specifications
Parameters
Condition
Min.
Typ.
Max.
Units
Ω||pF
Barrier Impedance
>1014 ||3
>1014 ||3
>1014 ||7
Single Channel
Dual Channel
Quad Channel
Creepage Distance (External)
mm
8-Pin PDIP
8-Pin SOIC
16-Pin SOIC Narrow Body
16-Pin SOIC Wide Body
Leakage Current
7.036
4.026
4.026
8.077
µA
0.2
240 VRMS
60 Hz
Absolute Maximum Ratings
Parameters
Symbol
Min.
Max.
Units
TS
–55
175
°C
TA
–55
125
°C
Supply Voltage
VDD1, VDD2
–0.5
7
V
Input Voltage
VIN
–0.5
VDD1 +0.5
V
Voltage Output Enable (HCPL-9000/-0900)
VOE
–0.5
VDD2 +0.5
V
Output Voltage
VOUT
–0.5
VDD2 +0.5
V
Output Current Drive
IOUT
10
mA
260
°C
Storage Temperature
Ambient Operating
Temperature [1]
Lead Solder Temperature (10s)
ESD
2 kV Human Body Model
Notes:
1. Absolute Maximum ambient operating temperature means the device will not be damaged if operated under these conditions. It does not
guarantee performance.
Recommended Operating Conditions
Parameters
Symbol
Min.
Max.
Units
Ambient Operating Temperature
TA
–40
100
°C
Supply Voltage
VDD1, VDD2
3.0
5.5
V
Logic High Input Voltage
VIH
2.4
VDD1
V
Logic Low Input Voltage
VIL
0
0.8
V
Input Signal Rise and Fall Times
tIR, tIF
1
µs
This product has been tested for electrostatic sensitivity to the limits stated in the specifications. However, Agilent recommends that all integrated circuits
be handled with appropriate care to avoid damage. Damage caused by inappropriate handling or storage could range from performance degradation to
complete failure.
7
Electrical Specifications
Test conditions that are not specified can be anywhere within the recommended operating range.
All typical specifications are at TA=+25°C, VDD1 = VDD2 = +3.3 V.
Parameter
Symbol
Quiescent Supply Current 1
IDD1
Min.
HCPL-9000/-0900
HCPL-9030/-0930
HCPL-9031/-0931
HCPL-900J/-090J
HCPL-901J/-091J
HCPL-902J/-092J
Quiescent Supply Current 2
Max.
0.008
0.008
1.5
0.016
3.3
1.5
0.01
0.01
2.0
0.02
4.0
2.0
3.3
3.3
1.5
5.5
3.3
3.0
4.0
4.0
2.0
8.0
4.0
6.0
IDD2
HCPL-9000/-0900
HCPL-9030/-0930
HCPL-9031/-0931
HCPL-900J/-090J
HCPL-901J/-091J
HCPL-902J/-092J
Logic Input Current
IIN
Logic High Output Voltage
VOH
-10
VDD2 – 0.1
0.8 * VDD2
Logic Low Output Voltage
Typ.
VOL
10
VDD2
VDD2 – 0.5
Units Test Conditions
mA
VIN = 0V
mA
VIN = 0V
µA
V
IOUT = -20 µA, VIN = VIH
V
IOUT = -4 mA, VIN = VIH
0
0.1
V
IOUT = 20 µA, VIN = VIL
0.5
0.8
V
IOUT = 4 mA, VIN = VIL
MBd
CL = 15 pF
Switching Specifications
Maximum Data Rate
100
110
Clock Frequency
fmax
50
MHz
Propagation Delay Time to Logic
Low Output
tPHL
12
18
ns
Propagation Delay Time toLogic
High Output
tPLH
12
18
ns
Pulse Width
tPW
Pulse Width Distortion [1]
|PWD|
2
3
ns
Propagation Delay Skew [2]
tPSK
4
6
ns
Output Rise Time (10 – 90%)
tR
2
4
ns
Output Fall Time (10 – 90%)
tF
2
4
ns
3
5
ns
tPLZ
3
5
ns
10
ns
|tPHL – tPLH|
Propagation Delay Enable to Output (Single Channel)
High to High Impedance
tPHZ
Low to High Impedance
High Impedance to High
tPZH
3
5
ns
High Impedance to Low
tPZL
3
5
ns
Channel-to-Channel Skew
(Dual and Quad Channels)
tCSK
2
3
ns
Common Mode Transient Immunity
(Output Logic High or Logic Low) [3]
|CMH|
|CML|
15
18
kV/µs
Vcm = 1000V
Notes:
1. PWD is defined as |tPHL -tPLH|. %PWD is equal to the PWD divided by the pulse width.
2. tPSK is equal to the magnitude of the worst case difference in tPHL and/or tPLH that will be seen between units at 25°C.
3. CMH is the maximum common mode voltage slew rate that can be sustained while maintaining VOUT > 0.8VDD2. CML is the maximum common mode
input voltage that can be sustained while maintaining VOUT < 0.8V. The common mode voltage slew rates apply to both rising and falling common mode
voltage edges.
This product has been tested for electrostatic sensitivity to the limits stated in the specifications. However, Agilent recommends that all integrated circuits
be handled with appropriate care to avoid damage. Damage caused by inappropriate handling or storage could range from performance degradation to
complete failure.
8
Electrical Specifications
Test conditions that are not specified can be anywhere within the recommended operating range.
All typical specifications are at TA=+25°C, VDD1 = VDD2 = +5.0 V.
Parameter
Symbol
Quiescent Supply Current 1
IDD1
Min.
HCPL-9000/-0900
HCPL-9030/-0930
HCPL-9031/-0931
HCPL-900J/-090J
HCPL-901J/-091J
HCPL-902J/-092J
Quiescent Supply Current 2
Max.
0.012
0.012
2.5
0.024
5.0
2.5
0.018
0.018
3.0
0.036
6.0
3.0
5.0
5.0
2.5
8.0
5.0
6.0
6.0
6.0
3.0
12.0
6.0
9.0
IDD2
HCPL-9000/-0900
HCPL-9030/-0930
HCPL-9031/-0931
HCPL-900J/-090J
HCPL-901J/-091J
HCPL-902J/-092J
Logic Input Current
IIN
Logic High Output Voltage
VOH
-10
VDD2 – 0.1
0.8 * VDD2
Logic Low Output Voltage
Typ.
VOL
10
VDD2
VDD2 – 0.5
Units Test Conditions
mA
VIN = 0V
mA
VIN = 0V
µA
V
IOUT = -20 µA, VIN = VIH
V
IOUT = -4 mA, VIN = VIH
0
0.1
V
IOUT = 20 µA, VIN = VIL
0.5
0.8
V
IOUT = 4 mA, VIN = VIL
MBd
CL = 15 pF
Switching Specifications
Maximum Data Rate
100
Clock Frequency
fmax
Propagation Delay Time to Logic
Low Output
tPHL
Propagation Delay Time to Logic
High Output
tPLH
110
50
MHz
10
15
ns
10
15
ns
Pulse Width
tPW
Pulse Width Distortion [1]
|tPHL – tPLH|
|PWD|
10
2
3
ns
Propagation Delay Skew [2]
tPSK
4
6
ns
Output Rise Time (10 – 90%)
tR
1
3
ns
Output Fall Time (10 – 90%)
tF
1
3
ns
3
5
ns
Propagation Delay Enable to Output (Single Channel)
High to High Impedance
tPHZ
ns
Low to High Impedance
tPLZ
3
5
ns
High Impedance to High
tPZH
3
5
ns
High Impedance to Low
tPZL
3
5
ns
Channel-to-Channel Skew
(Dual and Quad Channels)
tCSK
2
3
ns
Common Mode Transient Immunity
(Output Logic High or Logic Low) [3]
|CMH|
|CML|
15
18
kV/µs
Vcm = 1000V
Notes:
1. PWD is defined as |tPHL -tPLH|. %PWD is equal to the PWD divided by the pulse width.
2. tPSK is equal to the magnitude of the worst case difference in tPHL and/or tPLH that will be seen between units at 25°C.
3. CMH is the maximum common mode voltage slew rate that can be sustained while maintaining VOUT > 0.8VDD2. CML is the maximum common mode
input voltage that can be sustained while maintaining VOUT < 0.8V. The common mode voltage slew rates apply to both rising and falling common mode
voltage edges.
This product has been tested for electrostatic sensitivity to the limits stated in the specifications. However, Agilent recommends that all integrated circuits
be handled with appropriate care to avoid damage. Damage caused by inappropriate handling or storage could range from performance degradation to
complete failure.
9
Applications Information
Power Consumption
The HCPL-90xx and HCPL-09xx
CMOS digital isolators achieves
low power consumption from the
manner by which they transmit
data across isolation barrier. By
detecting the edge transitions of
the input logic signal and converting this to a narrow current
pulse, which drives the isolation
barrier, the isolator then latches
the input logic state in the output
latch. Since the current pulses
are narrow, about 2.5 ns wide, the
power consumption is independent of mark-to-space ratio and
solely dependent on frequency.
The approximate power supply
current per channel is:
I(Input) = 40(f/fmax)(1/4) mA
where f = operating frequency,
fmax = 50 MHz.
VDD1
VDD2
C2
NC 3
HCPL-9000
or
HCPL-0900
2
GND1
to be connected directly to the
inputs and outputs. As shown in
Figure 1, the only external
components required for proper
operation are two 47 nF ceramic
capacitors for decoupling the
power supplies. For each capacitor, the total lead length between
both ends of the capacitor and the
power-supply pins should not
exceed 20 mm. Figure 2 illustrates
the recommended printed circuit
board layout for the HCPL-9000
or HCPL-0900. For data rates in
excess of 10MBd, use of ground
planes for both GND1 and GND2 is
highly recommended.
Bypassing and PC Board Layout
The HCPL-90xx and HCPL-09xx
digital isolators are extremely
easy to use. No external interface
circuitry is required because the
isolators use high-speed CMOS IC
technology allowing CMOS logic
8
1
C1
IN1
Signal Status on Start-up and
Shut Down
To minimize power dissipation,
the input signals to the channels
of HCPL-90xx and HCPL-09xx
digital isolators are differentiated and then latched on the
output side of the isolation
barrier to reconstruct the signal.
This could result in an ambiguous output state depending on
power up, shutdown and power
loss sequencing. Therefore, the
designer should consider the
inclusion of an initialization
signal in this start-up circuit.
4
7
VOE
OUT1
6
5
GND2
Note: C1, C2 = 47 nF ceramic capacitors
Figure 1. Functional Diagram of Single Channel HCPL-0900 or HCPL-0900.
VDD1
VDD2
C1
HCPL-9000
or
HCPL-0900
IN1
GND1
Figure 2. Recommended Printed Circuit Board Layout.
10
VOE
C2
OUT1
GND2
Propagation Delay, Pulse Width
Distortion and Propagation Delay Skew
Propagation Delay is a figure of
merit, which describes how
quickly a logic signal propagates
through a system as illustrated in
Figure 3.
The propagation delay from low to
high, tPLH , is the amount of time
required for an input signal to
propagate to the output, causing
the output to change from low to
high. Similarly, the propagation
delay from high to low, tPHL, is the
amount of time required for the
input signal to propagate to the
output, causing the output to
change from high to low.
Pulse Width Distortion, PWD, is
the difference between tPHL and
tPLH and often determines the
maximum data rate capability of
a transmission system. PWD can
be expressed in percent by
dividing the PWD (in ns) by the
minimum pulse width (in ns)
being transmitted. Typically, PWD
on the order of 20 – 30% of the
minimum pulse width is tolerable.
Propagation Delay Skew, tPSK,
and Channel-to-Channel Skew,
tCSK, are critical parameters to
consider in parallel data transmission applications where
synchronization of signals on
parallel data lines is a concern.
5 V CMOS
INPUT
VIN
50%
0V
tPLH
OUTPUT
VOUT
tPHL
90%
90%
10%
10%
VOH
2.5 V CMOS
VOL
50%
DATA
INPUTS
VOUT
2.5 V
CMOS
CLOCK
tPSK
DATA
VIN
50%
OUTPUTS
tPSK
CLOCK
tPSK
VOUT
2.5 V
CMOS
Figure 5. Parallel Data Transmission.
Figure 4. Timing Diagrams to Illustrate
Propagation Delay Skew.
11
tPSK is defined as the difference
between the minimum and
maximum propagation delays,
either tPLH or tPHL, among two or
more devices which are operating
under the same conditions (i.e.,
the same drive current, supply
voltage, output load, and operating temperature). tCSK is defined
as the difference between the
minimum and maximum propagation delays, either tPLH or tPHL,
among two or more channels
within a single device (applicable
to dual and quad channel devices) which are operating under
the same conditions.
As illustrated in Figure 4, if the
inputs of two or more devices are
switched either ON or OFF at the
same time, tPSK is the difference
between the minimum propagation delay, either tPLH or tPHL, and
the maximum propagation delay,
either tPLH or tPHL.
Figure 3. Timing Diagrams to Illustrate Propagation Delay, tPLH and tPHL.
VIN
If the parallel data is being sent
through channels of the digital
isolators, differences in propagation delays will cause the data to
arrive at the outputs of the
digital isolators at different
times. If this difference in
propagation delay is large
enough, it will limit the maximum transmission rate at which
parallel data can be sent through
the digital isolators.
As mentioned earlier, tPSK, can
determine the maximum parallel
data transmission rate. Figure 5
shows the timing diagram of a
typical parallel data transmission
application with both the clock
and data lines being sent through
the digital isolators. The figure
shows data and clock signals at
the inputs and outputs of the
digital isolators. In this case, the
data is clocked off the rising edge
of the clock.
Propagation delay skew represents the uncertainty of where
an edge might be after being sent
through a digital isolator. Figure
5 shows that there will be uncertainty in both the data and clock
lines. It is important that these
two areas of uncertainty not
overlap, otherwise the clock
signal might arrive before all of
the data outputs have settled, or
some of the data outputs may
start to change before the clock
signal has arrived. From these
considerations, the absolute
minimum pulse width that can be
sent through digital isolators in a
parallel application is twice tPSK.
A cautious design should use a
slightly longer pulse width to
ensure that any additional
uncertainty in the rest of the
circuit does not cause a problem.
Figure 6 shows the minimum
pulse width, rise and fall time,
and propagation delay enable to
output waveforms for HCPL-9000
or HCPL-0900.
50%
VIN
90%
tPZL
90%
tPLZ
50%
VOUT
tPZH
10%
tPW
tPHZ
10%
tF
tR
VOE
tPW
tPLZ
tPZH
Minimum Pulse Width
Propagation Delay, Low to High Impedance
Propagation Delay, High Impedance to High
tPHZ
tPZL
tR
tF
Propagation Delay, High to High Impedance
Propagation Delay, High Impedance to Low
Rise Time
Fall Time
Figure 6. Timing Diagrams to Illustrate the Minimum Pulse Width, Rise and Fall Time, and Propagation Delay Enable to
Output Waveforms for HCPL-9000 or HCPL-0900.
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Data subject to change.
Copyright © 2002 Agilent Technologies, Inc.
October 31, 2002
5988-5626EN
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