Low Cost, Industry Standard FDDI MIC Transceivers Technical Data HFBR-5111 (2x11) HFBR-5112 (Narrow 1x13) HFBR-5113 (Standard 1x13) Features • Full Compliance with the FDDI PMD Standard • Full Compliance with the Optical Performance Requirements of the ATM 100 Mbps Physical Layer • Full Compliance with the Optical Performance Requirements of the Fast Ethernet Physical Layer • Multisourced Package Style with: - 2x11 or 1x13 Pin Configuration - MIC Receptacle - Field Changeable Keying • Wave Solder and Aqueous Wash Process Compatible Package • Internal Shielding for Low EMI Emissions and High EMI Immunity • Single +5V Power Supply • Shifted ECL Logic Interface Directly Compatible with FDDI PHY Circuits • Manufactured in an ISO 9001 Certified Facility • Point-to-Point Data Communications • Replaces DLX2012-FD and DLX2020-FD Model Transceivers Description The HFBR-511X family of transceivers from Hewlett-Packard consists of high performance, cost effective modules for optical data communication applications at the 100 Mbps/125 MBd rate. The transceivers feature full compliance with the Fiber Distributed Data Interface (FDDI) Physical Media Dependent (PMD) standard. This standard has been approved as an International Standard, ISO/IEC 9314-3, and an American National Standard, ANSI X3.166 - 1990. The HFBR5111 represents the 2x11 package style. The “2x11” denotes two rows of eleven pins. The HFBR-5112 and HFBR-5113 represent the Narrow and Standard 1x13 package styles, respectively. The “1x13” denotes one row of thirteen pins. Applications • FDDI Concentrators, Bridges, Routers, and Network Interface Cards • 100 Mbps ATM Interfaces • Fast Ethernet Interfaces 92 The modules are designed for 50 or 62.5 µm core multimode optical fiber and operate at a nominal wavelength of 1300 nm. Each transceiver incorporates our high-performance, reliable, long-wavelength optical devices and proven circuit technology to give long life and consistent performance. The transceivers are optimized for 125 MBd operation but can be used over a wide range of signal rates. The transceivers are guaranteed to meet FDDI PMD specifications when used within the operating conditions specified in this document. These HFBR-511X Series transceivers are also useful for both ATM 100 Mbps interfaces and Fast Ethernet 100 Base-FX interfaces. The ATM Forum UserNetwork Interface (UNI) Standard, Version 3.0, defines the Physical Layer for 100 Mbps Multimode Fiber Interface for ATM in Section 2.3 to be the 5964-9019E (2/96) FDDI PMD standard. Likewise, the Fast Ethernet Alliance defines the Physical Layer for the 100 Base-FX Version of IEEE 802.3u to be the FDDI PMD standard. Hewlett-Packard also provides several other FDDI products compliant with the FDDI Low Cost Fiber (LCF) -PMD and Single Mode (SM) -PMD standards. These products are available with ST, SC, and FC connector styles. They are available in the 1x9 transceiver and 14- and 16-pin transmitter/ receiver package styles for those designs that require these alternate configurations. Contact your Hewlett-Packard sales representative for information on these alternative FDDI products. Transmitter Section The transmitter section of the HFBR-511X Series utilizes a 1300 nm surface emitting InGaAsP LED. The LED is packaged in the optical subassembly portion of the transmitter section. It is dccoupled to a custom IC which converts differential-input, PECL logic signals, ECL referenced (shifted) to a +5 V power supply, into an analog LED drive current. The PIN/preamplifier combination is ac-coupled to a custom quantizer IC which provides the final pulse shaping for the logic output and the Signal Detect function. Both the Data and Signal Detect outputs are Package The overall package concept for the HP transceiver consists of the following basic elements: two optical subassemblies, an electrical subassembly, and the housing with full compliance to the FDDI PMD standard. A block diagram is illustrated in Figure 1. The package outline drawings and pin-outs are shown in Figures 2 and 3. These are compliant with the industry standard 2x11 and 1x13 pin configurations. The optical subassemblies utilize a high-volume assembly process together with low-cost lens elements which result in a costeffective building block. The electrical subassemblies consist of a high-volume, multilayer printed circuit board on which the IC chips and various surface-mounted passive circuit elements are attached. Each transceiver package includes internal shields for the electrical and optical subassemblies to ensure low EMI emissions and high immunity to external EMI fields. The outer housings including the MIC receptacles are molded of filled non-conductive plastic to provide mechanical strength and electrical isolation. The solder posts of each package design are isolated from the circuit design of the transceiver and do not require connection to a ground plane on the circuit board. Each transceiver is attached to its printed circuit boards with the 2x11 or 1x13 signal pins and the solder posts which exit the bottom of the housing. The solder posts provide the primary mechanical strength to withstand the loads imposed on the transceiver when mating with MIC-connectored fiber cables. Application Information The Applications Engineering group of the Optical Communication Division is available to assist you with the technical under ELECTRICAL SUBASSEMBLY DIFFERENTIAL DATA OUT DIFFERENTIAL SIGNAL DETECT OUT PIN PHOTODIODE QUANTIZER IC DIFFERENTIAL DATA IN PREAMP IC OPTICAL SUBASSEMBLIES LED DRIVER IC MEDIA INTERFACE CONNECTOR RECEPTACLE Receiver Section The receiver section of the HFBR-511X Series utilizes an InGaAs PIN photodiode coupled to a custom silicon transimpedance preamplifier IC. They are packaged in the optical subassembly portion of the receiver. differential. Also, both Data and Signal Detect outputs are PECL compatible, ECL referenced (shifted) to a +5 V power supply. TOP VIEW Figure 1. HFBR-5111/-5112/-5113 Block Diagram. 93 4X 1.52 1.22 X 0.050 0.060 1.91 MAX. 0.075 34.34 1.352 4X ø 30.48 1.200 22X ø 3.80 2X ø 0.150 2.54 0.100 1.50 SOLDER POSTS 0.060 0.48 LEADS 0.019 5.08 0.200 H 81.32 3.202 63.5 2.500 45.72 44.45 1.800 1.750 OPTICAL REFERENCE PLANE 35.56 1.400 40.64 1.600 2.54 TYP. 0.100 2.95 0.116 PART NUMBER DATE CODE COUNTRY OF ORIGIN 82.5 MAX. 3.248 78.87 3.105 LATCH POINTS ACCEPTS SELF TAPPING 2X – M2X0.4 SCREW FOR OPTIONAL MOUNTING 2X 1.52 SQ. 0.060 2.95 0.116 16.00 MAX. 0.630 PLUG – REF. 35.80 MAX. 1.409 FDDI KEY LOCATION 0.85 0.034 33.02 MAX. 1.300 11.87 MAX. 0.467 NOTES: 1. ALL DIMENSIONS ARE MILLIMETERS OVER INCHES. 2. ALL DIMENSIONS ARE NOMINAL UNLESS OTHERWISE SPECIFIED. 3. THE LEADS ARE TIN-LEAD PLATED PHOSPHOR BRONZE. 4. THE POSTS ARE TIN-LEAD PLATED BRASS. 5. THE HOUSING IS GLASS FIBER FILLED BLACK POLYETHERIMIDE. 6. THE MODULE IS SHOWN WITHOUT THE FIELD KEY INSTALLED. 9.40 MAX. 0.370 Figure 2(a). HFBR-5111 Outline Drawing. 34.46 (1.357) 30.48 (1.200) 29.00 (1.142) 2.54 TYP. (0.100) 13X ∅ 0.48 LEADS (0.019) 2X ∅ 1.00 (0.039) 2X ∅ 1.52 SOLDER POSTS (0.060) 24.86 (0.979) 9.14 (0.360) 5.79 (0.228) 2.95 (0.116) 22.86 (0.900) 19.99 (0.787) OPTICAL REFERENCE PLANE 39.94 (1.533) LATCH POINTS 41.30 (1.626) H PART NUMBER DATE CODE COUNTRY OF ORIGIN 66.16 (2.605)MAX. 2X ∅ 3.00 (0.118) 3.68 (0.145) 16.00 MAX. (0.630) PLUG – REF. 33.02 (1.300)MAX. 0.80 (0.031) 11.87 MAX. (0.467) Figure 2(b). HFBR-5112 Outline Drawing. 94 9.40 MAX. (0.370) 35.80 MAX. (1.409) FDDI KEY LOCATION 38.10 (1.500) 13X ∅ 0.48 LEADS (0.019) 34.46 (1.357) 30.48 (1.200) 2X ∅ 1.00 (0.039) 29.00 (1.142) 2.54 TYP. (0.100) 17.24 (0.679) 12.37 (0.487) 4X ∅ 2.00 SOLDER POSTS (0.079) 15.24 (0.600) 13.41 16.76 (0.528) OPTICAL (0.660) REFERENCE PLANE 43.80 MAX. (1.724) 2.95 (0.116) 15.24 (0.600) 46.56 (1.833) LATCH POINTS 48.92 (1.926) H PART NUMBER DATE CODE COUNTRY OF ORIGIN 66.16 (2.605)MAX. 4X R 2.80 (0.110) 2X ∅ 3.00 (0.118) 4.50 (0.177) 16.00 MAX. (0.630) FDDI KEY LOCATION 0.80 (0.031) 33.02 (1.300)MAX. PLUG – REF. 35.80 MAX. (1.409) NOTES: 1. ALL DIMENSIONS ARE MILLIMETERS OVER (INCHES). 2. ALL DIMENSIONS ARE NOMINAL UNLESS OTHERWISE SPECIFIED. 3. THE LEADS ARE TIN-LEAD PLATED PHOSPHOR BRONZE. 4. THE POSTS ARE TIN-LEAD PLATED BRASS. 5. THE HOUSING IS GLASS FIBER FILLED BLACK POLYETHERIMIDE. 6. THE MODULE IS SHOWN WITHOUT THE FIELD KEY INSTALLED. 11.87 MAX. (0.467) 9.40 MAX. (0.370) Figure 2(c). HFBR-5113 Outline Drawing. TOP VIEW 13 GND 1 22 GND NC VCC VCC GND 2 3 4 5 20 VCC 19 VCC 18 VCC GND 6 17 GND SD 7 SD 8 16 GND 15 GND VCC 9 21 VCC DATA OUT 10 14 VBB 13 DATA IN DATA OUT 11 12 DATA IN (a) HFBR-5111 TOP VIEW 1 GND VB DATA IN DATA IN TX VCC GND GND RX VCC SD SD DATA OUT DATA OUT GND (b) HFBR-5112/-5113 Figure 3. Pin Assignments. 95 12 62.5/125 µm 10 8 6 4 50/125 µm 2 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 FIBER OPTIC CABLE LENGTH – km Figure 4. Optical Power Budget at BOL vs. Fiber Optic Cable Length. standing and design trade-offs associated with this transceiver. You can contact them through your Hewlett-Packard sales representative. The following information is provided to answer some of the most common questions about the use of these parts. Transceiver Optical Power Budget versus Link Length The Optical Power Budget (OPB) is the available optical power for a fiber-optic link to accommodate fiber cable losses plus losses due to in-line connectors, splices, optical switches, and to provide margin for link aging and unplanned losses due to cable plant reconfiguration or repair. Figure 4 illustrates the predicted OPB associated with the transceivers specified in this data sheet at the Beginning of Life (BOL). This curve represents the attenuation and chromatic plus modal dispersion losses associated with the 62.5/125 µm and 50/125 µm fiber cables only. The area under the curve represents the remaining OPB at any link length, which is available for overcoming non-fiber cable related losses. 96 Hewlett-Packard LED technology has produced 1300 nm LED devices with lower aging characteristics than normally associated with these technologies in the industry. The industry convention is 1.5 dB aging for 1300 nm LEDs, however HP 1300 nm LEDs will experience less than 1 dB of aging over normal commercial equipment mission life periods. Contact your HewlettPackard sales representative for additional details. Figure 4 was generated with a Hewlett-Packard fiber-optic link model containing the current industry conventions for fiber cable specifications and the FDDI PMD optical parameters. These parameters are reflected in the guaranteed performance of the transceiver specifications in this data sheet. This same model has been used extensively in the ANSI and IEEE committees, including the ANSI X3T9.5 committee, to establish the optical performance requirements for various fiberoptic interface standards. The cable parameters used come from the ISO/IEC JTC1/SC 25/WG3 Generic Cabling for Customer Premises per DIS 11801 document and the EIA/TIA-568-A Commercial Building Telecommunications Cabling Standard per SP-2840. Transceiver Signaling Operating Rate Range and BER Performance For purposes of definition, the symbol rate (Baud), also called signaling rate, is the reciprocal of the symbol time. Data rate (bits/ sec) is the symbol rate divided by the encoding factor used to encode the data (symbols/bit). When used in FDDI 100 Mbps applications, the performance of the 1300 nm transceivers is guaranteed over the signaling rate of 10 MBd to 125 MBd to the full conditions listed in the individual product specification tables. The transceivers may be used for other applications at signaling rates outside of the 10 MBd to 125 MBd range with some penalty in the link optical power budget primarily caused by a reduction of receiver sensitivity. Figure 5 gives an indication of the typical performance of these 1300 nm products at different rates. These transceivers can also be used for applications which require different bit error rate (BER) performance. Figure 6 illustrates the typical trade-off between link BER and the receiver’s input optical power level. TRANSCEIVER RELATIVE OPTICAL POWER BUDGET AT CONSTANT BER – dB OPB – OPTICAL POWER BUDGET – dB 14 3.0 2.5 2.0 1.5 1.0 0.5 0 0 25 50 75 100 125 150 175 200 SIGNAL RATE (MBd) CONDITIONS: 1. PRBS 27-1 2. DATA SAMPLED AT CENTER OF DATA SYMBOL. 3. BER = 10-6 4. TA = 25° C 5. VCC = 5 Vdc 6. INPUT OPTICAL RISE/FALL TIMES = 1.0/2.1 ns. Figure 5. Transceiver Relative Optical Power Budget at Constant BER vs. Signaling Rate. 1 x 10-2 BIT ERROR RATE 1 x 10-3 E1 of Annex E. They represent the worst-case jitter contribution that the transceivers are allowed to make to the overall system jitter without violating the Annex E allocation example. In practice, the typical contribution of the HP transceiver is well below the maximum amount. CENTER OF SYMBOL 1 x 10-4 1 x 10-5 1 x 10-6 1 x 10-7 1 x 10-8 2.5 x 10-10 1 x 10-11 1 x 10-12 -6 -4 -2 0 2 4 RELATIVE INPUT OPTICAL POWER – dB CONDITIONS: 1. 125 MBd 2. PRBS 27-1 3. CENTER OF SYMBOL SAMPLING. 4. TA = 25° C 5. VCC = 5 Vdc 6. INPUT OPTICAL RISE/FALL TIMES = 1.0/2.1 ns. Figure 6. Bit Error Rate vs. Relative Receiver Input Optical Power. Transceiver Jitter Performance The Hewlett-Packard 1300 nm transceivers are designed to operate per the system jitter allocations stated in Table E1 of Annex E of the FDDI PMD standard. The HP 1300 nm transmitters will tolerate the worst-case input electrical jitter allowed in the table without violating the worstcase output optical jitter requirement of Sections 8.1 Active Output Interface of the FDDI PMD standard. The HP 1300 nm receivers will tolerate the worst-case input optical jitter allowed in Section 8.2 Active Input Interface of the FDDI PMD standard without violating the worst-case output electrical jitter allowed in the Table E1 of the Annex E. The jitter specifications stated in the following 1300 nm transceiver specification table are derived from the values in Table Recommended Handling Precautions It is advised that normal static precautions be taken in the handling and assembly of these transceivers to prevent damage which may be induced by electrostatic discharge (ESD). The HFBR-511X Series meets MIL-STD-883C Method 3015.4 Class 2. Care should be taken to avoid shorting the receiver Data or Signal Detect outputs directly to ground without proper currentlimiting impedance. Solder and Wash Process Compatibility Each transceiver is delivered with a protective port plug inserted into the MIC receptacle. This port process plug protects the optical subassembly during wave solder and aqueous wash processing and acts as a dust cover during shipping. The port process plugs have been tested up to and found to withstand 110 psi and 190°F. These transceivers are compatible with either industry standard wave- or hand-solder processes. Shipping Container Each transceiver is packaged in a shipping container designed to protect it from mechanical and ESD damage during shipment or storage. Board Layout–Decoupling Circuit and Ground Planes It is important to take care in the layout of your circuit board to achieve optimum performance from these transceivers. Figure 7 provides a good example of schematics for decoupling circuits that work well with this product. It is further recommended that a contiguous ground plane be provided in the circuit board directly under the transceiver to provide a low inductance ground for signal return current. This recommendation is in keeping with good high frequency board layout practices. Board Layout–Hole Pattern The hole pattern shown in Figure 8 for the 2x11 package style complies with the pin sizes specified by the multisource agreement. Hole patterns are also provided for the Standard and Narrow 1x13 package styles. These drawings can be used as a guide in the mechanical layout of your circuit board. Board Layout–Art Work The Applications Engineering group has developed Gerber file artwork for various fiber optic transceiver layouts. Contact your local Hewlett-Packard sales representative for details. Regulatory Compliance These transceiver products are intended to enable commercial system designers to develop equipment that complies with the various international regulations governing certification of Information Technology Equipment. See Table 1 for details. Additional information is available from your Hewlett-Packard sales representative. 97 VCC L1 1 C1 20 Rx Tx GND 1 2 3 4 C5 0.1 R1 82 R2 82 DATA 5 R9 82 VCC VCC VCC VCC GND GND SD SD GND GND 9 VCC VBB DATA OUT DATA OUT GND R4 130 R10 82 GND NC VCC VCC GND 7 8 11 R3 130 GND GND 6 10 DATA C3 10 L2 1 DATA IN DATA IN 22 21 20 19 18 C4 0.1 17 16 15 R5 82 14 R6 82 DATA 13 12 DATA GND R7 130 TOP VIEW R8 130 C2 0.1 SIGNAL DETECT SIGNAL DETECT R11 130 R12 130 (a) HFBR-5111 GND VB DATA IN DATA IN TX VCC GND GND RX VCC SD SD DATA OUT DATA OUT GND TOP VIEW 13 12 11 10 9 8 7 6 5 4 3 2 1 R6 82 R5 82 DATA IN DATA IN C4 0.1 C5 0.1 R8 130 L2 1 L1 1 C1 20 C2 0.1 C3 10 R9 82 R7 130 R10 82 R2 82 R1 82 VCC SD SD DATA OUT DATA OUT R11 130 R12 130 R4 130 NOTES: 1. PLACE TERMINATION RESISTORS NEAR INPUT DATA PINS OF TRANSCEIVER AND PHY DEVICES. 2. MAKE DIFFERENTIAL SIGNAL PATHS SHORT AND OF THE SAME LENGTH WITH EQUAL TERMINATIONS TO VCC – 2 VOLTS. 3. SIGNAL TRACES SHOULD BE 50 Ω TRANSMISSION LINES: MICROSTRIP (OR STRIPLINE). USE GROUND PLANE (OR MULTI-LAYER) PRINTED CIRCUIT BOARD FOR BEST HIGH FREQUENCY PERFORMANCE. 4. RESISTORS IN Ω. CAPACITORS IN MICROFARADS. INDUCTORS IN MICROHENRIES. 5. USE HIGH-FREQUENCY MONOLITHIC CERAMIC BYPASS CAPACITORS AND LOW SERIES DC RESISTANCE INDUCTORS. FERRITE INDUCTORS CAN BE USED. LOCATE POWER SUPPLY FILTER COMPONENTS CLOSE TO FIBER-OPTIC DEVICES. 6. CAUTION: DO NOT DIRECTLY CONNECT FIBER-OPTIC MODULE PECL OUTPUTS (DATA, DATA, SIGNAL DETECT, SIGNAL DETECT) TO GROUND WITHOUT PROPER CURRENT LIMITING IMPEDANCE. 7. DEVICE GROUND PINS SHOULD BE DIRECTLY AND INDIVIDUALLY CONNECTED TO GROUND. 8. DEVICE SOLDER POSTS SHOULD BE DIRECTLY CONNECTED TO PCB FOR OPTIMUM MECHANICAL SUPPORT. (b) HFBR-5112/-5113 Figure 7. Recommended Decoupling Circuit Diagram. 98 R3 130 4X φ 1.93 ± 0.15 0.076 ± 0.006 φ 0.000 M A –A– 22X φ 1.04 ± 0.15 0.041 ± 0.006 φ 0.000 M A 2.54 TYP 0.100 40.64 1.600 5.08 0.200 30.48 1.200 NOTES: 1. DIMENSIONS ARE IN MILLIMETERS OVER INCHES. 2. DIMENSIONS PER ANSI Y 14.5 M. 2X (a) HFBR-5111 φ 1.93 ± 0.15 0.076 ± 0.006 φ 0.000 M A –A– 22.86 0.900 2.54 TYP 0.100 13X 30.48 1.200 φ 1.00 ± 0.15 0.039 ± 0.006 φ 0.000 M A NOTES: 1. DIMENSIONS ARE IN MILLIMETERS OVER INCHES. 2. DIMENSIONS PER ANSI Y 14.5 M. (b) HFBR-5112 4 – ∅ 2.4 ± 0.1 ∅ 0.1 M A B 19.05 19.05 5.08 MIN. 30.48 13 – ∅ 1.0 ± 0.1 ∅ 0.1 M 15.24 B 2.54 x 12 3.81 A UNIT: mm NOTES: 1. TOLERANCE ± 0.05 mm, UNLESS OTHERWISE SPECIFIED. 2. SOLDER POSTS SHOULD BE CONNECTED TO PCB FOR OPTIMUM MECHANICAL SUPPORT. (c) HFBR-5113 Figure 8. Board Layout–Hole Pattern. 99 Electrostatic Discharge There are two design cases in which immunity to ESD damage is important. The first is during handling of the transceiver prior to mounting it on the circuit board. It is important to use normal ESD handling precautions for ESDsensitive devices. These precautions include using grounded wrist straps, work benches, and floor mats in ESD-controlled areas. The second case to consider is static discharges to the exterior of the equipment chassis containing the transceiver parts. To the extent that the MIC connector is exposed to the outside of the equipment chassis, it may be subject to whatever ESD system level test criteria that the equipment is intended to meet. Electromagnetic Interference (EMI) Most equipment designs utilizing these high speed transceivers from Hewlett-Packard will be required to meet the requirements of FCC in the United States, CENELEC EN55022 (CISPR 22) in Europe and VCCI in Japan. Hence, the HFBR-511X Series of fiber optic transceivers meet the regulatory requirements listed in Table 1. Immunity Equipment utilizing these transceivers will be subject to radio-frequency electromagnetic fields in some environments. These transceivers have a high immunity to such fields. The internal construction of the HFBR-511X Series is similar to that of the HFBR-510X/-520X series. Therefore, for additional information regarding EMI susceptibility, ESD, and conducted noise testing procedures and results, please refer to Application Note 1075, Testing and Measuring Electromagnetic Compatibility Performance of the HFBR-510X/-520X Fiber Optic Transceivers. Flammability Rating The housing material of the HFBR-5111/-5112/-5113 transceiver has been approved for UL flammability rating of 94V-0 under General Electric’s UL file number E121562 and similarly under CSA file number LS88480. Transceiver Reliability and Performance Qualification Data As with all HP components, the HFBR-511X series transceivers undergo extensive HewlettPackard reliability and performance qualification testing. Details are available from your HewlettPackard sales representative. These transceivers are manufactured at the Hewlett-Packard Singapore location which is an ISO 9001 certified facility. Ordering Information The Hewlett-Packard FDDI transceivers are available packaged with or without key inserts per Table 2. The key inserts are colored-coded plastic parts with an identifying key letter molded into the top surface of each key. The HFBR-5111/-5112/-5113 products are available through the Hewlett-Packard Component Field Sales Offices and Authorized Distributors worldwide. Table 1. Regulatory Compliance Table Feature Electrostatic Discharge (ESD) to the Electrical Pins Test Method MIL-STD-883C Method 3015.4 Electrostatic Discharge (ESD) to the MIC Receptacle Variation of IEC 801-2 Electromagnetic Interference (EMC) FCC Class B CENELEC CEN55022 Class B (CISPR 22B) VCCI Class 2 Variation of IEC 801-3 Immunity 100 Performance Meets Class 2 (2000 to 3999 Volts) Withstands up to 2200 V applied between electrical pins. Typically withstand at least 25 kV without damage when the MIC Receptacle is contacted by a Human Body Model probe. Typically provide a 13 dB margin to the noted standard limits when tested at a certified test range with the transceiver mounted to a circuit card without a chassis enclosure. Typically show no measurable effect from a 10 V/m field swept from 10 to 450 MHz applied to the transceiver when mounted to a circuit card without a chassis enclosure. Table 2. Ordering Information ∆λ – TRANSMITTER OUTPUT OPTICAL SPECTRAL WIDTH (FWHM) –nm Part Number Transceivers HFBR-5111 HFBR-5111 Option FDA HFBR-5111 Option FDB HFBR-5111 Option FDM HFBR-5111 Option FDS HFBR-5111 Option FDN HFBR-5112 HFBR-5112 Option FDA HFBR-5112 Option FDB HFBR-5112 Option FDM HFBR-5112 Option FDS HFBR-5112 Option FDN HFBR-5113 HFBR-5113 Option FDA HFBR-5113 Option FDB HFBR-5113 Option FDM HFBR-5113 Option FDS HFBR-5113 Option FDN Accessories HFBR-5001 HFBR-5198 Description 2x11 Transceiver with a set of 4 key inserts (A, B, M, and S) 2x11 Transceiver with A-key installed 2x11 Transceiver with B-key installed 2x11 Transceiver with M-key installed 2x11 Transceiver with S-key installed 2x11 Transceiver with no key inserts included Narrow 1x13 Transceiver with a set of 4 key inserts (A, B, M, and S) Narrow 1x13 Transceiver with A-key intalled Narrow 1x13 Transceiver with B-key installed Narrow 1x13 Transceiver with M-key installed Narrow 1x13 Transceiver with S-key installed Narrow 1x13 Transceiver with no key inserts included Standard 1x13 Transceiver with a set of 4 key inserts (A, B, M, and S) Standard 1x13 Transceiver with A-key intalled Standard 1x13 Transceiver with B-key installed Standard 1x13 Transceiver with M-key installed Standard 1x13 Transceiver with S-key installed Standard 1x13 Transceiver with no key inserts included One Port Process Plug One Bag of 4 Key Inserts (A,B,M, and S) 200 180 160 3.0 1.5 2.0 140 2.5 120 3.0 3.5 tr/f – TRANSMITTER OUTPUT OPTICAL RISE/FALL TIMES – ns 3.5 100 1200 1300 1320 1340 1360 1380 λC – TRANSMITTER OUTPUT OPTICAL CENTER WAVELENGTH –nm HFBR-511X FDDI TRANSMITTER TEST RESULTS OF λC, ∆λ AND tr/f ARE CORRELATED AND COMPLY WITH THE ALLOWED SPECTRAL WIDTH AS A FUNCTION OF CENTER WAVELENGTH FOR VARIOUS RISE AND FALL TIMES. Figure 9. Transmitter Output Optical Spectral Width (FWHM) vs. Transmitter Output Optical Center Wavelength and Rise/Fall Times. 101 1.25 4.850 10.0 RELATIVE AMPLITUDE 1.025 1.00 0.975 0.90 5.6 1.525 0.525 0.075 100% TIME INTERVAL 40 ± 0.7 0.50 ± 0.725 ± 0.725 RELATIVE INPUT OPTICAL POWER – dB 4.40 1.975 4 3 2.5 x 10-10 BER 2 1.0 x 10-12 BER 1 0 -4 -3 -2 -1 0 1 2 3 4 EYE SAMPLING TIME POSITION (ns) CONDITIONS: 1.TA = 25° C 2. VCC = 5 Vdc 3. INPUT OPTICAL RISE/FALL TIMES = 1.0/2.1 ns. 4. INPUT OPTICAL POWER IS NORMALIZED TO CENTER OF DATA SYMBOL. 5. NOTE 20 AND 21 APPLY. 0% TIME INTERVAL 0.10 0.025 0.0 -0.025 -0.05 0.075 5.6 10.0 1.525 0.525 4.850 80 ± 500 ppm 1.975 4.40 Figure 11. Relative Input Optical Power vs. Eye Sampling Time Position. TIME – ns THE HFBR-511X OUTPUT OPTICAL PULSE SHAPE FITS WITHIN THE BOUNDARIES OF THE PULSE ENVELOPE FOR RISE AND FALL TIME MEASUREMENTS. Figure 10. Output Optical Pulse Envelope. -31.0 dBm OPTICAL POWER MIN (PO + 4.0 dB OR -31.0 dBm) PA (PO + 1.5 dB < PA < -31.0 dBm) INPUT OPTICAL POWER (> 1.5 dB STEP INCREASE) PO = MAX (PS OR -45.0 dBm) (PS = INPUT POWER FOR BER < 102) INPUT OPTICAL POWER (> 4.0 dB STEP DECREASE) SIGNAL DETECT OUTPUT -45.0 dBm AS – MAX ANS – MAX SIGNAL – DETECT (ON) SIGNAL – DETECT (OFF) TIME AS – MAX — MAXIMUM ACQUISITION TIME (SIGNAL). AS – MAX IS THE MAXIMUM SIGNAL – DETECT ASSERTION TIME FOR THE STATION. AS – MAX SHALL NOT EXCEED 100.0 µs. THE DEFAULT VALUE OF AS – MAX IS 100.0 µs. ANS – MAX — MAXIMUM ACQUISITION TIME (NO SIGNAL). ANS – MAX IS THE MAXIMUM SIGNAL – DETECT DEASSERTION TIME FOR THE STATION. ANS – MAX SHALL NOT EXCEED 350 µs. THE DEFAULT VALUE OF AS – MAX IS 350 µs. Figure 12. Signal Detect Thresholds and Timing. 102 5 Absolute Maximum Ratings Parameter Storage Temperature Lead Soldering Temperature Lead Soldering Time Supply Voltage Data Input Voltage Differential Input Voltage Output Current Symbol TS TSOLD tSOLD VCC VI VD IO Min. -40 Typ. Max. 100 260 10 7.0 VCC 1.4 50 -0.5 -0.5 Unit °C °C sec. V V V mA Reference Note 1 Recommended Operating Conditions Parameter Ambient Operating Temperature Supply Voltage Data Input Voltage – Low Data Input Voltage – High Data and Signal Detect Output Load Signaling Rate Symbol TA VCC VIL - VCC VIH - VCC RL fS Min. 0 4.75 -1.810 -1.165 10 Typ. Max. 70 5.25 -1.475 -0.880 50 125 Unit °C V V V Ω MBd Reference Note 2 Note 3 Figures 5, 6 Transmitter Electrical Characteristics (TA = 0°C to 70°C, VCC = 4.75 V to 5.25 V) Parameter Supply Current Power Dissipation Threshold Voltage Data Input Current – Low Data Input Current – High Symbol ICC PDISS VBB - VCC IIL IIH Min. -1.42 -350 Typ. 145 0.76 -1.3 0 14 Max. 185 0.97 -1.24 350 Unit mA W V µA µA Reference Note 4 Note 5 Receiver Electrical Characteristics (TA = 0°C to 70°C, VCC = 4.75 V to 5.25 V) Parameter Supply Current Power Dissipation Data Output Voltage – Low Data Output Voltage – High Data Output Rise Time Data Output Fall Time Signal Detect Output Voltage – Low Signal Detect Output Voltage – High Signal Detect Output Rise Time Signal Detect Output Fall Time Symbol ICC PDISS VOL – VCC VOH – VCC tr tf VOL – VCC VOH – VCC tr tf Min. -1.840 -1.045 0.35 0.35 -1.840 -1.045 0.35 0.35 Typ. 102 0.3 Max. 165 0.5 -1.620 -0.880 2.2 2.2 -1.620 -0.880 2.2 2.2 Unit mA W V V ns ns V V ns ns Reference Note 6 Note 7 Note 8 Note 8 Note 9 Note 9 Note 8 Note 8 Note 9 Note 9 103 Transmitter Optical Characteristics (TA = 0°C to 70°C, VCC = 4.75 V to 5.25 V) Parameter Symbol Output Optical Power BOL PO 62.5/125 µm, NA = 0.275 Fiber EOL Output Optical Power BOL PO 50/1255 µm, NA = 0.20 Fiber EOL Optical Extinction Ratio Output Optical Power at Logic “0” State Center Wavelength Typ. -16.8 Max. -14 Unit dBm avg. Reference Note 13 -20.3 -14 dBm avg. Note 13 0.001 -50 % dB dBm avg. nm Note 14 1308 0.03 -35 -45 1380 137 170 nm Optical Rise Time tr 0.6 1.0 3.0 ns Optical Fall Time tf 0.6 2.1 3.0 ns DCD 0.02 0.6 ns p-p Note 15 Note 16 Figure 9 Note 16 Figure 9 Note 16, 17 Figure 9, 10 Note 16, 17 Figure 9, 10 Note 18 DDJ 0.02 0.6 ns p-p Note 19 RJ 0 0.69 ns p-p Note 20 Spectral Width – FWHM Duty Cycle Distortion Contributed by the Transmitter Data Dependent Jitter Contributed by the Transmitter Random Jitter Contributed by the Transmitter PO (“0”) λC Min. -19 -20 -22.5 -23.5 1270 ∆λ Receiver Optical Characteristics (TA = 0°C to 70°C, VCC = 4.75 V to 5.25 V) Parameter Symbol Min. Input Optical Power Minimum at PIN Min. (W) Window Edge Input Optical Power Minimum PIN Min. (C) at Eye Center Input Optical Power Maximum PIN Max. -14 Operating Wavelength λ 1270 Duty Cycle Distortion Contributed DCD by the Receiver Data Dependent Jitter Contributed DDJ by the Receiver Random Jitter Contributed by the RJ Receiver Signal Detect – Asserted PA PD + 1.5 dB Signal Detect – Deasserted Signal Detect – Hysteresis Signal Detect Assert Time (off to on) 0.35 1.0 ns p-p Note 11 1.0 2.14 ns p-p Note 12 -33 PD -45 PA - PD AS_Max 1.5 0 2.4 55 100 0 110 350 Signal Detect Deassert Time (on to off) ANS_Max 104 Typ. Max. Unit Reference -33.5 -31 dBm avg. Note 21 Figure 11 -34.5 -31.8 dBm avg. Note 22 Figure 11 -11.8 dBm avg. Note 21 1380 nm 0.02 0.4 ns p-p Note 10 dBm avg. Note 23, 24 Figure 12 dBm avg. Note 25, 26 Figure 12 dB Figure 12 µs Note 23, 24 Figure 12 µs Note 25, 26 Figure 12 Notes: 1. This is the maximum voltage that can be applied across the Differential Transmitter Data Inputs to prevent damage to the input ESD protection circuit. 2. The outputs are terminated with 50 Ω connected to VCC - 2 V. 3. The specified signaling rate of 10 MBd to 125 MBd guarantees operation of the transmitter and receiver link to the full conditions listed in the FDDI Physical Layer Medium Dependent standard. Specifically, the link bit error ratio will be equal to or better than 2.5 x 10-10 for any valid FDDI pattern. The transmitter section of the link is capable of dc to 125 MBd. The receiver is internally ac-coupled which limits the lower signaling rate to 10 MBd. For purposes of definition, the symbol rate (Baud), also called signaling rate, fs, is the reciprocal of the shortest symbol time. Data rate (bits/sec) is the symbol rate divided by the encoding factor used to encode the data (symbols/bit). 4. The power supply current needed to operate the transmitter is provided to differential ECL circuitry. This circuitry maintains a nearly constant current flow from the power supply. Constant current operation helps to prevent unwanted electrical noise from being generated and conducted or emitted to neighboring circuitry. 5. This value is measured with an output load RL = 10 kΩ. 6. This value is measured with the outputs terminated into 50 Ω connected to VCC - 2 V and an Input Optical Power level of -14 dBm average. 7. The power dissipation value is the power dissipated in the receiver itself. Power dissipation is calculated as the sum of the products of supply voltage and currents, minus the sum of the products of the output voltages and currents. 8. This value is measured with respect to VCC with the output terminated into 50 Ω connected to VCC - 2 V. 9. The output rise and fall times are measured between 20% and 80% levels with the output connected to VCC - 2 V through 50 Ω. 10. Duty Cycle Distortion contributed by the receiver is measured at the 50% threshold using an IDLE Line State, 125 MBd (62.5 MHz square-wave), 11. 12. 13. 14. input signal. The input optical power level is -20 dBm average. See Application Information - Transmitter Jitter Section for further information. Data Dependent Jitter contributed by the receiver is specified with the FDDI DDJ test pattern described in the FDDI PMD Annex A.5. The input optical power level is -20 dBm average. See Application Information - Transmitter Jitter Section for further information. Random Jitter contributed by the receiver is specified with an IDLE Line State, 125 Mbd (62.5 MHz square-wave), input signal. The input optical power level is at maximum “PIN Min. (W).” See Application Information - Transmitter Jitter Section for further information. These optical power values are measured with the following conditions: • The Beginning of Life (BOL) to the End of Life (EOL) optical power degradation is typically 1.5 dB per the industry convention for long wavelength LEDs. The actual degradation observed in HewlettPackard’s 1300 nm LED products is < 1 dB, as specified in this data sheet. • Over the specified operation voltage and temperature ranges. • With HALT Line State, (12.5 MHz square-wave), input signal. • At the end of one meter of noted optical fiber with cladding modes removed. The average power value can be converted to a peak power value by adding 3 dB. Higher output optical power transmitters are available on special request. The Extinction Ratio is a measure of the modulation depth of the optical signal. The data “0” output optical power is compared to the data “1” peak output optical power and expressed as a percentage. With the transmitter driven by a HALT Line State (12.5 MHz square-wave) signal, the average optical power is measured. The data “1” peak power is then calculated by adding 3 dB to the measured average optical power. The data “0” output optical power is found by measuring the optical power when the transmitter is driven by a logic “0” input. The extinction ratio is the ratio of the optical power at the “0” level compared to the optical 15. 16. 17. 18. 19. 20. 21. power at the “1” level expressed as a percentage or in decibels. The transmitter provides compliance with the need for Transmit_Disable commands from the FDDI SMT layer by providing an Output Optical Power level of < -45 dBm average in response to a logic “0” input. This specification applies to either 62.5/125 µm or 50/125 µm fiber cables. This parameter complies with the FDDI PMD requirements for the tradeoffs between center wavelength, spectral width, and rise/fall times shown in Figure 9. This parameter complies with the optical pulse envelope from the FDDI PMD shown in Figure 10. The optical rise and fall times are measured from 10% to 90% when the transmitter is driven by the FDDI HALT Line State (12.5 MHz square-wave) input signal. Duty Cycle Distortion contributed by the transmitter is measured at a 50% threshold using an IDLE Line State, 125 MBd (62.5 MHz square-wave), input signal. See Application Information – Transceiver Jitter Performance Section of this data sheet for further details. Data Dependent Jitter contributed by the transmitter is specified with the FDDI test pattern described in FDDI PMD Annex A.5. See Application Information – Transceiver Jitter Performance Section of this data sheet for further details. Random Jitter contributed by the transmitter is specified with an IDLE Line State, 1256 MBd (62.5 MHz square-wave), input signal. See Application Information – Transceiver Jitter Performance Section of this data sheet for further details. This specification is intended to indicate the performance of the receiver section of the transceiver when Input Optical Power signal characteristics are present per the following definitions. The Input Optical Power dynamic range from the minimum level (with a window time-width) to the maximum level is the range over which the receiver is guaranteed to provide output data with a Bit Error Ratio (BER) better than or equal to 2.5 x 10-10. • At the Beginning of Life (BOL). • Over the specified operation temperature and voltage ranges. 105 • Input symbol pattern is the FDDI test pattern defined in FDDI PMD Annex A.5 with 4B/5B NRZI encoded data that contains a duty cycle base-line wander effect of 50 kHz. This sequence causes a near worst case condition for intersymbol interference. • Receiver data window time-width is 2.13 ns or greater and centered at mid-symbol. This worst case window time-width is the minimum allowed eye-opening presented to the FDDI PHY PM_Data indication input (PHY input) per the example in FDDI PMD Annex E. This minimum window time-width of 2.13 ns is based upon the worst case FDDI PMD Active Input Interface optical conditions for peak-to-peak DCD (1.0 ns), DDJ (1.2 ns) and RJ (0.76 ns) presented to the receiver. To test a receiver with the worst case FDDI PMD Active Input jitter condition requires exacting control over DCD, DDJ and RJ jitter components that is difficult to implement with production test equipment. The receiver can be equivalently tested to the worst case FDDI PMD input jitter conditions and meet the minimum output data window time-width of 2.13 ns. This is accomplished by using a nearly ideal input optical signal (no DCD, insignificant DDJ and RJ) and measuring for a wider 106 window time-width of 4.6 ns. This is possible due to the cumulative effect of jitter components through their superposition (DCD and DDJ are directly additive and RJ components are rms additive). Specifically, when a nearly ideal input optical test signal is used and the maximum receiver peak-to-peak jitter contributions of DCD (0.4 ns), DDJ (1.0 ns), and RJ (2.14 ns) exist, the minimum window time-width becomes 8.0 ns -0.4 ns 1.0 ns - 2.14 ns = 4.46 ns, or conservatively 4.6 ns. This wider window time-width of 4.6 ns guarantees the FDDI PMD Annex E minimum window time-width of 2.13 ns under worst case input jitter conditions to the Hewlett-Packard receiver. • Transmitter operating with an IDLE Line State pattern, 125 MBd (62.5 MHz square-wave), input signal to simulate any cross-talk present between the transmitter and receiver sections of the transmitter. 22. All conditions of Note 21 apply except that the measurement is made at the center of the symbol with no window time-width. 23. This value is measured during the transition from low to high levels of input optical power. 24. The Signal Detect output shall be asserted within 100 µs after a step increase of the Input Optical Power. The step will be from a low Input Optical Power, ≤ -45 dBm, into the range between greater than PA, and -14 dBm. The BER of the receiver output will be 10-2 or better during the time, LS_Max (15 µs) after Signal Detect has been asserted. See Figure 12 for more information. 25. This value is measured during the transition from high to low levels of input optical power. The maximum value will occur when the input optical power is either -45 dBm average or when the input optical power yields a BER of 10-2 or better, whichever power is higher. 26. Signal detect output shall be deasserted within 350 µs after a step decrease in the Input Optical Power from a level which is the lower of: -31 dBm or PD + 4 dB (PD is the power level at which signal detect was deasserted), to a power level of -45 dBm or less. This step decrease will have occurred in less than 8 ns. The receiver output will have a BER of 10-2 or better for a period of 12 µs or until signal detect is deasserted. The input data stream is the Quiet Line State. Also, signal detect will be deasserted within a maximum of 350 µs after the BER of the receiver output degrades above 10-2 for an input optical data stream that decays with a negative ramp function instead of a step function. See Figure 12 for more information. WWW.ALLDATASHEET.COM Copyright © Each Manufacturing Company. All Datasheets cannot be modified without permission. This datasheet has been download from : www.AllDataSheet.com 100% Free DataSheet Search Site. Free Download. No Register. Fast Search System. www.AllDataSheet.com