FUJITSU MB15E05PFV1

FUJITSU SEMICONDUCTOR
DATA SHEET
DS04-21330-1E
ASSP
Single Serial Input
PLL Frequency Synthesizer
On-Chip 2.0GHz Prescaler
MB15E05
■
DESCRIPTION
The Fujitsu MB15E05 is serial input Phase Locked Loop (PLL) frequency synthesizers with a 2.0 GHz prescaler. A
64/65 or a 128/129 can be selected for the prescaler that enables pulse swallow operation.
The latest BiCMOS process technology is used, resuItantly a supply current is limited as low as 6mA typ. This
operates with a supply voltage of 3.0V (typ.).
Furthermore, a super charger circuit is included to get a fast tuning as well as low noise performance. As a result of
this, MB15E05 is ideally suitable for digital mobile communications, such as PCN (Personal Communication Network),
PCS (Personal Communication Service), etc.
■
FEATURES
•
•
•
•
•
•
•
High frequency operation: 2.0 GHz max
Low power supply voltage: VCC = 2.7 to 3.6V
Very Low power supply current : ICC = 6.0 mA typ. (Vcc = 3V)
Power saving function : IPS = 10 µA max.
Pulse swallow function: 64/65 or 128/129
Serial input 14-bit programmable reference divider: R = 5 to 16,383
Serial input 18-bit programmable divider consisting of:
- Binary 7-bit swallow counter: 0 to 127
- Binary 11-bit programmable counter: 5 to 2,047
• Wide operating temperature: Ta = –40 to 85°C
• Plastic 16-pin SSOP package (FPT-16P-M05)
■
PACKAGE
16-pin, Plastic SSOP
(FPT-16P-M05)
This device contains circuitry to protect the inputs against damage due to high static voltages or electroc fields. However, it is advised that normal precautions
be taken to avoid application of any voltage higher than maximum rated voltages to this high impedance circuit.
1
MB15E05
■
PIN ASSIGNMENT
OSCin
1
16
φR
OSCout
2
15
φP
Vp
3
14
LD/fout
Vcc
4
TOP 13
VIEW
5
12
ZC
GND
6
11
LE
Xfin
7
10
Data
fin
8
9
Clock
Do
2
PS
MB15E05
■
PIN DESCRIPTIONS
Pin No.
Pin Name
I/O
Descriptions
1
OSCIN
I
Programmable reference divider input.
Oscillator input.
Connection for an crystal or a TCXO.
TCXO should be connected with a coupling capacitor.
2
OSCOUT
O
Oscillator output.
Connection for an external crystal.
3
VP
–
Power supply voltage input for the charge pump.
4
VCC
–
Power supply voltage input.
5
DO
O
Charge pump output.
Phase of the charge pump can be reversed by FC input.
6
GND
–
Ground.
7
Xfin
I
Prescaler complementary input, and should be grounded via a capacitor.
8
fin
I
Prescaler input.
Connection with an external VCO should be done with AC coupling.
9
Clock
I
Clock input for the 19-bit shift register.
Data is shifted into the shift register on the rising edge of the clock. (Open
is prohibited.)
10
Data
I
Serial data input using binary code.
The last bit of the data is a control bit. (Open is prohibited.)
Control bit = ”H” ; Data is transmitted to the programmable reference
counter.
Control bit = ”L” ; Data is transmitted to the programmable counter.
11
LE
I
Load enable signal input (Open is prohibited.)
When LE is high, the data in the shift register is transferred to a latch,
according to the control bit in the serial data.
I
Power saving control input. This pin should be set at ”L” at Power-ON.
(Open is prohibited.)
PS = ”H” ; Normal mode
PS = ”L” ; Power saving mode
I
Forced high-impedance control for the charge pump (with internal pull up
resistor.)
ZC = ”H” ; Normal Do output.
ZC = ”L” ; Do becomes high impedance.
12
13
PS
ZC
14
LD/fout
O
Lock detect signal output(LD)/ phase comparator monitoring
output (fout).
The output signal is selected by LDS bit in the serial data.
LDS = ”H” ; outputs fout (fr/fp monitoring output)
LDS = ”L” ; outputs LD (”H” at locking, ”L” at unlocking.)
15
φP
O
Phase comparator output for an external charge pump.
16
φR
O
Phase comparator output for an external charge pump.
3
MB15E05
■
BLOCK DIAGRAM 1
OSCIN 1
fr
Crystal
Oscillator
circuit
fp
Programmable
reference divider
OSCOUT 2
Lock
detector
fr
Intermittent
mode control
(power save)
16 φR
15 φP
LD
Binary 14-bit
reference counter
PS 12
Phase
comparator
SW
LDS
17-bit latch
FC
14-bit latch
LD/fr/fp
selector
3-bit latch
LE
14 LD/fout
fp
LE 11
1-bit
control
latch
19-bit shift register
C
N
T
Data 10
Charge
pump
19-bit shift register
3 VP
Super
charger
Clock 9
LE
18-bit latch
7-bit latch
11-bit latch
SW
Programmable divider
XfIN 7
fIN 8
Prescaler
64/65,
128/129
Binary 7-bit
swallow
counter
Binary 11-bit
programmable
counter
GND 6
VCC 4
4
MD
13 ZC
Control Circuit
fp
5 DO
MB15E05
■
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Rating
Unit
VCC
–0.5 to +4.0
V
VP
VCC to +6.0
V
Input voltage
VI
–0.5 to VCC +0.5
V
Output voltage
VO
–0.5 to VCC +0.5
V
Storage temperature
Tstg
–55 to +125
°C
Power supply voltage
Remark
Note: Permanent device damage may occur if the above Absolute Maximum Ratings are exceeded. Functional
operation should be restricted to the conditions as detailed in the operational sections of this data sheet.
Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
■
RECOMMENDED OPERATING CONDITIONS
Parameter
Symbol
Value
Unit
Min
Typ
Max
VCC
2.7
3.0
3.6
V
VP
VCC
–
6.0
V
Input voltage
VI
GND
–
VCC
V
Operating temperature
Ta
–40
–
+85
°C
Power supply voltage
Remark
Notes: To protect against damage by electrostatic discharge, note the following handling precautions:
-Store and transport devices in conductive containers.
-Use properly grounded workstations, tools, and equipment.
-Turn off power before inserting or removing this device into or from a socket.
-Protect leads with conductive sheet, when transporting a board mounted device.
5
MB15E05
■
ELECTRICAL CHARACTERISTICS
Parameter
Symbol
Condition
Min
Typ
Max
Unit
Power supply current*1
ICC
finIF =
2000MHz,
fosc = 12MHz
–
6.0
–
mA
Power saving current*2
Ips
Vcc current at
PS =”L” and
ZC = ”H”
–
–
10
µA
Operating frequency
fin
100
–
2000
MHz
Crystal oscillator operating frequency
fOSC
min. 500mVp-p
3
–
40
MHz
fin
VfinIF
50Ω termination (Refer to
the test circuit.)
–10
–
+2
dBm
OSCin
VOSC
500
–
VCC
mVp–p
Data,
Clock,
LE, PS, ZC
VIH
Vccx0.7
–
–
VIL
–
–
Vccx0.3
Data,
Clock,
LE, PS
IIH
–1.0
–
+1.0
IIL
–1.0
–
+1.0
IIH
–1.0
–
+1.0
–100
–
0
IIH
0
–
+100
IIL
–100
–
0
–
–
0.4
Input sensitivity
Input voltage
Input current
ZC
OSCin
Output voltage
High impedance
cutoff current
IIL
Pull up input
Open drain
output
V
µA
µA
µA
φP
VOL
φR,
LD/fout
VOH
Vcc-0.4
–
–
VOL
–
–
0.4
VDOH
Vcc-0.4
–
–
VDOL
–
–
0.4
Do
IOFF
–
–
1.1
µA
φP
IOL
1.0
–
–
mA
φR,
LD/fou
IOH
–
–
–1.0
IOL
1.0
–
–
–10.0*2
–
Do
Output current
Open drain
output
IDOH
Vcc = 3.0V,
Vp = 5V,
VDOH = 4.0V
–
IDOL
Vcc = 3.0V,
Vp = 5V,
VDOL = 1.0V
–
Do
*1: Conditions ; Vcc = 3.0V, Ta = 25°C, in locking state.
*2: Conditions ; Ta = 25°C
6
Value
V
V
V
mA
mA
10.0*2
–
MB15E05
■
FUNCTION DESCRIPTIONS
Pulse Swallow Function
The divide ratio can be calculated using the following equation:
fVCO = [(M x N) + A] x fOSC ÷ R (A < N)
fVCO : Output frequency of external voltage controlled oscillator (VCO)
N
: Preset divide ratio of binary 11-bit programmable counter (5 to 2,047)
A
: Preset divide ratio of binary 7-bit swallow counter (0 ≤ A ≤ 127)
fOSC : Output frequency of the reference frequency oscillator
R
: Preset divide ratio of binary 14-bit programmable reference counter (5 to 16,383)
M
: Preset divide ratio of modules prescaler (64 or 128)
Serial Data Input
Serial data is processed using the Data, Clock, and LE pins. Serial data controls the programmable reference
divider and the programmable divider separately.
Binary serial data is entered through the Data pin.
One bit of data is shifted into the shift register on the rising edge of the clock. When the load enable pin is high,
stored data is latched according to the control bit data as follows:
Table.1 Control Bit
Control bit (CNT)
Destination of serial data
H
17 bit latch (for the programmable reference divider)
L
18 bit latch (for the programmable divider)
Shift Register Configuration
Programmable Reference Counter
MSB
Data Flow
LSB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
C
N
T
R
1
R
2
R
3
R
4
R
5
R
6
R
7
R
8
R
9
R
10
R
11
R
12
R
13
R
14 SW FC LDS
CNT
R1 to R14
SW
FC
LDS
16
: Control bit
: Divide ratio setting bit for the programmable reference counter (5 to 16,383)
: Divide ratio setting bit for the prescaler (64/65 or 128/129)
: Phase control bit for the phase comparator
: LD/fout signal select bit
17
18
[Table. 1]
[Table. 2]
[Table. 5]
[Table. 7]
[Table. 6]
Note: Start data input with MSB first
7
MB15E05
Programmable Reference Counter
MSB
Data Flow
LSB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
C
N
A
1
A
2
A
3
A
4
A
5
A
6
A
7
N
1
N
2
N
3
N
4
N
5
N
6
N
7
N
8
N
9
N
10
N
11
T
CNT
: Control bit
N1 to N11 : Divide ratio setting bits for the programmable counter (5 to 2,047)
A1 to A7 : Divide ratio setting bits for the swallow counter (0 to 127)
[Table. 1]
[Table. 3]
[Table. 4]
Note: Start data input with MSB first
Table2. Binary 14-bit Programmable Reference Counter Data Setting
Divide
ratio
(R)
R
14
R
13
R
12
R
11
R
10
R
9
R
8
R
7
R
6
R
5
R
4
R
3
R
2
R
1
5
0
0
0
0
0
0
0
0
0
0
0
1
0
1
6
0
0
0
0
0
0
0
0
0
0
0
1
1
0
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
16383
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Note: • Divide ratio less than 5 is prohibited.
Table.3 Binary 11-bit Programmable Counter Data Setting
Divide
ratio
(N)
N
11
N
10
N
9
N
8
N
7
N
6
N
5
N
4
N
3
N
2
N
1
5
0
0
0
0
0
0
0
0
1
0
1
6
0
0
0
0
0
0
0
0
1
1
0
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
2047
1
1
1
1
1
1
1
1
1
1
1
Note: • Divide ratio less than 5 is prohibited.
• Divide ratio (N) range = 5 to 2,047
8
MB15E05
Table.4 Binary 7-bit Swallow Counter Data Setting
Divide
ratio
(A)
A
7
A
6
A
5
A
4
A
3
A
2
A
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
1
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
127
1
1
1
1
1
1
1
Note: • Divide ratio (A) range = 0 to 127
Table. 5 Prescaler Data Setting
SW
Prescaler Divide ratio
H
64/65
L
128/129
Table. 6 LD/fout Output Select Data Setting
LDS
LD/fout output signal
H
fout signal
L
LD signal
Relation between the FC input and phase characteristics
The FC bit changes the phase characteristics of the phase comparator. Both the internal charge pump output level
(DO) and the phase comparator output (φR, φP) are reversed according to the FC bit. Also, the monitor pin (fOUT)
output is controlled by the FC bit. The relationship between the FC bit and each of DO, φR, and φP is shown below.
Table. 7 FC Bit Data Setting (LDS = ”H”)
FC = High
FC = Low
Do
φR
φP
LD/fout
Do
φR
φP
LD/fout
fr > fp
H
L
L
(fr)
L
H
Z*
(fp)
fr < fp
L
H
Z*
(fr)
H
L
L
(fp)
fr = fp
Z*
L
Z*
(fr)
Z*
L
Z*
(fp)
* : High impedance
9
MB15E05
When designing a synthesizer, the FC pin setting depends on the VCO and LPF characteristics.
∗: When the LPF and VCO characteristics are
similar to ① , set FC bit high.
∗: When the VCO characteristics are similar to
②, set FC bit low.
①
VCO
Output
Frequency
PLL
LPF
VCO
②
LPF Input Voltage
Power Saving Mode (Intermittent Mode Control Circuit)
Setting a PS pin to Low, the IC enters into power saving mode resultatly current sonsumption can be limited to
10µA (max.). Setting PS pin to High, power saving mode is released so that the IC works normally.
In addition, the intermittent operation control circuit is included which helps smooth start up from the power saving
mode. In general, the power consumption can be saved by the intermittent operation that powering down or waking
up the synthesizer. Such case, if the PLL is powered up uncontrolled, the resulting phase comparator output signal
is unpredictable due to an undefined phase relation between reference frequency (fr) and comparison frequency
(fp) and may in the worst case take longer time for lock up of the loop.
To prevent this, the intermittent operation control circuit enforces a limited error signal output of the phase detector
during power up, thus keeping the loop locked.
During the power saving mode, the corresponding section except for indispensable circuit for the power saving
function stops working, then current consumption is reduced to 10µA per one PLL section.
At that time, the Do and LD become the same state as when a loop is locking. That is, the Do becomes high
impedance.
A VCO control voltage is naturally kept at the locking voltage which defined by a LPF”s time constant. As a result
of this, VCO’s frequency is kept at the locking frequency.
Note: • While the power saving mode is executed, ZC pin should be set at ”H” or open. If ZC is set at ”L”
during power saving mode, approximately 10 µA current flows.
• PS pin must be set ”L” at Power-ON.
• The power saving mode can be released (PS : L → H) 1µs later after power supply remains stable.
• During the power saving mode, it is possible to input the serial data.
Table.8 PS Pin Setting
PS pin
Status
H
Normal mode
L
Power saving mode
Table.9 ZC Pin Setting
ZC pin
10
Do output
H
Normal output
L
High impedance
MB15E05
■
SERIAL DATA INPUT TIMING
Data
MSB
LSB
Clock
LE
t2
t5
t3
t1
t6
t7
t4
On rising edge of the clock, one bit of the data is transferred into the shift register.
Parameter
Min.
t1
20
t2
Typ.
Max.
Unit
Parameter
–
–
ns
t5
30
20
–
–
ns
t6
t3
30
–
–
ns
t7
t4
20
–
–
ns
Min.
Typ.
Max.
Unit
–
–
ns
100
–
–
ns
100
–
–
ns
11
MB15E05
■
PHASE COMPARATOR OUTPUT WAVEFORM
fr
fp
tWU
tWL
LD
[ FC = ”H” ]
φP
φR
H
Do
Z
L
[ FC = ”L” ]
φP
φR
H
Do
L
Z
Notes: 1. Phase error detection range: –2π to +2π
2. Pulses on Do output signal during locked state are output to prevent dead zone.
3. LD output becomes low when phase is tWU or more. LD output becomes high when phase error is tWL
or less and continues to be so for three cysles or more.
4. tWU and tWL depend on OSCin input frequency.
tWU > 8/fosc (e. g. tWU > 625ns, foscin = 12.8 MHz)
tWL < 16/fosc (e. g. tWL < 1250ns, foscin = 12.8 MHz)
5. LD becomes high during the power saving mode (PS = ”L”.)
12
MB15E05
■
TEST CIRCUIT (for Measuring Input Sensitivity fin/OSCin)
VCC
VP
0.1µ
1000p
1000p
0.1µ
P•G
50 Ω
P•G
1000p
8
7
6
5
4
3
2
1
50 Ω
9 10 11 12 13 14 15 16
Oscilloscope
Controller
(setting divide ratio)
Vcc
13
MB15E05
■
APPLICATION EXAMPLE
Output
LPF
VCO
10k
12k
To a lock detect.
12k
φR
16
φP
15
10k
From
a controller
LD/FOUT ZC
14
13
PS
12
LE
Data
Clock
11
10
9
6
7
8
MB15E05
1
2
OSCIN
3
OSCOUT
4
VP
5
VCC
DO
GND
XfIN
1000p
X’ tal
C1
C2
0.1µ
C1, C2
14
:
0.1µ
Depend on the crystal parameters
fIN
1000p
MB15E05
TYPICAL CHARACTERISTICS
Do Output Current
[Ta = +25°C]
[VCC = 3 V, Vp =3 V, 5 V]
[Ta = +25°C]
[VCC = 3 V, Vp =3 V, 5 V]
Vp = 3 V
5.0
Vp = 5 V
4.0
4.0
3.0
3.0
2.0
1.0
Vp = 3 V
5.0
VOL (V)
VOH (V)
Vp = 5 V
2.0
1.0
0
0
–5
0
–10
IOH (mA)
–15
–20
0
5
10
IOL (mA)
15
20
fin Input Sensitivity
Main. counter div. ratio = 4104
Swallow="ON"
VCC = Vp
Vfin vs. fin
[Ta = +25°C]
+10
0
Vfin (dBm)
SPEC
–10
–20
VCC=2.7 V
VCC=3.0 V
–30
VCC=3.6 V
–40
0
1000
OSCin Input Characteristics
2000
fin (MHz)
Vfiosc vs. fosc
3000
4000
Ref. counter div. ratio = 767
fin, Xfin : OPEN
[Ta = +25°C]
+10
SPEC
0
Vfosc (dBm)
■
–10
–20
VCC=2.7 V
–30
VCC=3.0 V
VCC=3.6 V
–40
0
50
100
fosc (MHz)
150
200
(Continued)
15
MB15E05
(Continued)
fin Input Impedance
4: 18.13 Ω
14.664 Ω
1.1669 nH
2 000.000 000 MHz
1:
4
fin
19.508 Ω
–124.4 Ω
500 MHz
2:
10.139 Ω
–47.135 Ω
1 GHz
3:
10.783 Ω
–11.995 Ω
1.5 GHz
3
1
2
OSCin Input Impedance
3: 484.25 Ω
OSCin
16
–2.8518 kΩ 2.7905 pF
20.000 000 MHz
3
1
2
4
1:
28.348 kΩ
–19.661 kΩ
1 MHz
2:
593.25 Ω
–5.615 kΩ
10 MHz
4:
152.56 Ω
–1.2722 kΩ
50 MHz
MB15E05
■
REFERENCE INFORMATION
Typical plots measured with the
test circuit are shown below.
Each plot shows lock up time,
phase noise and reference
leakage.
Test Circuit
S.G
OSCin
Do
fin
LPF
•
•
•
•
•
fvco = 1835 MHz
Kv = 87 MHz/v
fr = 200 kHz
fosc = 13 MHz
LPF:
15 kΩ
Spectrum
Analyzer
3000 pF
PLL Lock Up Time = 500 µs
(1797.6 MHz → 1872.4 MHz, within ± 1kHz)
∆ MKr x : 500.01844 µs
y : –74.8009 MHz
910 Ω
VCO
0.03 µF
400 pF
PLL Phase Noise
@ within loop band = 69.4 dBc/Hz
REF
0.0 dBm
ATT 10 dB
10dB/
38.00500
MHz
2.000
kHz/div
RBW
300 Hz
VBW
300 Hz
29.99500
MHz
18.1339 µs
1.9903829 ms
SPAN 50.0 kHz CENTER 1.8350000 GH z
∆ MKr x : 500.01844 µs
y : –74.8009 MHz
PLL Reference Leakage
@ 200 kHz offset = 74.6 dBc
250.0000
MHz
REF
0.0 dBm
ATT 10 dB
10dB/
50.00000
MHz/div
0
Hz
18.1339 µs
1.9903829 ms
RBW
10 kHz
VBW
10 kHz
SPAN 1.00 MHz CENTER 1.8350000 GHz
17
MB15E05
■
18
ORDERING INFORMATION
Part number
Package
MB15E05PFV1
16-pin Plastic SSOP
(FPT-16P-M05)
Remarks
MB15E05
■
PACKAGE DIMENSION
16 pins, Plastic SSOP
(FPT-16P-M05)
* : These dimensions do not include resin protrusion.
+0.20
* 5.00±0.10(.197±.004)
1.25 –0.10
+.008
.049 –.004
0.10(.004)
INDEX
*4.40±0.10
(.173±.004)
0.65±0.12
(.0256±.0047)
4.55(.179)REF
C
1994 FUJITSU LIMITED F16013S-2C-4
+0.10
0.22 –0.05
+.004
.009 –.002
6.40±0.20
(.252±.008)
5.40(.213)
NOM
"A"
+0.05
0.15 –0.02
+.002
.006 –.001
Details of "A" part
0.10±0.10(.004±.004)
(STAND OFF)
0
10°
0.50±0.20
(.020±.008)
Dimensions in mm (inches)
19
FUJITSU LIMITED
For further information please contact:
Japan
FUJITSU LIMITED
Corporate Global Business Support Division
Electronic Devices
KAWASAKI PLANT, 4-1-1, Kamikodanaka
Nakahara-ku, Kawasaki-shi
Kanagawa 211-88, Japan
Tel: (044) 754-3763
Fax: (044) 754-3329
North and South America
FUJITSU MICROELECTRONICS, INC.
Semiconductor Division
3545 North First Street
San Jose, CA 95134-1804, U.S.A.
Tel: (408) 922-9000
Fax: (408) 432-9044/9045
Europe
FUJITSU MIKROELEKTRONIK GmbH
Am Siebenstein 6-10
63303 Dreieich-Buchschlag
Germany
Tel: (06103) 690-0
Fax: (06103) 690-122
Asia Pacific
FUJITSU MICROELECTRONICS ASIA PTE. LIMITED
#05-08, 151 Lorong Chuan
New Tech Park
Singapore 556741
Tel: (65) 281-0770
Fax: (65) 281-0220
All Rights Reserved.
The contents of this document are subject to change without
notice. Customers are advised to consult with FUJITSU sales
representatives before ordering.
The information and circuit diagrams in this document presented
as examples of semiconductor device applications, and are not
intended to be incorporated in devices for actual use. Also,
FUJITSU is unable to assume responsibility for infringement of
any patent rights or other rights of third parties arising from the
use of this information or circuit diagrams.
FUJITSU semiconductor devices are intended for use in
standard applications (computers, office automation and other
office equipment, industrial, communications, and measurement
equipment, personal or household devices, etc.).
CAUTION:
Customers considering the use of our products in special
applications where failure or abnormal operation may directly
affect human lives or cause physical injury or property damage,
or where extremely high levels of reliability are demanded (such
as aerospace systems, atomic energy controls, sea floor
repeaters, vehicle operating controls, medical devices for life
support, etc.) are requested to consult with FUJITSU sales
representatives before such use. The company will not be
responsible for damages arising from such use without prior
approval.
Any semiconductor devices have inherently a certain rate of
failure. You must protect against injury, damage or loss from
such failures by incorporating safety design measures into your
facility and equipment such as redundancy, fire protection, and
prevention of over-current levels and other abnormal operating
conditions.
If any products described in this document represent goods or
technologies subject to certain restrictions on export under the
Foreign Exchange and Foreign Trade Control Law of Japan, the
prior authorization by Japanese government should be required
for export of those products from Japan.
F9703
 FUJITSU LIMITED Printed in Japan
24