FUJITSU MB90372PMT-G-XXX

FUJITSU SEMICONDUCTOR
DATA SHEET
Version 1.3
16-bit Proprietary Microcontroller
CMOS
F2MC-16LX MB90370 Series
MB90372/F372/V370
DESCRIPTION
The MB90370 series is a line of general-purpose, 16-bit microcontrollers designed for those applications which
require high-speed real-time processing. The instruction set is designed to be optimized for controller applications
which inheriting the AT architecture of F2MC-16LX series and allow a wide range of control tasks to be processed
efficiently at high speed.
A built-in LPC interface, serial IRQ and PS/2 interface simplifies communication with host CPU and PS/2 devices
in computer system. Moreover, SMbus compliant I2C, comparator for battery control and A/D converter implements
the smart battery control. With these features, the MB90370 series matches itself as keyboard controller with
smart battery control.
While inheriting the AT architecture of the F 2MC*1 family, the instruction set for the F2MC-16LX CPU core of the
MB90370 series incorporates additional instructions for high-level languages, supports extended addressing
modes, and contains enhanced multiplication and division instructions as well as a substantial collection of
improved bit manipulation instructions. In addition, the MB90370 has an on-chip 32-bit accumulator which
enables processing of long-word data.
Notes: *1: F2MC stands for FUJITSU Flexible Microcontroller, a registered trademark of FUJITSU LIMITED.
*2: Purchase of Fujitsu I2C components conveys a license under the Philips I 2C Patent Rights to use these
components in an I2C system, provided that the system conforms to the I 2C Standard Specification as
defined by Philips.
FEATURES
Clock
•
Embedded PLL clock multiplication circuit
•
Operating clock (PLL clock) can selected from divided-by-2 of oscillation or one to four times
the oscillation (at oscillation of 4 MHz to 16 MHz)
•
Minimum instruction execution time of 62.5 ns (at oscillation of 4 MHz, four times the PLL
clock, operation at VCC of 3.3 V)
CPU addressing space of 16 Mbytes
•
Internal 24-bit addressing
Instruction set optimized for controller applications
•
Rich data types (bit, byte, word, long word)
•
Rich addressing mode (23 types)
MB90370 Series
•
High code efficiency
•
Enhanced precision calculation realized by the 32-bit accumulator
Instruction set designed for high level language (C) and multi-task operations
•
Adoption of system stack pointer
•
Enhanced pointer indirect instructions
•
Barrel shift instructions
Program patch function (2 address pointer)
Improved execution speed
•
4-byte instruction queue
Powerful interrupt function
•
Priority level programmable : 8 levels
•
32 factors of stronger interrupt function
Automatic data transmission function independent of CPU operation
•
Extended intelligent I/O service function (EI2 OS)
•
Maximum 16 channels
Low-power consumption (standby) mode
•
Sleep mode (mode in which CPU operating clock is stopped)
•
Timebase timer mode (mode in which operations other than timebase timer and watch timer
are stopped)
•
Stop mode (mode in which all oscillations are stopped)
•
CPU intermittent operation mode
•
Watch mode
Package
•
LQFP-144 (FPT-144P-M12 : 0.4 mm pitch)
Process
•
2
CMOS technology
MB90370 Series
PRODUCT LINEUP
Part number
Parameter
MB90V370
MB90F372
MB90372
—
Flash type ROM
Mask ROM
Classification
ROM size
—
RAM size
15.7K Bytes
CPU function
I/O port
16-bit reload timer
16-bit PPG timer
Bit decoder
64K Bytes
6K Bytes
Number of instruction
Minimum execution time
Addressing mode
Data bit length
Maximum memory space
: 351
: 62.5 ns / 4 MHz (PLL x 4)
: 23
: 1, 8, 16 bits
: 16 MBytes
I/O port (N-channel)
I/O port (CMOS)
I/O port (CMOS with pull-up control)
Total
: 16
: 72
: 32
: 120
Reload timer
: 4 channels
Reload mode, single-shot mode or event count mode selectable
PPG timer
: 3 channels
PWM mode or single-shot mode selectable
Bit decoder
: 1 channel
Parity generator
Selectable odd/even parity
: 1 channel
PS/2 interface
PS/2 interface
4 selectable sampling clocks
: 3 channels
LPC interface
LPC bus interface
Universal peripheral Interface
GA20 output control
Data buffer array
: 1 channel
: 4 channels
: for UPI channel 0 only
: 48 bytes
Serial IRQ request
LPC clock monitor / control
: 6 channels
Parity generator
Serial IRQ controller
UART
With full-duplex double buffer (variable data length)
Clock asynchronized or clock synchronized transmission (with start and stop bits) can be
selectively used
IC
I2C (SMbus compliant)
: 1 channel
Support I2C bus of PHILIPS and the SMbus proposed by Intel I2C bus
Selectable packet error check
Timeout detection function
Multi-address I2C
Multi-address I2C (SMbus compliant) : 1 channel
Support I2C bus of PHILIPS and the SMbus proposed by Intel I2C bus
Selectable packet error check
Timeout detection function
6 addresses support
ALERT function
2
Bridge circuit
Part number
Parameter
Comparator
Three bus connection routes can be switched by I2C / multi-address I2C
MB90V370
MB90F372
MB90372
A comparator that can change the hysteresis width is contained
Battery voltage, mounting/dismounting and instantaneous interruption can be
detected
Parallel and serial charging/discharging
3
MB90370 Series
Part number
Parameter
MB90V370
MB90F372
MB90372
External
interrupt
6 independent channels
Selectable causes
: Rise/fall edge, fall edge, “L” level or “H” level
Key-on wake-up
interrupt
8 independent channels
Causes
: “L” level
8/10-bit resolution
Conversion time
: 12 channels
: Less than 6.13 S (16 MHz internal clock)
8-bit resolution
: 2 channels
8/10-bit A/D
converter
8-bit D/A
converter
LCD controller/driver
Low-power
consumption
Up to 9 SEG x 4 COM
Selectable LCD output or CMOS I/O port
Stop mode / Sleep mode / CPU intermittent operation mode / Watch mode
Process
Package
CMOS
PGA256
LQFP-144 (FPT-144P-M12: 0.4 mm pitch)
Operating voltage
3.0~3.6 V @ 16 MHz *
*: Varies with conditions such as the operating frequency (see Section “ ELECTRICAL CHARACTERISTICS”).
Assurance for the MB90V370 is given only for operation with a tool at power supply voltage of 3.0 V to 3.6 V,
an operating temperature of 0 to +25 C, and an operating frequency of 1 MHz to 16 MHz.
PACKAGE AND CORRESPONDING PRODUCTS
Package
MB90V370
PGA256
FPT-144P-M12
MB90F372
MB90372
X
X
X
: Available
X : Not available
Note: For more information about each package, see Section “
PACKAGE DIMENSIONS”.
DIFFERENCES AMONG PRODUCTS
Memory size
In evaluation with an evaluation product, note the difference between the evaluation product and the product
actually used. The following items must be taken into consideration.
• The MB90V370 does not have an internal ROM, however, operations equivalent to chips with an internal ROM
can be evaluated by using a dedicated development tool, enabling selection of ROM size by settings of the
development tool.
• In the MB90V370, images from FF4000H to FFFFFF H are mapped to bank 00, and FF0000H to FF3FFFH are
mapped to bank FF only. (This setting can be changed by the development tool configuration.)
• In the MB90372/F372, images from FF4000H to FFFFFF H are mapped to bank 00, and FF0000H to FF3FFFH
are mapped to bank FF only.
4
MB90370 Series
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
P37/ADTG
P36
P35
P34
P33
P32
P31
P30
P27
P26
P25
P24
P23
P22
P21
X1
X0
Vss
Vcc
P20
P17
P16
P15
P14
P13
P12
P11
P10
P07/KSI7
P06/KSI6
P05/KSI5
P04/KSI4
P03/KSI3
P02/KSI2
P01/KSI1
P00/KSI0
PIN ASSIGNMENT
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
LQFP-144
(TOP VIEW)
(FPT-144P-M12)
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
P77/PPG1
P76/UI3
P75/UO3
P74/UCK3
P73/UI2
P72/UO2
P71/UCK2
P70/UI1
P67/UO1
P66/UCK1
P65/INT5
P64/INT4
P63/INT3
P62/INT2
P61/INT1
P60/INT0
PD7/PPG3
Vss
Vcc
PF7/V3*
PF6/V2*
PF5/V1*
PF4/COM3*
PF3/COM2*
PF2/COM1*
PF1/COM0*
PF0/SEG8*
PE7/TO4/SEG7
PE6/TIN4/SEG6
PE5/TO3/SEG5
PE4/TIN3/SEG4
PE3/TO2/SEG3
PE2/TIN2/SEG2
PE1/TO1/SEG1
PE0/TIN1/SEG0
P82/ALERT
PB3/VSI1
PB4/VOL2
PB5/VSI2
PB6/VOL3
PB7/VSI3
AVcc
AVR
AVss
PC0/AN0/SW1
PC1/AN1/SW2
PC2/AN2/SW3
PC3/AN3
PC4/AN4
PC5/AN5
PC6/AN6
PC7/AN7
PD0/AN8
Vcc
Vss
MD2
MD1
MD0
PD1/AN9
PD2/AN10
PD3/AN11
PD4/DA1
PD5/DA2
PD6/PPG2
P90/SCL2
P91/SDA2
P92/SCL3
P93/SDA3
P94/SCL4
P95/SDA4
P80/SCL1
P81/SDA1
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
P40/PSCK0
P41/PSDA0
P42/PSCK1
P43/PSDA1
P44/PSCK2
P45/PSDA2
P46/CLKRUN
P47/SERIRQ
P50/GA20
P51/LFRAME
P52/LRESET
P53/LCK
P54/LAD0
P55/LAD1
P56/LAD2
P57/LAD3
RST
Vcc
Vss
X0A
X1A
PA0/ALR1
PA1/ALR2
PA2/ALR3
PA3/ACO
PA4/OFB1
PA5/OFB2
PA6/OFB3
CVcc
CVRH1
CVRH2
CVRL
CVss
PB0/DCIN
PB1/DCIN2
PB2/VOL1
* Heavy current pins
5
MB90370 Series
PIN DESCRIPTION
Pin no.
Pin status
during
reset
Pin name
I/O circuit
128,129
X0,X1
A
Oscillating Main oscillation input pins.
20,21
X0A,X1A
A
Oscillating Sub-clock oscillation input pins.
17
RST
B
Reset input External reset input pin.
58, 57, 56
MD0 ~ 2
C
Mode input Input pin for operation mode specification. Connect this pin directly to Vcc or Vss.
LQFP-144
P00 ~ P07
109 ~ 116
General-purpose I/O ports.
D
Can be used as key-on wake-up interrupt input channel 0 ~ 7. Input is enabled when
1 is set in EICR: EN0 ~ 7 in standby mode.
KSI0 ~ KSI7
117 ~ 124
P10 ~ P17
E
General-purpose I/O ports.
125, 130~136
P20 ~ P27
E
General-purpose I/O ports.
137 ~ 143
P30 ~ P36
E
General-purpose I/O ports.
P37
144
General-purpose I/O ports.
E
ADTG
External trigger input pin (ADTG) for the A/D converter.
P40
1
General-purpose N-ch open-drain I/O port.
F
Serial clock I/O pin for PS/2 interface channel 0. This function is selected when PS/2
interface channel 0 is enabled.
PSCK0
P41
2
General-purpose N-ch open-drain I/O port.
F
Serial data I/O pin for PS/2 interface channel 0. This function is selected when PS/2
interface channel 0 is enabled.
PSDA0
P42
3
General-purpose N-ch open-drain I/O port.
F
PSCK1
P43
4
P44
5
PSCK2
P45
PSDA2
P46
CLKRUN
P47
Serial data I/O pin for PS/2 interface channel 2. This function is selected when PS/2
interface channel 2 is enabled.
LPC clock status / restart request I/O pin for serial IRQ controller. This function is
selected when serial IRQ and LPC clock restart request is enabled.
General-purpose I/O port.
H
SERIRQ
Serial clock I/O pin for PS/2 interface channel 2. This function is selected when PS/2
interface channel 2 is enabled.
General-purpose N-ch open-drain I/O port.
G
8
Serial data I/O pin for PS/2 interface channel 1. This function is selected when PS/2
interface channel 1 is enabled.
General-purpose N-ch open-drain I/O port.
F
7
Serial clock I/O pin for PS/2 interface channel 1. This function is selected when PS/2
interface channel 1 is enabled.
General-purpose N-ch open-drain I/O port.
F
6
Port input
General-purpose N-ch open-drain I/O port.
F
PSDA1
6
Function
Serial IRQ data I/O pin for serial IRQ controller. This function is selected when serial
IRQ is enabled.
MB90370 Series
(Continued)
Pin no.
Pin name
I/O circuit
LQFP-144
P50
9
GA20
P51
LFRAME
P52
LFRAME input for LPC interface. This function is selected when LPC interface is
enabled.
General-purpose I/O port.
H
LRESET
Reset input for LPC interface. This function is selected when LPC interface is enabled.
P53
12
General-purpose I/O port.
H
LCK
Clock input for LPC interface. This function is selected when LPC interface is enabled.
P54 ~ P57
13 ~ 16
GA20 output for LPC interface. This function is selected when GA20 function is
enabled.
General-purpose I/O port.
H
11
Function
General-purpose I/O port.
H
10
Pin status
during
reset
LAD0 ~
LAD3
General-purpose I/O ports.
H
P60 ~ P65
93 ~ 98
General-purpose I/O ports.
I
INT0 ~ INT5
P66
99
UCK1
I
UO1
P70
UI1
P71
UCK2
P72
UO2
P73
UI2
P74
UCK3
P75
Serial clock I/O pin for UART channel 3. This function is enabled when UART channel 3
enables clock output.
General-purpose I/O port.
I
UO3
Serial data input pin for UART channel 2. While UART channel 2 is operating for input,
the input of this pin is used as required and must not be used for any other input.
General-purpose I/O port.
I
106
Serial data output pin for UART channel 2. This function is enabled when UART
channel 2 enables data output.
General-purpose I/O port.
I
105
Serial clock I/O pin for UART channel 2. This function is enabled when UART channel 2
enables clock output.
General-purpose I/O port.
I
104
Serial data input pin for UART channel 1. While UART channel 1 is operating for input,
the input of this pin is used as required and must not be used for any other input.
General-purpose I/O port.
I
103
Serial data output pin for UART channel 1. This function is enabled when UART
channel 1 enables data output.
General-purpose I/O port.
I
102
Serial clock I/O pin for UART channel 1. This function is enabled when UART channel 1
enables clock output.
Port input General-purpose I/O port.
P67
101
Can be used as DTP/external interrupt request input channel 0 ~ 5. Input is enabled
when 1 is set in ENIR: EN0 ~ 5 in standby mode.
General-purpose I/O port.
I
100
Address/Data I/O for LPC interface. This function is selected when LPC interface is
enabled.
Serial data output pin for UART channel 3. This function is enabled when UART
channel 3 enables data output.
7
MB90370 Series
(Continued)
Pin no.
Pin name
I/O circuit
LQFP-144
Pin status
during reset
P76
107
General-purpose I/O port.
I
Serial data input pin for UART channel 3. While UART channel 3 is operating for
input, the input of this pin is used as required and must not be used for any other
input.
UI3
P77
108
General-purpose I/O port.
I
Output pin for PPG channel 1. This function is enabled when PPG channel 1
output is enabled.
PPG1
P80
71
General-purpose N-ch open-drain I/O port.
T
SCL1
Serial clock I/O pin for multi-address I2 C.
P81
72
General-purpose N-ch open-drain I/O port.
T
SDA1
Serial data I/O pin for multi-address I2C.
P82
73
General-purpose N-ch open-drain I/O port.
J
ALERT
ALERT output pin for multi-address I2C.
P90
65
General-purpose N-ch open-drain I/O port.
T
SCL2
Serial clock I/O pin for bridge circuit.
P91
66
General-purpose N-ch open-drain I/O port.
T
SDA2
Port input
P92
67
General-purpose N-ch open-drain I/O port.
Serial clock I/O pin for bridge circuit.
P93
68
General-purpose N-ch open-drain I/O port.
T
SDA3
Serial data I/O pin for bridge circuit.
P94
69
General-purpose N-ch open-drain I/O port.
T
SCL4
Serial clock I/O pin for bridge circuit.
P95
70
General-purpose N-ch open-drain I/O port.
T
SDA4
Serial data I/O pin for bridge circuit.
PA0 ~ PA2
ALR1 ~
ALR3
General-purpose I/O ports.
H
Alarm signal output when battery 1 ~ 3 run down in comparator circuit.
PA3
25
General-purpose I/O port.
H
ACO
AC power set signal output in comparator circuit.
PA4 ~ PA6
26 ~ 28
OFB1 ~
OFB3
General-purpose I/O ports.
H
Battery 1 ~ 3 discharge control signal output in comparator circuit.
PB0 ~ PB1
34, 35
DCIN ~
DCIN2
General-purpose I/O ports.
K
AC power monitoring input in comparator circuit.
Comparator
input
PB2
36
General-purpose I/O ports.
K
VOL1
8
Serial data I/O pin for bridge circuit.
T
SCL3
22 ~ 24
Function
Battery 1 power instantaneous interruption monitoring input in comparator circuit.
MB90370 Series
(Continued)
Pin no.
Pin name
I/O circuit
LQFP-144
Pin status
during reset
PB3
37
General-purpose I/O ports.
K
VSI1
Battery 1 indicator monitoring input in comparator circuit.
PB4
38
General-purpose I/O ports.
K
VOL2
Battery 2 power instantaneous interruption monitoring input in comparator circuit.
PB5
39
K
VSI2
Comparator General-purpose I/O ports.
input
Battery 2 indicator monitoring input in comparator circuit.
PB6
40
General-purpose I/O ports.
K
VOL3
Battery 3 power instantaneous interruption monitoring input in comparator circuit.
PB7
41
General-purpose I/O ports.
K
VSI3
Battery 3 indicator monitoring input in comparator circuit.
PC0 ~ PC2
45 ~ 47
Function
SW1 ~ SW3
General-purpose I/O ports.
L
AN0 ~ AN2
Comparator
input
Battery 1 ~ 3 mount / dismount detection input in comparator circuit.
or
A/D input A/D converter analog input pin 0 ~ 2. This function is enabled when the analog
input specification is enabled (ADER1).
PC3 ~ PC7
48 ~ 52
General-purpose I/O ports.
M
A/D converter analog input pin 3 ~ 7. This function is enabled when the analog
input specification is enabled (ADER1).
AN3 ~ AN7
A/D input
PD0 ~ PD3
53, 59 ~ 61
General-purpose I/O ports.
M
A/D converter analog input pin 8 ~ 11. This function is enabled when the analog
input specification is enabled (ADER2).
AN8 ~ AN11
PD4 ~ PD5
62 ~ 63
General-purpose I/O ports.
N
D/A converter analog output 1 ~ 2. This function is selected when D/A converted is
enabled.
DA1 ~ DA2
PD6 ~ PD7
64, 92
PPG2 ~
PPG3
General-purpose I/O port.
H
Output pin for PPG channel 2 ~ 3. This function is selected when PPG channel 2 ~
3 output is enabled.
PE0
74
SEG0
General-purpose I/O port.
Port input
TIN1
PE1
75
76
SEG1
Segment output pin for LCD controller/driver. This function is selected when LCD
segment output is enabled.
O
External clock input pin for reload timer 1.
General-purpose I/O port.
O
Segment output pin for LCD controller/driver. This function is selected when LCD
segment output is enabled.
TO1
Event output pin for reload timer 1.
PE2
General-purpose I/O port.
SEG2
TIN2
O
Segment output pin for LCD controller/driver. This function is selected when LCD
segment output is enabled.
External clock input pin for reload timer 2.
9
MB90370 Series
(Continued)
Pin no.
Pin name
I/O circuit
LQFP-144
Pin status
during
reset
PE3
77
78
79
SEG3
General-purpose I/O port.
Segment output pin for LCD controller/driver. This function is selected when LCD
segment output is enabled.
O
TO2
Event output pin for reload timer 2.
PE4
General-purpose I/O port.
SEG4
Segment output pin for LCD controller/driver. This function is selected when LCD
segment output is enabled.
O
TIN3
External clock input pin for reload timer 3.
PE5
General-purpose I/O port.
SEG5
Segment output pin for LCD controller/driver. This function is selected when LCD
segment output is enabled.
O
TO3
Event output pin for reload timer 3.
PE6
80
81
SEG6
Port input General-purpose I/O port.
Segment output pin for LCD controller/driver. This function is selected when LCD
segment output is enabled.
O
TIN4
External clock input pin for reload timer 4.
PE7
General-purpose I/O port.
SEG7
Segment output pin for LCD controller/driver. This function is selected when LCD
segment output is enabled.
O
TO4
Event output pin for reload timer 4.
PF0
82
General-purpose I/O port.
P
Segment output pin for LCD controller/driver. This function is selected when LCD
segment output is enabled.
SEG8
PF1 ~ PF4
83 ~ 86
COM0 ~
COM3
General-purpose I/O port.
P
COM output pin for LCD controller/driver. This function is selected when LCD COM
output is enabled.
PF5 ~ PF7
87 ~ 89
Q
V1 ~ V3
42
10
Function
AVCC
Power
input
R
General-purpose I/O port.
Power input pin for LCD controller/driver. This function is selected when external
voltage divider is enabled.
Vcc power input pin for analog circuits.
Power
input
Vref+ input pin for the A/D converter. This voltage must not exceed Vcc. Vref- is
fixed to AVSS.
43
AVR
S
44
AVSS
R
Vss power input pin for analog circuits.
29
CVCC
R
Vcc power input pin for analog circuits.
30
CVRH1
R
31
CVRH2
R
32
CVRL
R
33
CVSS
R
19,55,91,127
Vss
–
18,54,90,126
Vcc
–
Power
input
Standard power input pin of the comparator.
Vss power input pin for analog circuits.
Power
input
Power (0 V) input pin.
Power (3.3 V) input pin.
MB90370 Series
I/O CIRCUIT TYPE
Classification
Type
Remarks
X1/X1A
Xout
N-ch P-ch
A
P-ch
X0/X0A
N-ch
Main/Sub clock (main/sub clock
crystal oscillator)
• At an oscillation feedback
resistor of approximately 1
M
Standby mode control
B
• Hysteresis input
• Pull-up resistor
approximately 50 k
R
• Hysteresis input
C
R
P-ch
Pull-up control
P-ch
Pout
D
Nout
N-ch
• CMOS output
• Hysteresis input
• Selectable pull-up resistor
approximately 50 k
• IOL = 4 mA
Hysteresis input
Standby mode control
R
P-ch
Pull-up control
P-ch
E
N-ch
Pout
Nout
• CMOS output
• CMOS input
• Selectable pull-up resistor
approximately 50 k
• IOL = 4 mA
CMOS input
Standby mode control
N-ch
F
N-ch
Nout
Hysteresis input
•
•
•
•
N-ch open-drain output
Hysteresis input
IOL = 4 mA
5V tolerant
Standby mode control
11
MB90370 Series
Classification
Type
Remarks
P-ch
G
N-ch
Nout
• N-ch open-drain output
• CMOS input
• IOL = 4 mA
CMOS input
Standby mode control
P-ch
H
N-ch
Pout
Nout
• CMOS output
• CMOS input
• IOL = 4 mA
CMOS input
Standby mode control
P-ch
I
N-ch
Pout
Nout
• CMOS output
• Hysteresis input
• IOL = 4 mA
Hysteresis input
Standby mode control
N-ch
J
N-ch
Nout
CMOS input
•
•
•
•
N-ch open-drain output
CMOS input
IOL = 4 mA
5V tolerant
•
•
•
•
CMOS output
CMOS input
Comparator input
IOL = 4 mA
Standby mode control
P-ch
N-ch
Pout
Nout
K
CMOS input
Standby mode control
Comparator input
12
MB90370 Series
Classification
Type
P-ch
N-ch
Remarks
Pout
Nout
CMOS input
L
Standby mode control
Comparator input
•
•
•
•
•
CMOS output
CMOS input
Comparator input
A/D analog input
IOL = 4 mA
•
•
•
•
CMOS output
CMOS input
A/D analog input
IOL = 4 mA
•
•
•
•
CMOS output
CMOS input
D/A analog output
IOL = 4 mA
•
•
•
•
CMOS output
CMOS input
Segment output
IOL = 4 mA
Analog input
P-ch
M
N-ch
Pout
Nout
CMOS input
Standby mode control
Analog input
P-ch
N
N-ch
Pout
Nout
CMOS input
Standby mode control
Analog output
P-ch
O
N-ch
Pout
Nout
CMOS input
Standby mode control
Segment output
13
MB90370 Series
Classification
Type
Remarks
P-ch
P
Pout
Nout
N-ch
CMOS input
•
•
•
•
CMOS output
CMOS input
Segment output
IOL = 12 mA
•
•
•
•
CMOS output
CMOS input
LCD driving power supply
IOL = 12 mA
Standby mode control
Segment output
P-ch
Q
Pout
Nout
N-ch
CMOS input
Standby mode control
LCD driving power supply
P-ch
R
• Power supply input
protection circuit
IN
N-ch
P-ch
Analog input enable
S
IN
N-ch
• A/D converter reference
voltage (AVR) input pin with
protection circuit
Analog input enable
N-ch
T
N-ch
Nout
CMOS input
Standby mode control
14
•
•
•
•
N-ch open-drain output
CMOS input
IOL = 4 mA
5V tolerant
MB90370 Series
HANDLING DEVICES
Be sure that the maximum rated voltage is not exceeded (latch-up prevention).
A latch-up may occur on a CMOS IC if a voltage higher than VCC or lower than VSS is applied
to an input or output pin other than medium-to-high voltage pins. A latch-up may also occur if
a voltage higher than the rating is applied between VCC and VSS. A latch-up causes a rapid
increase in the power supply current, which can result in thermal damage to an element.
Take utmost care that the maximum rated voltage is not exceeded.
When turning the power on or off to analog circuits, be sure that the analog supply voltages
(AVCC, CVCC, AVR, CVRH1, CVRH2 and CVRL) and analog input voltage do not exceed the
digital supply voltage (VCC).
Stabilize the supply voltages
Even within the operation guarantee range of the VCC supply voltage, a malfunction can be
caused if the supply voltage undergoes a rapid change. For voltage stabilization guidelines,
the VCC ripple fluctuations (P-P value) at commercial frequencies (50 to 60 Hz) should be
suppressed to "10%" or less of the reference VCC value. During a momentary change such
as when switching a supply voltage, voltage fluctuations should also be suppressed so that
the "transient fluctuation rate" is 0.1 V/ms or less.
Power-on
To prevent a malfunction in the built-in voltage drop circuit, secure "50 s (between 0.2 V and
1.8 V)" or more for the voltage rise time during power-on.
Treatment of unused input pins
An unused input pin may cause a malfunction if it is left open. Every unused input pin should
be pulled up or down.
Treatment of A/D converter, D/A converter and comparator power pin
When the A/D converter, D/A converter and comparator is not used, connect the pins as
follows: AVCC = CVCC = VCC, AVSS = AVR = CVSS = CVRL = CVRH1 = CVRH2 = VSS.
Notes on external clock
When an external clock is used, the oscillation stabilization wait time is required at power-on
reset or at cancellation of sub-clock mode or stop mode. As shown in diagram below, when
an external clock is used, connect only the X0 pin and leave the X1 pin open.
X0
MB90370 series
Open
X1
15
MB90370 Series
Power supply pins
When a device has two or more VCC or VSS pins, the pins that should have equal potential are
connected within the device in order to prevent a latch-up or other malfunction. To reduce
extraneous emission, to prevent a malfunction of the strobe signal due to an increase in the
group level, and to maintain the local output current rating, connect all these power supply
pins to an external power supply and ground them.
The current source should be connected to the VCC and VSS pins of the device with minimum
impedance. It is recommended that a bypass capacitor of about 0.1 F be connected near
the terminals between VCC and VSS.
Analog power-on sequence of A/D converter, D/A converter and comparator
The power to the A/D converter, D/A converter and comparator (AVCC, CVCC, AVR, CVRH1,
CVRH2 and CVRL) and analog inputs (AN0 ~ AN11, VOL1 ~ 3, VSI1 ~ 3, SW1 ~ 3, DCIN
and DCIN2) must be turned on after the power to the digital circuits (VCC) is turned on. When
turning off the power, turn off the power to the digital circuits (VCC) after turning off the power
to the A/D converter, D/A converter, comparator and analog inputs. When the power is
turned on or off, AVR should not exceed AVCC. And CVRH1, CVRH2 and CVRL should not
exceed CVCC. Also, when a pin that is used for A/D analog input is also used as an input port,
the input voltage should not exceed AVCC. And when comparator analog input is also used as
an input port, the input voltage should not exceed CVCC. (The power to the analog circuits
and the power to the digital circuits can be simultaneously turned on or off.)
16
MB90370 Series
BLOCK DIAGRAM
X0, X0A
Clock control
circuit
X1, X1A
Reset circuit
(Watchdog timer)
RST
Other pins
Vss x 4, Vcc x 4, MD0-2, AVcc, AVss, CVcc, CVss
CPU
F2MC-16LX series core
Delayed interrupt generator
N-ch open-drain I/O port 8,9
Interrupt controller
P00/KSI0 to 8
P07/KSI7
P10 to P17
P20 to P27
P30 to P36
P37/ADTG
Timebase timer
I2C bus
(Multi-address)
CMOS I/O port 0,1,2,3*
I2C bus
8
8
Key-on wake-up
interrupt
8
8
P40/PSCK0
P41/PSDA0
P42/PSCK1
P43/PSDA1
P44/PSCK2
P45/PSDA2
P46/CLKRUN
P47/SERIRQ
Bridge circuit
N-ch open-drain I/O port 4
(P47 is CMOS I/O port)
6
2
P80/SCL1
P81/SDA1
P82/ALERT
P90/SCL2
P91/SDA2
P92/SCL3
P93/SDA3
P94/SCL4
P95/SDA4
3CH PS/2 interface
6
CMOS I/O port A,B
Comparator
Serial IRQ (6 channels)
Battery select circuit
7
LPC Interface
GateA20 control
7
Bus interface
P50/GA20
P51/LFRAME
P52/LRESET
P53/LCK
P54/LAD0
P55/LAD1
P56/LAD2
P57/LAD3
8
Voltage comparator
CVRH1, CVRH2, CVRL
AVR
A/D converter
CMOS I/O port 5
P60/INT0 to 6
P65/INT5
P66/UCK1
P67/UO1
P70/UI1
P71/UCK2
P72/UO2
P73/UI2
P74/UCK3
P75/UO3
P76/UI3
P77/PPG1
6
3
UPI
(Ch0,1,2,3)
DTP/External interrupt
UART
(Ch1,2,3)
12
(8/10 bit)
D/A converter
2
16-bit PPG
(Ch2,3)
16-bit PPG (Ch1)
CMOS I/O port C,D
CMOS I/O port 6,7
CMOS I/O port E,F
RAM
ROM
ROM correction
16-bit reload timer
(Ch1,2,3,4)
LCD controller
(9SEG x 4COM)
ROM mirroring
Note:
PA0/ALR1 to
PA2/ALR3
PA3/ACO
PA4/OFB1 to
PA6/OFB3
PB0/DCIN
PB1/DCIN2
PB2/VOL1
PB3/VSI1
PB4/VOL2
PB5/VSI2
PB6/VOL3
PB7/VSI3
P00 to P07, P10 to P17, P20 to P27, P30 to P37: With registers that can be used as input pull-up resistors
PF0 to PF7: High current pins
16
PC0/AN0/SW1
PC1/AN1/SW2
PC2/AN2/SW3
PC3/AN3 to
PC7/AN7
PD0/AN8 to
PD3/AN11
PD4/DA1
PD5/DA2
PD6/PPG2
PD7/PPG3
PE0/TIN1/SEG0
PE1/TO1/SEG1
PE2/TIN2/SEG2
PE3/TO2/SEG3
PE4/TIN3/SEG4
PE5/TO3/SEG5
PE6/TIN4/SEG6
PE7/TO4/SEG7
PF0/SEG8*
PF1/COM0* to
PF4/COM3*
PF5/V1* to
PF7/V3*
17
MB90370 Series
MEMORY MAP
Single-chip mode
(with ROM mirroring function)
FFFFFFH
ROM area
Address #1
FC0000H
010000H
ROM area
(FF bank image)
Address #2
004000H
003FC0H
Address #3
Peripheral area
RAM
area
Register
000100H
: Internal access memory
0000F8H
000000H
Peripheral area
: Access not allowed
Model
Address #1
Address #2
Address #3
MB90372
FF0000H
004000H
001900H
MB90F372
FF0000H
004000H
001900H
MB90V370
FF0000H*1
004000H*1
003FC0H
*1: The MB90V370 does not contain ROM. Assume that the development tool uses these area
for its ROM decode areas.
Notes:
18
•
If single-chip mode (without ROM mirroring function) is selected, see Chapter 31, "ROM
Mirroring Function Selection Module" of the MB90370 series H/W manual.
•
ROM data in the FF bank can be seen as an image in the higher 00 bank to validate the small
model C compiler. Because addresses of the 16 low-order bits in the FF bank are the same, the
table in ROM can be referenced without the "far" specification. For example, when 00C000H is
accessed, the contents of ROM at FFC000 H are actually accessed. The ROM area in the FF
bank exceeds 48 kilobytes, and all areas cannot be seen as images in the 00 bank. Because
ROM data from FF4000H to FFFFFFH is seen as an image at 004000H to 00FFFFH, the ROM
data table should be stored in the area from FF4000H to FFFFFFH.
MB90370 Series
F2MC-16LX CPU PROGRAMMING MODEL
• Dedicated registers
AH
AL
Accumulator (A)
USP
User Stack Pointer (USP)
SSP
System Stack Pointer (SSP)
PS
Processor Status (PS)
PC
Program Counter (PC)
DPR
Direct Page Register (DPR)
PCB
Program Bank Register (PCB)
DTB
Data Bank Register (DTB)
USB
User Stack Bank Register (USB)
SSB
System Stack Bank Register (SSB)
ADB
Additional Data Bank Register (ADB)
8 bits
16 bits
32 bits
19
MB90370 Series
• General-purpose registers
Dedicated register
General-purpose
register
Accumulator
User stack pointer
System stack pointer
Internal bus
Processor status
Program counter
Direct page register
Program bank register
Data bank register
User stack bank register
System stack bank register
Additional data bank register
• Processor status (PS)
15
13 12
PS
Default value
Default value
87
ILM
RP
000
00000
CCR
-01XXXXX
7
6
5
4
3
2
1
0
–
I
S
T
N
Z
V
C
–
0
1
X
X
X
X
X
B4 B3 B2 B1 B0
Default value
Default value
20
0
0
0
0
0
: CCR
: RP
0
ILM2
ILM1
ILM0
0
0
0
: ILM
- : Not used
X : Undefined
MB90370 Series
I/O MAP
Byte
access
Word
access
Resource name
Initial value
Port 0 data register
R/W
R/W
Port 0
XXXXXXXXB
PDR1
Port 1 data register
R/W
R/W
Port 1
XXXXXXXXB
000002H
PDR2
Port 2 data register
R/W
R/W
Port 2
XXXXXXXXB
000003H
PDR3
Port 3 data register
R/W
R/W
Port 3
XXXXXXXXB
000004H
PDR4
Port 4 data register
R/W
R/W
Port 4
X1111111B
000005H
PDR5
Port 5 data register
R/W
R/W
Port 5
XXXXXXXXB
000006H
PDR6
Port 6 data register
R/W
R/W
Port 6
XXXXXXXXB
000007H
PDR7
Port 7 data register
R/W
R/W
Port 7
XXXXXXXXB
000008H
PDR8
Port 8 data register
R/W
R/W
Port 8
-----111B
000009H
PDR9
Port 9 data register
R/W
R/W
Port 9
--111111B
00000AH
PDRA
Port A data register
R/W
R/W
Port A
-XXXXXXXB
Address
Abbreviation
000000H
PDR0
000001H
Register
00000BH
PDRB
Port B data register
R/W
R/W
Port B
XXXXXXXXB
00000CH
PDRC
Port C data register
R/W
R/W
Port C
XXXXXXXX B
00000DH
PDRD
Port D data register
R/W
R/W
Port D
XXXXXXXX B
00000EH
PDRE
Port E data register
R/W
R/W
Port E
XXXXXXXXB
00000F H
PDRF
Port F data register
R/W
R/W
Port F
XXXXXXXX B
000010H
DDR0
Port 0 direction register
R/W
R/W
Port 0
00000000B
000011H
DDR1
Port 1 direction register
R/W
R/W
Port 1
00000000B
000012H
DDR2
Port 2 direction register
R/W
R/W
Port 2
00000000B
000013H
DDR3
Port 3 direction register
R/W
R/W
Port 3
00000000B
000014H
DDR4
Port 4 direction register
R/W
R/W
Port 4
0-------B
000015H
DDR5
Port 5 direction register
R/W
R/W
Port 5
00000000B
000016H
DDR6
Port 6 direction register
R/W
R/W
Port 6
00000000B
000017H
DDR7
Port 7 direction register
R/W
R/W
Port 7
00000000B
000018H
PGDR
Parity generator data register
R/W
R/W
000019H
PGCSR
Parity generator control status
register
R/W
R/W
00001AH
DDRA
Port A direction register
R/W
R/W
Port A
-0000000B
00001BH
DDRB
Port B direction register
R/W
R/W
Port B
00000000B
00001CH
DDRC
Port C direction register
R/W
R/W
Port C
00000000B
00001DH
DDRD
Port D direction register
R/W
R/W
Port D
00000000B
XXXXXXXXB
Parity generator
X------0B
21
MB90370 Series
(Continued)
Address
Abbreviation
00001EH
DDRE
00001FH
DDRF
Byte
access
Word
access
Resource name
Initial value
Port E direction register
R/W
R/W
Port E
00000000B
Port F direction register
R/W
R/W
Port F
00000000B
Register
000020H
SMR1
Serial mode register 1
R/W
R/W
00000-00B
000021H
SCR1
Serial control register 1
R/W
R/W
00000100B
000022H
SIDR1/
SODR1
Input data register 1 /
Output data register 1
R/W
R/W
000023H
SSR1
Serial status register 1
R/W
R/W
00001000B
000024H
M2CR1
Mode 2 control register 1
R/W
R/W
----1000B
000025H
CDCR1
Clock division control register 1
R/W
R/W
000026H
ENIR
Interrupt / DTP enable register
R/W
R/W
000027H
EIRR
Interrupt / DTP cause register
R/W
R/W
R/W
R/W
R/W
R/W
000028H
ELVR
UART1
Communication
prescaler 1
XXXXXXXXB
00--0000B
--000000B
DTP/external
interrupt
--XXXXXXB
00000000B
Request level setting register
000029H
----0000B
00002AH
ADER1
Analog input enable register 1
R/W
R/W
Port C, A/D
11111111B
00002BH
ADER2
Analog input enable register 2
R/W
R/W
Port D, A/D
----1111B
00002CH
BRSR
Bridge circuit selection register
R/W
R/W
Bridge circuit
00002DH
ADC0
A/D control register
R/W
R/W
00002EH
ADCR0
R
R
A/D data register
00002FH
ADCR1
000030H
ADCS0
000031H
ADCS1
000032H
SICRL
000033H
--000000B
00000000B
XXXXXXXXB
8/10-bit A/D
converter
R/W
R/W
00000-XXB
R/W
R/W
00--------B
R/W
R/W
00000000B
Serial interrupt request register
R/W
R/W
00000000B
SICRH
Serial interrupt control register
R/W
R/W
00000000B
000034H
SIFR1
Serial interrupt frame number
register 1
R/W
R/W
--000000B
000035H
SIFR2
Serial interrupt frame number
register 2
R/W
R/W
000036H
SIFR3
Serial interrupt frame number
register 3
R/W
R/W
--000000B
000037H
SIFR4
Serial interrupt frame number
register 4
R/W
R/W
--000000B
000038H
PDCRL1
-
R
11111111B
-
R
11111111B
-
W
XXXXXXXXB
-
W
-
W
-
W
A/D control status register
Serial IRQ
--000000B
PPG1 down counter register
000039H
PDCRH1
00003AH
PCSRL1
00003BH
PCSRH1
00003CH
PDUTL1
PPG1 period setting register
16-bit PPG timer
(CH1)
XXXXXXXXB
XXXXXXXXB
PPG1 duty setting register
00003DH
PDUTH1
00003EH
PCNTL1
00003FH
PCNTH1
XXXXXXXXB
R/W
R/W
--000000B
R/W
R/W
00000000B
PPG1 control status register
22
MB90370 Series
(Continued)
Address
Abbreviation
000040H
PDCRL2
Register
Byte
access
Word
access
-
R
11111111B
-
R
11111111B
-
W
XXXXXXXXB
-
W
-
W
-
W
XXXXXXXXB
R/W
R/W
--000000B
Resource name
Initial value
PPG2 down counter register
000041H
PDCRH2
000042H
PCSRL2
000043H
PCSRH2
000044H
PDUTL2
PPG2 period setting register
16-bit PPG timer
(CH2)
XXXXXXXXB
XXXXXXXXB
PPG2 duty setting register
000045H
PDUTH2
000046H
PCNTL2
PPG2 control status register
000047H
PCNTH2
R/W
R/W
00000000B
000048H
PDCRL3
-
R
11111111B
-
R
11111111B
-
W
XXXXXXXXB
PPG3 down counter register
000049H
PDCRH3
00004AH
PCSRL3
PPG3 period setting register
00004BH
PCSRH3
-
W
00004CH
PDUTL3
-
W
-
W
XXXXXXXXB
R/W
R/W
--000000B
16-bit PPG timer
(CH3)
XXXXXXXXB
XXXXXXXXB
PPG3 duty setting register
00004DH
PDUTH3
00004EH
PCNTL3
PPG3 control status register
00004FH
PCNTH3
R/W
R/W
00000000B
000050H
PSCR0
PS/2 interface control register 0
R/W
R/W
0--00000B
000051H
PSSR0
PS/2 interface status register 0
R/W
R/W
00000000B
000052H
PSCR1
PS/2 interface control register 1
R/W
R/W
0--00000B
000053H
PSSR1
PS/2 interface status register 1
R/W
R/W
00000000B
000054H
PSCR2
PS/2 interface control register 2
R/W
R/W
000055H
PSSR2
PS/2 interface status register 2
R/W
R/W
000056H
PSDR0
PS/2 interface data register 0
R/W
R/W
00000000B
000057H
PSDR1
PS/2 interface data register 1
R/W
R/W
00000000B
000058H
PSDR2
PS/2 interface data register 2
R/W
R/W
00000000B
000059H
PSMR
PS/2 interface mode register
R/W
R/W
----0000B
00005AH
DAT0
D/A converter data register 0
R/W
R/W
XXXXXXXXB
3-channel PS/2
interface
0--00000B
00000000B
00005BH
DAT1
D/A converter data register 1
R/W
R/W
00005CH
DACR0
D/A control register 0
R/W
R/W
XXXXXXXXB
-------0B
00005DH
DACR1
D/A control register 1
R/W
R/W
-------0B
D/A converter
23
MB90370 Series
(Continued)
Address
Abbreviation
00005EH
UPAL1
00005FH
UPAH1
Word
access
UPI1 address register (lower)
R/W
R/W
XXXXXXXXB
UPI1 address register (upper)
R/W
R/W
XXXXXXXXB
Resource name
Initial value
000060H
UPAL2
UPI2 address register (lower)
R/W
R/W
XXXXXXXXB
000061H
UPAH2
UPI2 address register (upper)
R/W
R/W
XXXXXXXXB
000062H
UPAL3
UPI3 address register (lower)
R/W
R/W
XXXXXXXXB
000063H
UPAH3
UPI3 address register (upper)
R/W
R/W
XXXXXXXXB
000064H
UPCL
UPI control register (lower)
R/W
R/W
00000000B
000065H
UPCH
UPI control register (upper)
R/W
R/W
-000-000B
000066H
UPDI0/
UPDO0
UPI0 data input register / data
output register
R/W
R/W
XXXXXXXXB
000067H
UPS0
UPI0 status register
R/W
R/W
000068H
UPDI1/
UPDO1
UPI1 data input register / data
output register
R/W
R/W
XXXXXXXXB
000069H
UPS1
UPI1 status register
R/W
R/W
00000000B
00006AH
UPDI2/
UPDO2
UPI2 data input register / data
output register
R/W
R/W
XXXXXXXXB
00006BH
UPS2
UPI2 status register
R/W
R/W
00000000B
00006CH
UPDI3/
UPDO3
UPI3 data input register / data
output register
R/W
R/W
XXXXXXXXB
00006DH
UPS3
UPI3 status register
R/W
R/W
00000000B
00006EH
LCR
LPC control register
R/W
R/W
-----000B
00006FH
ROMM
W
W
000070H
TMCSRL1
Timer control status register CH1
(lower)
R/W
R/W
000071H
TMCSRH1
Timer control status register CH1
(upper)
R/W
R/W
000072H
TMR1/
TMRD1
-
R/W
XXXXXXXXB
000073H
ROM mirroring function selection
register
LPC interface
ROM mirroring
function
00000000B
-------1B
00000000B
16-bit reload
timer (CH1)
----0000B
16-bit timer/reload register CH1
000074H
TMCSRL2
Timer control status register CH2
(lower)
000075H
TMCSRH2
Timer control status register CH2
(upper)
000076H
TMR2/
TMRD2
000077H
24
Byte
access
Register
-
R/W
XXXXXXXXB
R/W
R/W
00000000B
R/W
R/W
-
R/W
XXXXXXXXB
-
R/W
XXXXXXXXB
16-bit reload
timer (CH2)
----0000B
16-bit timer/reload register CH2
MB90370 Series
(Continued)
Byte
access
Word
access
Timer control status register CH3
(lower)
R/W
R/W
TMCSRH3
Timer control status register CH3
(upper)
R/W
R/W
-
R/W
XXXXXXXXB
TMR3/TMRD3
16-bit timer/reload register CH3
-
R/W
XXXXXXXXB
00000000B
Address
Abbreviation
000078H
TMCSRL3
000079H
Register
00007AH
00007BH
Resource name
Initial value
00000000B
16-bit reload
timer (CH3)
----0000B
00007CH
TMCSRL4
Timer control status register CH4
(lower)
R/W
R/W
00007DH
TMCSRH4
Timer control status register CH4
(upper)
R/W
R/W
-
R/W
XXXXXXXXB
TMR4/TMRD4
16-bit timer/reload register CH4
00007EH
00007FH
000080H
IBCRL
16-bit reload
timer (CH4)
----0000B
-
R/W
XXXXXXXXB
2
R/W
R/W
----0000B
2
I C bus control register (lower)
000081H
IBCRH
I C bus control register (upper)
R/W
R/W
00000000B
000082H
IBSRL
I2C bus status register (lower)
R
R
00000000B
000083H
IBSRH
I2C bus status register (upper)
000084H
000085H
IDAR
IADR
R/W
R/W
--000000B
2
R/W
R/W
XXXXXXXXB
2
R/W
R/W
I C data register
I C address register
-XXXXXXXB
I2C
2
000086H
ICCR
I C clock control register
R/W
R/W
0-000000B
000087H
ITCR
I2C timeout control register
R/W
R/W
-0-00000B
000088H
ITOC
I2C timeout clock register
R/W
R/W
00000000B
000089H
ITOD
I2C timeout data register
00008AH
ISTO
R/W
R/W
00000000B
2
R/W
R/W
00000000B
2
00000000B
I C slave timeout register
00008BH
IMTO
I C master timeout register
R/W
R/W
00008CH
RDR0
Port 0 pull-up resistor setting
register
R/W
R/W
Port 0
00000000B
00008DH
RDR1
Port 1 pull-up resistor setting
register
R/W
R/W
Port 1
00000000B
00008EH
RDR2
Port 2 pull-up resistor setting
register
R/W
R/W
Port 2
00000000B
00008FH
RDR3
Port 3 pull-up resistor setting
register
R/W
R/W
Port 3
00000000B
000090H
~ 9DH
Prohibited area
00009EH
PACSR
Program address detect control
status register
R/W
R/W
Address match
detection
00000000B
00009FH
DIRR
Delayed interrupt cause / clear
register
R/W
R/W
Delayed
interrupt
-------0B
25
MB90370 Series
(Continued)
Address
Abbreviation
0000A0H
LPMCR
0000A1H
CKSCR
Byte
access
Word
access
Low-power consumption mode
register
R/W
R/W
Clock selection register
R/W
Register
0000A2H
~ A3H
0000A4H
Initial value
00011000B
R/W
Low-power
consumption
control register
R/W
Clock modulation
-------0B
11111100B
Prohibited area
CKMC
Clock modulation control register
0000A5H
~ A7H
R/W
Prohibited area
0000A8H
WDTC
Watchdog control register
R/W
R/W
Watchdog timer
X-XXX111B
0000A9H
TBTC
Timebase timer control register
R/W
R/W
Timebase timer
1--00100B
0000AAH
WTC
Watch timer control register
R/W
R/W
Watch timer
10001000B
Wake-up
interrupt
00000000B
0000ABH
Prohibited area
0000ACH
EICR
Wake-up interrupt control register
R/W
R/W
0000ADH
EIFR
Wake-up interrupt flag register
R/W
R/W
0000AEH
FMCS
Flash memory control status
register
R/W
R/W
0000B0H
ICR00
Interrupt control register 00
R/W
R/W
00000111B
0000B1H
ICR01
Interrupt control register 01
R/W
R/W
00000111B
0000B2H
ICR02
Interrupt control register 02
R/W
R/W
00000111B
0000B3H
ICR03
Interrupt control register 03
R/W
R/W
00000111B
0000B4H
ICR04
Interrupt control register 04
R/W
R/W
00000111B
0000B5H
ICR05
Interrupt control register 05
R/W
R/W
00000111B
0000B6H
ICR06
Interrupt control register 06
R/W
R/W
00000111B
0000B7H
ICR07
Interrupt control register 07
R/W
R/W
0000B8H
ICR08
Interrupt control register 08
R/W
R/W
0000B9H
ICR09
Interrupt control register 09
R/W
R/W
00000111B
0000BAH
ICR10
Interrupt control register 10
R/W
R/W
00000111B
0000BBH
ICR11
Interrupt control register 11
R/W
R/W
00000111B
0000BCH
ICR12
Interrupt control register 12
R/W
R/W
00000111B
0000BDH
ICR13
Interrupt control register 13
R/W
R/W
00000111B
0000BEH
ICR14
Interrupt control register 14
R/W
R/W
00000111B
0000BFH
ICR15
Interrupt control register 15
R/W
R/W
00000111B
0000AFH
26
Resource name
Flash memory
interface circuit
-------0B
00010000B
Prohibited area
Interrupt
controller
00000111B
00000111B
MB90370 Series
(Continued)
Address
Abbreviation
Register
Byte
access
Word
access
0000C0H
MBCRL
MI2C bus control register (lower)
0000C1H
MBCRH
Resource name
Initial value
R/W
R/W
----0000B
2
R/W
R/W
00000000B
2
R
R
00000000B
2
R/W
R/W
--000000B
2
R/W
XXXXXXXXB
MI C bus control register (upper)
0000C2H
MBSRL
0000C3H
MBSRH
0000C4H
MDAR
MI C data register
R/W
0000C5H
MALR
MI2C alert register
R/W
R/W
----0000B
0000C6H
MADR1
MI2C address register 1
0000C7H
MADR2
0000C8H
MADR3
MI C bus status register (lower)
MI C bus status register (upper)
R/W
R/W
-XXXXXXXB
2
R/W
R/W
-XXXXXXXB
2
R/W
R/W
MI C address register 2
MI C address register 3
-XXXXXXXB
MI2C
2
0000C9H
MADR4
MI C address register 4
R/W
R/W
-XXXXXXXB
0000CAH
MADR5
MI2C address register 5
R/W
R/W
-XXXXXXXB
0000CBH
MADR6
MI2C address register 6
R/W
R/W
-XXXXXXXB
0000CCH
MCCR
MI2C clock control register
0000CDH
MTCR
0000CEH
MTOC
R/W
R/W
0-000000B
2
R/W
R/W
-0-00000B
2
R/W
R/W
00000000B
2
MI C timeout control register
MI C timeout clock register
0000CFH
MTOD
MI C timeout data register
R/W
R/W
00000000B
0000D0H
MSTO
MI2C slave timeout register
R/W
R/W
00000000B
0000D1H
MMTO
MI2C master timeout register
R/W
R/W
00000000B
0000D2H
SMR2
Serial mode register 2
R/W
R/W
00000-00B
0000D3H
SCR2
Serial control register 2
R/W
R/W
00000100B
0000D4H
SIDR2/
SODR2
Input data register 2 /
output data register 2
R/W
R/W
UART2
XXXXXXXXB
0000D5H
SSR2
Status register 2
R/W
R/W
00001000B
0000D6H
M2CR2
Mode 2 control register 2
R/W
R/W
----1000B
0000D7H
CDCR2
Clock division control register 2
R/W
R/W
Communication
prescaler 2
00--0000B
27
MB90370 Series
(Continued)
Byte
access
Word
access
Comparator control register
(lower)
R/W
R/W
--000000B
COCRH
Comparator control register
(upper)
R/W
R/W
00011111B
0000DAH
COSRL1
Comparator status register 1
(lower)
R/W
R/W
00000000B
0000DBH
COSRH1
Comparator status register 1
(upper)
R/W
R/W
Address
Abbreviation
0000D8H
COCRL
0000D9H
Register
Initial value
--000000B
Voltage
comparator
0000DCH
CICRL
Comparator interrupt control
register (lower)
R/W
R/W
0000DDH
CICRH
Comparator interrupt control
register (upper)
R/W
R/W
--000000B
0000DEH
COSRL2
Comparator status register 2
(lower)
R
R
XXXXXXXXB
0000DFH
COSRH2
Comparator status register 2
(upper)
R
R
--XXXXXXB
0000E0H
CIER
Comparator input enable register
R/W
R/W
---11111B
0000E1H
BDR
Bit data register
R/W
R/W
----XXXXB
Bit decoder
00000000B
0000E2H
BRRL
Bit result register (lower)
R
R
0000E3H
BRRH
Bit result register (upper)
R
R
XXXXXXXXB
0000E4H
SMR3
Serial mode register 3
R/W
R/W
00000-00B
0000E5H
SCR3
Serial control register 3
R/W
R/W
00000100B
0000E6H
SIDR3 /
SODR3
Input data register 3 /
output data register 3
R/W
R/W
UART3
XXXXXXXXB
XXXXXXXXB
0000E7H
SSR3
Status register 3
R/W
R/W
00001000B
0000E8H
M2CR3
Mode 2 control register 3
R/W
R/W
----1000B
0000E9H
CDCR3
Clock division control register 3
R/W
R/W
Communication
prescaler 3
00--0000B
0000EAH
PDL3
Port 3 data latch register
R/W
R/W
Port 3 data latch
00000000B
0000EBH
~ EDH
28
Resource name
Prohibited area
0000EEH
LCRL
LCD control register 0
R/W
R/W
0000EFH
LCRH
LCD control register 1
R/W
R/W
0000F0H
~ F4H
VRAM
LCD display RAM
R/W
-
0000F5H
~ F7H
Prohibited area
0000F8H
~ FFH
External area
00010000B
LCD controller /
driver
00000000B
XXXXXXXXB
MB90370 Series
(Continued)
Address
Abbreviation
001FF0H
001FF1H
PADR0
001FF2H
001FF3H
001FF4H
001FF5H
PADR1
Byte
access
Word
access
Program address detection
register 0
R/W
R/W
XXXXXXXXB
Program address detection
register 1
R/W
R/W
XXXXXXXXB
Program address detection
register 2
R/W
R/W
Program address detection
register 3
R/W
R/W
XXXXXXXXB
Program address detection
register 4
R/W
R/W
XXXXXXXXB
Program address detection
register 5
R/W
R/W
XXXXXXXXB
Register
Resource name
Initial value
XXXXXXXXB
Address match
detection
29
MB90370 Series
(Continued)
30
Byte
access
Word
access
UP data register 0 (lower)
R/W
R/W
XXXXXXXXB
UDRH0
UP data register 0 (upper)
R/W
R/W
XXXXXXXXB
003FC2H
UDRL1
UP data register 1 (lower)
R/W
R/W
XXXXXXXXB
003FC3H
UDRH1
UP data register 1 (upper)
R/W
R/W
XXXXXXXXB
003FC4H
UDRL2
UP data register 2 (lower)
R/W
R/W
XXXXXXXXB
003FC5H
UDRH2
UP data register 2 (upper)
R/W
R/W
XXXXXXXXB
003FC6H
UDRL3
UP data register 3 (lower)
R/W
R/W
XXXXXXXXB
003FC7H
UDRH3
UP data register 3 (upper)
R/W
R/W
XXXXXXXXB
003FC8H
UDRL4
UP data register 4 (lower)
R/W
R/W
XXXXXXXXB
003FC9H
UDRH4
UP data register 4 (upper)
R/W
R/W
XXXXXXXXB
003FCAH
UDRL5
UP data register 5 (lower)
R/W
R/W
XXXXXXXXB
Address
Abbreviation
003FC0H
UDRL0
003FC1H
Register
Resource name
Initial value
003FCBH
UDRH5
UP data register 5 (upper)
R/W
R/W
XXXXXXXXB
003FCCH
UDRL6
UP data register 6 (lower)
R/W
R/W
XXXXXXXXB
003FCDH
UDRH6
UP data register 6 (upper)
R/W
R/W
XXXXXXXXB
003FCEH
UDRL7
UP data register 7 (lower)
R/W
R/W
XXXXXXXXB
003FCFH
UDRH7
UP data register 7 (upper)
R/W
R/W
XXXXXXXXB
003FD0H
UDRL8
UP data register 8 (lower)
R/W
R/W
XXXXXXXXB
003FD1H
UDRH8
UP data register 8 (upper)
R/W
R/W
003FD2H
UDRL9
UP data register 9 (lower)
R/W
R/W
003FD3H
UDRH9
UP data register 9 (upper)
R/W
R/W
XXXXXXXXB
003FD4H
UDRLA
UP data register A (lower)
R/W
R/W
XXXXXXXXB
003FD5H
UDRHA
UP data register A (upper)
R/W
R/W
XXXXXXXXB
003FD6H
UDRLB
UP data register B (lower)
R/W
R/W
XXXXXXXXB
003FD7H
UDRHB
UP data register B (upper)
R/W
R/W
XXXXXXXXB
003FD8H
UDRLC
UP data register C (lower)
R/W
R/W
XXXXXXXXB
003FD9H
UDRHC
UP data register C (upper)
R/W
R/W
XXXXXXXXB
003FDAH
UDRLD
UP data register D (lower)
R/W
R/W
XXXXXXXXB
LPC data buffer
array
XXXXXXXXB
XXXXXXXXB
003FDBH
UDRHD
UP data register D (upper)
R/W
R/W
XXXXXXXXB
003FDCH
UDRLE
UP data register E (lower)
R/W
R/W
XXXXXXXXB
003FDDH
UDRHE
UP data register E (upper)
R/W
R/W
XXXXXXXXB
003FDEH
UDRLF
UP data register F (lower)
R/W
R/W
XXXXXXXXB
003FDFH
UDRHF
UP data register F (upper)
R/W
R/W
XXXXXXXXB
003FE0H
DNDL0
DOWN data register 0 (lower)
R
R
XXXXXXXXB
003FE1H
DNDH0
DOWN data register 0 (upper)
R
R
XXXXXXXXB
003FE2H
DNDL1
DOWN data register 1 (lower)
R
R
XXXXXXXXB
003FE3H
DNDH1
DOWN data register 1 (upper)
R
R
XXXXXXXXB
MB90370 Series
(Continued)
Byte
access
Word
access
DOWN data register 2 (lower)
R
R
XXXXXXXXB
DNDH2
DOWN data register 2 (upper)
R
R
XXXXXXXXB
003FE6H
DNDL3
DOWN data register 3 (lower)
R
R
XXXXXXXXB
003FE7H
DNDH3
DOWN data register 3 (upper)
R
R
XXXXXXXXB
003FE8H
DNDL4
DOWN data register 4 (lower)
R
R
XXXXXXXXB
003FE9H
DNDH4
DOWN data register 4 (upper)
R
R
XXXXXXXXB
003FEAH
DNDL5
DOWN data register 5 (lower)
R
R
Address
Abbreviation
003FE4H
DNDL2
003FE5H
Register
Resource name
Initial value
XXXXXXXXB
LPC data buffer
array
003FEBH
DNDH5
DOWN data register 5 (upper)
R
R
003FECH
DNDL6
DOWN data register 6 (lower)
R
R
XXXXXXXXB
003FEDH
DNDH6
DOWN data register 6 (upper)
R
R
XXXXXXXXB
003FEEH
DNDL7
DOWN data register 7 (lower)
R
R
XXXXXXXXB
003FEFH
DNDH7
DOWN data register 7 (upper)
R
R
XXXXXXXXB
003FF0H
DBAAL
Data buffer array address
register (lower)
R/W
R/W
XXXXXXXXB
003FF1H
DBAAH
Data buffer array address
register (upper)
R/W
R/W
XXXXXXXXB
003FF2H
~ 003FFFH
XXXXXXXXB
Prohibited area
Meaning of abbreviations used for reading and writing
R/W: Read and write enabled
R:
Read-only
W:
Write-only
Explanation of initial values
0: The bit is initialized to 0.
1: The bit is initialized to 1.
X: The initial value of the bit is undefined.
-:
The bit is not used. Its initial value is undefined.
Instruction using IO addressing e.g. MOV A, io, is not supported for registers area
003FC0H to 003FFFH.
31
MB90370 Series
INTERRUPT FACTORS, INTERRUPT VECTORS, INTERRUPT CONTROL REGISTER
Interrupt cause
Interrupt vector
EI2OS
support
Number
Interrupt control
register
Address
ICR
Address
Reset
X
#08
08H
FFFFDCH
-
-
INT9 instruction
X
#09
09H
FFFFD8 H
-
-
Exception processing
X
#10
0AH
FFFFD4 H
-
-
A/D converter conversion termination
O
#11
0BH
FFFFD0 H
Timebase timer
#12
0CH
FFFFCCH
ICR00
0000B0H*1
UPI0 IBF / LPC reset
#13
0DH
FFFFC8 H
UPI1 IBF
#14
0EH
FFFFC4 H
ICR01
0000B1H*1
UPI2 IBF
#15
0FH
FFFFC0 H
UPI3 IBF
#16
10H
FFFFBCH
ICR02
0000B2H*1
ICR03
0000B3H*1
ICR04
0000B4H*1
ICR05
0000B5H*2
ICR06
0000B6H*1
ICR07
0000B7H*1
ICR08
0000B8H*1
ICR09
0000B9H*1
ICR10
0000BAH*1
ICR11
0000BBH*1
ICR12
0000BCH*1
ICR13
0000BDH*1
ICR14
0000BEH*1
ICR15
0000BF H*1
DTP/ext. interrupt channels 0/1 detection
O
#17
11H
FFFFB8H
DTP/ext. interrupt channels 2/3 detection
O
#18
12H
FFFFB4H
DTP/ext. interrupt channels 4/5 detection
O
#19
13H
FFFFB0H
#20
14H
FFFFACH
#21
15H
FFFFA8H
#22
16H
FFFFA4H
Wake-up interrupt detection
UPI0/1/2/3 OBE
16-bit PPG timer 1
O
PS/2 interface 0/1
#23
17H
FFFFA0H
PS/2 interface 2
#24
18H
FFFF9CH
Watch timer
#25
19H
FFFF98H
I2C transfer complete / bus error
#26
1AH
FFFF94H
16-bit PPG timer 2/3
#27
1BH
FFFF90H
Voltage comparator 1
O
#28
1CH
FFFF8CH
MI2C transfer complete / bus error
#29
1DH
FFFF88H
Voltage comparator 2
#30
1EH
FFFF84H
I2C timeout / standby wake-up
#31
1FH
FFFF80H
O
#32
20H
FFFF7CH
#33
21H
FFFF78H
O
#34
22H
FFFF74H
UART1 receive
#35
23H
FFFF70H
UART1 send
#36
24H
FFFF6CH
UART2 receive
#37
25H
FFFF68H
UART2 send
#38
26H
FFFF64H
UART3 receive
#39
27H
FFFF60H
UART3 send
#40
28H
FFFF5CH
Flash memory status
#41
29H
FFFF58H
Delayed interrupt generator module
#42
2AH
FFFF54H
16-bit reload timer 1/2 underflow
MI2C timeout / standby wake-up
16-bit reload timer 3/4 underflow
O: Can be used and interrupt request flag is cleared by EI2OS interrupt clear signal.
X: Cannot be used.
: Can be used and support the EI2OS stop request.
: Can be used.
32
Priority
*2
High
Low
MB90370 Series
*1: -
For peripheral functions that share the ICR register, the interrupt level will be the same.
-
If the extended intelligent I/O service is to be used with a peripheral function that shares
the ICR register with another peripheral function, the service can be started by either of
the function. And if EI2OS clear is supported, both interrupt request flags for the two
interrupt causes are cleared by EI2OS interrupt clear signal. It is recommended to mask
either of the interrupt request during the use of EI2OS.
-
EI2OS service cannot be started multiple times simultaneously. Interrupt other than the
operating interrupt is masked during EI2OS operation. It is recommended to mask either
of the interrupt requests during the use of EI2 OS.
*2: This priority is applied when interrupts of the same level occur simultaneously.
33
MB90370 Series
PERIPHERAL RESOURCES
1. Low-power Consumption Control Circuit
The MB90370 series has the following CPU operating mode selected by the configuration of an operating clock
and clock operation control.
Clock Mode
•
PLL clock mode
In this mode, a PLL clock that is a multiple of the oscillation clock (HCLK) is used to operate
the CPU and peripheral functions.
•
Main clock mode
In this mode, the main clock, with the oscillation clock (HCLK) frequency divided by 2 is used
to operate the CPU and peripheral functions. In the main clock mode, the PLL multiplier
circuit is inactive.
•
Sub-clock mode
In this mode, the sub-clock, with the sub-clock (SCLK) frequency divided by 4 is used to
operate the CPU and peripheral functions. In the sub-clock mode, the main clock and PLL
multiplier circuit are inactive.
Reference
For the clock mode, see Section 4.4 "Clock Mode" of the MB90370 series H/W manual.
CPU Intermittent Operating Mode
In this mode, the CPU is operated intermittently while high-speed clock pluses are supplied to
peripheral functions, thereby reducing power consumption. In this mode, intermittent clock
pulses are supplied only to the CPU while it is accessing a register, internal memory,
peripheral function, or external unit.
Standby Mode
In this mode, the low-power consumption control circuit stops supplying the clock to the CPU
(sleep mode) or the CPU and peripheral functions (timebase timer mode) or stops the
oscillation clock itself (stop mode), thereby reducing power consumption.
•
PLL sleep mode
The PLL sleep mode is activated to stop the CPU operating clock in the PLL clock mode.
Components excluding the CPU operate on the PLL clock.
•
Main sleep mode
The main sleep mode is activated to stop the CPU operating clock in the main clock mode.
Components excluding the CPU operate on the main clock.
•
Sub-sleep mode
The sub-sleep mode is activated to stop the CPU operating clock in the sub-clock mode.
Components excluding the CPU operate on the divided-by-four sub-clock.
•
Timebase timer mode
The timebase timer mode causes the operation of functions, excluding the oscillation clock,
timebase timer, and watch timer, to stop. All functions other than the timebase timer and
watch timer are inactivated.
34
MB90370 Series
•
Watch mode and main watch mode
The watch mode and main watch mode operates the watch timer only. The sub-clock
operates but the main clock and PLL multiplier circuit stop.
•
Stop mode
The stop mode causes the oscillation to stop. All functions are inactivated.
Note
Because the stop mode turns the oscillation clock off, data can be retained by the lowest
power consumption.
(1) Register configuration
Clock Selection Register
Address: 0000A1H
Read/write
Initial value
15
14
13
12
11
10
9
8
SCM
MCM
WS1
WS0
SCS
MCS
CS1
CS0
R
1
R
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
0
R/W
0
Lower Power Consumption Mode Control Register
7
6
5
Address: 0000A0H
Read/write
Initial value
Bit number
4
3
2
1
0
STP
SLP
SPL
RST
TMD
CG1
CG0
Reserved
W
0
W
0
R/W
0
W
1
W
1
R/W
0
R/W
0
R/W
0
CKSCR
Bit number
LPMCR
35
MB90370 Series
(2) Block diagram
Low power consumption mode control register (LPMCR)
STP SLP SPL RST TMD CG1 CG0
RESV
Pin highimpedance
control circuit
Internal reset
Internal reset
generation
circuit
Intermittent cycle
selection
RSTX Pin
CPU intermittent
operation selector
CPU clock
control circuit
Standby
control circuit
2
Pin Hi-Z control
CPU clock pulse
Stop and sleep signals
Interrupt clearing
Stop signal
Machine clock
Oscillation stabilization wait clearing
Clock generation part
Peripheral
clock control
circuit
Oscillation
stabilization
wait time
selector
Clock selector
2
Divideby-4
Sub-clock
X0A
Pin
X1A
Pin
2
PLL multiplier
circuit
Sub-clock
generation
circuit
System clock
generation
circuit
X0
Pin
X1
Pin
SCM MCM WS1 WS0 SCS MCS CS1 CS0
Clock selection register (CKSCR)
Divideby-2
Main clock
36
Peripheral clock
Divideby-8
Divideby-16
Divideby-128
Divideby-4
Divideby-8
Timebase timer
MB90370 Series
2. I/O Ports
(1) Outline of I/O ports
Each I/O port outputs data from the CPU to the I/O pins or inputs signals from the I/O pins to the CPU as directed
by the port data register (PDR). Each CMOS I/O port can also designate the direction of a data flow (input or
output) at the I/O pins in bit units using the port data direction register (DDR). Or N-channel open-drain port can
designate the direction of a data flow (input or output) at the I/O pins in bit units using the port data register
(PDR). The function of each port and the resources using it are described below:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Port 0
Port 1
Port 2
Port 3
Port 4
Port 5
Port 6
Port 7
Port 8
Port 9
Port A
Port B
Port C
Port D
Port E
Port F
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
General-purpose I/O port/resource (Key-on wake-up interrupt)
General-purpose I/O port
General-purpose I/O port
General-purpose I/O port/resource (A/D converter external trigger)
General-purpose I/O port/resource (PS/2 interface / serial IRQ controller)
General-purpose I/O port/resource (LPC interface)
General-purpose I/O port/resource (DTP / UART1)
General-purpose I/O port/resource (UART1 / UART2 / UART3 / PPG1)
General-purpose I/O port/resource (Multi-address I2C)
General-purpose I/O port/resource (I2C / Multi-address I2C)
General-purpose I/O port/resource (Comparator)
General-purpose I/O port/resource (Comparator)
General-purpose I/O port/resource (Comparator / A/D converter)
General-purpose I/O port/resource (A/D converter / D/A converter / PPG2 / PPG3)
General-purpose I/O port/resource (Reload timer1 ~ 4 / LCD controller)
General-purpose I/O port/resource (LCD controller)
(2) Register configuration
Register
Read/Write
Address
Initial value
Port 0 data register (PDR0)
R/W
000000H
XXXXXXXXB
Port 1 data register (PDR1)
R/W
000001H
XXXXXXXXB
Port 2 data register (PDR2)
R/W
000002H
XXXXXXXXB
Port 3 data register (PDR3)
R/W
000003H
XXXXXXXXB
Port 4 data register (PDR4)
R/W
000004H
X1111111 B
Port 5 data register (PDR5)
R/W
000005H
XXXXXXXXB
Port 6 data register (PDR6)
R/W
000006H
XXXXXXXXB
Port 7 data register (PDR7)
R/W
000007H
XXXXXXXXB
Port 8 data register (PDR8)
R/W
000008H
-----111B
Port 9 data register (PDR9)
R/W
000009H
--111111B
Port A data register (PDRA)
R/W
00000AH
-XXXXXXXB
Port B data register (PDRB)
R/W
00000BH
XXXXXXXXB
Port C data register (PDRC)
R/W
00000CH
XXXXXXXXB
Port D data register (PDRD)
R/W
00000DH
XXXXXXXXB
Port E data register (PDRE)
R/W
00000EH
XXXXXXXXB
Port F data register (PDRF)
R/W
00000F H
XXXXXXXXB
Port 0 data direction register (DDR0)
R/W
000010H
00000000B
37
MB90370 Series
Register
Read/Write
Initial value
Port 1 data direction register (DDR1)
R/W
000011H
00000000B
Port 2 data direction register (DDR2)
R/W
000012H
00000000B
Port 3 data direction register (DDR3)
R/W
000013H
00000000B
Port 4 data direction register (DDR4)
R/W
000014H
0-------B
Port 5 data direction register (DDR5)
R/W
000015H
00000000B
Port 6 data direction register (DDR6)
R/W
000016H
00000000B
Port 7 data direction register (DDR7)
R/W
000017H
00000000B
Port A data direction register (DDRA)
R/W
00001AH
-0000000B
Port B data direction register (DDRB)
R/W
00001BH
00000000B
Port C data direction register (DDRC)
R/W
00001CH
00000000B
Port D data direction register (DDRD)
R/W
00001DH
00000000B
Port E data direction register (DDRE)
R/W
00001EH
00000000B
Port F data direction register (DDRF)
R/W
00001FH
00000000B
Analog data input enable register (ADER1)
R/W
00002AH
11111111B
Analog data input enable register (ADER2)
R/W
00002BH
----1111B
Comparator input enable register (CIER)
R/W
0000E0H
---11111B
LCD control register 1 (LCRH)
R/W
0000EFH
00000000B
Port 0 pull-up resistor setting register (RDR0)
R/W
00008CH
00000000B
Port 1 pull-up resistor setting register (RDR1)
R/W
00008DH
00000000B
Port 2 pull-up resistor setting register (RDR2)
R/W
00008EH
00000000B
Port 3 pull-up resistor setting register (RDR3)
R/W
00008F H
00000000B
Port 3 data latch register (PDL3)
R/W
0000EAH
00000000B
R/W : Read/write enabled
38
Address
R
: Read-only
X
: Undefined
–
: Not used
MB90370 Series
(3) Block diagram of I/O ports
• Block diagram of port 0 pins
RDR
Resource input
Port data register (PDR)
Pull-up resistor
About 50K
Internal data bus
PDR read
Output latch
PDR write
Pin
Port data direction register (DDR)
Direction latch
DDR write
DDR read
Standby control (SPL = 1)
• Block diagram of port 1 pins
RDR
Port data register (PDR)
Pull-up resistor
About 50K
PDR read
Output latch
PDR write
Pin
Port data direction register (DDR)
Direction latch
DDR write
DDR read
Standby control (SPL = 1)
39
MB90370 Series
• Block diagram of port 2 pins
RDR
Port data register (PDR)
Pull-up resistor
About 50K
Internal data bus
PDR read
Output latch
PDR write
Pin
Port data direction register (DDR)
Direction latch
DDR write
DDR read
Standby control (SPL = 1)
• Block diagram of port 3 pins
RDR
Port data register (PDR)
Resource input
Pull-up resistor
About 50K
Internal data bus
PDR read
Output latch
PDR write
Pin
Port data direction register (DDR)
Direction latch
DDR write
DDR read
Standby control (SPL = 1)
Port data latch register (PDL)
Input latch
R
40
MB90370 Series
• Block diagram of port 47 pin
Resource output
Resource input
Resource output enable
Port data register (PDR)
Internal data bus
PDR read
Output latch
PDR write
Pin
Port data direction register (DDR)
Direction latch
DDR write
DDR read
Standby control (SPL = 1)
• Block diagram of port 46 pin
Resource output
Resource input
Resource output enable
Port data register (PDR)
Internal data bus
PDR read
Output latch
PDR write
Pin
Read-Modify-Write instruction
Standby control (SPL = 1)
41
MB90370 Series
• Block diagram of port 45 ~ 40 pins
Resource output
Resource input
Resource output enable
Port data register (PDR)
Internal data bus
PDR read
Output latch
PDR write
Pin
Read-Modify-Write instruction
Standby control (SPL = 1)
• Block diagram of port 5 pins
Resource output
Resource input
Resource output enable
Port data register (PDR)
Internal data bus
PDR read
Output latch
PDR write
Pin
Port data direction register (DDR)
Direction latch
DDR write
DDR read
42
Standby control (SPL = 1)
MB90370 Series
• Block diagram of port 6 pins
Resource output
Resource input
Resource output enable
Port data register (PDR)
Internal data bus
PDR read
Output latch
PDR write
Pin
Port data direction register (DDR)
Direction latch
DDR write
DDR read
Standby control (SPL = 1)
• Block diagram of port 7 pins
Resource output
Resource input
Resource output enable
Port data register (PDR)
Internal data bus
PDR read
Output latch
PDR write
Pin
Port data direction register (DDR)
Direction latch
DDR write
DDR read
Standby control (SPL = 1)
43
MB90370 Series
• Block diagram of port 8 pins
Resource output
Resource input
Resource output enable
Port data register (PDR)
Internal data bus
PDR read
Output latch
PDR write
Pin
Read-Modify-Write instruction
Standby control (SPL = 1)
• Block diagram of port 9 pins
Resource output
Resource input
Resource output enable
Port data register (PDR)
Internal data bus
PDR read
Output latch
PDR write
Pin
Read-Modify-Write instruction
Standby control (SPL = 1)
44
MB90370 Series
• Block diagram of port A pins
Resource output
Resource output enable
Port data register (PDR)
Internal data bus
PDR read
Output latch
PDR write
Pin
Port data direction register (DDR)
Direction latch
DDR write
DDR read
Standby control (SPL = 1)
• Block diagram of port B pins
CIER
Port data register (PDR)
Internal data bus
PDR read
Output latch
PDR write
Pin
Port data direction register (DDR)
Direction latch
DDR write
Standby control (SPL = 1)
DDR read
Comparator
operation
enable
Comparator input
45
MB90370 Series
• Block diagram of port C7 ~ C3 pins
ADER
Port data register (PDR)
Internal data bus
PDR read
Output latch
PDR write
Pin
Port data direction register (DDR)
Direction latch
DDR write
Standby control (SPL = 1)
A/D converter
channel
selection bit
DDR read
to A/D converter analog input
• Block diagram of port C2 ~ C0 pins
CIER
Comparator
ADER
Comparator operation
enable bit
(COCRH)
Port data register (PDR)
Internal data bus
PDR read
Output latch
PDR write
Pin
Port data direction register (DDR)
Direction latch
A/D converter
channel
selection bit
DDR write
Standby control (SPL = 1)
DDR read
to A/D converter analog input
46
MB90370 Series
• Block diagram of port D7 ~ D6 pins
Resource output
Resource output enable
Port data register (PDR)
Internal data bus
PDR read
Output latch
PDR write
Pin
Port data direction register (DDR)
Direction latch
DDR write
DDR read
Standby control (SPL = 1)
• Block diagram of port D5 ~ D4 pins
Port data register (PDR)
PDR read
Output latch
PDR write
Pin
Port data direction register (DDR)
Direction latch
DDR write
DDR read
Standby control (SPL = 1)
Analog output
D/A output enable
47
MB90370 Series
• Block diagram of port D3 ~ D0 pins
ADER
A/D input
Port data register (PDR)
PDR read
Output latch
PDR write
Pin
Port data direction register (DDR)
Direction latch
DDR write
DDR read
Standby control (SPL = 1)
• Block diagram of port E pins
Resource output
Resource input
Resource output enable
Port data register (PDR)
PDR read
Output latch
PDR write
Pin
Port data direction register (DDR)
Direction latch
DDR write
DDR read
Standby control (SPL = 1)
LCD output
LCD output enable
48
MB90370 Series
• Block diagram of port F7 ~ F5 pins
LCRH
VS
LCD input (V1~3)
Port data register (PDR)
PDR read
Output latch
PDR write
Pin
Port data direction register (DDR)
Direction latch
DDR write
DDR read
Standby control (SPL = 1)
• Block diagram of port F4 ~ F0 pins
Port data register (PDR)
PDR read
Output latch
PDR write
Pin
Port data direction register (DDR)
Direction latch
DDR write
DDR read
Standby control (SPL = 1)
LCD output
LCD output enable
49
MB90370 Series
3. Timebase timer
The timebase timer is an 18-bit free-running counter (timebase counter) that counts up in synchronization with
the internal count clock (one-half of the source oscillation).
Features of timebase timer :
• Interrupt generated when counter overflow
• EI2OS supported
• Interval timer function :
An interrupt generated at four different time intervals
• Clock supply function :
Four different clock can be selected as watchdog timer’s count clock
Supply clock for oscillation stabilization
(1) Register configuration
Timebase Timer Control Register
15
Address: 0000A9H
12
11
10
9
8
Reserved
TBIE
TBOF
TBR
TBC1
TBC0
R/W
1
R/W
0
R/W
0
W
1
R/W
0
R/W
0
Read/write
Initial value
14
13
Bit number
TBTC
(2) Block diagram of timebase timer
To watchdog timer
Timebase
timer counter
Divide-by
-two HCLK
21
22
23
...
27
...
28
29
210
211
OF
Power-on reset
Stop mode start
CKSCR: MCS = 1 0 (*1)
SCS = 1 0 (*2)
212
213
OF
214
215
216
OF
217
218
OF
To the oscillation
stabilization wait
time selector in the
clock control
section
Counter
clear circuit
Interval
timer selector
TBOF set
Timebase timer
interrupt signal
#12 (0CH)
: Unused
RESV —
—
TBIE TBOF TBR TBC1 TBC0
OF:Overflow
Timebase timer interrupt register (TBTC)
HCLK: Oscillation clock
*1 Switching of the machine clock from the oscillation clock to the PLL clock
*2 Switching from main clock to sub-clock
50
MB90370 Series
4. Watchdog timer
The watchdog timer is a 2-bit counter that uses the timebase timer’s supply clock as the count clock. After
activation, if the watchdog timer is not cleared within a given period, the CPU will be reset.
• Features of watchdog timer :
Reset CPU at four different time intervals
Status bits to indicate the reset causes
(1) Register configuration of watchdog timer
Watchdog Timer Control Register
7
Address: 0000A8H
5
4
3
2
1
0
PONR
WRST
ERST
SRST
WTE
WT1
WT0
R
X
R
X
R
X
R
X
W
1
W
1
W
1
Read/write
Initial value
6
Bit number
WDTC
(2) Block diagram of watchdog timer
Watchdog timer control register (WDTC)
WRST ERST SRST WTE
PONR
WT1
WT0
2
Watchdog timer
Activation with CLR
Start of watch mode
Start of sleep mode
Start of stop mode
reset generation
WDCS (from watch timer
control register, WTC)
Count
Counter
clear control
circuit
2-bit
counter
clock
selector
Overflow
CLR
To the
internal
reset
generator
Watchdog
reset
generator
CLK
4
4
(Timebase timer counter)
One-half of HCLK
Sub-clock divide by 4
X2
1
X22
X21 X22
...
X28 X29 X210 X211 X212 X213 X214 X215 X216 X217 X218
.........
X210 X211 X212 X2 13 X214 X215
Watch timer counter
HCLK: Oscillation clock
51
MB90370 Series
5. Watch timer
The watch timer is a 15-bit timer that uses sub-clocks and can generate an interval interrupt. It can also be used
as the watchdog timer clock source and sub-clock oscillation wait time.
Features of the watch timer :
• Provides the watchdog timer clock source
• Sub-clock oscillation stabilization wait timer function
• Interval timer function that generates interrupts in a given cycle
(1) Register configuration of watch timer
Watch Timer Control Register
Address: 0000AAH
Read/write
Initial value
7
6
5
4
3
2
WDCS
SCE
WTIE
WTOF
WTR
WTC2
R
0
R/W
0
R/W
0
W
1
R/W
0
R/W
1
1
0
WTC1 WTC0
R/W
0
Bit number
WTC
R/W
0
(2) Block diagram of watch timer
Watch timer control register (WTC)
WDCS
SCE
WTIE
WTOF
WTR
Clear
The subclock
divided by 4
213
214
WTC1
WTC0
28
29
210
211
212
213
214
215
Watch counter
210
WTC2
Interval selector
Interrupt
generator
Watch
timer
interrupt
215
To the watchdog
timer
52
MB90370 Series
6. 16-bit PPG timer (x 3)
The 16-bit PPG (Programmable Pulse Generator) timer consists of a 16-bit down counter, prescaler, 16-bit
period setting register, 16-bit duty setting register, 16-bit control register and a PPG output pin.
Features of 16-bit PPG timer :
• 8 types of counter operation clock ( , /2, /4, /8, /16, /32, /64, /128) can be selected ( is the machine
clock)
• An interrupt is generated when there is a trigger or an counter borrow or when PPG rising (normal polarity) /
PPG falling (inverted polarity)
• PPG output operation
The 16-bit PPG timer can output pulse waveforms with variable period and duty ratio. Also, it can be used as
D/A converter in conjunction with an external circuit.
(1) Register configuration of PPG timer
PPG Down Counter Register (Upper)
Address: ch1 000039H
ch2 000041H
ch3 000049H
Read/write
Initial value
15
14
12
11
10
9
8
Bit number
PDCRH1 ~ 3
DC15 DC14 DC13 DC12 DC11 DC10 DC09 DC08
R
1
R
1
R
1
R
1
R
1
R
1
R
1
R
1
7
6
5
4
3
2
1
PPG Down Counter Register (Lower)
Address: ch1 000038H
ch2 000040H
ch3 000048H
13
0
PDCRL1 ~ 3
DC07 DC06 DC05 DC04 DC03 DC02 DC01 DC00
Read/write
Initial value
R
1
R
1
R
1
R
1
R
1
R
1
R
1
R
1
PPG Period Setting Buffer Register (Upper)
15
14
13
12
11
10
9
8
Address: ch1 00003BH
ch2 000043H
ch3 00004BH CS15 CS14 CS13 CS12 CS11 CS10 CS09 CS08
Read/write
Initial value
W
X
W
X
PPG Period Setting Buffer Register (Lower)
Address: ch1 00003AH
ch2 000042H
ch3 00004AH
Read/write
Initial value
7
W
X
W
X
W
X
W
X
W
X
W
X
6
5
4
3
2
1
W
X
W
X
W
X
W
X
W
X
W
X
Bit number
PCSRH1 ~ 3
0
CS07 CS06 CS05 CS04 CS03 CS02 CS01 CS00
W
X
Bit number
Bit number
PCSRL1 ~ 3
W
X
53
MB90370 Series
(Continued)
PPG Duty Setting Buffer Register (Upper)
15
14
13
12
11
10
9
8
Address: ch1 00003DH
ch2 000045H
ch3 00004DH DU15 DU14 DU13 DU12 DU11 DU10 DU09 DU08
Read/write
Initial value
W
X
PPG Duty Setting Buffer Register (Lower)
Address: ch1 00003CH
ch2 000044H
ch3 00004CH
W
X
W
X
W
X
W
X
W
X
W
X
W
X
7
6
5
4
3
2
1
Bit number
PDUTH1 ~ 3
0
Bit number
PDUTL1 ~ 3
DU07 DU06 DU05 DU04 DU03 DU02 DU01 DU00
Read/write
Initial value
W
X
W
X
W
X
W
X
W
X
W
X
W
X
W
X
PPG Control Status Register (Upper)
15
Address: ch1 00003FH
ch2 000047H
ch3 00004FH
14
13
12
11
10
9
8
Bit number
PCNTH1 ~ 3
CNTE STGR MDSE RTRG CKS2
Read/write
Initial value
R/W
0
R/W
0
CKS1 CKS0 PGMS
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
6
5
4
3
2
IREN
IRQF
IRS1
IRS0
POEN OSEL
R/W
0
R/W
0
R/W
0
R/W
0
PPG Control Status Register (Lower)
7
Address: ch1 00003EH
ch2 000046H
ch3 00004EH
Read/write
Initial value
-
-
1
R/W
0
Note : Registers PDCR1 ~ 3, PCSR1 ~ 3 and PDUT1 ~ 3 are word access only
54
R/W
0
0
Bit number
PCNTL1 ~ 3
MB90370 Series
(2) Block diagram of PPG timer
Duty setting buffer register 1/2/3
Period setting buffer register 1/2/3
Prescaler
CKS1
CKS0
Period setting register 1/2/3
1/1
1/2
1/4
1/8
1/16
1/32
1/64
1/128
Duty setting register 1/2/3
Comparator
CLK
LOAD
16-bit down counter
MDSE PGMS OSEL POEN
STOP
START
BORROW
Machine clock
P77/PPG1
or
PD6/PPG2
or
PD7/PPG3
Pin
S
Down counter register 1/2/3
Q
R
Interrupt
selection
Gate input
CKS2
IRS1
IRS0
Interrupt
#22 (for PPG1)
or
#27 (for PPG2/3)
IRQF
IREN
STGR CNTE RTRG
55
MB90370 Series
7. 16-bit reload timer (x 4)
The 16-bit reload timer provides two operating mode, internal clock mode and event count mode. In each
operating mode, the 16-bit down counter can be reloaded (reload mode) or stopped when underflow (one-shot
mode).
Output pins TO1 ~ TO4 are able to output different waveform according to the counter operating mode. TO1 ~
TO4 toggles when counter underflow if counter is operated as reload mode. TO1 ~ TO4 output specified level
(“H” or “L”) when counter is counting if the counter is in one-shot mode.
Features of the 16-bit reload timer :
• Interrupt generated when timer underflow
• EI2OS supported
• Internal clock operating mode :
Three internal count clocks can be selected
Counter can be activated by software or external trigger (signal at TIN1 ~ TIN4 pin)
Counter can be reloaded or stopped when underflow after activated
• Event count operating mode :
Counter counts down by one when specified edge at TIN1 ~ TIN4 pin
Counter can be reloaded or stopped when underflow
(1) Register configuration of reload timer
Timer Control Status Register (Upper)
Address: ch1 000071H
ch2 000075H
ch3 000079H
ch4 00007DH
Read/write
Initial value
15
14
13
12
11
CSL1
R/W
0
10
9
8
CSL0 MOD2
R/W
0
Bit number
MOD1
R/W
0
R/W
0
TMCSRH1 ~ 4
Timer Control Status Register (Lower)
Address: ch1 000070H
ch2 000074H
ch3 000078H
ch4 00007CH
Read/write
Initial value
7
MOD0
R/W
0
6
5
OUTE OUTL
R/W
0
R/W
0
3
2
1
0
Bit number
RELD
INTE
UF
CNTE
TRG
TMCSRL1 ~ 4
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
4
16-bit Timer Register / 16-bit Reload Register (Upper)
Address: ch1 000073H
ch2 000077H
ch3 00007BH
ch4 00007FH
Read/write
Initial value
15
14
13
12
11
10
9
8
Bit number
D15
D14
D13
D12
D11
D10
D09
D08
R/W
X
R/W
X
TMR1 ~ 4 /
TMRD1 ~ 4
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
3
2
1
0
Bit number
D03
D02
D01
D00
R/W
X
R/W
X
TMR1 ~ 4 /
TMRD1 ~ 4
16-bit Timer Register / 16-bit Reload Register (Lower)
Address: ch1 000072H
ch2 000076H
ch3 00007AH
ch4 00007EH
Read/write
Initial value
56
7
6
5
4
D07
D06
D05
D04
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
MB90370 Series
(2) Block diagram of reload timer
F2MC-16LX Bus
TMRD0*1
TMRD1*1
<TMRD1>
<TMRD2,3,4>
16-bit reload register
Reload signal
TMR1*1
<TMR2,3,4>
Reload control circuit
16-bit timer register
Count clock generation
circuit
Machine
clock
Gate
input
Prescaler
Valid
clock
judgment
circuit
Wait signal
To UART1*1
<UART2/3,
A/D converter>
Clear
PE0/TIN1/SEG0
PE2/TIN2/SEG2
PE4/TIN3/SEG4
PE6/TIN4/SEG6
Pin
P15
Internal
clock
Input
control
circuit
Output control circuit
Clock
selector
Invert
Output signal
generation
circuit
Pin
PE1/TO1/SEG1
PE3/TO2/SEG3
PE5/TO3/SEG5
PE7/TO4/SEG7
External clock
Select
signal
Function selection
Timer control status register TMCSR1*1
<TMCSR2,3,4>
Operation
control
circuit
Interrupt request signal
#32 (20H)*1*2
<#34 (22H)>
*1 This register includes channel 1,2,3 and 4. The register enclosed in < and > indicates the
channel 2,3 and 4 register.
*2 Interrupt number, channel 1 and 2 share one interrupt number, channel 3 and 4 share another
57
MB90370 Series
8. I2C
The I2 C (Inter IC Bus) interface is a simple structure bidirectional bus consisting of two wires : a serial data line
(SDA) and a serial clock line (SCL). Among the devices connected with these two wires, information is transmitted
to one another. By recognizing the unique address of each device, it can operate as a transmitting or receiving
device in accordance with the function of each device. Among these devices, the master/slave relation is
established.
The I2C interface can connect two or more devices to the bus provided the upper limit of the bus capacitance
does not exceed 400 pF. It is a full-fledged multi-master bus equipped with collision detection and communication
adjustment procedures designed to avoid the destruction of data if two or more masters attempt to start data
transfer simultaneously.
The communication adjustment procedure permits only one master to control the bus when two or more masters
attempt to control the bus so that messages are not lost or the contents of messages are not changed. Multimaster means that multiple masters attempt to control the bus simultaneously without losing messages.
This I2C interface includes MCU standby mode wake-up function, and a CRC-8 calculator that performs automatic
Packet Error Code (PEC) generation and verification.
(1) Register configuration of I2C
I2C Bus Control Register (Lower)
7
6
5
4
Address: 000080H
Read/write
Initial value
-
3
2
1
RES
PECE
LBT
WUE
R/W
0
R/W
0
R/W
0
R/W
0
-
-
-
15
14
13
12
11
10
9
BER
BEIE
SCC
MSS
ACK
GCAA
R/W
0
R/W
0
R/W
0
R/W
0
0
Bit number
IBCRL
I2C Bus Control Register (Upper)
Address: 000081H
Read/write
Initial value
R/W
0
R/W
0
8
Bit number
INTE
INT
IBCRH
R/W
0
R/W
0
I2C Bus Status Register (Lower)
7
Address: 000082H
Read/write
Initial value
BB
R
0
6
RSC
R
0
5
4
3
2
1
0
AL
LRB
TRX
AAS
GCA
FBT
R
0
R
0
R
0
R
0
R
0
R
0
12
11
10
9
Bit number
IBSRL
I2C Bus Status Register (Upper)
15
14
PMATCH
WUF
TDR
TCR
-
-
R
0
R/W
0
R/W
0
R/W
0
7
6
5
4
3
D7
D6
D5
D4
R/W
X
R/W
X
R/W
X
R/W
X
Address: 000083H
Read/write
Initial value
13
8
Bit number
MTR
STR
IBSRH
R/W
0
R/W
0
2
1
0
Bit number
D3
D2
D1
D0
IDAR
R/W
X
R/W
X
R/W
X
R/W
X
I2C Data Register
Address: 000084H
Read/write
Initial value
(Continued)
58
MB90370 Series
(Continued)
I2C Address Register
15
14
13
12
11
10
A6
A5
A4
A3
-
R/W
X
R/W
X
R/W
X
R/W
X
7
6
5
4
3
EN
CS4
CS3
CS2
-
R/W
0
R/W
0
R/W
0
R/W
0
14
13
12
11
TOE
EXT
Address: 000085H
Read/write
Initial value
9
8
Bit number
A2
A1
A0
R/W
X
R/W
X
R/W
X
2
1
0
Bit number
CS1
CS0
ICCR
R/W
0
R/W
0
IADR
I2C Clock Control Register
Address: 000086H
DMBP
Read/write
Initial value
R/W
0
I2C Timeout Control Register
15
Address: 000087H
Read/write
Initial value
AAC
-
R/W
0
7
6
C7
R/W
0
-
R/W
0
R/W
0
5
4
C6
C5
R/W
0
10
TS2
9
TS1
8
Bit number
TS0
ITCR
R/W
0
R/W
0
R/W
0
3
2
1
0
Bit number
C4
C3
C2
C1
C0
ITOC
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
14
13
12
11
10
9
8
D7
D6
D5
D4
D3
D2
D1
D0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
I2C Timeout Clock Register
Address: 000088H
Read/write
Initial value
I2C Timeout Data Register
15
Address: 000089H
Read/write
Initial value
Bit number
ITOD
I2C Slave Timeout Register
7
6
5
4
3
2
1
0
Bit number
S6
S6
S5
S4
S3
S2
S1
S0
ISTO
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
15
14
13
12
11
10
9
8
Address: 00008BH
M7
M6
M5
M4
M3
M2
M1
M0
Read/write
Initial value
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Address: 00008AH
Read/write
Initial value
I2C Master Timeout Register
Bit number
IMTO
59
MB90370 Series
(2) Block diagram of I2C
I 2 C enable
ICCR
Peripheral clock
Clock frequency divider 1
DMBP
5
EN
6
7
8
Clock selector 1
CS4
CS3
Clock frequency divider 2
CS2
CS1
CS0
4
8
16
32
64
128
256
Clock selector 2
IBSRL
BB
Shift clock
generator
Shift clock edge
Bus busy
RSC
Repeat start
LRB
Last bit
Transmission/
reception
TRX
Sync
512
Start/stop condition
detector
Error
First byte
FBT
AL
Arbitration lost detector
IBCRH
BER
BEIE
Interrupt #26
INTE
INT
End
Start
Master
Enables ACK
SCC
MSS
ACK
Start/stop condition
generator
Enables GC-ACK
GCAA
CRC-8 calculator
IBCRL
LBT
IDAR register
IBSRL
Slave
AAS
GCA
Slave address comparator
General call
IADR register
ITCR
Timeout detector
SCL line
IBSRH
TDR
TCR
MTR
SDA line
STR
ITOD
IBCRL
Interrupt #31
ITOC
ISTO
IMTO
60
WUE
WUF
IBSRH
MB90370 Series
9. MI2C
The Multi-address I2C (Inter IC Bus) interface is a simple structure bidirectional bus consisting of two wires : a
serial data line (SDA) and a serial clock line (SCL). Among the devices connected with these two wires, information is transmitted to one another. By recognizing the unique address of each device, it can operate as a
transmitting or receiving device in accordance with the function of each device. Among these devices, the master/
slave relation is established.
The Multi-address I2C interface can connect two or more devices to the bus provided the upper limit of the bus
capacitance does not exceed 400 pF. It is a full-fledged multi-master bus equipped with collision detection and
communication adjustment procedures designed to avoid the destruction of data if two or more masters attempt
to start data transfer simultaneously. This macro provides 6 addresses to implement the multi-address function.
The communication adjustment procedure permits only one master to control the bus when two or more masters
attempt to control the bus so that messages are not lost or the contents of messages are not changed. Multimaster means that multiple masters attempt to control the bus simultaneously without losing messages.
This Multi-address I2 C interface includes MCU standby mode wake-up function, and a CRC-8 calculator that
performs automatic Packet Error Code (PEC) generation and verification.
(1) Register configuration of MI2C
Multi-address I2C Bus Control Register (Lower)
7
6
5
4
Address: 0000C0H
Read/write
Initial value
-
-
3
2
1
RES
PECE
R/W
0
R/W
0
R/W
0
LBT
-
-
12
11
10
9
ACK
GCAA
0
WUE
Bit number
MBCRL
R/W
0
Multi-address I 2C Bus Control Register (Upper)
15
14
13
8
Bit number
Address: 0000C1H
BER
BEIE
SCC
MSS
Read/write
Initial value
INTE
INT
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
MBCRH
R/W
0
R/W
0
4
3
2
1
0
AL
LRB
TRX
AAS
GCA
FBT
R
0
R
0
R
0
R
0
R
0
12
11
10
9
PMATCH
WUF
TDR
TCR
MTR
-
R
0
R/W
0
R/W
0
7
6
5
4
3
D7
D6
D5
D4
R/W
X
R/W
X
R/W
X
R/W
X
Multi-address I2C Bus Status Register (Lower)
7
Address: 0000C2H
Read/write
Initial value
BB
R
0
6
5
RSC
R
0
Bit number
MBSRL
R
0
Multi-address I 2C Bus Status Register (Upper)
15
14
Address: 0000C3H
Read/write
Initial value
-
13
R/W
0
R/W
0
8
Bit number
STR
MBSRH
R/W
0
Multi-address I2C Data Register
Address: 0000C4H
Read/write
Initial value
2
1
0
Bit number
D3
D2
D1
D0
MDAR
R/W
X
R/W
X
R/W
X
R/W
X
(Continued)
61
MB90370 Series
(Continued)
Multi-address I2C Alert Register
15
14
13
12
Address: 0000C5H
Read/write
Initial value
-
-
-
11
10
ARAE
ARO
ARF
AEN
R/W
0
R/W
0
R/W
0
R/W
0
-
9
8
Bit number
MALR
Multi-address I2C Address Register 1/3/5
7
6
Address ch1 : 0000C6H
Address ch3 : 0000C8H
Address ch5 : 0000CAH
Read/write
Initial value
5
4
3
2
1
0
Bit number
MADR1/3/5
-
A6
A5
A4
A3
A2
A1
A0
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
Multi-address I2C Address Register 2/4/6
15
Address ch2 : 0000C7H
Address ch4 : 0000C9H
Address ch6 : 0000CBH
Read/write
Initial value
14
13
12
11
10
9
8
Bit number
MADR2/4/6
-
A6
A5
A4
A3
A2
A1
A0
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
Multi-address I2C Clock Control Register
7
Address: 0000CCH
Read/write
Initial value
6
DMBP
-
R/W
0
5
4
3
2
1
0
EN
CS4
CS3
CS2
CS1
CS0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
13
12
11
10
TOE
EXT
Bit number
MCCR
Multi-address I2C Timeout Control Register
15
Address: 0000CDH
14
AAC
Read/write
Initial value
-
-
R/W
0
R/W
0
R/W
0
3
TS2
R/W
0
9
TS1
R/W
0
8
Bit number
TS0
MTCR
R/W
0
Multi-address I2C Timeout Clock Register
2
1
0
Bit number
C3
C2
C1
C0
MTOC
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
13
12
11
10
9
8
D6
D5
D4
D3
D2
D1
D0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
7
6
5
4
Address: 0000CEH
C7
C6
C5
C4
Read/write
Initial value
R/W
0
R/W
0
R/W
0
14
D7
R/W
0
Multi-address I2C Timeout Data Register
15
Address: 0000CFH
Read/write
Initial value
62
Bit number
MTOD
MB90370 Series
(Continued)
Multi-address I2C Slave Timeout Register
Address: 0000D0H
Read/write
Initial value
7
6
5
4
3
2
1
0
Bit number
S6
S6
S5
S4
S3
S2
S1
S0
MSTO
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Multi-address I2C Master Timeout Register
15
14
13
12
11
10
9
8
Address: 0000D1H
M7
M6
M5
M4
M3
M2
M1
M0
Read/write
Initial value
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit number
MMTO
63
MB90370 Series
(2) Block diagram of MI2C
Multi-address I2 C enable
MCCR
DMBP
5
EN
6
8
16
32
64
128
256
Sync
512
Clock selector 2
Shift clock
generator
Shift clock edge
Bus busy
RSC
Repeat start
LRB
Last bit
Transmission/
reception
TRX
8
Clock frequency divider 2
4
MBSRL
BB
7
Clock selector 1
CS4
CS3
CS2
CS1
CS0
Peripheral clock
Clock frequency divider 1
Start/stop condition
detector
Error
First byte
FBT
AL
Arbitration lost detector
MBCRH
BER
BEIE
Interrupt #29
INTE
INT
SCC
MSS
ACK
End
Start
Master
Enables ACK
Start/stop condition
generator
Enables GC-ACK
GCAA
CRC-8 calculator
MBCRL
LBT
MDAR register
MBSRL
Slave
AAS
GCA
Slave address comparator
General call
MADR1~6 registers
MTCR
Timeout detector
SCL line
MBSRH
TDR TCR MTR STR
MALR
MTOD
MTOC
MMTO
MSTO
SDA line
ARAE
ARO
ARF
AEN
64
MBCRL
ALERT line
WUE
WUF
MBSRH
Interrupt #33
MB90370 Series
10. Bridge circuit
The bridge circuit can switch the I/O path of each port to I2C or Multi-address I2C.
(1) Register configuration of bridge circuit
Bridge Circuit Selection Register
7
6
Address: 00002CH
Read/write
Initial value
5
4
3
2
1
0
Bit number
BM4
BI4
BM3
BI3
BM2
BI2
BRSR
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
(2) Block diagram of bridge circuit
I2C I/O
P81/SDA1
P80/SCL1
Multi-address I2C
BRSR
P91/SDA2
P90/SCL2
BM2
P93/SDA3
P92/SCL3
BM3
P95/SDA4
P94/SCL4
BM4
I2C
BI2
BI3
BI4
65
MB90370 Series
11. Comparator
This comparator circuit monitors voltage of up to three batteries and automatically controls electric discharge.
Either parallel discharge or sequential discharge can be selected.
• Parallel discharge control
In parallel discharge control, all batteries are allowed to discharge when power is not being supplied from
the AC adapter.
• If power is being supplied from the AC adapter, the permission/prohibition of discharge for batteries is
controlled by software.
• Sequential discharge control
In sequential discharge control, the comparator controls discharge in a specified order, while monitoring
intermittent interruption of power, voltage level, and mount/dismount of batteries, when power is not being
supplied from the AC adapter.
• If power is being supplied from the AC adapter, the permission/prohibition of discharge for batteries is
controlled by software.
• Up to three batteries can be controlled, and the order of discharge can be selected.
66
•
The affect of intermittent interruption of power is automatically filtered.
•
Mount/dismount of batteries is automatically detected and discharge is controlled.
•
Battery voltage is monitored, and if battery voltage is below the specified voltage, change
over to the next battery is automatically done.
MB90370 Series
(1) Register configuration of comparator
Comparator Control Register (Lower)
7
6
Address: 0000D8H
Read/write
Initial value
5
3
2
1
0
SPM1
SPM0
R/W
0
R/W
0
R/W
0
BOF1 SPM2
BOF3
BOF2
R/W
0
R/W
0
R/W
0
-
-
4
Bit number
COCRL
Comparator Control Register (Upper)
8
Bit number
DC1
COCRH
15
14
13
12
11
10
9
Address: 0000D9H
SPL3
SPL2
SPL1
B3
B2
B1
DC2
Read/write
Initial value
R/W
0
R/W
0
R/W
0
R/W
1
6
5
4
COR7
COR6
COR5
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
14
13
12
11
10
SW1
VAR3
VAR2
R/W
0
R/W
0
R/W
0
R/W
0
2
1
0
R/W
1
R/W
1
R/W
1
R/W
1
2
1
0
Bit number
COR2
COR1
COSRL1
R/W
0
R/W
0
Comparator Status Register 1 (Lower)
7
Address: 0000DAH
COR8
Read/write
Initial value
R/W
0
3
COR4 COR3
Comparator Status Register 1 (Upper)
15
Address: 0000DBH
Read/write
Initial value
SWR3 SWR2
-
-
9
8
VAR1
R/W
0
R/W
0
6
5
4
CEN7
CEN6
CEN5
CEN4
CEN3
CEN2
CEN1
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit number
COSRH1
Comparator Interrupt Control Register (Lower)
7
Address: 0000DCH
Read/write
Initial value
CEN8
R/W
0
3
Bit number
CICRL
(Continued)
67
MB90370 Series
(Continued)
Comparator Interrupt Control Register (Upper)
15
14
Address: 0000DDH
Read/write
Initial value
-
-
13
12
11
10
8
SEN3
SEN2
SEN1
VEN3
VEN2
VEN1
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
5
4
9
Bit number
CICRH
Comparator Status Register 2 (Lower)
7
Address: 0000DEH
Read/write
Initial value
6
COS8
COS7
R
X
R
X
R
X
R
X
14
13
12
SWS3
SWS2
COS6 COS5
3
2
1
0
COS4
COS3
COS2
COS1
R
X
R
X
R
X
R
X
Bit number
COSRL2
Comparator Status Register 2 (Upper)
15
Address: 0000DFH
Read/write
Initial value
-
-
11
10
SWS1 VAL3
R
X
R
X
R
X
5
4
3
9
8
Bit number
VAL2
VAL1
COSRH2
R
X
R
X
R
X
2
1
0
BIE1
DIE2
DIE1
Comparator Input Enable Register
7
6
Address: 0000E0H
Read/write
Initial value
68
BIE3
-
-
-
R/W
1
BIE2
R/W
1
R/W
1
R/W
1
R/W
1
Bit number
CIER
MB90370 Series
(2) Block diagram of comparator
Pin
PB0/DCIN
Battery selection circuit
Pin
CVRH2
SW
+
Pin
PA3/ACO
-
Pin
Comparator 1
CVRL
IN
OUT
RH
RL (Voltage
Pin
PB1/DCIN2
comparator 2)
Pin
CVRH1
PB5/VSI2
+
Pin
PC1/AN1/SW2
SW
Battery
VSI supervisory
circuit 2
ALARM
IN
OUT
RH (Voltage
RL comparator 6)
Pin
SPL
VALID
VOL
IN
OUT
RH (Voltage
RL comparator 5)
Pin
PB4/VOL2
SW
Pin
PA4/OFB1
O12
SW
Pin
PA1/ALR2
OFB
Comparator 2
IN
OUT
RH (Voltage
RL comparator 7)
Pin
PB6/VOL3
VALID
Battery
VSI supervisory
circuit 3
IN
OUT
RH (Voltage
RL comparator 8)
Pin
PB7/VSI3
O13
ALARM
+
-
Pin
PC2/AN2/SW3
SPL
VOL
SW
SW
Pin
PA2/ALR3
OFB
Comparator 3
Pin
IN
OUT
RH (Voltage
RL comparator 3)
PB2/VOL1
Battery
VSI supervisory
circuit 1
IN
OUT
RH (Voltage
RL comparator 4)
Pin
PB3/VSI1
O21
O23
ALARM
+
-
Pin
PC0/AN0/SW1
SPL
VALID
VOL
SW
SW
Pin
PA5/OFB2
SW
Pin
PA0/ALR1
OFB
Comparator 4
Pin
Watch
prescaler
XOA
Pin
O31
X1A
Power-on
reset
Pin
SW
Pin
PA6/OFB3
O32
VCC
Pin
RSTX
8
3
3
SPL3 SPL2 SPL1 B3
B2
B1
DC2 DC1
3
(COCRH) Comparator control register (upper)
3
COS8 COS7 COS6 COS5 COS4 COS3 COS2 COS1
6
(COSRL2) Comparator status register 2 (lower)
COR8 COR7 COR6 COR5 COR4 COR3 COR2 COR1
SWR3 SWR2 SWR1 VAR3 VAR2 VAR1
(COSRL1) Comparator status register 1 (lower)
(COSRH1) Comparator status register 1 (upper)
interrupt request
#28
(CICRH) Comparator interrupt control register (upper)
interrupt request
#30
SEN3 SEN2 SEN1 VEN3 VEN2 VEN1
(CICRL) Comparator interrupt control register (lower)
CEN8 CEN7 CEN6 CEN5 CEN4 CEN3 CEN2 CEN1
Decoder
SWS3 SWS2 SWS1 VAL3 VAL2 VAL1
(COSRH2) Comparator status register 2 (upper)
BOF3 BOF2 BOF1 SPM2 SPM1 SPM0
(COCRL) Comparator control register (lower)
Internal data bus
69
MB90370 Series
12. UART (x 3)
The UART (Universal Asychronous Receiver Transmitter) is a serial I/O port for asynchronous (start-stop)
communication or clock-synchronous communication.
The UART has the following features :
• Full-duplex double buffering
• Capable of asynchronous (start-stop bit) and CLK-synchronous communications
• Support for the multiprocessor mode
• Various method of baud rate generation :
- External clock input possible
- Internal clock (a clock supplied from 16-bit reload timer can be used)
- Embedded dedicated baud rate generator
Operation
Baud rate
Asynchronous
76923 / 38461 / 19230 / 9615 / 500K / 250K bps
CLK synchronous 16M / 8M / 4M / 2M / 1M / 500K bps
• Error detection functions (parity, framing, overrun)
• NRZ (Non Return to Zero) signal format
• Interrupt request :
- Receive interrupt (receive complete, receive error detection)
- Transmit interrupt (transmission complete)
- Transmit / receive conforms to extended intelligent I/O service (EI2OS)
70
MB90370 Series
(1) Register configuration of UART
Serial Mode Register
7
Address: ch1 000020H
ch2 0000D2H
ch3 0000E4H
6
5
4
3
2
1
0
Bit number
SMR1/2/3
Read/write
Initial value
MD1
MD0
R/W
0
R/W
0
CS2
CS1
R/W
0
CS0
R/W
0
R/W
0
SCKE
SOE
R/W
0
R/W
0
Serial Control Register
15
Address: ch1 000021H
ch2 0000D3H
ch3 0000E5H
14
13
12
11
10
9
A/D
REC
RXE
8
Bit number
SCR1/2/3
PEN
Read/write
Initial value
P
R/W
0
SBL
R/W
0
CL
R/W
0
R/W
0
R/W
0
W
1
TXE
R/W
0
R/W
0
UART Input Data Register / Output Data Register
7
Address: ch1 000022H
ch2 0000D4H
ch3 0000E6H
Read/write
Initial value
6
D7
D6
R/W
X
R/W
X
5
D5
4
3
2
1
0
Bit number
SIDR1/2/3
SODR1/2/3
D4
D3
D2
D1
D0
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
13
12
11
10
9
8
UART Status Register
15
Address: ch1 000023H
ch2 0000D5H
ch3 0000E7H
Read/write
Initial value
14
Bit number
SSR1/2/3
PE
ORE
R
0
R
0
FRE
RDRF TDRE
R
0
R
0
R
1
BDS
RIE
TIE
R/W
0
R/W
0
R/W
0
Clock Division Control Register
15
Address: ch1 000025H
ch2 0000D7H
ch3 0000E9H
Read/write
Initial value
14
13
12
11
10
9
8
Bit number
CDCR1/2/3
MD
SRST
DIV3
DIV2
DIV1
DIV0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
4
3
Mode 2 Control Register
7
Address: ch1 000024H
ch2 0000D6H
ch3 0000E8H
Read/write
Initial value
6
5
2
1
SCKL
M2L2
M2L1
R/W
1
R/W
0
R/W
0
0
Bit number
M2CR1/2/3
M2L0
R/W
0
71
MB90370 Series
(2) Block diagram of UART
From
communication
prescaler
Reception interrupt
#35 (23H)*
<#37 (25H)*>
<#39 (27H)*>
Transmission
interrupt
#36 (24H)*
<#38 (26H)*>
<#40 (28H)*>
Baud rate
generator
16-bit reload timer 1/2/3
Clock
selection
circuit
P66/UCK1
<P71/UCK2> External clock
<P74/UCK3>
P70/UI1
<P73/UI2>
<P76/UI3>
Transmission clock
Reception clock
Reception control
circuit
Transmission control
circuit
Start bit detect
circuit
Transmission
start circuit
Reception bit
counter
Transmission bit
counter
Reception parity
counter
Transmission
parity counter
P67/UO1
<P72/UO2>
<P75/UO3>
Reception status
judgment circuit
Transmission shifter
Reception shifter
SIDR1/2/3
SODR1/2/3
EI2OS reception error
signal (to CPU)
F2MC-16LX bus
SMR1/2/3
register
MD1
MD0
CS2
CS1
CS0
SCKE
SOE
*: Interrupt number
72
SCR1/2/3
register
PEN
P
SBL
CL
A/D
REC
RXE
TXE
SSR1/2/3
register
PE
ORE
FRE
RDRF
TDRE
BDS
RIE
TIE
M2CR1/2/3
register
Control signal
SCKL
M2L2
M2L1
M2L0
MB90370 Series
13. LCD controller/driver
The LCD (Liquid Crystal Display) controller/driver function displays the contents of a display data memory directly
to the LCD panel by segment and common outputs.
• Up to nine segment outputs (SEG0 to SEG8) and four common outputs (COM0 to COM3) may be used.
• Built-in display RAM.
• Three selectable duty ratios (1/2, 1/3, and 1/4). Not all duty ratios are available with all bias settings, however.
• Either the main or sub-clock can be selected as the drive clock.
• LCD can be driven directly.
Table below shows the duty ratios available with each bias setting.
Part number
Bias
1/2 duty ratio
1/3 duty ratio
1/4 duty ratio
X
X
1/2 bias
MB90370 series
1/3 bias
:
X :
X
Recommended mode
Do not use
(1) Register configuration of LCD
LCDC Control Register (Upper)
Address: 0000EFH
Read/write
Initial value
15
14
13
12
11
10
9
8
SS4
VS
CS1
CS0
SS3
SS2
SS1
SS0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
6
5
4
3
2
1
0
Bit number
BK
MS1
MS0
FP1
FP0
LCRL
R/W
1
R/W
0
R/W
0
R/W
0
R/W
0
Bit number
LCRH
LCDC Control Register (Lower)
7
Address: 0000EEH
Read/write
Initial value
CSS LCEN VSEL
R/W
0
R/W
0
R/W
0
73
MB90370 Series
(2) Block diagram of LCD
LCDC supply voltage (V1to V3)
4
Prescaler
4
Segment output driver
Sub-clock
(32 kHz)
Timing
controller
V/I converter
Internal bus
HCLK / 28
9
Display RAM
9 x 4 bit
Controller
74
Common output driver
LCDC control register
(LCR)
Driver
COM0
COM1
COM2
COM3
SEG0
SEG1
SEG2
SEG3
SEG4
:
SEG5
:
SEG6
SEG7
SEG8
MB90370 Series
14. A/D converter
The A/D (Analog to Digital) converter converts the analog voltage input to an analog input pin (input voltage) to
a digital value.
The converter has the following features :
• The minimum conversion time is 6.13 µs (for a machine clock of 16 MHz; includes the sampling time).
• The minimum sampling time is 3.75 µs (for a machine clock of 16 MHz).
• The converter uses the RC-type successive approximation conversion method with a sample and hold circuit.
• A resolution of 10 bits or 8 bits can be selected.
• Up to twelve channels for analog input pins can be selected by a program.
• Various conversion mode :
- Single conversion mode : Selectively convert one channel.
- Scan conversion mode : Continuously convert multiple channels. Maximum of 12 selectable channels.
- Continuous conversion mode : Repeatedly convert specified channels.
- Stop conversion mode : Convert one channel then halt until the next activation. (Enables synchronization of
the conversion start timing.)
• At the end of A/D conversion, an interrupt request can be generated and EI²OS can be activated.
• In the interrupt-enabled state, the conversion data protection function prevents any part of the data from being
lost through continuous conversion.
• The conversion can be activated by software, 16-bit reload timer 4 (rise edge) and ADTG.
(1) Register configuration of A/D converter
Analog Input Enable Register 2
15
14
13
12
Address: 00002BH
11
10
9
8
Bit number
ADE11 ADE10 ADE9 ADE8
Read/write
Initial value
R/W
1
R/W
1
3
2
R/W
1
ADER2
R/W
1
Analog Input Enable Register 1
7
Address: 00002AH
Read/write
Initial value
6
5
4
1
0
ADE7
ADE6
ADE5
ADE4
ADE3
ADE2
ADE1
ADE0
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
15
14
13
12
11
10
BUSY
INT
INTE
PAUS
STS1
STS0
STRT
RESV
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
W
0
R/W
0
7
6
5
2
1
0
MD1
MD0
R/W
0
R/W
0
Bit number
ADER1
A/D Control Status Register 1
Address: 000031H
Read/write
Initial value
9
8
Bit number
ADCS1
A./D Control Status Register 0
Address: 000030H
Read/write
Initial value
4
3
Bit number
ADCS0
(Continued)
75
MB90370 Series
(Continued)
A/D Control Register
15
14
13
12
11
10
ANS3
ANS2
ANS1
ANS0
ANE3
ANE2
ANE1
ANE0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
15
14
13
12
11
10
Address: 00002FH
S10
ST1
ST0
CT1
Read/write
Initial value
R/W
0
W
0
W
0
Address: 00002DH
Read/write
Initial value
9
8
Bit number
ADC0
A/D Data Register (Upper)
9
8
Bit number
CT0
D9
D8
ADCR1
W
0
W
0
R
X
R
X
A/D Data Register (Lower)
Address: 00002EH
Read/write
Initial value
7
6
5
4
3
2
1
0
Bit number
D7
D6
D5
D4
D3
D2
D1
D0
ADCR0
R
X
R
X
R
X
R
X
R
X
R
X
R
X
R
X
(2) Block diagram of A/D converter
AVCC
AVR
AVSS
D/A converter
MPX
AN0
AN1
AN2
AN3
AN4
AN5
AN6
Sequential compare register
Comparator
AN7
AN8
AN9
AN10
AN11
Sample and hold circuit
Data register
ADCR0/1
A/D control register
A/D control status register 0
A/D control status register 1
ADCS0/1
16-bit reload timer 4
Operation clock
P37/ADTG
: Machine clock
76
Prescaler
MB90370 Series
15. D/A converter
The D/A (Digital to Analog) converter is used to generate an analog output from an 8-bit digital input. By setting
the enable bit in the D/A control register (DACR) to 1, it will enable the corresponding D/A output channel. Hence,
setting this bit to 0 will disable that channel.
If D/A output is disabled, the analog switch inserted to the output of each D/A converter channel in series is
turned off. In the D/A converter, the bit is cleared to 0 and the direct-current path is shut off. The above is also
true in the stop mode.
The output voltage of the D/A converter ranges from 0 V to 255/256 x DVR. To change the output voltage range,
adjust the DVR voltage externally.
The D/A converter output does not have the internal buffer amplifier. The analog switch (= 100
is inserted to
the output in series. To apply load to the output externally, estimate a sufficient stabilization time.
Table below lists the theoretical values of output voltage of the D/A converter.
Value written to DA07 to DA00
and DA17 to DA10
00H
Theoretical value of output voltage
0/256
DVR (= 0 V)
01H
1/256
DVR
02H
2/256
DVR
:
:
FDH
253/256
DVR
FEH
254/256
DVR
FFH
255/256
DVR
77
MB90370 Series
(1) Register configuration of D/A converter
D/A converter register 1
Bit
Address:00005BH
Read/write
Initial value
15
14
13
12
DA17 DA16 DA15 DA14
11
10
DA13
DA12
9
8
DA11 DA10 DAT1
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
7
6
5
4
3
2
1
0
DA03
DA02
D/A converter register 0
Bit
Address:00005AH
Read/write
Initial value
DA07
DA06 DA05 DA04
DA01 DA00 DAT0
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
15
14
13
12
11
10
9
8
-
-
-
-
-
-
-
DAE1 DACR1
-
-
-
-
-
-
-
R/W
0
7
6
5
4
3
2
1
0
-
-
-
-
-
-
DAE0 DACR0
-
-
-
-
-
-
-
R/W
0
D/A control register 1
Bit
Address:00005DH
Read/write
Initial value
D/A control register 0
Bit
Address:00005CH
Read/write
Initial value
78
MB90370 Series
(2) Block diagram of D/A converter
F 2 M2C16LX-BUS
DA DA DA DA DA DA DA DA
17 16 15 14 13 12 11 10
DA DA DA DA DA DA DA DA
07 06 05 04 03 02 01 00
DVR
DVR
DA17
DA07
2R
2R
R
DA16
R
DA06
2R
2R
R
R
DA15
DA05
DA11
DA01
2R
2R
R
DA10
R
DA00
2R
2R
2R
2R
DAE1
DAE0
Standby control
Standby control
DA output ch.1
DA output ch.0
79
MB90370 Series
16. LPC interface
The LPC (Low Pin Count) interface consists of an LPC bus interface, universal parallel interface (UPI x 4
channels), gate address A20 function and LPC data buffer array. By using the LPC bus interface and UPI, data
can be exchanged with an external host CPU synchronously via an external LPC bus.
• LPC bus interface
The LPC bus interface provides direct access of host CPU to UPI.
• It supports I/O read and I/O write cycle only. Other cycle types will be ignored.
• It supports LPC clock running at 33 MHz.
• Universal parallel interface, UPI x 4 channels
The UPI is used to exchange parallel data to serial data in LPC bus with host CPU.
• An 8-bit data will be transmitted or received.
• A buffer function is available for independent input and output.
• The I/O buffer status can be output externally through LPC bus interface.
• Gate address A20 function for UPI channel 0
The GA20 (Gate Address A20) is intended to implement the memory management in a PC architecture.
This allows the access to the extended memory needed by the operating system. On-chip logic is provided
to speed up the generation of GA20.
• Data buffer array
The data buffer array is consisted of 32 bytes UP data register and 16 bytes DOWN data register to speed
up the data transfer between MCU and external host through LPC bus.
(1) Register configuration of LPC bus interface register
LPC Control Register
2
1
0
Bit number
00006EH
LRF
LRIE
LPE
LCR
Read/write
Initial value
R/W
0
R/W
0
R/W
0
7
Address:
80
6
5
4
3
MB90370 Series
(2) Register configuration of UPI registers
UPI Address Register (Upper)
15
Address: ch1 00005FH
ch2 000061H
ch3 000063H
14
13
12
11
10
9
8
Bit number
UPAH1 ~ 3
UPA15 UPA14 UPA13 UPA12 UPA11 UPA10 UPA09 UPA08
Read/write
Initial value
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
7
6
5
4
3
R/W
X
R/W
X
UPI Address Register (Lower)
Address: ch1 00005EH
ch2 000060H
ch3 000062H
2
1
0
Bit number
UPAL1 ~ 3
UPA07 UPA06 UPA05 UPA04 UPA03 UPA02 UPA01 UPA00
Read/write
Initial value
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
UPI Control Register (Upper)
15
14
13
UPE3
Address: 000065H
Read/write
Initial value
12
11
10
IBFE3 OBEE3
R/W
0
R/W
0
9
UPE2
R/W
0
8
Bit number
UPCH
IBFE2 OBEE2
R/W
0
R/W
0
R/W
0
UPI Control Register (Lower)
7
Address: 000064H
6
5
4
3
2
1
0
Bit number
DBAE UPE1 IBFE1 OBEE1 GA20E UPE0 IBFE0 OBEE0
Read/write
Initial value
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
15
14
13
12
UPCL
UPI Status Register
Address: ch0 000067H
ch1 000069H
ch2 00006BH
ch3 00006DH
Read/write
Initial value
UF4
R/W
0
11
10
9
8
UF3
UF2
UF1
A2
UF0
IBF
R/W
0
R/W
0
R/W
0
R
0
R/W
0
R
0
R
0
6
5
3
2
1
Bit number
UPS0 ~ 3
OBF
UPI Data Input Register / Data Output Register
Address: ch0 000066H
ch1 000068H
ch2 00006AH
ch3 00006CH
Read/write
Initial value
7
UPD7
R/W
X
4
UPD6 UPD5 UPD4
R/W
X
R/W
X
R/W
X
0
UPD3 UPD2 UPD1 UPD0
R/W
X
R/W
X
R/W
X
Bit number
UPDI0 ~ 3 /
UPDO0 ~ 3
R/W
X
81
MB90370 Series
(3) Register configuration of LPC data buffer registers
Data Buffer Array Address Register (Upper)
15
Address: 003FF1H
14
13
12
11
10
9
8
Bit number
DA15
DA14
DA13
DA12
DA11
DA10
DA09
DA08
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
Read/write
Initial value
Data Buffer Array Address Register (Lower)
7
6
Address: 003FF0H
Read/write
Initial value
5
4
3
2
DA07
DA06
DA05
DA04
R/W
R/W
R/W
R/W
R/W
X
X
X
X
X
1
DA03 DA02
DBAAH
0
Bit number
DA01
DA00
R/W
R/W
R/W
X
X
X
10
9
8
DBAAL
UP Data Register (upper)
Address: ch0 003FC1H
ch1 003FC3H
~
chF 003FDFH
Read/write
Initial value
15
UP15
14
13
12
11
UP14
UP13
UP12
UP11
UP10
UP09
UP08
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
7
6
5
4
3
2
UP07
UP06
UP05
UP03
UP02
UP01
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
14
13
12
11
10
R/W
X
Bit number
UDRH0 ~ F
UP Data Register (lower)
Address: ch0 003FC0H
ch1 003FC2H
~
chF 003FDEH
1
0
Bit number
UDRL0 ~ F
Read/write
Initial value
UP04
UP00
R/W
X
R/W
X
DOWN Data Register (upper)
Address: ch0 003FE1H
ch1 003FE3H
~
ch7 003FEFH
Read/write
Initial value
15
DN15
DN14
R
X
9
8
DN13
DN12
DN11
DN10
DN09
DN08
R
X
R
X
R
X
R
X
R
X
R
X
3
2
R
X
Bit number
DNDH0 ~ 7
DOWN Data Register (lower)
Address: ch0 003FE0H
ch1 003FE2H
~
ch7 003FEEH
Read/write
Initial value
7
6
5
4
DN06
DN05
DN04
DN03 DN02
R
X
R
X
1
0
Bit number
DNDL0 ~ 7
DN07
R
X
R
X
R
X
R
X
DN01
DN00
R
X
R
X
(Continued)
82
MB90370 Series
(Continued)
Index Register
7
6
5
Address:
Read/write
Initial value
Data Port Register
7
Address:
Read/write
Initial value
6
4
3
2
1
0
Bit number
IX05
IX04
IX03
IX02
IX01
IX00
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
5
4
3
DP07
DP06
DP05
DP04
R/W
R/W
R/W
R/W
R/W
X
X
X
X
X
2
1
DP03 DP02
IXR
0
Bit number
DP01
DP00
R/W
R/W
R/W
X
X
X
DPR
(4) Block diagram of LPC interface
Address
comparator
UPI address register, UPAH1~3, UPAL1~3
Data buffer array address register, DBAA
UPE
LPC R/W
DBAE
R/W
comp
match
Interrupt request #16
Interrupt request #15
Interrupt request #14
UPI0 ~ 3
UPE
IBFE OBEE
Interrupt request #13
Interrupt request #21
UPS
UF4
OBF0~3
UF3
UF2
UF1
UF0
A2
IBF
OBF
LCR
LRF LRIE LPE
UPDI
UPD7 UPD6 UPD5 UPD4 UPD3 UPD2 UPD1 UPD0
UPDO
UPD7 UPD6 UPD5 UPD4 UPD3 UPD2 UPD1 UPD0
LPC internal data bus
F2MC-16LX internal data bus
UPC
LA3 LA2 LA1 LA0
EN
R/W
4
for UPI0 only
UPC
GA20E
EN
LFRAME
LRESET
LCLK
State
machine
GA20 output
generator
LAD3~LAD0
LD7 LD6 LD5 LD4 LD3 LD2 LD1 LD0
LPC bus interface
GA20
DBAE
UPC
UP data register (32 bytes)
DOWN data register (16 bytes)
Data buffer array
IXR
Index register
Data port register
DPR
83
MB90370 Series
17. Serial IRQ controller
The serial IRQ controller consists of a 6-channel serial IRQ control circuit and an LPC clock monitor / control
circuit. By using this serial IRQ controller, host interrupt requests can be transferred serially through a single
signal wire (SERIRQ), synchronized with the LPC clock.
• 6-channel serial IRQ control circuit
• The 6-channel serial IRQ control circuit consists of a serial interrupt control register (SICR), 4 serial
interrupt frame number registers (SIFR1 ~ 4), a protocol state machine and a serial interrupt data latch
and output control.
• For channel 0A, 0B and 1 ~ 3, if SICR : OBE bit (OBF controlled enable bit) = 0, then serial IRQ can be
controlled by software setting of SICR : IRR bit. If SICR : OBE bit = 1, then software control is disabled
and serial IRQ is controlled by OBF flag (Output buffer full flag) from LPC UPI0 ~ 3.
• For channel 4, serial IRQ can be controlled by software setting of SICR : IRR bit.
• For channel 0A and 0B, additional enable bit (SICR : EN0A/0B bit) can be used to latch and keep the
OBF0 or IRR0A/0B bit status.
• The serial interrupt data latch transfers serial IRQs serially according to their frame number. The frame
number for channel 0A is fixed to “IRQ1”, for channel 0B is fixed to “IRQ12”, and the frame number for
channel 1 ~ 4 are software programmable (IRQ1 ~ 15, and IRQ21 ~ 31) by setting the SIFR1 ~ 4.
• By monitoring the SERIRQ and the LPC clock pin, the protocol state machine can detect the START
frame condition. Then it starts counting the DATA frame and transfers its serial IRQs through SERIRQ.
Finally it can switch to continuous/quiet mode operation by determine the STOP frame condition.
• The serial interrupt output control support both continuous and quiet mode operation. In continuous
mode operation, only the host can initiate the serial IRQs transfer; In quiet mode operation, both the
host and slave (e.g. the serial IRQ controller) can initiate the serial IRQs transfer.
• LPC clock monitor / control circuit
• The LPC clock monitor / control circuit consists of a clock-run monitor / control circuit. By monitoring the
clock-run pin (CLKRUN), the clock monitor / control circuit can determine whether the host has stopped
LPC clock in quiet mode operation or not. If LPC clock is stopped and the controller want to initiate the
serial IRQs transfer, then it can request the host to restart the LPC clock by controlling the CLKRUN pin.
84
MB90370 Series
(1) Register configuration of serial IRQ controller
Serial Interrupt Control Register (Lower)
7
Address: 000032H
Read/write
Initial value
6
5
4
3
2
1
0
EN0B
EN0A
IRR4
IRR3
IRR2
IRR1
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
13
12
10
9
8
IRR0B IRR0A
Bit number
SICRL
Serial Interrupt Control Register (Upper)
15
Address: 000033H
Read/write
Initial value
14
IRQEN RSEN
R/W
0
R/W
0
11
BUSY OBE3
OBE2
R
0
R/W
0
R/W
0
4
3
OBE1 OBE0B OBE0A
R/W
0
R/W
0
R/W
0
2
1
0
Bit number
SICRH
Serial Interrupt Frame Number Register 1
Address: 000034H
Read/write
Initial value
7
6
5
-
-
LV1
FR14
FR13
FR12
FR11
FR10
-
-
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
9
8
Bit number
SIFR1
Serial Interrupt Frame Number Register 2
15
14
13
12
11
10
Address: 000035H
-
-
LV2
FR24
FR23
FR22
FR21
FR20
Read/write
Initial value
-
-
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
4
3
2
1
0
Bit number
SIFR2
Serial Interrupt Frame Number Register 3
Address: 000036H
Read/write
Initial value
7
6
5
-
-
LV3
FR34
FR33
FR32
FR31
FR30
-
-
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
9
8
Bit number
SIFR3
Serial Interrupt Frame Number Register 4
15
14
13
12
11
10
Address: 000037 H
-
-
LV4
FR44
FR43
FR42
FR41
FR40
Read/write
Initial value
-
-
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit number
SIFR4
85
MB90370 Series
(2) Block diagram of the serial IRQ controller
Serial IRQ controller
OBF0
OBF1
OBF2
OBF3
6-channel serial
IRQ control circuit
LCLK stop
status
OBF0
OBF1
OBF2
OBF3
}
from UPI0~3
in LPC
interface
SIRQ
Pin
SERIRQ
LCLK
Pin
LCLK
LRESET
Pin
LRESET
Pin
CLKRUN
LCLK restart
request
LPC clock
monitor / control
circuit
LCLK
LRESET
CRUN
86
MB90370 Series
(3) Block diagram of the 6-channel serial IRQ control circuit
IRQEN
SERIRQ
busy
OBE0A, OBE0B, OBE1~3
Serial interrupt
control register (upper)
SIRQ enable
OBF0
OBF1
OBF2
OBF3
Register
write
disable
Serial interrupt
control register (lower)
IRR0A, IRR0B, IRR1~3
F2MC-16LX bus
Software
control
Hardware
control
Serial IRQ control
selector for channel
0A, 0B, 1~3
IRR4
Serial interrupt
frame number register
Latches for
channel 0A, 0B
Serial IRQs
frame no. for
channel 1~4
channel 1~4
EN0A, EN0B
Serial interrupt
data latch and
output control
SIRQO
LCLK
LRESET
Serial IRQ
sample cycle
Frame
cycle count
Initiate serial
IRQ transfer
request
Protocol
state
machine
SIRQI
LCLK stop
status
LCLK
restart
request
87
MB90370 Series
(4) Block diagram of the LPC clock monitor / control circuit
F2MC-16LX bus
RSEN
LCLK
restart
request
IRQEN
CRUNO enable
LCLK stop
status
LCLK
restart
request
CRUNO
Clock-run
monitor /
control
CRUNI
LCLK
LRESET
88
MB90370 Series
18. 3-channel PS/2 interface
The 3-channel PS/2 interface consists of 3 individual channels of PS/2 interface that can be operated concurrently. PS/2 interface is a two wires, bidirectional serial bus providing economical way for data exchange between
host (keyboard controller) and device (keyboard / mouse etc).
(1) Register configuration of 3-channel PS/2 interface
PS/2 Interface Mode Register
15
14
13
12
11
Address: 000059H
10
NFS1 NFS0
Read/write
Initial value
Bit number
9
8
DIV1
DIV0
R/W
0
R/W
0
R/W
0
R/W
0
PSMR
PS/2 Interface Data Register (Ch 1)
Address: ch1 000057H
Read/write
Initial value
15
14
13
12
11
10
9
8
Bit number
D7
D6
D5
D4
D3
D2
D1
D0
PSDR1
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
PS/2 Interface Data Register (Ch 0, Ch 2)
7
5
4
3
2
1
0
Bit number
PSDR0/2
Address: ch0 000056H
ch2 000058 H
Read/write
Initial value
6
D7
D6
D5
D4
D3
D2
D1
D0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
9
8
PS/2 Interface Status Register
15
Address: ch0 000051H
ch1 000053H
ch2 000055H
Read/write
Initial value
14
13
12
11
10
Bit number
PSSR0/1/2
PE
FED
FRE/NAK
RAF
TS
TBC
BNR
R
0
R
0
R
0
R
0
5
TC
R
0
R
0
R
0
R/W
0
4
3
2
1
PS/2 Interface Control Register
7
Address: ch0 000050H
ch1 000052H
ch2 000054H
Read/write
Initial value
6
0
Bit number
PSCR0/1/2
PS2E
FEDE
IE
R/W
0
R/W
0
R/W
0
BREQ
R/W
0
TE
RE
R/W
0
R/W
0
89
MB90370 Series
(2) Block diagram of 3-channel PS/2 interface
F2MC-16LX bus
PSCKI0
NFS1 NFS0 DIV1
DIV0
PSDAI0
Noise filter
Noise filter
2
PSMR
PSCKI1
PSDAI1
Noise filter
Noise filter
PSCKI2
Noise filter
PSDAI2
Noise filter
1/4
1/16
1/32
90
Selector
Prescaler
circuit
1/8
PSCKO0
Channel 0
transmission/reception
circuit
Sampling clock
PSDAO0
Interrupt
request 0
PSCKO1
Channel 1
transmission/reception
circuit
PSDAO1
Interrupt
request 1
PSCKO2
Channel 2
transmission/reception
circuit
PSDAO2
Interrupt
request 2
MB90370 Series
(3) Block diagram of PS/2 interface transmission/reception circuit (1 channel)
F2MC-16LX bus
Sampling
clock
PSDAI
PSCKI
PSDR
SYNDA
Synchronous
circuit
SYNCK
D7
D6
D5
D4
D3
D2
D1
PSDAO
D0
Start of
transmission
Start of
reception
Transmission control circuit
Reception control circuit
Acknowledge reception
generator
Reception completion
detector
Parity checker
Parity generator
Reception start bit
detection circuit
Reception
enable
Transmission completion
detector
Reception status
judgment circuit
PE & FRE
Acknowledge
result
Reception Reception
complete
active
Transfer
break request
Transmission
enable
Transmission
complete
Transfer complete
processing circuit
PSCKO
Transfer
status flags
clear
Error flags
Falling edge
detection
PS2E
PSCR
FEDE
IE
BREQ
TE
RE
PE
FED FRE/ RAF
NAK
TS
TBC BNR
TC
PS/2 interface
interrupt
#23 (17H)* ch0/1
#24 (18H)* ch2
PSSR
F2MC-16LX bus
*: Interrupt number
91
MB90370 Series
19. Parity generator
The parity generator is a simple circuit that generates odd / even parity based on the input data. It consists of a
parity generator data register (PGDR), an odd / even parity generation logic and a parity generator control status
register (PGCSR).
An 8-bit data can be loaded into PGDR, then the parity generator will generate odd / even parity based on the
input data. Either odd or even parity can be generated by setting the PGCSR.
For odd parity generation, if the number of “1”s in the PGDR is even number, then the parity bit in PGCSR will
be set to “1”, otherwise the parity bit will be set to “0”.
For even parity generation, if the number of “1”s in the PGDR is even number, then the parity bit in PGCSR will
be set to “0”, otherwise the parity bit will be set to “1”.
Table shows some examples of odd / even parity generation.
Input data
Parity bit (odd parity)
Parity bit (even parity)
1
1
0
0
0
0
1
1
0000 0000B
0101 0101B
1000 0000B
1010 1011 B
(1) Register configuration of parity generator
Parity Generator Data Register
Address : 000018H
Read/write
Initial value
7
6
5
4
3
2
1
0
D7
D6
D5
D4
D3
D2
D1
D0
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
12
11
9
8
Bit number
PGDR
Parity Generator Control Status Register
15
92
Address : 000019H
PRTY
Read/write
Initial value
R
X
14
13
10
PSEL
-
-
-
-
-
-
R/W
0
Bit number
PGCSR
MB90370 Series
(2) Block diagram of parity generator
2
F MC16LX Internal bus
8
Parity generator data register
8
Parity generation logic
result
2
odd /
even
Parity generator
control status register
93
MB90370 Series
20. Bit decoder
The bit decoder is a simple one-hot decoder that can be used together with the keyscan inputs. It consists of a
bit data register (BDR), a decoder logic and a bit result register (BRR). A 4-bit encoded data can be loaded into
BDR, then the decoder logic will decode the data and store the 16-bit resulted data into BRR. Below shows the
decoder’s logic table.
4-bit encoded data
16-bit resulted data
0000 0000 0000 0001B
0000 0000 0000 0010B
0000 0000 0000 0100B
0000 0000 0000 1000B
0000 0000 0001 0000B
0000 0000 0010 0000B
0000 0000 0100 0000B
0000 0000 1000 0000B
0000 0001 0000 0000B
0000 0010 0000 0000B
0000 0100 0000 0000B
0000 1000 0000 0000B
0001 0000 0000 0000B
0010 0000 0000 0000B
0100 0000 0000 0000B
1000 0000 0000 0000B
0H
1H
2H
3H
4H
5H
6H
7H
8H
9H
AH
BH
CH
DH
EH
FH
(1) Register configuration of bit decoder
Bit Data Register
15
14
13
12
Address : 0000E1H
Read/write
Initial value
11
10
9
8
Bit number
BDR
D3
D2
D1
D0
R/W
X
R/W
X
R/W
X
R/W
X
10
9
8
Bit number
BRRH
-
-
-
-
15
14
13
12
11
R15
R14
R13
R12
R11
R10
R9
R8
R
X
R
X
R
X
R
X
R
X
R
X
R
X
R
X
Bit Result Register (Upper)
Address : 0000E3H
Read/write
Initial value
Bit Result Register (Lower)
Address : 0000E2H
Read/write
Initial value
94
7
6
5
4
3
2
1
0
R7
R6
R5
R4
R3
R2
R1
R0
R
X
R
X
R
X
R
X
R
X
R
X
R
X
R
X
Bit number
BRRL
MB90370 Series
(2) Block diagram of bit decoder
2
F MC16LX Internal bus
4
Bit data register
4
Decoder logic
16
16
Bit result register
95
MB90370 Series
21. Wake-up interrupt
The wake-up interrupt circuit detects the signals of the “L” levels input to the external interrupt pins and to
generate interrupt request to the CPU. These interrupts can wake up the CPU from standby mode.
Wake-up interrupt pins:
8 pins (P00/KSI0 to P07/KSI7).
Wake-up interrupt sources:
“L” level signal input to a wake-up interrupt pin.
Interrupt control:
Enables or disables to input wake-up interrupt controlled by
wake-up interrupt control register (EICR).
Interrupt flag:
IRQ flag bit of wake-up interrupt flag register (EIFR). Flag set
when there is an IRQ.
Interrupt request:
Interrupt request #20 is generated if any enabled external
interrupt pin goes LOW.
(1) Register configuration of wake-up interrupt
Wake-up Interrupt Flag Register
15
14
13
12
11
10
9
8
Address: 0000ADH
WIF
Read/write
Initial value
R/W
0
Wake-up Interrupt Control Register
7
Address: 0000ACH
Read/write
Initial value
6
5
4
3
2
1
0
EN7
EN6
EN5
EN4
EN3
EN2
EN1
EN0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
5
3
(2) Block diagram of wake-up interrupt
7
6
4
2
1
0
EICR
P07/KS17
P06/KS16
P05/KS15
EIFR
P04/KS14
P03/KS13
P02/KS12
P01/KS11
P00/KS10
Interrupt Request Generator
96
Bit number
EIFR
Bit number
EICR
MB90370 Series
22. DTP/External interrupts
The DTP (Data Transfer Peripheral)/external interrupt circuit is activated by the signal supplied to a DTP/external
interrupt pin. The CPU accepts the signal using the same procedure it uses for normal hardware interrupts and
generates external interrupts or activates the extended intelligent I/O service (EI2OS).
Features of DTP/External interrupt :
• Total 6 external interrupt channels
• Two request levels (“H” and “L”) are provided for the intelligent I/O service
• Four request levels (rise/fall edge, fall edge, “H” level and “L” level) are provided for external interrupt requests
(1) Register configuration
DTP/Interrupt Source Register
15
14
___
___
___
___
___
___
Address: 000027H
Read/write
Initial value
13
12
11
10
9
8
ER5
ER4
ER3
ER2
ER1
ER0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
5
4
3
2
1
0
EN5
EN4
EN3
EN2
EN1
EN0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
DTP/Interrupt Enable Register
7
6
Address: 000026H
___
___
Read/write
Initial value
___
___
___
___
Bit number
EIRR
Bit number
ENIR
Request Level Setting Register (Upper)
15
14
13
12
11
10
9
8
Address: 000029H
___
___
___
___
LB5
LA5
LB4
LA4
Read/write
Initial value
___
___
___
___
___
___
___
___
R/W
0
R/W
0
R/W
0
R/W
0
5
4
3
2
1
0
Request Level Setting Register (Lower)
7
6
Address: 000028H
LB3
LA3
LB2
LA2
LB1
LA1
LB0
LA0
Read/write
Initial value
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit number
ELVRH
Bit number
ELVRL
97
MB90370 Series
(2) Block diagram of DTP/External interrupts
Request level setting register (ELVR)
LB5 LA5 LB4 LA4 LB3 LA3 LB2 LA2 LB1 LA1 LB0 LA0
2
2
2
2
2
2
Selector
Pin
P60/INT0
Selector
Pin
P61/INT1
Pin
Selector
Selector
Internal data bus
P65/INT5
Pin
P62/INT2
Pin
Selector
Selector
Pin
P64/INT4
P63/INT3
ER5
ER4
ER3
ER2
ER1
ER0
DTP/interrupt cause register
(EIRR)
Interrupt request number
#17(11H)
#18(12H)
#19(13H)
EN5
98
EN4
EN3
EN2
EN1
EN0
DTP/interrupt enable register
(ENIR)
MB90370 Series
23. Delayed interrupt generation module
The delayed interrupt generation module is used to generate a task switching interrupt. Interrupt requests to the
F2MC-16LX CPU can be generated and cleared by software using this module.
(1) Register configuration
Delayed Interrupt Generator Module Register
15
14
13
12
11
10
Address: 00009FH
9
8
R0
Read/write
Initial value
Bit number
DIRR
R/W
0
F2MC-16LX bus
(2) Block diagram
Delayed interrupt cause issuance / cancellation decoder
Interrupt cause latch
99
MB90370 Series
24. ROM correction function
When an address matches the value set in the address detection register, the instruction code to be loaded into
the CPU is forced to be replaced with the INT9 instruction code (01H). When executing a set instruction, the
CPU executes the INT9 instruction. The address match detection function is implemented by processing using
the INT9 interrupt routine.
The device contains two address detection registers, each provided with a compare enable bit. When the value
set in the address detection register matches an address and the interrupt enable bit is “1”, the instruction code
to be loaded into the CPU is forced to be replaced with the INT9 instruction code.
(1) Register configuration
Program Address Detection Control / Status Register
7
6
5
4
Address: 00009EH
Read/write
Initial value
3
2
1
0
AD1E
AD1D
AD0E
AD0D
R/W
0
R/W
0
R/W
0
R/W
0
Bit number
PACSR
Program Address Detection Register 0 (Upper Byte)
7
6
5
4
3
2
1
0
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
9
8
Address: 001FF2H
Read/write
Initial value
PADRH0
Program Address Detection Register 0 (Middle Byte)
15
14
13
12
11
10
Address: 001FF1H
Read/write
Initial value
Bit number
Bit number
PADRM0
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
1
0
Program Address Detection Register 0 (Lower Byte)
7
6
5
4
3
2
Address: 001FF0H
Read/write
Initial value
Bit number
PADRL0
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
(Continued)
100
MB90370 Series
(Continued)
Program Address Detection Register 1 (Upper Byte)
15
14
13
12
11
10
9
8
Address: 001FF5H
Read/write
Initial value
PADRH1
R/W
X
R/W
X
R/W
X
R/W
X
Program Address Detection Register 1 (Middle Byte)
7
6
5
4
R/W
X
R/W
X
3
2
R/W
X
1
R/W
X
0
Address: 001FF4H
Read/write
Initial value
Bit number
PADRM1
R/W
X
R/W
X
R/W
X
R/W
X
Program Address Detection Register 1 (Lower Byte)
15
14
13
12
R/W
X
R/W
X
11
10
R/W
X
R/W
X
9
8
Address: 001FF3H
Read/write
Initial value
Bit number
Bit number
PADRL1
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
(2) Block diagram
Address latch
Comparator
INT9
command
F2MC-16LX bus
Address detection register 0/1
F2MC-16LX
AD0E/AD1E AD0D/AD1D
PACSR
CPU
101
MB90370 Series
25. ROM mirroring function selection module
The ROM mirroring function selection module can select what the FF bank allocated the ROM sees through the
00 bank according to register settings.
(1) Register configuration
ROM Mirror Function Selection Register
15
14
13
12
11
10
Address : 0006FH
Read/write
Initial value
Bit number
M1
ROMM
1
ROM mirroring register
F2MC-16LX bus
8
W
(2) Block diagram
Address area
FF bank
00 bank
ROM
102
9
MB90370 Series
26. 512K bit flash memory
The 512K bit flash memory is allocated in the FEH to FFH banks on the CPU memory map. Like masked ROM,
flash memory is read-accessible and program-accessible to the CPU using the flash memory interface circuit.
The flash memory can be programmed/erased by the instruction from the CPU via the flash memory interface
circuit. The flash memory can therefore be reprogrammed (updated) while still on the circuit board under
integrated CPU control, allowing program code and data to be improved efficiently.
Note that sector operations such as “enable sector protect” cannot be used.
Features of 512K bit flash memory :
• 64K words x 8 bits / 32K words x 16 bits (16K + 8K + 8K + 32K) sector configuration
• Automatic program algorithm (same as the Embedded Algorithm* : MBM29F400TA)
• Installation of the deletion temporary stop/delete restart function
• Write/delete completion detected by the data polling or toggle bit
• Write/delete completion detected by the CPU interrupt
• Compatibility with the JEDEC standard-type command
• Each sector deletion can be executed (Sectors can be freely combined)
• Number of write/delete operations 10,000 times guaranteed
* : Embedded Algorithm is a trademark of Advanced Micro Devices, Inc.
(1) Register configuration
Flash Memory Control Status Register
7
6
Address: 0000AEH
Read/write
Initial value
5
4
3
2
1
0
INTE RDYINT
WE
RDY
Reserved
LPM1
Reserved
LPM0
R/W
0
R/W
0
R
1
W
0
R/W
0
W
0
R/W
0
R/W
0
Bit number
FMCS
103
MB90370 Series
(2) Sector configuration of 512K bit flash memory
The 512K bit flash memory has the sector configuration illustrated below. The addresses in the illustration are
the upper and lower addresses of each sector.
When accessed from the CPU, SA0 and SA1 to SA3 are allocated in the FF bank registers, respectively.
Flash memory
SA3 (16 Kbytes)
SA2 (8 Kbytes)
SA1 (8 Kbytes)
SA0 (32 Kbytes)
CPU address
*Writer address
FFFFFFH
7FFFFH
FFC000H
FFBFFFH
7C000H
7BFFFH
FFA000H
7A000H
FF9FFF H
79FFF H
FF8000H
FF7FFFH
78000H
77FFFH
FF0000H
70000H
* : Writer addresses correspond to CPU addresses when data is programmed in flash memory by a parallel writer.
Writer addresses are used to program/erase data using a general-purpose writer.
104
MB90370 Series
ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
(VSS
Parameter
Symbol
Value
Min.
Max.
Unit
AVSS
CVSS
0.0 V)
Remarks
VCC
VSS
0.3
VSS
4.0
V
CVCC
VSS
0.3
VSS
4.0
V
VCC
CVCC *1
AVCC
VSS
0.3
VSS
4.0
V
VCC
AVCC *1
A/D converter reference
input voltage
AVR
VSS
0.3
VSS
4.0
V
AVCC
AVR, AVR
Comparator reference
input voltage
CVRH1
CVRH2
CVRL
VSS
0.3
VSS
4.0
V
CVCC
CVCC
CVCC
CVRH1, CVRH1 CVSS
CVRH2, CVRH2 CVSS
CVRL, CVRL CVSS
LCD power supply voltage
V1 ~ V3
VSS
0.3
VSS
4.0
V
V1 to V3 must not exceed VCC
VI1
VSS
0.3
VSS
4.0
V
All pins except P40 ~ P45, P80 ~
P82, P90 ~ P95 *2
VI2
VSS
0.3
VSS
6.0
V
P40 ~ P45, P80 ~ P82, P90 ~ P95
VO
VSS
0.3
VSS
4.0
V
*2
+2.0
mA
*4
Power supply voltage
Input voltage
Output voltage
Maximum clamp current
ICLAMP
Total maximum clamp current
|ICLAMP|
20
mA
*4
IOL1
10
mA
All pins except PF0 ~ PF7*3
IOL2
20
mA
PF0 ~ PF7*3
IOLAV1
4
mA
All pins except PF0 ~ PF7
Average output current = operating
current operating efficiency
IOLAV2
12
mA
PF0 ~ PF7
Average output current = operating
current operating efficiency
IOL
100
mA
“L” level total average
output current
IOLAV
50
mA
Average output current = operating
current operating efficiency
“H” level maximum output
current
IOH
10
mA
*3
“H” level average output
current
IOHAV
3
mA
Average output current = operating
current operating efficiency
“H” level total maximum
output current
IOH
100
mA
“H” level total average
output current
IOHAV
50
mA
Power consumption
PD
200
mW
Operating temperature
TA
85
C
“L” level maximum output
current
-2.0
AVSS
“L” level average output
current
“L” level total maximum
output current
40
Average output current = operating
current operating efficiency
105
MB90370 Series
Parameter
Symbol
Storage temperature
Tstg
Value
Min.
Max.
55
150
Unit
Remarks
C
*1 : Set AVCC, CVCC and VCC at the same voltage. Take care so that AVR, CVRH1, CVRH2 and CVRL do not exceed
VCC + 0.3 V when the power is turned on.
*2 : VI and VO shall never exceed VCC + 0.3 V.
*3 : The maximum output current is a peak value for a corresponding pin.
*4 : - Use within recommended operating conditions.
- Use at DC voltage (current).
- The +B signal should always be applied a limiting resistance placed between the +B signal and the microcontroller.
- The value of the limiting resistance should be set so that when the +B signal is applied the input current to
the microcontroller pin does not exceed rated values, either instantaneously or for prolonged periods.
- Note that when the microcontroller drive current is low, such as in the power saving modes, the +B input
potential may pass through the protective diode and increase the potential at the Vcc pin, and this may affect
other devices.
- Note that if a +B signal is input when the microcontroller power supply is off (not fixed at 0V), the power supply
is provided from the pins, so that incomplete operation may result.
- Note that if the +B input is applied during power-on, the power supply is provided from the pins and the resulting
supply voltage may not be sufficient to poerate the power-on reset.
- Care must be taken not to leave the +B input pin open.
- Note that analog system input/output pins other than the A/D input pins (LCD drive pins, comparator input
pins, etc.) cannot accept +B signal input.
- Sample recommended circuits:
Input/Output Equivalent circuits
Protective diode
Vcc
P-ch
Limiting
resistance
+B input (0V to 16V)
N-ch
R
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
106
MB90370 Series
2. Recommended Operating Conditions
(VSS
Parameter
Symbol
Value
Min.
Max.
Unit
AVSS
CVSS = 0.0 V)
Remarks
3.0 *1
3.6
V
CVCC
3.3
3.6
V
VCC
1.8
3.6
V
Retains the RAM state in stop mode
A/D converter
reference input
voltage *3
AVR
0
AVCC
V
Normal operation assurance range
LCD power
supply voltage
V1 ~ V3
VSS
VCC
V
V1 ~ V3 pins
(The optimum value is dependent on the LCD
element in use.)
TA
40
85
VCC
Power supply
voltage *2
Operating
temperature
Normal operation assurance range
C
*1 : The operating voltage varies with the operation frequency.
*2 : Set AVCC, CVCC and VCC at the same voltage.
*3 : Take care so that AVR, CVRH1, CVRH2 and CVRL do not exceed VCC + 0.3 V when power is turned on.
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device’s electrical characteristics are warranted when the device is
operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representatives beforehand.
107
MB90370 Series
3. DC Characteristics
(VCC
Parameter
Symbol
VIH
“H” level input
voltage
VIHS
Pin name
P10 ~ P17
P20 ~ P27
P30 ~ P37
P46 ~ P47
P50 ~ P57
PA0 ~ PA6
PB0 ~ PB7
PC0 ~ PC7
PD0 ~ PD7
PF0 ~ PF7
P00 ~ P07
P60 ~ P67
P70 ~ P77
PE0 ~ PE7
RST
CVCC
3.0 V to 3.6 V, VSS
Condition
AVSS
CVSS
0.0 V, TA
Value
Min.
Typ.
Max.
40 C to 85 C)
Unit
Remarks
0.7 VCC
VCC 0.3
V
CMOS
input pins
0.8 VCC
VCC 0.3
V
CMOS
hysteresis
input pins
VIHS5
P40 ~ P45
0.8 VCC
VSS + 5.5
V
5 V tolerant
CMOS
hysteresis
input pins
VIH5
P82
0.7 VCC
VSS + 5.5
V
5 V tolerant
CMOS
input pin
2.1
VSS + 5.5
V
VIHSM
VIHM
VIL
“L” level input
voltage
VILS
VILSM
VILM
108
AVCC
P80 ~ P81
P90 ~ P95
MD0 ~ MD2
P10 ~ P17
P20 ~ P27
P30 ~ P37
P46 ~ P47
P50 ~ P57
P82
PA0 ~ PA6
PB0 ~ PB7
PC0 ~ PC7
PD0 ~ PD7
PF0 ~ PF7
P00 ~ P07
P40 ~ P45
P60 ~ P67
P70 ~ P77
PE0 ~ PE7
RST
P80 ~ P81
P90 ~ P95
MD0 ~ MD2
SMbus
input pins
Mode pins
VCC
0.3
VCC 0.3
V
VSS
0.3
0.3 VCC
V
CMOS
input pins
VSS
0.3
0.2 VCC
V
CMOS
hysteresis
input pins
VSS
0.3
0.8
V
SMbus
input pins
VSS
0.3
VSS + 0.3
V
Mode pins
MB90370 Series
Parameter
Open-drain
output pin
application
voltage
“H” level output
voltage
“L” level output
voltage
Symbol
VD5
VD
VOH1
Pin name
Condition
P40 ~ P45
P80 ~ P82
P90 ~ P95
P46
All port pins
except
P40 ~ P46
P80 ~ P82
P90 ~ P95
PF0 ~ PF7
Min.
Value
Typ.
Max.
Unit
VSS
0.3
VSS + 5.5
V
VSS
0.3
VCC 0.3
V
VCC
IOH1
3.0 V
4.0 mA
VCC
0.5
V
VCC
0.5
V
VOH2
PF0 ~ PF7
VCC
IOH2
3.0 V
8.0 mA
VOL1
All port pins
except
PF0 ~ PF7
IOL1
4.0 mA
0.4
V
VOL2
PF0 ~ PF7
IOL2
12.0 mA
0.4
V
All input pins
VCC
VSS
3.3 V,
VI VCC
Input leakage
current (Hi-Z
output leakage
current)
IIL
Open-drain
output leakage
current
ILEAK
P40 ~ P46
P80 ~ P82
P90 ~ P95
5
5
A
5
A
Remarks
109
MB90370 Series
Parameter
Value
Typ.
Max.
37
45
30
TBD
15
20
mA
23
80
A
ICCLS
VCC 3.3 V,
External 32 kHz,
Internal operation
at 8 kHz,
In sub-clock sleep
mode,
TA 25 C
10
50
A
ICCWAT
VCC 3.3 V,
External 32 kHz,
Internal operation
at 8 kHz,
In watch mode,
TA 25 C
1.5
30
A
ICCT
VCC 3.3 V,
Internal operation
at 16 MHz,
In timebase timer
mode
1.3
2
mA
1
20
A
10
80
pF
Symbol
Pin name
ICCS
ICCL
VCC
Power supply
current*
VCC
LCD divided
resistance
110
CIN
RLCD
VCC 3.3 V,
Internal operation
at 16 MHz,
In sleep mode
VCC 3.3 V,
External 32 kHz,
Internal operation
at 8 kHz,
In sub-clock mode,
TA 25 C
VCC 3.3 V,
In stop mode,
TA 25 C
ICCH
Input
capacitance
Min.
VCC 3.3 V,
Internal operation
at 16 MHz
ICC
Power supply
current*
Condition
All input pins
except VCC,
AVCC, CVCC,
VSS, AVSS, CVSS
Between VCC and V3
at VCC = 3.3 V
100
200
400
Between V3 and V2
Between V2 and V1
Between V1 and VSS
at VCC = 3.3 V
50
100
200
Unit
Remarks
mA MB90F372
mA MB90372
k
MB90370 Series
Parameter
Symbol
Pin name
COM0 ~ COM3
output
impedance
RVCOM
COM0 ~ COM3
SEG0 ~ SEG8
output
impedance
RVSEG
LCD leakage
current
Condition
Min.
Value
Typ.
Max.
Unit
5
k
SEG0 ~ SEG8
5
k
LLCDL
V1 ~ V3
COM0 ~ COM3
SEG0 ~ SEG8
1
Pull-up
resistance
RUP
P00 ~ P07
P10 ~ P17
P20 ~ P27
P30 ~ P37
RST
25
50
100
k
Pull-down
resistance
RDOWN
MD2
25
50
100
k
Remarks
V1 ~ V3 = 3.3 V
A
MB90V370,
MB90372
only
* : The current value is preliminary value and may be subject to change for enhanced characteristics without
previous notice. The power supply current is measured with an external clock.
111
MB90370 Series
4. AC Characteristics
(1) Clock Timings
(VCC
Parameter
Clock frequency
Clock cycle time
Frequency fluctuation
rate locked*
Input clock pulse width
Input clock rise/fall time
Internal operating clock
frequency
Internal operating clock
cycle time
AVCC
CVCC
3.0 V to 3.6 V, VSS
Symbol Pin name Condition
AVSS
CVSS
Value
Min.
Typ.
Max.
0.0 V, TA
Unit
40 C to 85 C)
Remarks
FCH
X0, X1
3
16
MHz Crystal oscillator
FCH
X0, X1
3
32
MHz External clock
FCL
X0A, X1A
tHCYL
X0, X1
tLCYL
X0A, X1A
32.768
31.25
kHz
333
30.5
f
s
5
PWH
PWL
X0
PWHL
PWLL
X0A
tCR
tCF
X0
5
15.2
5
fCP
1.5
16
8.192
fLCP
tCP
62.5
tLCP
%
ns
Recommend duty
ratio of 30% to 70%
s
Recommend duty
ratio of 30% to 70%
ns
External clock
operation
MHz Main clock operation
kHz Sub-clock operation
666
122.1
ns
ns
Main clock operation
s
Sub-clock operation
*: The frequency fluctuation rate is the maximum deviation rate of the preset center frequency when the multiplied
PLL signal is locked.
x 100 (%)
f=
fo
112
Center
frequency
fo
MB90370 Series
X0, X1 clock timing
tHCYL
0.8VCC
X0
0.2VCC
PWH
tCF
PWL
tCR
X0A, X1A clock timing
tLCYL
0.8VCC
X0A
0.2VCC
PWHL
tCF
PWLL
tCR
113
MB90370 Series
PLL operation guarantee range
Power supply voltage VCC (V)
Relationship between internal operating clock frequency and power supply voltage
3.6
Operation guarantee range of PLL
3.0
Normal operation guarantee range
1.5 4
16
Internal operating clock fCP (MHz)
Internal operating clock fCP (MHz)
Relationship between oscillating frequency and internal operating clock frequency
16
Multiplied- Multipliedby-3
by-4
Multipliedby-2
12
9
8
6
Not multiplied
4
3
3
4
8
Oscillation clock FC (MHz)
114
Multipliedby-1
16
MB90370 Series
The AC ratings are measured for the following measurement reference voltages:
Input signal waveform
Output signal waveform
Hysteresis input pin
Output pin
0.8 VCC
0.2 VCC
2.4 V
0.8 V
CMOS input pin
0.7 VCC
0.3 VCC
SMbus input pin
2.1 V
0.8 V
115
MB90370 Series
(2) Reset Input Timing
(VCC
Parameter
Reset input time
Symbol
tRSTL
AVCC
CVCC
Pin name
3.0 V to 3.6 V, VSS
Condition
RST
AVSS
CVSS
0.0 V, TA
Value
Min.
Max.
Unit
40 C to 85 C)
Remarks
16 tCP
ns
Normal
operation
Oscillation time of
oscillator* + 16 tCP
ms
In stop mode
and sub-clock
mode
* : Oscillation time of oscillator is the time to reach to 90% of the oscillation amplitude from stand still. In the crystal
oscillator, the oscillation time is between several ms to tens of ms. In FAR/ceramic oscillator, the oscillation time
is between hundreds of s to several ms. In the external clock, the oscillation time is 0 ms.
In stop mode
tRSTL
RST
0.2VCC
0.2VCC
90% of the oscillation amplitude
X0
Internal
operation
clock
Oscillation time of
oscillator
16tCP
Oscillator stabilization time
Internal reset
116
Instruction
execution
MB90370 Series
(3) Power-on Reset
(VCC
Parameter
AVCC
CVCC
3.0 V to 3.6 V, VSS
Symbol Pin name Condition
Power supply rise time
Power supply cut-off time
tR
VCC*
tOFF
VCC*
AVSS
CVSS
Value
Min.
Max.
50
1
0.0 V, TA
40 C to 85 C)
Unit
Remarks
ms
ms
Due to repeated
operations
* : VCC must be kept lower than 0.2 V before power-on.
Note: The above values are used for causing a power-on reset.
Some registers in the device are initialized only upon a power-on reset. To initialize these registers, turn on
the power supply using the above values.
Note: Make sure that power supply rises within the selected oscillation stabilization time. If the power supply
voltage needs to be varied in the course of operation, a smooth voltage rise is recommended.
tR
tOFF
2.2V
0.2V
0.2V
VCC
0.2V
Sudden changes in the power supply voltage may cause a power-on reset.
To change the power supply voltage while the device is in operation, it is recommneded
to raise the voltage smoothly to suppress fluctuations as shown below. In this case,
change the supply voltage with the PLL clock not used. If the voltage drop is 1 mV
or fewer per second, however, you can use the PLL clock.
VCC
1.8V
RAM data hold
It is recommended to keep
the rising speed of the supply
voltage at 50 mV/ms or slower.
VSS
117
MB90370 Series
(4) UART1 to UART3
(VCC
Parameter
CVCC
3.0 V to 3.6 V, VSS
Symbol
Pin name
Serial clock cycle time
tSCYC
UCK1 ~ UCK3
UCK
t SLOV
UCK1 ~ UCK3
UO1 ~ UO3
UO delay time
Valid UI
UCK
tIVSH
UCK1 ~ UCK3
UI1 ~ UI3
UCK
valid UI hold time
tSHIX
Serial clock “H” pulse width
Serial clock “L” pulse width
UCK
UO delay time
AVSS
CVSS
Condition
0.0 V, TA
Value
Min.
Max.
8 tCP
CL = 80 pF + 1 TTL
for an output pin of
internal shift clock
mode
80
40 C to 85 C)
Unit Remarks
ns
80
ns
100
ns
UCK1 ~ UCK3
UI1 ~ UI3
tCP
ns
tSHSL
UCK1 ~ UCK3
4 tCP
ns
tSLSH
UCK1 ~ UCK3
4 tCP
ns
t SLOV
UCK1 ~ UCK3
UO1 ~ UO3
Valid UI
UCK
tIVSH
UCK1 ~ UCK3
UI1 ~ UI3
UCK
valid UI hold time
tSHIX
UCK1 ~ UCK3
UI1 ~ UI3
Note :
118
AVCC
CL = 80 pF + 1 TTL
for an output pin of
external shift clock
mode
These are AC ratings in the CLK synchronous mode.
CL is the load capacitance value connected to pins while testing.
tCP is the internal operating clock cycle time.
150
ns
60
ns
60
ns
MB90370 Series
Internal shift clock mode
tSCYC
UCK
2.4V
0.8V
0.8V
tSLOV
2.4V
UO
0.8V
tSHIX
tIVSH
0.8VCC
0.8VCC
0.2VCC
0.2VCC
UI
External shift clock mode
tSLSH
tSHSL
UCK
0.8VCC
0.2VCC
0.8VCC
0.2VCC
tSLOV
2.4V
UO
0.8V
tIVSH
tSHIX
0.8VCC
0.8VCC
0.2VCC
0.2VCC
UI
119
MB90370 Series
(5) Resources Input Timing
(VCC
Parameter
AVCC
CVCC
3.0 V to 3.6 V, VSS
Symbol
Pin name
tTIWH
tTIWL
TIN1 ~ TIN4
Timer input pulse width
AVSS
CVSS
0.0 V, TA
Value
Condition
Min.
Max.
4 tCP
0.8VCC
40 C to 85 C)
Unit
Remarks
ns
0.8VCC
TIN1 ~ TIN4
0.2VCC
0.2VCC
tTIWH
tTIWL
(6) Trigger Input Timing
(VCC
AVCC
CVCC
Parameter
Symbol
Pin name
Input pulse width
tTRGH
tTRGL
ADTG
INT0 ~ INT5
KSI0 ~ KSI7
3.0 V to 3.6 V, VSS
Condition
0.8VCC
AVSS
CVSS
Value
Min.
Max.
0.0 V, TA
Unit
5 tCP
ns
1
s
40 C to 85 C)
Remarks
Normal operation
Stop mode
0.8VCC
INT0 ~ INT5
KSI0 ~ KSI7
0.2VCC
tTRGL
tTRGH
0.7VCC
0.2VCC
0.7VCC
ADTG
0.3VCC
tTRGH
120
0.3VCC
tTRGL
MB90370 Series
(7) I2C / MI2C Timing
(VCC
Parameter
AVCC
CVCC
3.0 V to 3.6 V, VSS
AVSS
CVSS
0.0 V, TA
Value
Symbol Pin name
Min.
Max.
40 C to 85 C)
Unit
Remarks
Start condition output
tSTA
SCL
SDA
tCP (m x n/2 -1) - 20
tCP (m x n/2 -1) + 20
ns
Master
mode
Stop condition output
tSTO
SCL
SDA
tCP (m x n/2 + 3) - 20
tCP (m x n/2 + 3) + 20
ns
Master
mode
Start condition detect
tSTA
SCL
SDA
tCP + 40
ns
Stop condition detect
tSTO
SCL
SDA
tCP + 40
ns
Restart condition output
tSTASU
SCL
SDA
tCP (m x n/2 + 3) - 20
Restart condition detect
tSTASU
SCL
SDA
tCP + 40
SCL output “L” width
tLOW
SCL
tCP x m x n/2 - 20
tCP x m x n/2 + 20
ns
Master
mode
SCL output “H” width
tHIGH
SCL
tCP (m x n/2 + 2) - 20
tCP (m x n/2 + 2) + 20
ns
Master
mode
SDA output delay
tDO
SDA
tCP x 3 - 20
tCP x 3 + 20
ns
SDA output setup time
after interrupt
tDOSU
SDA
SCL input “L” pulse
tLOW
SCL input “H” pulse
tCP (m x n/2 +3) + 20
ns
Master
mode
ns
tCP x m x n/2 - 20
ns
*1
tCP x 4 - 20
ns
*2
SCL
tCP x 3 + 40
ns
tHIGH
SCL
tCP + 40
ns
SDA output setup time
tSU
SDA
40
ns
SDA hold time
tHO
SDA
0
ns
Note
• tCP is the internal operating clock cycle time.
• m is the setting bit of shift clock oscillation defined in the “ICCR register (CS4 ~ CS3)” and “MCCR register
(CS4 ~ CS3)”. Please refer to the MB90370 series H/W manual for details.
• n is the setting bit of shift clock oscillation defined in the “ICCR register (CS2 ~ CS0)” and “MCCR register
(CS2 ~ CS0)”. Please refer to the MB90370 series H/W manual for details.
• tDOSU is shown in the interrupt time is longer than the “L” width of SCL.
• SDA and SCL output value is specified on condition that the rise/fall time is “0 ns”.
*1: At the stop condition or transferring of next byte.
*2: After setting register bit IBCRH : SCC at restart.
121
MB90370 Series
Data transmit (master / slave)
tDO
tDO
tSU
tHO
tDOSU
tDO
tDOSU
ACK
SDA
tSTASU
tSTA
tLOW
tHO
1
SCL
9
Data receive (master / slave)
tHO
tSU
tDO
ACK
SDA
tHIGH
SCL
122
6
7
tSTO
tLOW
8
9
MB90370 Series
(8) PS/2 Interface Timing
(VCC
Parameter
PSCK clock
cycle time
PSCK
PSDA
Symbol
Pin name
tPCYC
PSCK0 ~ 2
PSDA0 ~ 2
tPLOV
AVCC
CVCC
3.0 V to 3.6 V, VSS
Condition
Min.
0.0 V, TA
Value
Typ.
Max.
40 C to 85 C)
Unit Remarks
4 tCP
ns
PSCK0 ~ 2
Transmission Mode
PSDA0 ~ 2
PSCK0 ~ 2
PSDA0 ~ 2
Reception Mode
PSCK0 ~ 2
PSDA0 ~ 2
2 tCP
ns
1 tCP
ns
1 tCP
ns
Valid PSDA
PSCK
tPIVSH
PSCK
valid
PSDA hold time
tPHIX
PSCK clock “H”
pulse width
tPHSL
PSCK0 ~ 2
PSDA0 ~ 2
2 tCP
ns
PSCK clock “L”
pulse width
tPLSH
PSCK0 ~ 2
PSDA0 ~ 2
2 tCP
ns
Note: tCP is the internal operating clock cycle time.
tPCYC
PSCK0
PSCK1
PSCK2
0.8VCC
0.8VCC
0.2VCC
tPLOV
Transmission Mode
2.4V
PSDA0
PSDA1
PSDA2
0.8V
Reception Mode
tPIVSH
PSDA0
PSDA1
PSDA2
0.8VCC
tPHIX
0.2VCC
123
MB90370 Series
(9) LPC Timing
(VCC
Parameter
AVCC
CVCC
3.0 V to 3.6 V, VSS
Symbol Pin name Condition
AVSS
Min.
Typ.
0.0 V, TA
Max.
40 C to 85 C)
Unit
LCLK cycle time
tCYCLE
30
ns
LCLK high time
tHIGH
12
ns
LCLK low time
tLOW
12
ns
LCLK AC timing
tCYCLE
tHIGH
0.7VCC
0.3VCC
LCLK
tLOW
124
CVSS
Value
Remarks
MB90370 Series
LAD, LFRAME, GA20 AC timing
0.4VCC
LCLK
tVAL
OUTPUT
Delay
tON
Tri-state
OUTPUT
tOFF
0.4VCC
LCLK
tS
tH
INPUT
125
MB90370 Series
5. A/D Converter Electrical Characteristics
(2.7 V
AVR
Parameter
AVSS, VCC
AVCC
Symbol
Pin
name
CVCC
3.0 V to 3.6 V, VSS
AVSS
Value
Min.
Typ.
Max.
CVSS
Unit
Resolution
Total error
10
3.0
bit
LSB
Non-linear error
2.5
LSB
Differential linearity
error
1.9
LSB
Zero transition
voltage
VOT
Full-scale transition
voltage
VFST
AN0 ~
AN11
AVSS
1.5 LSB
AVSS +
0.5 LSB
AVSS
5.5 LSB
AVSS
2.5 LSB
mV
AN0 ~
AN11
AVR
3.5 LSB
AVR
1.5 LSB
AVR
0.5 LSB
mV
3.1
Conversion time
Sampling period
2
Analog port input
current
IAIN
AN0 ~
AN11
Analog input
voltage
VAIN
AN0 ~
AN11
AVR
Reference voltage
IA
Power supply
current
IAH
Reference voltage
supply current
IRH
Offset between
channels
IR
—
AVCC
AVR
AN0 ~
AN11
0.1
AVSS
AVSS
2.7
1.4
94
0.0 V, TA
40 C to 85 C)
Remarks
For MB90V370
For MB90F372/372
s
Actual value is specified as
a sum of values specified in
ADCR0 : CT1, CT0 and
ADCR0 : ST1, ST0. Be sure
that the setting value is
greater than the min value
s
Actual value is specified in
ADCR0 : ST1, ST0 bits. Be
sure that the setting value is
greater than the min value
10
A
AVR
V
AVCC
6.4
V
mA
5
A
300
A
5
A
4
LSB
*
*
*: The current when the A/D converter is not operating or the CPU is in stop mode (for VCC = AVCC = AVR = 3.0 V).
126
MB90370 Series
6. A/D Converter Glossary
Resolution : Analog changes that are identifiable with the A/D converter.
Linearity error : The deviation of the straight line connecting the zero transition point (“00 0000 0000”
“00
“11 1111 1111”) from actual
0000 0001”) with the full-scale transition point (“11 1111 1110”
conversion characteristics.
Differential linearity error : The deviation of input voltage needed to change the output code by 1 LSB from the
theoretical value.
Total error : The total error is defined as a difference between the actual value and the theoretical value, which
includes zero-transition error/full-scale transition error and linearity error.
Total error
Digital output
3FF
3FE
3FD
Actual conversion
value
0.5 LSB
{1 LSB x (N - 1) + 0.5 LSB}
004
VNT
003
Actual conversion
value
Theoretical
characteristics
002
001
(Measured value)
0.5 LSB
AVRL
AVRH
Analog input
VNT
Total error for digital output N =
1 LSB
(Theoretical value)
{1 LSB
AVR AVss
1024
VOT (Theoretical value)
AVss
0.5 LSB [V]
VFST (Theoretical value)
AVR
1.5 LSB [V]
(N 1)
1 LSB
0.5 LSB}
[LSB]
[V]
VNT : Voltage at a transition of digital output from (N - 1) to N
(Continued)
127
MB90370 Series
(Continued)
Linearity error
Theoretical
characteristics
Actual conversion
value
{1 LSB x (N -1)
+ VOT }
004
003
002
001
Actual conversion
value
N+1
VFST
(Measured
value)
VNT
(Measured value)
Digital output
Digital output
3FF
3FE
3FD
Differential linearity error
Actual conversion
value
Theoretical
characteristics
VOT (Measured value)
N
V(N + 1)T
N-1
(Measured value)
Actual conversion
value
N-2
AVRH
AVRL
VNT
AVRH
AVRL
Analog input
Analog input
Linearity error of
digital output N
Differential linearity error
of digital output N
1 LSB
VNT
V (N
{1 LSB (N
1 LSB
1) T
VNT
1 LSB
VFST VOT
1022
1)
VOT}
[LSB]
1 [LSB]
[V]
VOT : Voltage at transition of digital output from “000H” to “001H”
VFST : Voltage at transition of digital output from “3FE H” to “3FFH”
128
(Measured
value)
MB90370 Series
7. Notes on Using A/D Converter
Select the output impedance value for the external circuit of analog input according to the following conditions.
Output impedance values of the external circuit of 4 k
or lower are recommended.
When capacitors are connected to external pins, the capacitance of several thousand times the internal capacitor
value is recommended to minimized the effect of voltage distribution between the external capacitor and internal
capacitor.
When the output impedance of the external circuit is too high, the sampling period for analog voltages may not
be sufficient.
Equipment of analog input circuit model
Sampling and hold circuit
Analog input
Comparator
R
C
R : about 1.9 k
C : about 32.3 pF
Note: Listed values must be considered as standards.
• Error
The smaller the | AVR - AVSS |, the greater the error would become relatively.
8. D/A Electrical Characteristics
(VCC
Parameter
AVCC
CVCC
Symbol Pin name
3.0 V to 3.6V, VSS
Condition
AVSS
CVSS
0.0 V, TA
Value
Min.
Resolution
Typ.
Max.
8
40 C to 85 C)
Unit
bit
Differential linearity error
0.9
LSB
Non-linearity error
1.5
LSB
0.6
Conversion time
Analog output impedance
2.0
Power supply
IDVR
AVCC
Current
IDVRS
AVCC
2.9
s
3.8
460
0.1
Remarks
*
k
A
A
D/A stops
* : With load capacitance is 20 pF.
129
MB90370 Series
9. Comparator Electrical Characteristics
(VCC
Parameter
AVCC
CVCC
Symbol Pin name Condition
Reference voltage
AVSS
CVSS
0.0 V, TA
Value
Min.
Typ.
40 C to 85 C)
Unit
Max.
CVRH2
1.1
2.9
V
CVRH1
CVRL
2.9
V
CVRL
1.1
CVRH1
V
Reference voltage
supply current
ICR
CVRH2
CVRH1
CVRL
Comparator
supply current
ICV
CVCC
VIH
DCIN
DCIN2
VOL1 ~ 3
VSI1 ~ 3
Analog input voltage
3.3 V to 3.6 V, VSS
CVSS
Remarks
1
A
50
A
active
10
A
inactive
CVCC
V
10. Serial IRQ Electrical Characteristics
(VCC
Parameter
AVCC
CVCC
3.0 V to 3.6 V, VSS
Symbol Pin name Condition
AVSS
CVSS
0.0 V, TA
Value
Min.
Typ.
40 C to 85 C)
Unit
Max.
“H” level input voltage
VIH
0.7VCC
VCC
V
“L” level input voltage
VIL
VSS
0.3VCC
V
“H” level output voltage
VOH
VCC - 0.5
“L” level output voltage
VOL
Remarks
V
0.4
V
11. Flash Memory Program/Erase Characteristics
Parameter
Condition
Value
Min.
Sector erase time
Chip erase time
TA +25 C
VCC 3.0 V
130
Max.
1
15
4
Word (16 bit width)
programing time
Program/Erase cycle
Typ.
16
10,000
3,600
Unit
Remarks
s
Excludes 00H programming prior
to erasure
s
Excludes 00H programming prior
to erasure
s
Except for the over head time of
the system
V
MB90370 Series
EXAMPLE CHARACTERISTICS (MB90F372)
• Power Supply Current
Ta=25[
ICC[mA]
]
Ta=25[
ICCS[mA]
Fcin=16[MHz]
50.0
]
18.0
Fcin= 16[MHz]
16.0
40.0
Fcin=12[MHz]
14.0
Fcin=12[MHz]
Fcin= 10[MHz]
30.0
12.0
Fcin= 10[MHz]
10.0
Fcin=8[MHz]
Fcin= 8[MHz]
8.0
20.0
6.0
Fcin= 4[MHz]
Fcin=4[MHz]
4.0
10.0
Fcin=2[MHz]
Fcin= 2[MHz]
2.0
Vcc[V]
0.0
2.0
2.5
3.0
Ta=25[
ICCH[ A]
2.5
3.5
4.0
Vcc[V]
0.0
2.0
2.5
3.0
3.5
4.0
]
Fc=32.0[kHz]
2.0
1.5
1.0
0.5
Vcc[V]
0.0
2.5
3.0
3.5
4.0
(Continued)
131
MB90370 Series
(Continued)
V CC-VOH1 [V]
2.0
Ta=25[
]
Ta=25[
V CC-VOH2[V]
0.7
]
0.6
1.5
0.5
Vcc=2.5[V]
Vcc=2.5[V]
0.4
Vcc=3.0[V]
1.0
Vcc=3.0[V]
Vcc=3.5[V]
Vcc=4.0[V]
Vcc=3.5[V]
Vcc=4.0[V]
0.3
0.2
0.5
0.1
0.0
IOH1[mA]
0
-2
VOL1[V]
0.8
-4
-6
Ta=25[
]
-8
-10
IOH2[mA]
0.0
0
-2
VOL2[V]
0.3
Vcc=2.5[V]
Vcc=3.0[V]
Vcc=4.0[V]
Vcc=3.5[V]
0.6
-4
-6
Ta=25[
]
-8
-10
Vcc=2.5[V]
Vcc=3.0[V]
Vcc=3.5[V]
Vcc=4.0[V]
0.2
0.4
0.1
0.2
IOL1[mA]
0.0
0
132
2
4
6
8
10
0.0
0
2
4
6
8
IOL2[mA]
10
MB90370 Series
INSTRUCTIONS (351 INSTRUCTIONS)
Table 1
Item
Mnemonic
#
~
RG
B
Operation
LH
AH
I
S
T
N
Z
V
C
RMW
Explanation of Items in Tables of Instructions
Meaning
Upper-case letters and symbols: Represented as they appear in assembler.
Lower-case letters:
Replaced when described in assembler.
Numbers after lower-case letters: Indicate the bit width within the instruction code.
Indicates the number of bytes.
Indicates the number of cycles.
m : When branching
n : When not branching
See Table 4 for details about meanings of other letters in items.
Indicates the number of accesses to the register during execution of the instruction.
It is used calculate a correction value for intermittent operation of CPU.
Indicates the correction value for calculating the number of actual cycles during execution of the
instruction. (Table 5)
The number of actual cycles during execution of the instruction is the correction value summed
with the value in the “~” column.
Indicates the operation of instruction.
Indicates special operations involving the upper 8 bits of the lower 16 bits of the accumulator.
Z : Transfers “0”.
X : Extends with a sign before transferring.
– : Transfers nothing.
Indicates special operations involving the upper 16 bits in the accumulator.
* : Transfers from AL to AH.
– : No transfer.
Z : Transfers 00H to AH.
X : Transfers 00H or FFH to AH by signing and extending AL.
Indicates the status of each of the following flags: I (interrupt enable), S (stack), T (sticky bit),
N (negative), Z (zero), V (overflow), and C (carry).
* : Changes due to execution of instruction.
– : No change.
S : Set by execution of instruction.
R : Reset by execution of instruction.
Indicates whether the instruction is a read-modify-write instruction. (a single instruction that
reads data from memory, etc., processes the data, and then writes the result to memory.)
* : Instruction is a read-modify-write instruction.
– : Instruction is not a read-modify-write instruction.
Note: A read-modify-write instruction cannot be used on addresses that have different
meanings depending on whether they are read or written.
• Number of execution cycles
The number of cycles required for instruction execution is acquired by adding the number of cycles for each
instruction, a corrective value depending on the condition, and the number of cycles required for program fetch.
Whenever the instruction being executed exceeds the two-byte (word) boundary, a program on an internal
ROM connected to a 16-bit bus is fetched. If data access is interfered with, therefore, the number of execution
cycles is increased.
For each byte of the instruction being executed, a program on a memory connected to an 8-bit external data
bus is fetched. If data access in interfered with, therefore, the number of execution cycles is increased.
When a general-purpose register, an internal ROM, an internal RAM, an internal I/O device, or an external
bus is accessed during intermittent CPU operation, the CPU clock is suspended by the number of cycles
specified by the CG1/0 bit of the low-power consumption mode control register. When determining the number
of cycles required for instruction execution during intermittent CPU operation, therefore, add the value of the
number of times access is done the number of cycles suspended as the corrective value to the number of
ordinary execution cycles.
133
MB90370 Series
Table 2
Explanation of Symbols in Tables of Instructions
Symbol
A
32-bit accumulator
The bit length varies according to the instruction.
Byte : Lower 8 bits of AL
Word : 16 bits of AL
Long : 32 bits of AL and AH
AH
AL
Upper 16 bits of A
Lower 16 bits of A
SP
Stack pointer (USP or SSP)
PC
Program counter
PCB
Program bank register
DTB
Data bank register
ADB
Additional data bank register
SSB
System stack bank register
USB
User stack bank register
SPB
Current stack bank register (SSB or USB)
DPR
Direct page register
brg1
DTB, ADB, SSB, USB, DPR, PCB, SPB
brg2
DTB, ADB, SSB, USB, DPR, SPB
Ri
RWi
R0, R1, R2, R3, R4, R5, R6, R7
RW0, RW1, RW2, RW3, RW4, RW5, RW6, RW7
RWj
RW0, RW1, RW2, RW3
RLi
RL0, RL1, RL2, RL3
dir
Compact direct addressing
addr16
addr24
ad24 0 to 15
ad24 16 to 23
Direct addressing
Physical direct addressing
Bit 0 to bit 15 of addr24
Bit 16 to bit 23 of addr24
io
imm4
imm8
imm16
imm32
ext (imm8)
disp8
disp16
bp
I/O area (000000H to 0000FFH)
4-bit immediate data
8-bit immediate data
16-bit immediate data
32-bit immediate data
16-bit data signed and extended from 8-bit immediate data
8-bit displacement
16-bit displacement
Bit offset
vct4
vct8
Vector number (0 to 15)
Vector number (0 to 255)
( )b
Bit address
rel
ear
eam
rlst
134
Meaning
PC relative addressing
Effective addressing (codes 00 to 07)
Effective addressing (codes 08 to 1F)
Register list
MB90370 Series
Table 3
Code
00
01
02
03
04
05
06
07
Notation
R0
R1
R2
R3
R4
R5
R6
R7
RW0
RW1
RW2
RW3
RW4
RW5
RW6
RW7
Effective Address Fields
Address format
RL0
(RL0)
RL1
(RL1)
RL2
(RL2)
RL3
(RL3)
Number of bytes in address
extension *
Register direct
“ea” corresponds to byte, word, and
long-word types, starting from the left
08
09
0A
0B
@RW0
@RW1
@RW2
@RW3
Register indirect
0C
0D
0E
0F
@RW0 +
@RW1 +
@RW2 +
@RW3 +
Register indirect with post-increment
10
11
12
13
14
15
16
17
@RW0 + disp8
@RW1 + disp8
@RW2 + disp8
@RW3 + disp8
@RW4 + disp8
@RW5 + disp8
@RW6 + disp8
@RW7 + disp8
Register indirect with 8-bit
displacement
18
19
1A
1B
@RW0 + disp16
@RW1 + disp16
@RW2 + disp16
@RW3 + disp16
Register indirect with 16-bit
displacement
1C
1D
1E
1F
@RW0 + RW7
@RW1 + RW7
@PC + disp16
addr16
Register indirect with index
Register indirect with index
PC indirect with 16-bit displacement
Direct address
—
0
0
1
2
0
0
2
2
Note : The number of bytes in the address extension is indicated by the “+” symbol in the “#” (number of bytes)
column in the tables of instructions.
135
MB90370 Series
Table 4
Number of Execution Cycles for Each Type of Addressing
(a)
Code
Operand
Number of execution cycles
for each type of addressing
Number of register accesses
for each type of addressing
00 to 07
Ri
RWi
RLi
08 to 0B
@RWj
2
1
0C to 0F
@RWj +
4
2
10 to 17
@RWi + disp8
2
1
18 to 1B
@RWj + disp16
2
1
1C
1D
1E
1F
@RW0 + RW7
@RW1 + RW7
@PC + disp16
addr16
4
4
2
1
2
2
0
0
Listed in tables of instructions
Listed in tables of instructions
Note : “(a)” is used in the “~” (number of states) column and column B (correction value) in the tables of instructions.
Table 5
Compensation Values for Number of Cycles Used to Calculate Number of Actual Cycles
Operand
(c) word
(d) long
Cycles
Access
Cycles
Access
Cycles
Access
Internal register
+0
1
+0
1
+0
2
Internal memory even address
Internal memory odd address
+0
+0
1
1
+0
+2
1
2
+0
+4
2
4
Even address on external data bus (16 bits)
Odd address on external data bus (16 bits)
+1
+1
1
1
+1
+4
1
2
+2
+8
2
4
External data bus (8 bits)
+1
1
+4
2
+8
4
Notes:
“(b)”, “(c)”, and “(d)” are used in the “~” (number of states) column and column B (correction value)
in the tables of instructions.
When the external data bus is used, it is necessary to add in the number of wait cycles used for ready
input and automatic ready.
Table 6
Correction Values for Number of Cycles Used to Calculate Number of Program Fetch Cycles
Instruction
Byte boundary
Word boundary
Internal memory
—
+2
External data bus (16 bits)
—
+3
External data bus (8 bits)
+3
—
Notes:
136
(b) byte
When the external data bus is used, it is necessary to add in the number of wait cycles used for ready
input and automatic ready.
Because instruction execution is not slowed down by all program fetches in actuality, these correction
values should be used for “worst case” calculations.
MB90370 Series
Table 7
Mnemonic
#
~
Transfer Instructions (Byte) [41 Instructions]
RG
B
Operation
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOVN
A, dir
A, addr16
A, Ri
A, ear
A, eam
A, io
A, #imm8
A, @A
A, @RLi+disp8
A, #imm4
2
3
3
4
1
2
2
2
2+ 3+ (a)
2
3
2
2
2
3
3
10
1
1
0
0
1
1
0
0
0
0
2
0
(b)
(b)
0
0
(b)
(b)
0
(b)
(b)
0
byte (A)
byte (A)
byte (A)
byte (A)
byte (A)
byte (A)
byte (A)
byte (A)
byte (A)
byte (A)
MOVX
MOVX
MOVX
MOVX
MOVX
MOVX
MOVX
MOVX
MOVX
MOVX
A, dir
A, addr16
A, Ri
A, ear
A, eam
A, io
A, #imm8
A, @A
A,@RWi+disp8
A, @RLi+disp8
2
3
3
4
2
2
2
2
2+ 3+ (a)
2
3
2
2
2
3
2
5
3
10
0
0
1
1
0
0
0
0
1
2
(b)
(b)
0
0
(b)
(b)
0
(b)
(b)
(b)
byte (A)
(dir)
(addr16)
byte (A)
byte (A)
(Ri)
byte (A)
(ear)
(eam)
byte (A)
byte (A)
(io)
byte (A)
imm8
byte (A)
((A))
byte (A)
((RWi)+disp8)
byte (A) ((RLi)+disp8)
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
/MOV
dir, A
addr16, A
Ri, A
ear, A
eam, A
io, A
@RLi+disp8, A
Ri, ear
Ri, eam
ear, Ri
eam, Ri
Ri, #imm8
io, #imm8
dir, #imm8
ear, #imm8
eam, #imm8
@AL, AH
@A, T
2
3
1
2
2+
2
3
2
2+
2
2+
2
3
3
3
3+
3
4
2
2
3+ (a)
3
10
3
4+ (a)
4
5+ (a)
2
5
5
2
4+ (a)
0
0
1
1
0
0
2
2
1
2
1
1
0
0
1
0
2
3
0
XCH
XCH
XCH
XCH
A, ear
A, eam
Ri, ear
Ri, eam
2
4
2+ 5+ (a)
2
7
2+ 9+ (a)
2
0
4
2
(dir)
(addr16)
(Ri)
(ear)
(eam)
(io)
imm8
((A))
((RLi)+disp8)
imm4
LH AH
I
S
T
N
Z
V
C
RMW
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
*
*
*
*
*
*
*
–
*
*
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
– *
– *
– *
– *
– *
– *
– *
– *
– *
– R
*
*
*
*
*
*
*
*
*
*
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
X *
X *
X *
X *
X *
X *
X *
X –
X *
X *
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
–
–
*
–
*
*
*
*
*
*
*
*
*
*
*
*
–
–
*
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
byte (dir)
(A)
–
byte (addr16)
(A)
–
byte (Ri)
(A)
–
byte (ear)
(A)
–
byte (eam)
(A)
–
byte (io)
(A)
–
byte ((RLi) +disp8) (A) –
byte (Ri)
(ear)
–
byte (Ri)
(eam)
–
(Ri)
byte (ear)
–
byte (eam)
(Ri)
–
byte (Ri)
imm8
–
imm8
byte (io)
–
byte (dir)
imm8
–
byte (ear)
imm8
–
byte (eam)
imm8
–
(b)
byte ((A))
(AH)
Z
0
(ear)
Z
2 (b) byte (A)
0
byte (A)
(eam)
–
2 (b) byte (Ri)
(ear)
–
byte (Ri)
(eam)
(b)
(b)
0
0
(b)
(b)
(b)
0
(b)
0
(b)
0
(b)
(b)
0
(b)
Note : For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,”
and Table 6, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”
137
MB90370 Series
Table 8
Mnemonic
RG
B
2
3
3
4
1
1
1
2
2
2
2+ 3+ (a)
2
3
2
3
3
2
2
5
3
10
0
0
0
1
1
0
0
0
0
1
2
(c)
(c)
0
0
0
(c)
(c)
(c)
0
(c)
(c)
word (A)
word (A)
word (A)
word (A)
word (A)
word (A)
word (A)
word (A)
word (A)
MOVW dir, A
MOVW addr16, A
MOVW SP, A
MOVW RWi, A
MOVW ear, A
MOVW eam, A
MOVW io, A
MOVW @RWi+disp8, A
MOVW @RLi+disp8, A
MOVW RWi, ear
MOVW RWi, eam
MOVW ear, RWi
MOVW eam, RWi
MOVW RWi, #imm16
MOVW io, #imm16
MOVW ear, #imm16
MOVW eam, #imm16
MOVW @AL, AH
/[email protected], T
2
3
1
1
2
2+
2
2
3
2
2+
2
2+
3
4
4
4+
3
4
1
2
2
3+ (a)
3
5
10
3
4+ (a)
4
5+ (a)
2
5
2
4+ (a)
0
0
0
1
1
0
0
1
2
2
1
2
1
1
0
1
0
(c)
(c)
0
0
0
(c)
(c)
(c)
(c)
(0)
(c)
0
(c)
0
(c)
0
(c)
(A)
word (dir)
word (addr16)
(A)
word (SP)
(A)
(A)
word (RWi)
word (ear)
(A)
word (eam)
(A)
word (io)
(A)
2
3
0
(c)
word ((A))
XCHW
XCHW
XCHW
XCHW
2
4
2+ 5+ (a)
2
7
2+ 9+ (a)
2
0
0 2 (c)
0
4
2 2 (c)
(ear)
word (A)
word (A)
(eam)
word (RWi)
(ear)
(eam)
word (RWi)
MOVL A, ear
MOVL A, eam
MOVL A, #imm32
2
4
2+ 5+ (a)
5
3
2
0
0
0
(d)
0
long (A)
long (A)
long (A)
MOVL ear, A
MOVL eam, A
2
4
2+ 5+ (a)
2
0
0
(d)
long (ear)
long (eam)
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
A, dir
A, addr16
A, SP
A, RWi
A, ear
A, eam
A, io
A, @A
A, #imm16
A, @RWi+disp8
A, @RLi+disp8
A, ear
A, eam
RWi, ear
RWi, eam
#
Transfer Instructions (Word/Long Word) [38 Instructions]
~
Operation
LH AH
I
S
T
N
Z
V
C
RMW
–
–
–
–
–
–
–
–
–
((RWi) +disp8) –
((RLi) +disp8) –
*
*
*
*
*
*
*
–
*
*
*
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
word ((RWi) +disp8)
(A) –
word ((RLi) +disp8)
(A) –
(ear)
word (RWi)
–
word (RWi)
(eam)
–
word (ear)
(RWi)
–
word (eam)
(RWi)
–
word (RWi)
imm16
–
word (io)
imm16
–
word (ear)
imm16
–
word (eam)
imm16
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
*
*
–
*
–
*
*
*
*
*
*
*
*
*
*
*
*
*
*
–
*
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
(ear)
(eam)
imm32
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
–
–
–
–
–
–
–
–
–
(A)
(A)
–
–
–
–
–
–
–
–
–
–
*
*
*
*
–
–
–
–
–
–
word (A)
word (A)
(dir)
(addr16)
(SP)
(RWi)
(ear)
(eam)
(io)
((A))
imm16
(AH)
Note : For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,”
and Table 6, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”
138
MB90370 Series
Table 9
Addition and Subtraction Instructions (Byte/Word/Long Word) [42 Instructions]
Mnemonic
ADD
ADD
ADD
ADD
ADD
ADD
ADDC
ADDC
ADDC
ADDDC
SUB
SUB
SUB
SUB
SUB
SUB
SUBC
SUBC
SUBC
SUBDC
#
~
RG
B
Operation
2
2
2
2+
2
2+
1
2
2+
1
2
2
2
2+
2
2+
1
2
2+
1
2
5
3
4+ (a)
3
5+ (a)
2
3
4+ (a)
3
2
5
3
4+ (a)
3
5+ (a)
2
3
4+ (a)
3
0
0
1
0
2
0
0
1
0
0
0
0
1
0
2
0
0
1
0
0
0
(b)
0
(b)
0
2 (b)
0
0
(b)
0
0
(b)
0
(b)
0
2 (b)
0
0
(b)
0
byte (A)
(A) +imm8
(A) +(dir)
byte (A)
byte (A)
(A) +(ear)
(A) +(eam)
byte (A)
(ear) + (A)
byte (ear)
byte (eam)
(eam) + (A)
byte (A)
(AH) + (AL) + (C)
byte (A)
(A) + (ear) + (C)
byte (A)
(A) + (eam) + (C)
Z
Z
Z
Z
–
Z
Z
Z
Z
byte (A) (AH) + (AL) + (C) (decimal) Z
byte (A)
(A) –imm8
Z
byte (A)
(A) – (dir)
Z
(A) – (ear)
byte (A)
Z
byte (A)
(A) – (eam)
Z
byte (ear)
(ear) – (A)
–
(eam) – (A)
byte (eam)
–
byte (A)
(AH) – (AL) – (C) Z
byte (A)
(A) – (ear) – (C) Z
byte (A)
(A) – (eam) – (C) Z
byte (A) (AH) – (AL) – (C) (decimal) Z
1
2
2+
3
2
2+
2
2+
1
2
2+
3
2
2+
2
2+
2
3
4+ (a)
2
3
5+ (a)
3
4+ (a)
2
3
4+ (a)
2
3
5+ (a)
3
4+ (a)
0
1
0
0
2
0
1
0
0
1
0
0
2
0
1
0
0
0
(c)
0
0
2 (c)
0
(c)
0
0
(c)
0
0
2 (c)
0
(c)
(AH) + (AL)
word (A)
word (A)
(A) +(ear)
word (A)
(A) +(eam)
word (A)
(A) +imm16
word (ear)
(ear) + (A)
word (eam)
(eam) + (A)
word (A)
(A) + (ear) + (C)
word (A)
(A) + (eam) +
(C)
word (A)
(AH) – (AL)
word (A)
(A) – (ear)
word (A)
(A) – (eam)
word (A)
(A) –imm16
word (ear)
(ear) – (A)
word (eam)
(eam) – (A)
word (A)
(A) – (ear) – (C)
word (A)
(A) – (eam) – (C)
A, ear
2
6
2+ 7+ (a)
A, eam
4
A, #imm32 5
6
A, ear
2
A, eam
2+ 7+ (a)
4
A, #imm32 5
2
0
0
2
0
0
0
(d)
0
0
(d)
0
long (A)
long (A)
long (A)
long (A)
long (A)
long (A)
A,#imm8
A, dir
A, ear
A, eam
ear, A
eam, A
A
A, ear
A, eam
A
A, #imm8
A, dir
A, ear
A, eam
ear, A
eam, A
A
A, ear
A, eam
A
ADDW A
ADDW A, ear
ADDW A, eam
ADDW A, #imm16
ADDW ear, A
ADDW eam, A
ADDCW A, ear
ADDCW A, eam
SUBW A
SUBW A, ear
SUBW A, eam
SUBW A, #imm16
SUBW ear, A
SUBW eam, A
SUBCW A, ear
SUBCW A, eam
ADDL
ADDL
ADDL
SUBL
SUBL
SUBL
(A) + (ear)
(A) + (eam)
(A) +imm32
(A) – (ear)
(A) – (eam)
(A) –imm32
LH AH
I
S
T
N
Z
V
C
RMW
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
–
–
–
–
–
*
–
–
–
–
–
–
–
–
–
*
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
–
–
–
–
–
*
–
–
–
–
–
–
–
*
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
–
–
–
–
–
–
Note : For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,”
and Table 6, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”
139
MB90370 Series
Table 10
Increment and Decrement Instructions (Byte/Word/Long Word) [12 Instructions]
Mnemonic
#
~
RG
B
Operation
LH
AH
I
S
T
N
Z
V
C
RMW
INC
INC
ear
eam
2
2+
2
5+ (a)
2
0
byte (ear)
0
2 (b) byte (eam)
(ear) +1
(eam) +1
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
–
–
–
*
DEC
DEC
ear
eam
2
2+
3
5+ (a)
2
0
0
byte (ear)
2 (b) byte (eam)
(ear) –1
(eam) –1
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
–
–
–
*
INCW
INCW
ear
eam
2
2+
3
5+ (a)
2
0
word (ear)
0
2 (c) word (eam)
(ear) +1
(eam) +1
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
–
–
–
*
DECW ear
DECW eam
2
2+
3
5+ (a)
2
0
0
word (ear)
2 (c) word (eam)
(ear) –1
(eam) –1
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
–
–
–
*
INCL
INCL
ear
eam
2
2+
7
9+ (a)
4
0
long (ear)
0
2 (d) long (eam)
(ear) +1
(eam) +1
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
–
–
–
*
DECL
DECL
ear
eam
2
2+
7
9+ (a)
4
0
0
long (ear)
2 (d) long (eam)
(ear) –1
(eam) –1
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
–
–
–
*
Note : For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,”
and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”
Table 11
Mnemonic
Compare Instructions (Byte/Word/Long Word) [11 Instructions]
#
~
RG
B
Operation
LH
AH
I
S
T
N
Z
V
C
RMW
CMP
CMP
CMP
CMP
A
A, ear
A, eam
A, #imm8
1
2
2+
2
1
2
3+ (a)
2
0
1
0
0
0
0
(b)
0
byte (AH) – (AL)
(ear)
byte (A)
byte (A)
(eam)
byte (A)
imm8
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
–
–
–
–
CMPW
CMPW
CMPW
CMPW
A
1
A, ear
2
A, eam
2+
A, #imm16 3
1
2
3+ (a)
2
0
1
0
0
0
0
(c)
0
word (AH) – (AL)
word (A)
(ear)
word (A)
(eam)
word (A)
imm16
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
–
–
–
–
CMPL
CMPL
CMPL
A, ear
2
A, eam
2+
A, #imm32 5
6
7+ (a)
3
2
0
0
0
(d)
0
word (A)
word (A)
word (A)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
–
–
–
(ear)
(eam)
imm32
Note : For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,”
and Table 6, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”
140
MB90370 Series
Table 12
Mnemonic
DIVU
A
Multiplication and Division Instructions (Byte/Word/Long Word) [11 Instructions]
#
~
1
1
*
RG
0
B
Operation
0 word (AH) /byte (AL)
Quotient
DIVU
A, ear
2
*2
1
A, eam 2+ *3
0
2
*4
1
0
word (A) Remainder
word (A) Remainder
N
Z
V
C
RMW
–
–
–
–
–
–
–
*
*
–
–
–
–
–
–
–
–
*
*
–
–
–
–
–
–
–
–
*
*
–
–
–
–
–
–
–
–
*
*
–
–
–
–
–
–
–
–
*
*
–
word (ear)
*7 long (A)/word (eam)
Quotient
T
byte (eam)
0 long (A)/word (ear)
Quotient
DIVUW A, eam 2+ *5
byte (A) Remainder
S
byte (ear)
*6 word (A)/byte (eam)
Quotient
DIVUW A, ear
byte (A) Remainder
I
byte (AH)
0 word (A)/byte (ear)
Quotient
DIVU
byte (AL) Remainder
LH AH
word (ear)
A
1 *8
A, ear
2 *9
A, eam 2+ *10
0 0 byte (AH) *byte (AL) word (A)
1 0 byte (A) *byte (ear) word (A)
0 (b) byte (A) *byte (eam) word (A)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
MULUW A
1 *11
MULUW A, ear
2 *12
MULUW A, eam 2+ *13
0 0 word (AH) *word (AL) long (A)
1 0 word (A) *word (ear) long (A)
0 (c) word (A) *word (eam) long (A)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
MULU
MULU
MULU
*1:
*2:
*3:
*4:
*5:
*6:
*7:
*8:
*9:
*10:
*11:
*12:
*13:
3 when the result is zero, 7 when an overflow occurs, and 15 normally.
4 when the result is zero, 8 when an overflow occurs, and 16 normally.
6 + (a) when the result is zero, 9 + (a) when an overflow occurs, and 19 + (a) normally.
4 when the result is zero, 7 when an overflow occurs, and 22 normally.
6 + (a) when the result is zero, 8 + (a) when an overflow occurs, and 26 + (a) normally.
(b) when the result is zero or when an overflow occurs, and 2 (b) normally.
(c) when the result is zero or when an overflow occurs, and 2 (c) normally.
3 when byte (AH) is zero, and 7 when byte (AH) is not zero.
4 when byte (ear) is zero, and 8 when byte (ear) is not zero.
5 + (a) when byte (eam) is zero, and 9 + (a) when byte (eam) is not 0.
3 when word (AH) is zero, and 11 when word (AH) is not zero.
4 when word (ear) is zero, and 12 when word (ear) is not zero.
5 + (a) when word (eam) is zero, and 13 + (a) when word (eam) is not zero.
Note : For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,”
and Table 6, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”
141
MB90370 Series
Table 13
Signed Multiplication and Division Instructions (Byte/Word/Long Word) [11 Instructions]
Mnemonic
#
~
RG
B
0
DIV
A
2
*1
0
DIV
A, ear
2
*2
1
DIV
A, eam 2 +
*3
0
DIVW
A, ear
2
*4
1
DIVW
A, eam
2+
*5
0
MULU
MULU
MULU
MULUW
MULUW
MULUW
A
2
A, ear
2
A, eam 2 +
A
2
A, ear
2
A, eam 2 +
*8
*9
*10
*11
*12
*13
0
1
0
0
1
0
Operation
word (AH) /byte (AL)
byte (AL)
Quotient
Remainder
byte (AH)
0 word (A)/byte (ear)
Quotient
byte (A)
byte (ear)
Remainder
*6 word (A)/byte (eam)
Quotient
byte (A)
byte (eam)
Remainder
0 long (A)/word (ear)
Quotient
word (A)
word (ear)
Remainder
*7 long (A)/word (eam)
word (A)
Quotient
Remainder
word (eam)
0
0
(b)
0
0
(c)
byte (AH) *byte (AL)
byte (A) *byte (ear)
byte (A) *byte (eam)
word (AH) *word (AL)
word (A) *word (ear)
word (A) *word (eam)
word (A)
word (A)
word (A)
long (A)
long (A)
long (A)
LH
AH
I
S
T
N
Z
V
C
RMW
Z
–
–
–
–
–
–
*
*
–
Z
–
–
–
–
–
–
*
*
–
Z
–
–
–
–
–
–
*
*
–
–
–
–
–
–
–
–
*
*
–
–
–
–
–
–
–
–
*
*
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*1:
*2:
*3:
*4:
Set to 3 when the division-by-0, 8 or 18 for an overflow, and 18 for normal operation.
Set to 3 when the division-by-0, 10 or 21 for an overflow, and 22 for normal operation.
Set to 4 + (a) when the division-by-0, 11 + (a) or 22 + (a) for an overflow, and 23 + (a) for normal operation.
Positive dividend: Set to 4 when the division-by-0, 10 or 29 for an overflow, and 30 for normal operation.
Negative dividend: Set to 4 when the division-by-0, 11 or 30 for an overflow and 31 for normal operation.
*5: Positive dividend:Set to 4 + (a) when the division-by-0, 11 + (a) or 30 + (a) for an overflow, and 31 + (a) for
normal operation.
Negative dividend: Set to 4 + (a) when the division-by-0, 12 + (a) or 31 + (a) for an overflow, and 32 + (a) for
normal operation.
*6: When the division-by-0, (b) for an overflow, and 2 (b) for normal operation.
*7: When the division-by-0, (c) for an overflow, and 2 (c) for normal operation.
*8: Set to 3 when byte (AH) is zero, 12 when the result is positive, and 13 when the result is negative.
*9: Set to 3 when byte (ear) is zero, 12 when the result is positive, and 13 when the result is negative.
*10: Set to 4 + (a) when byte (eam) is zero, 13 + (a) when the result is positive, and 14 + (a) when the result is
negative.
*11: Set to 3 when word (AH) is zero, 12 when the result is positive, and 13 when the result is negative.
*12: Set to 3 when word (ear) is zero, 16 when the result is positive, and 19 when the result is negative.
*13: Set to 4 + (a) when word (eam) is zero, 17 + (a) when the result is positive, and 20 + (a) when the result is
negative.
Notes: • When overflow occurs during DIV or DIVW instruction execution, the number of execution cycles takes
two values because of detection before and after an operation.
• When overflow occurs during DIV or DIVW instruction execution, the contents of AL are destroyed.
• For (a) to (d), refer to “Table 4 Number of Execution Cycles for Effective Address in Addressing Modes”
and “Table 6 Correction Values for Number of Cycles for Calculating Actual Number of Cycles.”
142
MB90370 Series
Table 14
Mnemonic
#
~
Logical 1 Instructions (Byte/Word) [39 Instructions]
RG
B
Operation
LH
AH
I
S
T
N
Z
V
C
RMW
AND
AND
AND
AND
AND
A, #imm8
A, ear
A, eam
ear, A
eam, A
2
2
2
3
2+ 4+ (a)
2
3
2+ 5+ (a)
0
1
0
2
0
0
0
(b)
0
2 (b)
byte (A)
(A) and imm8
(A) and (ear)
byte (A)
byte (A)
(A) and (eam)
(ear) and (A)
byte (ear)
(eam) and (A)
byte (eam)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
R
R
R
R
R
–
–
–
–
–
–
–
–
–
*
OR
OR
OR
OR
OR
A, #imm8
A, ear
A, eam
ear, A
eam, A
2
2
2
3
2+ 4+ (a)
2
3
2+ 5+ (a)
0
1
0
2
0
0
0
(b)
0
2 (b)
byte (A)
(A) or imm8
byte (A)
(A) or (ear)
byte (A)
(A) or (eam)
byte (ear)
(ear) or (A)
(eam) or (A)
byte (eam)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
R
R
R
R
R
–
–
–
–
–
–
–
–
–
*
XOR
XOR
XOR
XOR
XOR
A, #imm8
A, ear
A, eam
ear, A
eam, A
2
2
2
3
2+ 4+ (a)
2
3
2+ 5+ (a)
0
1
0
2
0
0
0
(b)
0
2 (b)
byte (A)
(A) xor imm8
byte (A)
(A) xor (ear)
byte (A)
(A) xor (eam)
(ear) xor (A)
byte (ear)
byte (eam)
(eam) xor (A)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
R
R
R
R
R
–
–
–
–
–
–
–
–
–
*
NOT
NOT
NOT
A
ear
eam
1
2
2
3
2+ 5+ (a)
0
2
0
0
byte (A)
not (A)
0
byte (ear)
not (ear)
2 (b) byte (eam)
not (eam)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
R –
R –
R –
–
–
*
ANDW
ANDW
ANDW
ANDW
ANDW
ANDW
2
1
A
2
A, #imm16 3
3
2
A, ear
2+ 4+ (a)
A, eam
3
2
ear, A
2+ 5+ (a)
eam, A
0
0
1
0
2
0
0
0
0
(c)
0
2 (c)
word (A)
word (A)
word (A)
word (A)
word (ear)
word (eam)
(AH) and (A)
(A) and imm16
(A) and (ear)
(A) and (eam)
(ear) and (A)
(eam) and (A)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
R
R
R
R
R
R
–
–
–
–
–
–
–
–
–
–
–
*
ORW
ORW
ORW
ORW
ORW
ORW
2
1
A
2
A, #imm16 3
3
2
A, ear
2+ 4+ (a)
A, eam
3
2
ear, A
2+ 5+ (a)
eam, A
0
0
1
0
2
0
0
0
0
(c)
0
2 (c)
word (A)
(AH) or (A)
word (A)
(A) or imm16
word (A)
(A) or (ear)
word (A)
(A) or (eam)
word (ear)
(ear) or (A)
word (eam)
(eam) or (A)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
R
R
R
R
R
R
–
–
–
–
–
–
–
–
–
–
–
*
XORW
XORW
XORW
XORW
XORW
XORW
2
1
A
2
A, #imm16 3
3
2
A, ear
2+ 4+ (a)
A, eam
3
2
ear, A
eam, A
2+ 5+ (a)
0
0
1
0
2
0
0
0
0
(c)
0
2 (c)
word (A)
word (A)
word (A)
word (A)
word (ear)
word (eam)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
R
R
R
R
R
R
–
–
–
–
–
–
–
–
–
–
–
*
1
2
3
2
2+ 5+ (a)
0
2
0
0
word (A)
not (A)
not (ear)
0
word (ear)
2 (c) word (eam)
not (eam)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
R –
R –
R –
–
–
*
NOTW A
NOTW ear
NOTW eam
(AH) xor (A)
(A) xor imm16
(A) xor (ear)
(A) xor (eam)
(ear) xor (A)
(eam) xor (A)
Note : For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,”
and Table 6, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”
143
MB90370 Series
Table 15
Mnemonic
Logical 2 Instructions (Long Word) [6 Instructions]
#
~
RG
B
Operation
ANDL A, ear
ANDL A, eam
2
2+
6
7+ (a)
2
0
0
(d)
long (A)
long (A)
ORL
ORL
A, ear
A, eam
2
2+
6
7+ (a)
2
0
0
(d)
XORL A, ea
XORL A, eam
2
2+
6
7+ (a)
2
0
0
(d)
LH
AH
I
S
T
N
Z
V
C
RMW
(A) and (ear)
(A) and (eam)
–
–
–
–
–
–
–
–
–
–
*
*
*
*
R
R
–
–
–
–
long (A)
long (A)
(A) or (ear)
(A) or (eam)
–
–
–
–
–
–
–
–
–
–
*
*
*
*
R
R
–
–
–
–
long (A)
long (A)
(A) xor (ear)
(A) xor (eam)
–
–
–
–
–
–
–
–
–
–
*
*
*
*
R
R
–
–
–
–
Note : For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,”
and Table 6, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”
Table 16
Mnemonic
Sign Inversion Instructions (Byte/Word) [6 Instructions]
#
~
RG
B
2
0
0
NEG
A
1
NEG
NEG
ear
eam
2
3
2+ 5+ (a)
2
0
NEGW A
1
0
NEGW ear
NEGW eam
2
3
2+ 5+ (a)
2
2
0
Operation
LH
AH
I
S
T
N
Z
V
C
RMW
0 – (A)
X
–
–
–
–
*
*
*
*
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
–
*
–
–
–
–
–
*
*
*
*
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
–
*
byte (A)
0 – (ear)
0 – (eam)
byte (ear)
0
2 (b) byte (eam)
0
word (A)
0 – (A)
word (ear)
0
2 (c) word (eam)
0 – (ear)
0 – (eam)
Note : For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,”
and Table 6, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”
Table 17
Mnemonic
#
~
RG
B
NRML A, R0
2
*1
1
0
Normalize Instruction (Long Word) [1 Instruction]
Operation
LH
long (A)
Shift until first digit is “1” –
byte (R0)
Current shift count
AH
I
S
T
N
Z
V
C
RMW
–
–
–
–
–
*
–
–
–
*1: 4 when the contents of the accumulator are all zeroes, 6 + (R0) in all other cases (shift count).
Note : For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,”
and Table 6, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”
144
MB90370 Series
Table 18
Mnemonic
RORC A
ROLC A
RORC ear
RORC eam
ROLC ear
ROLC eam
ASR
LSR
LSL
A, R0
A, R0
A, R0
#
2
2
~
2
2
2
3
2+ 5+ (a)
2
3
2+ 5+ (a)
Shift Instructions (Byte/Word/Long Word) [18 Instructions]
RG
0
0
B
0
0
2
0
0 2 (b)
0
2
0 2 (b)
Operation
byte (ear)
byte (eam)
byte (ear)
byte (eam)
2
2
2
*1
*1
*1
1
1
1
0
0
0
byte (A)
byte (A)
byte (A)
ASRW A
1
LSRW A/SHRW A 1
LSLW A/SHLW A 1
2
2
2
0
0
0
0
0
0
word (A)
ASRW A, R0
LSRW A, R0
LSLW A, R0
2
2
2
*1
*1
*1
1
1
1
0
0
0
word (A)
R0)
word (A)
word (A)
ASRL A, R0
LSRL A, R0
LSLL A, R0
2
2
2
*2
*2
*2
1
1
1
0
0
0
long (A)
word (A)
word (A)
long (A)
long (A)
LH AH
I
T
N
Z
V
C
RMW
–
–
–
–
– – –
– – –
*
*
*
*
–
–
*
*
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
–
–
–
–
*
*
*
*
–
*
–
*
–
–
–
–
–
–
– – *
– – *
– – –
*
*
*
*
*
*
–
–
–
*
*
*
–
–
–
–
–
–
–
–
–
– – * * *
– – * R *
– – – * *
–
–
–
*
*
*
–
–
–
–
–
–
–
–
–
– – *
– – *
– – –
*
*
*
*
*
*
–
–
–
*
*
*
–
–
–
Arithmetic right shift (A, R0) –
–
–
–
– – *
– – *
– – –
*
*
*
*
*
*
–
–
–
*
*
*
–
–
–
Right rotation with carry
Left rotation with carry
byte (A)
byte (A)
Right rotation with carry
Right rotation with carry
Left rotation with carry
Left rotation with carry
Arithmetic right barrel shift (A, R0)
Logical right barrel shift (A, R0)
Logical left barrel shift (A, R0)
Arithmetic right shift (A, 1 bit)
Logical right shift (A, 1 bit)
Logical left shift (A, 1 bit)
Arithmetic right barrel shift (A,
Logical right barrel shift (A, R0)
Logical left barrel shift (A, R0)
Logical right barrel shift (A, R0)
Logical left barrel shift (A, R0)
–
–
S
–
–
–
–
*1: 6 when R0 is 0, 5 + (R0) in all other cases.
*2: 6 when R0 is 0, 6 + (R0) in all other cases.
Note : For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,”
and Table 6, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”
145
MB90370 Series
Table 19
Mnemonic
BZ/BEQ
BNZ/BNE
BC/BLO
BNC/BHS
BN
rel
BP
rel
BV
rel
BNV
rel
BT
rel
BNT
rel
BLT
rel
BGE
rel
BLE
rel
BGT
rel
BLS
rel
BHI
rel
BRA
rel
rel
rel
rel
rel
#
~
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
1
Branch 1 Instructions [31 Instructions]
RG
B
Operation
*
*1
*1
*1
*1
*1
*1
*1
*1
*1
*1
*1
*1
*1
*1
*1
*1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Branch when (Z) = 1
Branch when (Z) = 0
Branch when (C) = 1
Branch when (C) = 0
Branch when (N) = 1
Branch when (N) = 0
Branch when (V) = 1
Branch when (V) = 0
Branch when (T) = 1
Branch when (T) = 0
Branch when (V) xor (N) = 1
Branch when (V) xor (N) = 0
JMP
JMP
JMP
JMP
JMPP
JMPP
JMPP
@A
addr16
@ear
@eam
@ear *3
@eam *3
addr24
1
3
2
2+
2
2+
4
2
3
3
4+ (a)
5
6+ (a)
4
0
0
1
0
2
0
0
0
0
0
(c)
0
(d)
0
CALL
CALL
CALL
CALLV
CALLP
2
@ear *4
@eam *4 2+
addr16 *5 3
1
#vct4 *5
2
@ear *6
6
7+ (a)
6
7
10
1
0
0
0
2
(c)
2 (c)
(c)
2 (c)
2 (c)
CALLP @eam *6
2+ 11+ (a)
0
*2
CALLP addr24 *7
4
0
2 (c)
*1:
*2:
*3:
*4:
*5:
*6:
*7:
10
LH AH
I
S
T
N
Z
V
C
RMW
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Branch when ((V) xor (N)) or (Z) = 1
Branch when ((V) xor (N)) or (Z) = 0
Branch when (C) or (Z) = 1
Branch when (C) or (Z) = 0
Branch unconditionally
word (PC)
word (PC)
word (PC)
word (PC)
word (PC)
word (PC)
(A)
addr16
(ear)
(eam)
(ear), (PCB)
(eam), (PCB)
(ear +2)
(eam +2)
word (PC)
ad24 0 to 15,
(PCB)
ad24 16 to 23
word (PC)
(ear)
word (PC)
(eam)
word (PC)
addr16
Vector call instruction
word (PC)
(ear) 0 to 15,
(PCB)
(ear) 16 to 23
(eam) 0 to 15,
word (PC)
(PCB)
(eam) 16 to 23
word (PC)
addr0 to 15,
addr16 to 23
(PCB)
4 when branching, 3 when not branching.
(b) + 3 (c)
Read (word) branch address.
W: Save (word) to stack; R: read (word) branch address.
Save (word) to stack.
W: Save (long word) to W stack; R: read (long word) R branch address.
Save (long word) to stack.
Note : For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,”
and Table 6, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”
146
MB90370 Series
Table 20
Mnemonic
#
~
CBNE A, #imm8, rel
CWBNE A, #imm16, rel
3
4
1
*
*1
CBNE
ear, #imm8, rel
4
CBNE
eam, #imm8, rel*10 4+
CWBNE ear, #imm16, rel
CWBNE eam, #imm16, rel*10
Branch 2 Instructions [19 Instructions]
B
Operation
0
0
0
0
Branch when byte (A) imm8
Branch when word (A) imm16
*2
*3
5 *4
5+ *3
1
0
1
0
0
(b)
0
(c)
Branch when byte (ear) imm8
Branch when byte (eam) imm8
Branch when word (ear) imm16
Branch when word (eam) imm16
2
DBNZ
ear, rel
3
DBNZ
eam, rel
3+ *6
*5
RG
Z
V
C
RMW
–
–
– – – – * *
– – – – * *
*
*
*
*
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
–
–
–
–
–
– – – – * *
* –
–
–
– – – – * *
* –
*
Branch when word (ear) =
(ear) – 1, and (ear) 0
2 (c) Branch when word (eam) =
(eam) – 1, and (eam) 0
–
– – – – * *
* –
–
–
– – – – * *
* –
*
8
6
6
8
Software interrupt
Software interrupt
Software interrupt
Software interrupt
Return from interrupt
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
–
–
–
–
*
–
–
–
–
–
At constant entry, save old
frame pointer to stack, set
new frame pointer, and
allocate local pointer area
At constant entry, retrieve old
frame pointer from stack.
–
– – – – – – – –
–
–
– – – – – – – –
–
Return from subroutine
Return from subroutine
–
–
– – – – – – – –
– – – – – – – –
–
–
Branch when byte (ear) =
(ear) – 1, and (ear) 0
2 2 (b) Branch when byte (eam) =
(eam) – 1, and (eam) 0
0
DWBNZ ear, rel
3
*5
2
DWBNZ eam, rel
3+ *6
2
INT
INT
INTP
INT9
RETI
#vct8
addr16
addr24
2
3
4
1
1
20
16
17
20
15
0
0
0
0
0
LINK
#local8
2
6
0
(c)
UNLINK
1
5
0
(c)
RET *8
RETP *9
1
1
4
6
0
0
(c)
(d)
0
(c)
(c)
(c)
(c)
*7
LH AH
I
–
–
–
–
R
R
R
R
*
S
–
–
–
–
S
S
S
S
*
T
–
–
–
–
–
–
–
–
*
N
*
*
*
*
–
–
–
–
*
*
*
*
*
–
–
–
–
*
*1: 5 when branching, 4 when not branching
*2: 13 when branching, 12 when not branching
*3: 7 + (a) when branching, 6 + (a) when not branching
*4: 8 when branching, 7 when not branching
*5: 7 when branching, 6 when not branching
*6: 8 + (a) when branching, 7 + (a) when not branching
*7: Set to 3 (b) + 2 (c) when an interrupt request occurs, and 6 (c) for return.
*8: Retrieve (word) from stack
*9: Retrieve (long word) from stack
*10: In the CBNE/CWBNE instruction, do not use the RWj+ addressing mode.
Note : For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,”
and Table 6, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”
147
MB90370 Series
Table 21
Mnemonic
#
Other Control Instructions (Byte/Word/Long Word) [28 Instructions]
~
RG
B
Operation
LH AH
I
S
T
N
Z
V
C
RMW
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
–
–
–
– – – – – – –
– – – – – – –
* * * * * * *
– – – – – – –
–
–
–
–
–
–
*
*
*
*
*
*
*
–
(CCR) and imm8 –
(CCR) or imm8 –
–
–
*
*
*
*
*
*
*
*
*
*
*
*
*
*
–
–
PUSHW A
PUSHW AH
PUSHW PS
PUSHW rlst
1
1
1
2
4
4
4
*3
0
0
0
*5
(c)
(c)
(c)
*4
word (SP)
(SP) –2, ((SP))
(A)
word (SP) (SP) –2, ((SP)) (AH)
word (SP) (SP) –2, ((SP)) (PS)
(SP) –2n, ((SP))
(rlst)
(SP)
POPW
POPW
POPW
POPW
A
AH
PS
rlst
1
1
1
2
3
3
4
*2
0
0
0
*5
(c)
(c)
(c)
*4
word (A)
((SP)), (SP)
SP) +2
SP) +2
word (AH) ((SP)), (SP)
word (PS) ((SP)), (SP)
SP) +2
((SP)), (SP)
(SP) +2n
(rlst)
JCTX
@A
1
14
0
AND CCR, #imm8
OR CCR, #imm8
2
2
3
3
0
0
0
0
byte (CCR)
byte (CCR)
MOV RP, #imm8
MOV ILM, #imm8
2
2
2
2
0
0
0
0
byte (RP) imm8
byte (ILM) imm8
–
–
–
–
– – – – – – –
– – – – – – –
–
–
MOVEA RWi, ear
2
3
MOVEA RWi, eam 2+ 2+ (a)
MOVEA A, ear
2
1
MOVEA A, eam
2+ 1+ (a)
1
1
0
0
0
0
0
0
word (RWi) ear
word (RWi) eam
word(A) ear
word (A) eam
–
–
–
–
–
–
*
*
–
–
–
–
–
–
–
–
–
–
–
–
ADDSP #imm8
ADDSP #imm16
2
3
3
3
0
0
0
0
word (SP)
word (SP)
–
–
–
–
– – – – – – –
– – – – – – –
–
–
MOV
MOV
2
2
*1
1
0
0
0
0
byte (A) (brgl)
byte (brg2) (A)
Z
–
*
–
– – –
– – –
*
*
*
*
– –
– –
–
–
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
No operation
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
NOP
ADB
DTB
PCB
SPB
NCC
CMR
A, brgl
brg2, A
6 (c) Context switch instruction
Prefix
Prefix
Prefix
Prefix
(SP) +ext (imm8)
(SP) +imm16
code for accessing AD space
code for accessing DT space
code for accessing PC space
code for accessing SP space
Prefix code for no flag change
Prefix code for common register bank
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*1: PCB, ADB, SSB, USB, and SPB : 1 state
DTB, DPR
: 2 states
*2: 7 + 3 (pop count) + 2 (last register number to be popped), 7 when rlst = 0 (no transfer register)
*3: 29 + (push count) – 3 (last register number to be pushed), 8 when rlst = 0 (no transfer register)
*4: Pop count (c), or push count (c)
*5: Pop count or push count.
Note : For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,”
and Table 6, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”
148
MB90370 Series
Table 22
Mnemonic
Bit Manipulation Instructions [21 Instructions]
#
~
RG
B
MOVB A, dir:bp
MOVB A, addr16:bp
MOVB A, io:bp
3
4
3
5
5
4
0
0
0
(b)
(b)
(b)
MOVB dir:bp, A
MOVB addr16:bp, A
MOVB io:bp, A
3
4
3
7
7
6
0
0
0
SETB dir:bp
SETB addr16:bp
SETB io:bp
3
4
3
7
7
7
CLRB dir:bp
CLRB addr16:bp
CLRB io:bp
3
4
3
BBC
BBC
BBC
dir:bp, rel
addr16:bp, rel
io:bp, rel
BBS
BBS
BBS
Operation
LH AH
I
S
T
N
Z
V
C
RMW
Z
Z
Z
*
*
*
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
–
–
–
–
–
–
–
–
–
(A)
2 (b) bit (dir:bp) b
2 (b) bit (addr16:bp) b
(A)
2 (b) bit (io:bp) b
(A)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
–
–
–
–
–
–
*
*
*
0
0
0
2 (b) bit (dir:bp) b
1
2 (b) bit (addr16:bp) b
1
2 (b) bit (io:bp) b
1
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
7
7
7
0
0
0
2 (b) bit (dir:bp) b
0
2 (b) bit (addr16:bp) b
2 (b) bit (io:bp) b
0
0
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
4
5
4
*1
*1
*2
0
0
0
(b)
(b)
(b)
Branch when (dir:bp) b = 0
Branch when (addr16:bp) b = 0
Branch when (io:bp) b = 0
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
–
–
–
–
–
–
–
–
–
dir:bp, rel
addr16:bp, rel
io:bp, rel
4
5
4
*1
*1
*2
0
0
0
(b)
(b)
(b)
Branch when (dir:bp) b = 1
Branch when (addr16:bp) b = 1
Branch when (io:bp) b = 1
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
–
–
–
–
–
–
–
–
–
SBBS addr16:bp, rel
5
*3
0
2 (b)
Branch when (addr16:bp) b = 1, bit = 1
–
–
–
–
–
–
*
–
–
*
WBTS io:bp
3
*4
0
*5
Wait until (io:bp) b = 1
–
–
–
–
–
–
–
–
–
–
WBTC io:bp
3
*4
0
*5
Wait until (io:bp) b = 0
–
–
–
–
–
–
–
–
–
–
*1:
*2:
*3:
*4:
*5:
byte (A)
byte (A)
byte (A)
(dir:bp) b
(addr16:bp) b
(io:bp) b
8 when branching, 7 when not branching
7 when branching, 6 when not branching
10 when condition is satisfied, 9 when not satisfied
Undefined count
Until condition is satisfied
Note : For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,”
and Table 6, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”
Table 23
Mnemonic
SWAP
SWAPW
EXT
EXTW
ZEXT
ZEXTW
Accumulator Manipulation Instructions (Byte/Word) [6 Instructions]
#
~
RG
B
Operation
1
1
1
1
1
1
3
2
1
2
1
1
0
0
0
0
0
0
0
0
0
0
0
0
(A) 8 to 15
byte (A) 0 to 7
(AL)
word (AH)
byte sign extension
word sign extension
byte zero extension
word zero extension
LH
AH
I
S
T
N
Z
V
C
RMW
–
–
X
–
Z
–
–
*
–
X
–
Z
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
R
R
–
–
*
*
*
*
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Note: For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,”
and Table 6, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”
149
MB90370 Series
Table 24
String Instructions [10 Instructions]
Mnemonic
#
~
RG
B
MOVS/MOVSI
MOVSD
2
2
2
*
*2
5
*
*5
3
*
*3
Byte transfer @AH+
Byte transfer @AH–
Operation
SCEQ/SCEQI
SCEQD
2
2
*1
*1
*5
*5
*4
*4
Byte retrieval (@AH+) – AL, counter = RW0
Byte retrieval (@AH–) – AL, counter = RW0
FISL/FILSI
2 6m +6 *5
*3
Byte filling @AH+
@AL+, counter = RW0
@AL–, counter = RW0
AL, counter = RW0
MOVSW/MOVSWI 2
MOVSWD
2
*2
*2
*8
*8
*6
*6
Word transfer @AH+
Word transfer @AH–
SCWEQ/SCWEQI
SCWEQD
2
2
*1
*1
*8
*8
*7
*7
Word retrieval (@AH+) – AL, counter = RW0
Word retrieval (@AH–) – AL, counter = RW0
FILSW/FILSWI
2 6m +6 *8
*6
Word filling @AH+
@AL+, counter = RW0
@AL–, counter = RW0
AL, counter = RW0
LH AH
I
S
T
N
Z
V
C
RMW
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
–
–
–
–
–
–
–
*
*
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
–
–
–
–
–
–
–
*
*
–
–
–
m: RW0 value (counter value)
n: Loop count
*1: 5 when RW0 is 0, 4 + 7 (RW0) for count out, and 7 n + 5 when match occurs
*2: 5 when RW0 is 0, 4 + 8 (RW0) in any other case
*3: (b) (RW0) + (b) (RW0) when accessing different areas for the source and destination, calculate (b) separately for each.
*4: (b) n
*5: 2 (RW0)
*6: (c) (RW0) + (c)
(RW0) when accessing different areas for the source and destination, calculate (c)
separately for each.
*7: (c) n
*8: 2 (RW0)
Note : For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,”
and Table 6, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”
150
MB90370 Series
ORDERING INFORMATION
Part number
MB90F372PMT-G
MB90372PMT-G-XXX
Package
144-pin Plastic LQFP
(FPT-144P-M12)
Remarks
XXX is the ROM release number.
151
MB90370 Series
PACKAGE DIMENSIONS
144-pin plastic LQFP
(FPT-144P-M12)
144-pin plastic LQFP
Lead pitch
0.40 mm
Package width x
package length
16.0 x 16.0 mm
Lead shape
Gullwing
Sealing method
Plastic mold
Mounting height
1.70 mm MAX
Weight
0.88g
(FPT-144P-M12)
18.00±0.20(.709±.008)SQ
16.00±0.10(.630±.004)SQ
108
73
Details of "A" part
109
72
+0.20
1.50 –0.10
+.008
(Mounting height)
.059 –.004
0.08(.003)
0~8°
INDEX
0.45/0.75
(.018/.030)
144
37
0.25(.010)
"A"
LEAD No.
1
36
0.40(.016)
C
0.10±0.05
(.004±.002)
(Stand off)
1998 FUJITSU LIMITED F144024S-2C-2
0.18±0.035
.007±.001
+0.05
0.07(.003)
M
0.145 –0.03
+.002
.006 –.001
Dimensions mm (inches)
Dimensions in mm (inches)
152
MB90370 Series
FUJITSU LIMITED
For further information please contact:
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The contents of this document are subject to change without
notice.
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representatives before ordering.
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F0208
FUJITSU LIMITED Printed in Japan
The information and circuit diagrams in this document are
presented as examples of semiconductor device
applications, and are not intended to be incorporated in
devices for actual use. Also, FUJITSU is unable to assume
responsibility for infringement of any patent rights or other
rights of third parties arising from the use of this information
or circuit diagrams.
The products described in this document are designed,
developed and manufactured as contemplated for general
use, including without limitation, ordinary industrial use,
general office use, personal use, and household use, but are
not designed, developed and manufactured as contemplated
(1) for use accompanying fatal risks or dangers that, unless
extremely high safety is secured, could have a serious effect
to the public, and could lead directly to death, personal injury,
severe physical damage or other loss (i.e., nuclear reaction
control in nuclear facility, aircraft flight control, air traffic
control, mass transport control, medical life support system,
missile launch control in weapon system), or (2) for use
requiring extremely high reliability (i.e., submersible repeater
and artificial satellite).
Please note that Fujitsu will not be liable against you and/or
any third party for any claims or damages arising in
connection with above-mentioned uses of the products.
Any semiconductor devices have an inherent chance of
failure. You must protect against injury, damage or loss from
such failures by incorporating safety design measures into
your facility and equipment such as redundancy, fire
protection, and prevention of over-current levels and other
abnormal operating conditions.
If any products described in this document represent goods
or technologies subject to certain restrictions on export under
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