FUJITSU SEMICONDUCTOR
DATA SHEET
DS07-12608-2E
8-bit Proprietary Microcontrollers
CMOS
F2MC-8FX MB95140 Series
MB95F146S/F146W/FV100D-101
■ DESCRIPTION
The MB95140 series is general-purpose, single-chip microcontrollers. In addition to a compact instruction set,
the microcontrollers contain a variety of peripheral functions.
Note : F2MC is the abbreviation of FUJITSU Flexible Microcontroller.
■ FEATURE
• F2MC-8FX CPU core
Instruction set optimized for controllers
• Multiplication and division instructions
• 16-bit arithmetic operations
• Bit test branch instruction
• Bit manipulation instructions etc.
• Clock
• Main clock
• Main PLL clock
• Sub clock (for dual clock product)
• Sub PLL clock (for dual clock product)
(Continued)
Be sure to refer to the “Check Sheet” for the latest cautions on development.
“Check Sheet” is seen at the following support page
URL : http://www.fujitsu.com/global/services/microelectronics/product/micom/support/index.html
“Check Sheet” lists the minimal requirement items to be checked to prevent problems beforehand in system
development.
Copyright©2006-2007 FUJITSU LIMITED All rights reserved
MB95140 Series
(Continued)
• Timer
• 8/16-bit compound timer × 2 channels
• 8/16-bit PPG × 2 channels
• 16-bit PPG
• Timebase timer
• Watch prescaler (for dual clock product)
• LIN-UART
• Full duplex double buffer
• Clock asynchronous (UART) or clock synchronous (SIO) serial data transfer capable
• UART/SIO
• Full duplex double buffer
• Clock asynchronous (UART) or clock synchronous (SIO) serial data transfer capable
• External interrupt
• Interrupt by edge detection (rising, falling, or both edges can be selected)
• Can be used to recover from low-power consumption (standby) modes.
• 8/10-bit A/D converter
8-bit or 10-bit resolution can be selected.
• Low-power consumption (standby) mode
• Stop mode
• Sleep mode
• Watch mode (for dual clock product)
• Timebase timer mode
• I/O port
• The number of maximum ports
• Single clock product : 24 ports
• Dual clock product : 22 ports
• Port configuration
• General-purpose I/O ports (CMOS) : Single-clock product : 24 ports
: Dual-clock product : 22 ports
• Flash memory security function
Protects the content of Flash memory (Flash memory device only)
2
MB95140 Series
■ PRODUCT LINEUP
Part number*1
MB95F146S
MB95F146W
Parameter
Flash memory
product
Type
32K bytes
RAM capacity
1K byte
Reset output
No
Option
ROM capacity
Clock system
Dual clock
Low voltage
detection reset
CPU functions
General purpose
I/O ports
Peripheral functions
Single clock
No
Number of basic instructions
Instruction bit length
Instruction length
Data bit length
Minimum instruction execution time
Interrupt processing time
: 136
: 8 bits
: 1 to 3 bytes
: 1, 8, and 16 bits
: 61.5 ns (at machine clock frequency 16.25 MHz)
: 0.6 µs (at machine clock frequency 16.25 MHz)
Single clock product : 24 ports
Dual clock product : 22 ports
Timebase timer
Interrupt cycle : 0.5 ms, 2.1 ms, 8.2 ms, 32.8 ms (at 4 MHz main oscillation clock)
Watchdog timer
Reset generated cycle
At 10 MHz main oscillation clock : Min 105 ms
At 32.768 kHz sub oscillation clock (for dual clock product) : Min 250 ms
Wild register
Capable of replacing 3 bytes of ROM data
UART/SIO
Data transfer capable in UART/SIO
Full duplex double buffer, variable data length (5/6/7/8 bits), built-in baud rate generator
NRZ type transfer format, error detected function
LSB-first or MSB-first can be selected.
Clock asynchronous (UART) or clock synchronous (SIO) serial data transfer capable
LIN-UART
Dedicated reload timer allowing a wide range of communication speeds to be set.
Full duplex double buffer.
Clock asynchronous (UART) or clock synchronous (SIO) serial data transfer capable
LIN functions available as the LIN master or LIN slave.
8/10-bit A/D
converter
(8 channels)
8-bit or 10-bit resolution can be selected.
(Continued)
3
MB95140 Series
(Continued)
Part number*1
MB95F146S
MB95F146W
Parameter
Peripheral functions
Each channel of the timer can be used as “8-bit timer × 2 channels” or “16-bit timer × 1
channel”.
8/16-bit compound
Built-in timer function, PWC function, PWM function, capture function and square wave
timer (2 channels)
form output
Count clock : 7 internal clocks and external clock can be selected.
16-bit PPG
PWM mode or one-shot mode can be selected.
Counter operating clock : 8 selectable clock sources
Support for external trigger start
8/16-bit PPG
(2 channels)
Each channel of the PPG can be used as “8-bit PPG × 2 channels” or “16-bit PPG × 1
channel”.
Counter operating clock : 8 selectable clock sources
Watch counter
(for dual clock
product)
Count clock : 4 selectable clock sources (125 ms, 250 ms, 500 ms, or 1 s)
Counter value can be set from 0 to 63. (Capable of counting for 1 minute when selecting
clock source 1 second and setting counter value to 60)
Watch prescaler
(for dual clock
product)
4 selectable interval times (125 ms, 250 ms, 500 ms, or 1 s)
External interrupt
(12 channels)
Interrupt by edge detection (rising, falling, or both edges can be selected.)
Can be used to recover from standby modes.
Flash memory
Supports automatic programming, Embedded AlgorithmTM *2
Write/Erase/Erase-Suspend/Resume commands
A flag indicating completion of the algorithm
Number of write/erase cycles (Minimum) : 10000 times
Data retention time : 20 years
Boot block configuration
Erase can be performed on each block
Block protection with external programming voltage
Flash Security Feature for protecting the content of the Flash
Standby mode
Sleep, stop, watch (for dual clock product), and timebase timer
*1 : MASK ROM products are currently under consideration.
*2 : Embedded Algorithm is a trade mark of Advanced Micro Devices Inc.
Note : Part number of the evaluation device in MB95140 series is MB95FV100D-101. When using it, the MCU
board (MB2146-301A) is required.
4
MB95140 Series
■ OSCILLATION STABILIZATION WAIT TIME
The initial value of the main clock oscillation stabilization wait time is fixed to the maximum value.
The maximum value is shown as follows.
Oscillation stabilization wait time
(2 − 2) /FCH
14
Remarks
Approx. 4.10 ms (at 4 MHz main oscillation clock)
■ PACKAGES AND CORRESPONDING PRODUCTS
Part number
Package
MB95F146S
MB95F146W
MB95FV100D-101
FPT-32P-M21
BGA-224P-M08
: Available
: Unavailable
5
MB95140 Series
■ DIFFERENCES AMONG PRODUCTS AND NOTES ON SELECTING PRODUCTS
• Notes on Using Evaluation Products
The Evaluation product has not only the functions of the MB95140 series but also those of other products to
support software development for multiple series and models of the F2MC-8FX family. The I/O addresses for
peripheral resources not used by the MB95140 series are therefore access-barred. Read/write access to these
access-barred addresses may cause peripheral resources supposed to be unused to operate, resulting in
unexpected malfunctions of hardware or software.
Particularly, do not use word access to odd numbered byte address in the prohibited areas (If these access are
used, the address may be read or written unexpectedly).
Note that the values read from barred addresses are different between the Evaluation product and the Flash
memory product. Therefore, the value must not be used for program.
The Evaluation product does not support the functions of some bits in single-byte registers. Read/write access
to these bits does not cause hardware malfunctions. The Evaluation, and Flash memory products are designed
to behave completely the same way in terms of hardware and software.
• Difference of Memory Spaces
If the amount of memory on the Evaluation product is different from that of the Flash memory product, carefully
check the difference in the amount of memory from the model to be actually used when developing software.
For details of memory space, refer to “■ CPU CORE”.
• Current Consumption
For details of current consumption, refer to “■ ELECTRICAL CHARACTERISTICS”.
• Package
For details of information on each package, refer to “■ PACKAGES AND CORRESPONDING PRODUCTS” and
“■ PACKAGE DIMENSIONS”.
• Operating voltage
The operating voltage is different among the Evaluation and Flash memory products.
For details of operating voltage, refer to “■ ELECTRICAL CHARACTERISTICS”
• Difference between RST and MOD pins
The input type of RST and MOD pins is CMOS input on the Flash memory product.
6
MB95140 Series
■ PIN ASSIGNMENT
P61/PPG11
P60/PPG10
P14/PPG0
P13/TRG0/ADTG
P12/UCK0/EC0
P11/UO0
P10/UI0
P07/INT07/AN07
(TOP VIEW)
32 31 30 29 28 27 26 25
P06/INT06/AN06/TO01
1
24
P62/TO10
P05/INT05/AN05/TO00
2
23
P63/TO11
P04/INT04/AN04/SIN
3
22
P64/EC1
P03/INT03/AN03/SOT
4
21
RST
P02/INT02/AN02/SCK
5
20
PG1/X0A*
P01/INT01/AN01/PPG01
6
19
PG2/X1A*
P00/INT00/AN00/PPG00
7
18
PG0
AVss
8
17
Vcc
Vss
X1
X0
PF0
MOD
PF1
PF2
AVcc
9 10 11 12 13 14 15 16
(FPT-32P-M21)
* : The pins are general-purpose port in single clock product and sub clock oscillation pin in dual clock product.
7
MB95140 Series
■ PIN DESCRIPTION
I/O
circuit
type*
Function
D
General-purpose I/O port.
Shared with external interrupt input (INT05, INT06), A/D analog
input (AN05, AN06) and 8/16-bit compound timer ch.0 output (TO00,
TO01).
P04/INT04/
AN04/SIN
E
General-purpose I/O port.
Shared with external interrupt input (INT04), A/D converter analog
input (AN04) and LIN-UART data input (SIN).
4
P03/INT03/
AN03/SOT
D
General-purpose I/O port.
Shared with external interrupt input (INT03), A/D converter analog
input (AN03) and LIN-UART data output (SOT).
5
P02/INT02/
AN02/SCK
D
General-purpose I/O port.
Shared with external interrupt input (INT02), A/D converter analog
input (AN02) and LIN-UART clock I/O (SCK).
6
P01/INT01/
AN01/PPG01
D
7
P00/INT00/
AN00/PPG00
General-purpose I/O port.
Shared with external interrupt input (INT00, INT01), A/D converter
analog input (AN00, AN01) and 8/16-bit PPG ch.0 output (PPG00,
PPG01).
8
AVss
⎯
A/D converter power supply pin (GND)
9
AVcc
⎯
A/D converter power supply pin
10
PF2
11
PF1
K
General-purpose I/O port.
Large current port.
12
PF0
13
MOD
B
Operating mode designation pin
14
X0
15
X1
16
Vss
⎯
Power supply pin (GND)
17
Vcc
⎯
Power supply pin
18
PG0
H
General-purpose I/O port
19
PG2/X1A
20
PG1/X0A
21
RST
Pin no.
Pin name
1
P06/INT06/
AN06/TO01
2
P05/INT05/
AN05/TO00
3
A
H/A
B’
Main clock input oscillation pin
Main clock I/O oscillation pin
This pin is general-purpose port in single clock product (PG2) .
This pin is sub clock oscillation pin in dual clock product (32 kHz) .
This pin is general-purpose port in single clock product (PG1) .
This pin is sub clock oscillation pin in dual clock product (32 kHz) .
Reset pin
(Continued)
8
MB95140 Series
(Continued)
I/O
circuit
type*
Pin no.
Pin name
22
P64/EC1
23
P63/TO11
24
P62/TO10
25
P61/PPG11
26
P60/PPG10
K
General-purpose I/O port.
Shared with 8/16-bit PPG ch.1 output.
27
P14/PPG0
H
General-purpose I/O port.
Shared with 16-bit PPG ch.0 output.
28
P13/TRG0/
ADTG
H
General-purpose I/O port.
Shared with 16-bit PPG ch.0 trigger input (TRG0) and A/D trigger
input (ADTG).
29
P12/UCK0/EC0
H
General-purpose I/O port.
Shared with UART/SIO ch.0 clock I/O (UCK0) and 8/16-bit compound
timer ch.0 clock input (EC0).
30
P11/UO0
H
General-purpose I/O port.
Shared with UART/SIO ch.0 data output.
31
P10/UI0
G
General-purpose I/O port.
Shared with UART/SIO ch.0 data input.
32
P07/INT07/
AN07
D
General-purpose I/O port.
Shared with external interrupt input (INT07) and A/D converter analog
input (AN07).
Function
General-purpose I/O port.
Shared with 8/16-bit compound timer ch.1 clock input.
K
General-purpose I/O port.
Shared with 8/16-bit compound timer ch.1 output.
General-purpose I/O port.
Shared with 8/16-bit PPG ch.1 output.
* : For the I/O circuit type, refer to “■ I/O CIRCUIT TYPE”.
9
MB95140 Series
■ I/O CIRCUIT TYPE
Type
Circuit
Remarks
X1 (X1A)
A
Clock
input
N-ch
X0 (X0A)
Standby control
B
Mode input
B’
Reset input
• Oscillation circuit
• High-speed side
Feedback resistance : approx. 1 MΩ
• Low-speed side
Feedback resistance : approx. 24 MΩ
(Evaluation product : approx. 10 MΩ)
Dumping resistance : approx. 144 kΩ
(Evaluation product : without dumping
resistance)
• Only for input
• Hysteresis input
Hysteresis input
R
P-ch
Pull-up control
P-ch
N-ch
D
Digital output
•
•
•
•
CMOS output
Hysteresis input
Analog input
With pull - up control
•
•
•
•
•
CMOS output
CMOS input
Hysteresis input
Analog input
With pull - up control
Digital output
Analog input
Hysteresis
input
A/D control
Standby control
External control
Pull-up control
R
P-ch
P-ch
Digital output
Digital output
N-ch
E
Analog input
CMOS input
A/D control
Standby control
External control
Hysteresis
input
(Continued)
10
MB95140 Series
(Continued)
Type
Circuit
R
P-ch
Remarks
Pull-up control
P-ch
G
N-ch
Digital output
Digital output
Pull-up control
R
P-ch
P-ch
H
N-ch
• CMOS output
• Hysteresis input
• With pull - up control
Digital output
Digital output
Hysteresis
input
Standby control
P-ch
N-ch
Standby control
CMOS output
CMOS input
Hysteresis input
With pull - up control
CMOS input
Hysteresis
input
Standby control
K
•
•
•
•
• CMOS output
Digital output • Hysteresis input
Digital output
Hysteresis
input
11
MB95140 Series
■ HANDLING DEVICES
• Preventing Latch-up
Care must be taken to ensure that maximum voltage ratings are not exceeded when they are used.
Latch-up may occur on CMOS ICs if voltage higher than VCC or lower than VSS is applied to input and output pins
other than medium- and high-withstand voltage pins or if higher than the rating voltage is applied between VCC
pin and VSS pin.
When latch-up occurs, power supply current increases rapidly and might thermally damage elements.
Also, take care to prevent the analog power supply voltage (AVCC) and analog input voltage from exceeding the
digital power supply voltage (VCC) when the analog system power supply is turned on or off.
• Stable Supply Voltage
Supply voltage should be stabilized.
A sudden change in power-supply voltage may cause a malfunction even within the guaranteed operating range
of the VCC power-supply voltage.
For stabilization, in principle, keep the variation in VCC ripple (p-p value) in a commercial frequency range
(50/60 Hz) not to exceed 10% of the standard VCC value and suppress the voltage variation so that the transient
variation rate does not exceed 0.1 V/ms during a momentary change such as when the power supply is switched.
• Precautions for Use of External Clock
Even when an external clock is used, oscillation stabilization wait time is required for power-on reset, wake-up
from sub clock mode or stop mode.
■ PIN CONNECTION
• Treatment of Unused Pin
Leaving unused input pins unconnected can cause abnormal operation or latch-up, leaving to permanent damage.
Unused input pins should always be pulled up or down through resistance of at least 2 kΩ. Any unused input/
output pins may be set to output mode and left open, or set to input mode and treated the same as unused input
pins. If there is unused output pin, make it to open.
• Treatment of Power Supply Pins on A/D Converter
Connect to be AVCC = VCC and AVSS = VSS even if the A/D converter is not in use.
Noise riding on the AVCC pin may cause accuracy degradation. So, connect approx. 0.1 µF ceramic capacitor
as a bypass capacitor between AVCC and AVSS pins in the vicinity of this device.
• Power Supply Pins
In products with multiple VCC or VSS pins, the pins of the same potential are internally connected in the device
to avoid abnormal operations including latch-up. However, you must connect the pins to external power supply
and a ground line to lower the electro-magnetic emission level, to prevent abnormal operation of strobe signals
caused by the rise in the ground level, and to conform to the total output current rating.
Moreover, connect the current supply source with the VCC and VSS pins of this device at the low impedance.
It is also advisable to connect a ceramic bypass capacitor of approximately 0.1 µF between VCC and VSS pins
near this device.
12
MB95140 Series
• Mode Pin (MOD)
Connect the MOD pin directly to VCC or VSS pins.
To prevent the device unintentionally entering test mode due to noise, lay out the printed circuit board so as to
minimize the distance from the MOD pin to VCC or VSS pins and to provide a low-impedance connection.
• Analog Power Supply
Always set the same potential to AVCC and VCC pins. When VCC > AVCC, the current may flow through the AN00
to AN07 pins.
13
MB95140 Series
■ PROGRAMMING FLASH MEMORY MICROCONTROLLERS USING PARALLEL
PROGRAMMER
• Supported Parallel Programmers and Adapters
The following table lists supported parallel programmers and adapters.
Package
Applicable adapter model
FPT-32P-M21
TEF110-95F146
Parallel programmers
AF9708 (Ver 02.35G or more)
AF9709/B (Ver 02.35G or more)
Note : For information on applicable adapter models and parallel programmers, contact the following:
Flash Support Group, Inc. TEL: +81-53-428-8380
• Sector Configuration
The individual sectors of Flash memory correspond to addresses used for CPU access and programming by
the parallel programmer as follows:
Flash memory
CPU address
8000H
Programmer address*
18000H
FFFFH
1FFFFH
32 Kbytes
*: Programmer addresses are corresponding to CPU addresses, used when the parallel programmer
programs data into Flash memory.
These programmer addresses are used for the parallel programmer to program or erase data in Flash memory.
• Programming Method
1) Set the type code of the parallel programmer to “1723E”.
2) Load program data to programmer addresses 18000H to 1FFFFH.
3) Programmed by parallel programmer
14
MB95140 Series
■ BLOCK DIAGRAM
2
F MC-8FX CPU
RST
X0, X1
PG2/(X1A)*
PG1/(X0A)*
PG0
Reset control
ROM
RAM
Clock control
Interrupt control
Watch prescaler
Wild register
Watch counter
P00/INT00 to P07/INT07
External interrupt
8/16-bit PPG ch.1
P10/UI0
P11/UO0
UART/SIO
(P00/PPG00)
(P01/PPG01)
8/16-bit PPG ch.0
Internal bus
P14/PPG0
16-bit PPG
P61/PPG11
P62/TO10
8/16-bit compound
timer ch.1
P12/UCK0
P13/TRG0/ADTG
P60/PPG10
P63/TO11
P64/EC1
PF0 to PF2
PG0
(P02/SCK)
(P03/SOT)
LIN-UART
(P04/SIN)
(P05/TO00)
(P06/TO01)
(P12/EC0)
(P00/AN00 to P07/AN07)
AVCC
8/16-bit compound
timer ch.0
8/10-bit
A/D converter
AVSS
Port
Port
Other pins
MOD, VCC, VSS
* : The pins are general-purpose port in single clock product and sub clock oscillation pin in dual clock product.
15
MB95140 Series
■ CPU CORE
1. Memory space
Memory space of the MB95140 series is 64K bytes and consists of I/O area, data area, and program area. The
memory space includes special-purpose areas such as the general-purpose 7 registers and vector table. Memory
map of the MB95140 series is shown below.
• Memory Map
MB95F146S
MB95F146W
0000H
I/O
0080H
0100H
RAM 1 Kbyte
Register
0200H
MB95FV100D-101
0000H
I/O
0080H
0100H
RAM 3.75 Kbytes
Register
0200H
0480H
Access
prohibited
0F80H
0F80H
Extended I/O
1000H
Extended I/O
1000H
Access
prohibited
8000H
Flash memory
60 Kbytes
Flash memory
32 Kbytes
FFFFH
16
FFFFH
MB95140 Series
2. Register
The MB95140 series has two types of registers; dedicated registers in the CPU and general-purpose registers
in the memory. The dedicated registers are as follows:
Program counter (PC)
: A 16-bit register to indicate locations where instructions are stored.
Accumulator (A)
: A 16-bit register for temporary storage of arithmetic operations. In the case of
an 8-bit data processing instruction, the lower 1 byte is used.
Temporary accumulator (T) : A 16-bit register which performs arithmetic operations with the accumulator.
In the case of an 8-bit data processing instruction, the lower 1 byte is used.
Index register (IX)
: A 16-bit register for index modification
Extra pointer (EP)
: A 16-bit pointer to point to a memory address.
Stack pointer (SP)
: A 16-bit register to indicate a stack area.
Program status (PS)
: A 16-bit register for storing a register bank pointer, a direct bank pointer, and
a condition code register
Initial Value
16-bit
: Program counter
FFFDH
A
: Accumulator
0000H
T
: Temporary accumulator
0000H
IX
: Index register
0000H
EP
: Extra pointer
0000H
SP
: Stack pointer
0000H
PS
: Program status
0030H
PC
The PS can further be divided into higher 8 bits for use as a register bank pointer (RP) and a direct bank pointer
(DP) and the lower 8 bits for use as a condition code register (CCR) . (Refer to the diagram below.)
• Structure of the Program Status
bit15 bit14 bit13 bit12 bit11 bit10
PS
R4
R3
R2
RP
R1
R0
DP2
bit9
bit8
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
DP1
DP0
H
I
IL1
IL0
N
Z
V
C
DP
CCR
17
MB95140 Series
The RP indicates the address of the register bank currently being used. The relationship between the content
of RP and the real address conforms to the conversion rule illustrated below:
• Rule for Conversion of Actual Addresses in the General-purpose Register Area
RP upper
"0"
"0"
"0"
"0"
"0"
"0"
OP code lower
"0"
"1"
R4
R3
R2
R1
R0
b2
b1
b0
Generated address A15 A14 A13 A12 A11 A10 A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
The DP specifies the area for mapping instructions (16 different instructions such as MOV A, dir) using direct
addresses to 0080H to 00FFH.
Direct bank pointer (DP2 to DP0)
Specified address area
Mapping area
XXXB (no effect to mapping)
0000H to 007FH
0000H to 007FH (without mapping)
000B (initial value)
0080H to 00FFH (without mapping)
001B
0100H to 017FH
010B
0180H to 01FFH
011B
0080H to 00FFH
100B
0200H to 027FH
0280H to 02FFH
101B
0300H to 037FH
110B
0380H to 03FFH
111B
0400H to 047FH
The CCR consists of the bits indicating arithmetic operation results or transfer data contents and the bits that
control CPU operations at interrupt.
H flag
: Set to “1” when a carry or a borrow from bit 3 to bit 4 occurs as a result of an arithmetic operation.
Cleared to “0” otherwise. This flag is for decimal adjustment instructions.
I flag
: Interrupt is enabled when this flag is set to “1”. Interrupt is disabled when this flag is set to “0”.
The flag is cleared to “0” when reset.
IL1, IL0 : Indicates the level of the interrupt currently enabled. Processes an interrupt only if its request level
is higher than the value indicated by these bits.
IL1
IL0
Interrupt level
Priority
0
0
0
High
0
1
1
1
0
2
1
1
3
Low = no interruption
N flag
: Set to “1” if the MSB is set to “1” as the result of an arithmetic operation. Cleared to “0” when the
Z flag
V flag
: Set to “1” when an arithmetic operation results in “0”. Cleared to “0” otherwise.
bit is set to “0”.
C flag
18
: Set to “1” if the complement on 2 overflows as a result of an arithmetic operation. Cleared to “0”
otherwise.
: Set to “1” when a carry or a borrow from bit 7 occurs as a result of an arithmetic operation. Cleared
to “0” otherwise. Set to the shift-out value in the case of a shift instruction.
MB95140 Series
The following general-purpose registers are provided:
General-purpose registers: 8-bit data storage registers
The general-purpose registers are 8 bits and located in the register banks on the memory. 1-bank contains 8register. Up to a total of 32 banks can be used on the MB95140 series. The bank currently in use is specified
by the register bank pointer (RP), and the lower 3 bits of OP code indicates the general-purpose register 0 (R0)
to general-purpose register 7 (R7).
• Register Bank Configuration
8-bit
1F8H
This address = 0100H + 8 × (RP)
R0
Address 100H
R0
R0
R1
R2
R3
R4
R5
R6
107H
R1
R2
R3
R4
R5
R6
R1
R2
R3
R4
R5
R6
1FFH
R7
R7
R7
Bank 0
Memory area
Bank 31
32 banks
32 banks (RAM area)
The number of banks is
limited by the usable RAM
capacitance.
19
MB95140 Series
■ I/O MAP
Address
Register
abbreviation
Register name
R/W
Initial value
0000H
PDR0
Port 0 data register
R/W
00000000B
0001H
DDR0
Port 0 direction register
R/W
00000000B
0002H
PDR1
Port 1 data register
R/W
00000000B
0003H
DDR1
Port 1 direction register
R/W
00000000B
0004H
⎯
(Disabled)
⎯
⎯
0005H
WATR
Oscillation stabilization wait time setting register
R/W
11111111B
0006H
PLLC
PLL control register
R/W
00000000B
0007H
SYCC
System clock control register
R/W
1010X011B
0008H
STBC
Standby control register
R/W
00000000B
0009H
RSRR
Reset source register
R
XXXXXXXXB
000AH
TBTC
Timebase timer control register
R/W
00000000B
000BH
WPCR
Watch prescaler control register
R/W
00000000B
000CH
WDTC
Watchdog timer control register
R/W
00000000B
000DH
to
0015H
⎯
(Disabled)
⎯
⎯
0016H
PDR6
Port 6 data register
R/W
00000000B
0017H
DDR6
Port 6 direction register
R/W
00000000B
0018H
to
0027H
⎯
(Disabled)
⎯
⎯
0028H
PDRF
Port F data register
R/W
00000000B
0029H
DDRF
Port F direction register
R/W
00000000B
002AH
PDRG
Port G data register
R/W
00000000B
002BH
DDRG
Port G direction register
R/W
00000000B
002CH
PUL0
Port 0 pull-up register
R/W
00000000B
002DH
PUL1
Port 1 pull-up register
R/W
00000000B
002EH
to
0034H
⎯
(Disabled)
⎯
⎯
0035H
PULG
Port G pull-up register
R/W
00000000B
0036H
T01CR1
8/16-bit compound timer 01 control status register 1 ch.0
R/W
00000000B
0037H
T00CR1
8/16-bit compound timer 00 control status register 1 ch.0
R/W
00000000B
0038H
T11CR1
8/16-bit compound timer 11 control status register 1 ch.1
R/W
00000000B
0039H
T10CR1
8/16-bit compound timer 10 control status register 1 ch.1
R/W
00000000B
003AH
PC01
8/16-bit PPG1 control register ch.0
R/W
00000000B
(Continued)
20
MB95140 Series
Address
Register
abbreviation
Register name
R/W
Initial value
003BH
PC00
8/16-bit PPG0 control register ch.0
R/W
00000000B
003CH
PC11
8/16-bit PPG1 control register ch.1
R/W
00000000B
003DH
PC10
8/16-bit PPG0 control register ch.1
R/W
00000000B
003EH
to
0041H
⎯
(Disabled)
⎯
⎯
0042H
PCNTH0
16-bit PPG control status register (Upper byte) ch.0
R/W
00000000B
0043H
PCNTL0
16-bit PPG control status register (Lower byte) ch.0
R/W
00000000B
0044H
to
0047H
⎯
(Disabled)
⎯
⎯
0048H
EIC00
External interrupt circuit control register ch.0/ch.1
R/W
00000000B
0049H
EIC10
External interrupt circuit control register ch.2/ch.3
R/W
00000000B
004AH
EIC20
External interrupt circuit control register ch.4/ch.5
R/W
00000000B
004BH
EIC30
External interrupt circuit control register ch.6/ch.7
R/W
00000000B
004CH
to
004FH
⎯
(Disabled)
⎯
⎯
0050H
SCR
LIN-UART serial control register
R/W
00000000B
0051H
SMR
LIN-UART serial mode register
R/W
00000000B
0052H
SSR
LIN-UART serial status register
R/W
00001000B
0053H
RDR/TDR
LIN-UART reception/transmission data register
R/W
00000000B
0054H
ESCR
LIN-UART extended status control register
R/W
00000100B
0055H
ECCR
LIN-UART extended communication control register
R/W
000000XXB
0056H
SMC10
UART/SIO serial mode control register 1 ch.0
R/W
00000000B
0057H
SMC20
UART/SIO serial mode control register 2 ch.0
R/W
00100000B
0058H
SSR0
UART/SIO serial status register ch.0
R/W
00000001B
0059H
TDR0
UART/SIO serial output data register ch.0
R/W
00000000B
005AH
RDR0
UART/SIO serial input data register ch.0
R
00000000B
005BH
to
006BH
⎯
(Disabled)
⎯
⎯
006CH
ADC1
8/10-bit A/D converter control register 1
R/W
00000000B
006DH
ADC2
8/10-bit A/D converter control register 2
R/W
00000000B
006EH
ADDH
8/10-bit A/D converter data register (Upper byte)
R/W
00000000B
006FH
ADDL
8/10-bit A/D converter data register (Lower byte)
R/W
00000000B
(Continued)
21
MB95140 Series
Address
Register
abbreviation
Register name
R/W
Initial value
0070H
WCSR
Watch counter status register
R/W
00000000B
0071H
⎯
(Disabled)
⎯
⎯
0072H
FSR
Flash memory status register
R/W
000X0000B
0073H
SWRE0
Flash memory sector writing control register 0
R/W
00000000B
0074H
SWRE1
Flash memory sector writing control register 1
R/W
00000000B
0075H
⎯
(Disabled)
⎯
⎯
0076H
WREN
Wild register address compare enable register
R/W
00000000B
0077H
WROR
Wild register data test setting register
R/W
00000000B
0078H
⎯
(Mirror of register bank pointer (RP)
and direct bank pointer (DP) )
⎯
⎯
0079H
ILR0
Interrupt level setting register 0
R/W
11111111B
007AH
ILR1
Interrupt level setting register 1
R/W
11111111B
007BH
ILR2
Interrupt level setting register 2
R/W
11111111B
007CH
ILR3
Interrupt level setting register 3
R/W
11111111B
007DH
ILR4
Interrupt level setting register 4
R/W
11111111B
007EH
ILR5
Interrupt level setting register 5
R/W
11111111B
007FH
⎯
(Disabled)
⎯
⎯
0F80H
WRARH0
Wild register address setting register (Upper byte) ch.0
R/W
00000000B
0F81H
WRARL0
Wild register address setting register (Lower byte) ch.0
R/W
00000000B
0F82H
WRDR0
Wild register data setting register ch.0
R/W
00000000B
0F83H
WRARH1
Wild register address setting register (Upper byte) ch.1
R/W
00000000B
0F84H
WRARL1
Wild register address setting register (Lower byte) ch.1
R/W
00000000B
0F85H
WRDR1
Wild register data setting register ch.1
R/W
00000000B
0F86H
WRARH2
Wild register address setting register (Upper byte) ch.2
R/W
00000000B
0F87H
WRARL2
Wild register address setting register (Lower byte) ch.2
R/W
00000000B
0F88H
WRDR2
Wild register data setting register ch.2
R/W
00000000B
0F89H
to
0F91H
⎯
(Disabled)
⎯
⎯
0F92H
T01CR0
8/16-bit compound timer 01 control status register 0 ch.0
R/W
00000000B
0F93H
T00CR0
8/16-bit compound timer 00 control status register 0 ch.0
R/W
00000000B
0F94H
T01DR
8/16-bit compound timer 01 data register ch.0
R/W
00000000B
0F95H
T00DR
8/16-bit compound timer 00 data register ch.0
R/W
00000000B
0F96H
TMCR0
8/16-bit compound timer 00/01 timer mode control register
ch.0
R/W
00000000B
0F97H
T11CR0
8/16-bit compound timer 11 control status register 0 ch.1
R/W
00000000B
(Continued)
22
MB95140 Series
Address
Register
abbreviation
Register name
R/W
Initial value
0F98H
T10CR0
8/16-bit compound timer 10 control status register 0 ch.1
R/W
00000000B
0F99H
T11DR
8/16-bit compound timer 11 data register ch.1
R/W
00000000B
0F9AH
T10DR
8/16-bit compound timer 10 data register ch.1
R/W
00000000B
0F9BH
TMCR1
8/16-bit compound timer 10/11 timer mode control register
ch.1
R/W
00000000B
0F9CH
PPS01
8/16-bit PPG1 cycle setting buffer register ch.0
R/W
11111111B
0F9DH
PPS00
8/16-bit PPG0 cycle setting buffer register ch.0
R/W
11111111B
0F9EH
PDS01
8/16-bit PPG1 duty setting buffer register ch.0
R/W
11111111B
0F9FH
PDS00
8/16-bit PPG0 duty setting buffer register ch.0
R/W
11111111B
0FA0H
PPS11
8/16-bit PPG1 cycle setting buffer register ch.1
R/W
11111111B
0FA1H
PPS10
8/16-bit PPG0 cycle setting buffer register ch.1
R/W
11111111B
0FA2H
PDS11
8/16-bit PPG1 duty setting buffer register ch.1
R/W
11111111B
0FA3H
PDS10
8/16-bit PPG0 duty setting buffer register ch.1
R/W
11111111B
0FA4H
PPGS
8/16-bit PPG start register
R/W
00000000B
0FA5H
REVC
8/16-bit PPG output inversion register
R/W
00000000B
0FA6H
to
0FA9H
⎯
(Disabled)
⎯
⎯
0FAAH
PDCRH0
16-bit PPG down counter register (Upper byte) ch.0
R
00000000B
0FABH
PDCRL0
16-bit PPG down counter register (Lower byte) ch.0
R
00000000B
0FACH
PCSRH0
16-bit PPG cycle setting buffer register (Upper byte) ch.0
R/W
11111111B
0FADH
PCSRL0
16-bit PPG cycle setting buffer register (Lower byte) ch.0
R/W
11111111B
0FAEH
PDUTH0
16-bit PPG duty setting buffer register (Upper byte) ch.0
R/W
11111111B
0FAFH
PDUTL0
16-bit PPG duty setting buffer register (Lower byte) ch.0
R/W
11111111B
0FB0H
to
0FBBH
⎯
(Disabled)
⎯
⎯
0FBCH
BGR1
LIN-UART baud rate generator register 1
R/W
00000000B
0FBDH
BGR0
LIN-UART baud rate generator register 0
R/W
00000000B
0FBEH
PSSR0
UART/SIO dedicated baud rate generator
prescaler selection register ch.0
R/W
00000000B
0FBFH
BRSR0
UART/SIO dedicated baud rate generator
baud rate setting register ch.0
R/W
00000000B
0FC0H
to
0FC2H
⎯
(Disabled)
⎯
⎯
0FC3H
AIDRL
A/D input disable register (Lower byte)
R/W
00000000B
0FC4H
to
0FE2H
⎯
(Disabled)
⎯
⎯
(Continued)
23
MB95140 Series
(Continued)
Address
Register
abbreviation
Register name
R/W
Initial value
0FE3H
WCDR
Watch counter data register
R/W
00111111B
0FE4H
to
0FEDH
⎯
(Disabled)
⎯
⎯
0FEEH
ILSR
Input level select register
R/W
00000000B
0FEFH
WICR
Interrupt pin control register
R/W
01000000B
0FF0H
to
0FFFH
⎯
(Disabled)
⎯
⎯
• R/W access symbols
R/W : Readable/Writable
R
: Read only
W
: Write only
• Initial value symbols
0 : The initial value of this bit is “0”.
1 : The initial value of this bit is “1”.
X : The initial value of this bit is undefined.
Note : Do not write to the “ (Disabled) ”. Reading the “ (Disabled) ” returns an undefined value.
24
MB95140 Series
■ INTERRUPT SOURCE TABLE
Interrupt source
Interrupt
request
number
Vector table address
Same level
Bit name of
priority order
interrupt level
(at simultaneous
setting register
occurrence)
Upper
Lower
IRQ0
FFFAH
FFFBH
L00 [1 : 0]
IRQ1
FFF8H
FFF9H
L01 [1 : 0]
IRQ2
FFF6H
FFF7H
L02 [1 : 0]
IRQ3
FFF4H
FFF5H
L03 [1 : 0]
UART/SIO ch.0
IRQ4
FFF2H
FFF3H
L04 [1 : 0]
8/16-bit compound timer ch.0 (Lower)
IRQ5
FFF0H
FFF1H
L05 [1 : 0]
8/16-bit compound timer ch.0 (Upper)
IRQ6
FFEEH
FFEFH
L06 [1 : 0]
LIN-UART (reception)
IRQ7
FFECH
FFEDH
L07 [1 : 0]
LIN-UART (transmission)
IRQ8
FFEAH
FFEBH
L08 [1 : 0]
8/16-bit PPG ch.1 (Lower)
IRQ9
FFE8H
FFE9H
L09 [1 : 0]
8/16-bit PPG ch.1 (Upper)
IRQ10
FFE6H
FFE7H
L10 [1 : 0]
(Unused)
IRQ11
FFE4H
FFE5H
L11 [1 : 0]
8/16-bit PPG ch.0 (Upper)
IRQ12
FFE2H
FFE3H
L12 [1 : 0]
8/16-bit PPG ch.0 (Lower)
IRQ13
FFE0H
FFE1H
L13 [1 : 0]
8/16-bit compound timer ch.1 (Upper)
IRQ14
FFDEH
FFDFH
L14 [1 : 0]
16-bit PPG ch.0
IRQ15
FFDCH
FFDDH
L15 [1 : 0]
(Unused)
IRQ16
FFDAH
FFDBH
L16 [1 : 0]
(Unused)
IRQ17
FFD8H
FFD9H
L17 [1 : 0]
8/10-bit A/D converter
IRQ18
FFD6H
FFD7H
L18 [1 : 0]
Timebase timer
IRQ19
FFD4H
FFD5H
L19 [1 : 0]
Watch timer/Watch counter
IRQ20
FFD2H
FFD3H
L20 [1 : 0]
(Unused)
IRQ21
FFD0H
FFD1H
L21 [1 : 0]
8/16-bit compound timer ch.1 (Lower)
IRQ22
FFCEH
FFCFH
L22 [1 : 0]
Flash memory
IRQ23
FFCCH
FFCDH
L23 [1 : 0]
External interrupt ch.0
External interrupt ch.4
External interrupt ch.1
External interrupt ch.5
External interrupt ch.2
External interrupt ch.6
External interrupt ch.3
External interrupt ch.7
High
Low
25
MB95140 Series
■ ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
Parameter
Symbol
Power supply voltage*1
Input voltage*1
Output voltage*
1
Maximum clamp current
Total maximum clamp
current
“L” level maximum
output current
Rating
VCC
AVCC
VSS − 0.3
VSS + 4.0
V
*2
VI
VSS − 0.3
VSS + 4.0
V
*3
VO
VSS − 0.3
VSS + 4.0
V
*3
ICLAMP
− 2.0
+ 2.0
mA
Applicable to pins*4
Σ|ICLAMP|
⎯
20
mA
Applicable to pins*4
IOL1
IOL2
“L” level average
current
⎯
“H” level maximum
output current
mA
mA
12
ΣIOL
⎯
100
mA
ΣIOLAV
⎯
50
mA
IOH1
IOH2
“H” level average
current
⎯
− 15
− 15
mA
−4
⎯
mA
−8
IOHAV2
“H” level total average
output current
15
⎯
IOHAV1
“H” level total maximum
output current
15
4
IOLAV2
“L” level total average
output current
Remarks
Max
IOLAV1
“L” level total maximum
output current
Unit
Min
ΣIOH
⎯
− 100
mA
ΣIOHAV
⎯
− 50
mA
Other than PF0 to PF2
PF0 to PF2
Other than PF0 to PF2
Average output current =
operating current × operating ratio
(1 pin)
PF0 to PF2
Average output current =
operating current × operating ratio
(1 pin)
Total average output current =
operating current × operating ratio
(Total of pins)
Other than PF0 to PF2
PF0 to PF2
Other than PF0 to PF2
Average output current =
operating current × operating ratio
(1 pin)
PF0 to PF2
Average output current =
operating current × operating ratio
(1 pin)
Total average output current =
operating current × operating ratio
(Total of pins)
(Continued)
26
MB95140 Series
(Continued)
Parameter
Symbol
Rating
Min
Max
Unit
Power consumption
Pd
⎯
320
mW
Operating temperature
TA
− 40
+ 85
°C
Tstg
− 55
+ 150
°C
Storage temperature
Remarks
*1 : The parameter is based on AVSS = VSS = 0.0 V.
*2 : Apply equal potential to AVCC and VCC.
*3 : VI and Vo should not exceed VCC + 0.3 V. VI must not exceed the rating voltage. However, if the maximum
current to/from an input is limited by some means with external components, the ICLAMP rating supersedes the
VI rating.
*4 : Applicable to pins : P00 to P07, P10 to P14, P60 to P64, PF0 to PF2, PG0
• Use within recommended operating conditions.
• Use at DC voltage (current).
• The + B signal is an input signal that exceeds VCC voltage. The + B signal should always be applied a limiting
resistance placed between the + B signal and the microcontroller.
• The value of the limiting resistance should be set so that when the + B signal is applied the input current
to the microcontroller pin does not exceed rated values, either instantaneously or for prolonged periods.
• Note that when the microcontroller drive current is low, such as in the power saving modes, the +B input
potential may pass through the protective diode and increase the potential at the VCC pin, and this affects
other devices.
• Note that if the + B signal is inputted when the microcontroller power supply is off (not fixed at 0 V), the power
supply is provided from the pins, so that incomplete operation may result.
• Note that if the + B input is applied during power-on, the power supply is provided from the pins and the
resulting power supply voltage may not be sufficient to operate the power-on reset.
• Care must be taken not to leave the + B input pin open.
• Sample recommended circuits :
• Input/Output Equivalent Circuits
Protective diode
+ B input (0 V to 16 V)
Vcc
Limiting
resistance
P-ch
N-ch
R
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
27
MB95140 Series
2. Recommended Operating Conditions
(AVSS = VSS = 0.0 V)
Parameter
Power supply
voltage
Operating temperature
Symbol
VCC,
AVCC
TA
Value
Pin name
Condition
Min
Max
⎯
⎯
2.3*
3.3
At normal operating,
TA = −10 °C to +85 °C
⎯
⎯
2.4*
3.3
At normal operating,
TA = −40 °C to +85 °C
⎯
⎯
2.6
3.6
MB95FV100D-101
TA = +5 to +35
⎯
⎯
1.5
3.3
Retain status in stop mode
⎯
⎯
− 40
+ 85
Unit
V
Remarks
°C
* : The values vary with the operating frequency.
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device’s electrical characteristics are warranted when the device is
operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representatives beforehand.
28
MB95140 Series
3. DC Characteristics
(VCC = AVCC = 3.3 V, AVSS = VSS = 0.0 V, TA = − 40 °C to + 85 °C)
Parameter
“H” level input
voltage
“L” level input
voltage
Symbol
Min
Typ
Max
Unit
Remarks
*1
0.7 VCC
⎯
VCC + 0.3
V
At selecting CMOS
input level
VIHS
P00 to P07,
P10 to P14,
P60 to P64,
PF0 to PF2, PG0,
PG1*2, PG2*2
*1
0.8 VCC
⎯
VCC + 0.3
V
Hysteresis input
VIHM RST, MOD
⎯
0.8 VCC
⎯
VCC + 0.3
V
Hysteresis input
VIL
P04, P10
*1
VSS − 0.3
⎯
0.3 VCC
V
At selecting CMOS
input level
(Hysteresis input)
VILS
P00 to P07,
P10 to P14,
P60 to P64,
PF0 to PF2, PG0,
PG1*2, PG2*2
*1
VSS − 0.3
⎯
0.2 VCC
V
Hysteresis input
VILM
RST, MOD
⎯
VSS − 0.3
⎯
0.2 VCC
V
Hysteresis input
Output pin other
IOH = − 4.0 mA
than PF0 to PF2
2.4
⎯
⎯
V
IOH = − 8.0 mA
2.4
⎯
⎯
V
Output pin other
IOL = 4.0 mA
than PF0 to PF2
⎯
⎯
0.4
V
IOL = 12 mA
⎯
⎯
0.4
V
0.0 V < VI < VCC
−5
⎯
+5
µA
When the pull-up is
prohibition setting
25
50
100
kΩ
When the pull-up is
permission setting
⎯
11.0
14.0
At other than Flash
mA memory writing
and erasing
⎯
30.0
35.0
mA
⎯
17.6
22.4
At other than Flash
mA memory writing
and erasing
⎯
38.1
44.9
mA
“L” level output
voltage
VOL1
Power supply
current*3
Value
P04, P10
VOH1
Pull-up resistor
Conditions
VIH
“H” level output
voltage
Input leakage
current (Hi-Z
output leakage
current)
Pin name
VOH2 PF0 to PF2
VOL2 PF0 to PF2
ILI
All input pins
P00 to P07,
RPULL P10 to P14, PG0, VI = 0.0 V
PG1*2, PG2*2
ICC
VCC
(External clock
operation)
FCH = 20 MHz
FMP = 10 MHz
Main clock
mode
(divided by 2)
FCH = 32 MHz
FMP = 16 MHz
Main clock
mode
(divided by 2)
At Flash memory
writing and erasing
At Flash memory
writing and erasing
(Continued)
29
MB95140 Series
Parameter
Symbol
Pin name
FCH = 20 MHz
FMP = 10 MHz
Main Sleep mode
(divided by 2)
⎯
4.5
6.0
mA
FCH = 32 MHz
FMP = 16 MHz
Main Sleep mode
(divided by 2)
⎯
7.2
9.6
mA
ICCL
FCL = 32 kHz
FMPL = 16 kHz
Sub clock mode
(divided by 2) ,
TA = + 25 °C
⎯
25
35
µA
ICCLS
FCL = 32 kHz
FMPL = 16 kHz
Sub sleep mode
(divided by 2) ,
TA = + 25 °C
⎯
7
15
µA
ICCT
FCL = 32 kHz
Watch mode
Main stop mode
TA = + 25 °C
⎯
2
10
µA
FCH = 4 MHz
FMP = 10 MHz
Main PLL mode
(multiplied by 2.5)
⎯
10
14
mA
FCH = 6.4 MHz
FMP = 16 MHz
Main PLL mode
(multiplied by 2.5)
⎯
16.0
22.4
mA
FCL = 32 kHz
FMPL = 128 kHz
Sub PLL mode
(multiplied by 4) ,
TA = + 25 °C
⎯
190
250
µA
ICTS
FCH = 10 MHz
Timebase timer
mode
TA = + 25 °C
⎯
0.64
0.80
mA
ICCH
Sub stop mode
TA = + 25 °C
⎯
1
5
µA
ICCS
Power supply
current*3
(VCC = AVCC = 3.3 V, AVSS = VSS = 0.0 V, TA = − 40 °C to + 85 °C)
Value
Conditions
Unit
Remarks
Min
Typ
Max
ICCMPLL
ICCSPLL
VCC
(External clock
operation)
(Continued)
30
MB95140 Series
(Continued)
Parameter
(VCC = AVCC = 3.3 V, AVSS = VSS = 0.0 V, TA = − 40 °C to + 85 °C)
Symbol
Pin name
IA
Power supply
AVCC
current*3
IAH
Input
capacitance
CIN
Conditions
Value
Unit
Min
Typ
Max
FCH = 10 MHz
At operating of A/D
conversion
⎯
1.3
2.2
mA
FCH = 10 MHz
At stopping of A/D
conversion
TA = + 25 °C
⎯
1
5
µA
⎯
5
15
pF
Other than AVCC,
f = 1 MHz
AVSS, VCC, VSS
Remarks
*1 : P04, P10 can switch the input level to either the “CMOS input level” or “hysteresis input level”.
The switching of the input level can be set by the input level selection register (ILSR).
*2 : Single clock product only
*3 : Power supply current is regulated by external clock.
• Refer to “4. AC Characteristics (1) Clock Timing” for FCH and FCL.
• Refer to “4. AC Characteristics (2) Source Clock/Machine Clock” for FMP and FMPL.
31
MB95140 Series
4. AC Characteristics
(1) Clock Timing
(VCC = 3.3 V, AVSS = VSS = 0.0 V, TA = − 40 °C to + 85 °C)
Parameter
SymPin name Conditions
bol
FCH
X0, X1
Clock frequency
FCL
Value
Max
1.00
⎯
16.25 MHz
1.00
⎯
32.50 MHz When using external clock
3.00
⎯
10.00 MHz Main PLL multiplied by 1
3.00
⎯
8.13
MHz Main PLL multiplied by 2
3.00
⎯
6.50
MHz Main PLL multiplied by 2.5
3.00
⎯
4.06
MHz Main PLL multiplied by 4
⎯
32.768
⎯
kHz
⎯
32.768
⎯
When using sub PLL
kHz Flash memory product :
VCC = 2.3 V to 3.3 V
100
⎯
1000
ns
When using main
oscillation circuit
50
⎯
1000
ns
When using external clock
When using sub oscillation
circuit, When using
external clock
X0A, X1A
X0, X1
Clock cycle time
Input clock pulse
width
Input clock rise time
and fall time
32
Remarks
Typ
⎯
tHCYL
Unit
Min
When using main
oscillation circuit
When using sub oscillation
circuit
tLCYL
X0A, X1A
⎯
30.5
⎯
µs
tWH1
tWL1
X0
10
⎯
⎯
ns
tWH2
tWL2
X0A
⎯
15.2
⎯
µs
When using external clock
Duty ratio is about 30% to
70%.
tCR
tCF
X0, X0A
⎯
⎯
10
ns
When using external clock
MB95140 Series
• Input wave form for using external clock (main clock)
tHCYL
tWH1
tWL1
tCR
tCF
0.8 VCC 0.8 VCC
X0
0.2 VCC
0.2 VCC
0.2 VCC
• Figure of main clock input port external connection
When using a crystal or
ceramic oscillator
When using external clock
Microcontroller
Microcontroller
X0
X1
X0
X1
Open
FCH
FCH
C1
C2
• Input wave form for using external clock (sub clock)
tLCYL
tWH2
tCR
tWL2
tCF
0.8 VCC 0.8 VCC
X0A
0.1 VCC
0.1 VCC
0.1 VCC
• Figure of sub clock input port external connection
When using a crystal or
ceramic oscillator
Microcontroller
X0A
X1A
When using external clock
Microcontroller
X0A
FCL
X1A
Open
FCL
C1
C2
33
MB95140 Series
(2) Source Clock/Machine Clock
(VCC = 3.3 V, AVSS = VSS = 0.0 V, TA = − 40 °C to + 85 °C)
SymPin
bol name
Parameter
Value
Min
61.5
Typ
⎯
Max
2000
Unit
ns
When using main clock
Min : FCH = 8.125 MHz,
PLL multiplied by 2
Max : FCH = 1 MHz, divided by 2
µs
When using sub clock
Min : FCL = 32 kHz,
PLL multiplied by 4
Max : FCL = 32 kHz, divided by 2
1
Source clock cycle time*
(Clock before setting
division)
Source clock frequency
Machine clock cycle time*2
(Minimum instruction
execution time)
Machine clock frequency
tSCLK
⎯
7.6
⎯
61.0
16.25
Remarks
FSP
⎯
0.5
⎯
FSPL
⎯
16.384
⎯
100
⎯
32000
ns
When using main clock
Min : FSP = 16.25 MHz, no division
Max : FSP = 0.5 MHz, divided by 16
7.6
⎯
976.5
µs
When using sub clock
Min : FSPL = 131 kHz, no division
Max : FSPL = 16 kHz, divided by 16
0.031
⎯
16.250
1.024
⎯
131.072 kHz When using sub clock
tMCLK
FMP
FMPL
MHz When using main clock
131.072 kHz When using sub clock
⎯
⎯
MHz When using main clock
*1 : Clock before setting division due to machine clock division ratio selection bits (SYCC : DIV1 and DIV0) .
This source clock is divided by the machine clock division ratio selection bits (SYCC : DIV1 and DIV0) , and it
becomes the machine clock. Further, the source clock can be selected as follows.
• Main clock divided by 2
• PLL multiplication of main clock (select from 1, 2, 2.5, 4 multiplication)
• Sub clock divided by 2
• PLL multiplication of sub clock (select from 2, 3, 4 multiplication)
*2 : Operation clock of the microcontroller. Machine clock can be selected as follows.
• Source clock (no division)
• Source clock divided by 4
• Source clock divided by 8
• Source clock divided by 16
34
MB95140 Series
• Outline of Clock Generation Block
FCH
(main oscillation)
Divided by 2
Main PLL
×1
×2
× 2.5
×4
SCLK
(source clock)
FCL
(sub oscillation)
Divided by 2
Sub PLL
×2
×3
×4
Division
circuit
×1
× 1/4
× 1/8
× 1/16
MCLK
(machine clock)
Clock mode select bit
(SYCC: SCS1, SCS0)
35
MB95140 Series
• Operating Voltage - Operating Frequency (When TA = − 10 °C to + 85 °C)
• MB95F146S, MB95F146W
Sub PLL operation guarantee range
Sub clock mode and watch mode
operation guarantee range
Main clock mode and main PLL mode
operation guarantee range
3.3
2.3
16.384 kHz
32 kHz
131.072 kHz
Operating voltage (V)
Operating voltage (V)
3.3
2.7
2.3
0.5 MHz 3 MHz 5 MHz
PLL operation guarantee range
16.25 MHz
PLL operation guarantee range
Main clock operation guarantee range
Source clock frequency (FSP)
Source clock frequency (FSPL)
• Operating Voltage - Operating Frequency (When TA = − 40 °C to + 85 °C)
• MB95F146S, MB95F146W
Sub PLL operation guarantee range
Sub clock mode and watch mode
operation guarantee range
Main clock mode and main PLL mode
operation guarantee range
3.3
2.4
16.384 kHz
32 kHz
131.072 kHz
PLL operation guarantee range
Operating voltage (V)
Operating voltage (V)
3.3
2.7
2.4
0.5 MHz 3 MHz 5 MHz
16.25 MHz
PLL operation guarantee range
Main clock operation guarantee range
Source clock frequency (FSPL)
36
Source clock frequency (FSP)
MB95140 Series
• Operating voltage − Operating frequency (TA = + 5 °C to + 35 °C)
• MB95FV100D-101
Sub PLL, sub clock mode and watch
mode operation guarantee range
Main clock mode and main PLL mode
operation guarantee range
3.6
2.6
16.384 kHz
32 kHz
131.072 kHz
PLL operation guarantee range
Operating voltage (V)
Operating voltage (V)
3.6
3.3
2.6
0.5 MHz 3 MHz
10 MHz
16.25 MHz
PLL operation guarantee range
Main clock operation guarantee range
S ource clock frequency (F SPL)
Source clock frequency (FSP)
37
MB95140 Series
• Main PLL Operation Frequency
[MHz]
16.25
16
15
×4
Source clock frequency (FSP)
12
× 2.5
10
×1
×2
7.5
6
5
3
0
3
4
4.062
5
6.4
6.5
Machine clock frequency (FMP)
38
8
8.125
10 [MHz]
MB95140 Series
(3) External Reset
(VCC = 3.3 V, AVSS = VSS = 0.0 V, TA = − 40 °C to + 85 °C)
Parameter
Value
Symbol
RST “L” level pulse
width
tRSTL
Unit
Remarks
Min
Max
2 tMCLK*1
⎯
ns
At normal operating
Oscillation time of oscillator*2
+ 2 tMCLK*1
⎯
ns
At stop mode, sub clock mode,
sub sleep mode, and watch mode
*1 : Refer to “ (2) Source Clock/Machine Clock” for tMCLK.
*2 : Oscillation start time of oscillator is the time that the amplitude reaches 90 %. In the crystal oscillator, the
oscillation time is between several ms and tens of ms. In ceramic oscillators, the oscillation time is between
hundreds of µs and several ms. In the external clock, the oscillation time is 0 ms.
• At Normal Operating
tRSTL
RST
0.2 VCC
0.2 VCC
• At Stop Mode, Sub clock Mode, Sub Sleep Mode, Watch Mode, and Power-on
RST
tRSTL
0.2 VCC
0.2 VCC
90% of
amplitude
X0
Internal
operating
clock
2 tMCLK
Oscillation time Oscillation stabilization wait time
of oscillator
Execute instruction
Internal reset
39
MB95140 Series
(4) Power-on Reset
(AVSS = VSS = 0.0 V, TA = − 40 °C to + 85 °C)
Parameter
Symbol
Conditions
Power supply rising time
tR
Power supply cutoff time
tOFF
tR
Value
Unit
Min
Max
⎯
⎯
36
ms
⎯
1
⎯
ms
Remarks
Waiting time until
power-on
tOFF
1.5 V
VCC
0.2 V
0.2 V
0.2 V
Note : Sudden change of power supply voltage may activate the power-on reset function. When changing power
supply voltages during operation, set the slope of rising within 20 mV/ms as shown below.
VCC
Limiting the slope of rising within
20 mV/ms is recommended.
1.5 V
Hold condition in stop mode
VSS
40
MB95140 Series
(5) Peripheral Input Timing
(VCC = 3.3 V, AVSS = VSS = 0.0 V, TA = − 40 °C to + 85 °C)
Parameter
Value
Symbol
Pin name
Peripheral input “H” pulse width
tILIH
Peripheral input “L” pulse width
tIHIL
INT00 to INT07,
EC0, EC1, TRG0/ADTG
Unit
Min
Max
2 tMCLK*
⎯
ns
2 tMCLK*
⎯
ns
* : Refer to “ (2) Source Clock/Machine Clock” for tMCLK.
tILIH
INT00 to INT07,
EC0, EC1,
TRG0/ADTG
tIHIL
0.8 VCC 0.8 VCC
0.2 VCC
0.2 VCC
41
MB95140 Series
(6) UART/SIO, Serial I/O Timing
(VCC = 3.3 V, AVSS = VSS = 0.0 V, TA = − 40 °C to + 85 °C)
Parameter
Symbol
Pin name
Serial clock cycle time
tSCYC
UCK0
UCK ↓ → UO time
tSLOV
UCK0, UO0
Valid UI → UCK ↑
tIVSH
UCK0, UI0
UCK ↑ → valid UI hold time
tSHIX
UCK0, UI0
Serial clock “H” pulse width
tSHSL
UCK0
Serial clock “L” pulse width
tSLSH
UCK0
UCK ↓ → UO time
tSLOV
UCK0, UO0
Valid UI → UCK ↑
tIVSH
UCK0, UI0
UCK ↑ → valid UI hold time
tSHIX
UCK0, UI0
Value
Conditions
Internal clock
operation
output pin :
CL = 80 pF + 1TTL.
External clock
operation
output pin :
CL = 80 pF + 1TTL.
Max
4 tMCLK*
⎯
ns
− 190
+ 190
ns
2 tMCLK*
⎯
ns
2 tMCLK*
⎯
ns
4 tMCLK*
⎯
ns
4 tMCLK*
⎯
ns
0
190
ns
2 tMCLK*
⎯
ns
2 tMCLK*
⎯
ns
* : Refer to “ (2) Source Clock/Machine Clock” for tMCLK.
• Internal shift clock mode
tSCYC
UCK0
2.4 V
0.8 V
0.8 V
tSLOV
UO0
UI0
2.4 V
0.8 V
tIVSH
tSHIX
0.8 VCC
0.2 VCC
0.8 VCC
0.2 VCC
• External shift clock mode
tSLSH
tSHSL
0.8 VCC 0.8 VCC
UCK0
0.2 VCC 0.2 VCC
tSLOV
UO0
UI0
42
2.4 V
0.8 V
tIVSH
tSHIX
0.8 VCC
0.2 VCC
0.8 VCC
0.2 VCC
Unit
Min
MB95140 Series
(7) LIN-UART Timing
Sampling at the rising edge of sampling clock*1 and prohibited serial clock delay*2
(ESCR register : SCES bit = 0, ECCR register : SCDE bit = 0)
(VCC = 3.3 V, AVSS = VSS = 0.0 V, TA = −40 °C to + 85 °C)
Parameter
Serial clock cycle time
SCK ↓ → SOT delay time
SymPin name
bol
tSCYC
tSLOVI
Valid SIN → SCK ↑
tIVSHI
SCK ↑ → valid SIN hold time
tSHIXI
Serial clock “L” pulse width
tSLSH
Serial clock “H” pulse width
tSHSL
Value
Conditions
Max
5 tMCLK*3
⎯
ns
−95
+ 95
ns
⎯
ns
0
⎯
ns
3 tMCLK*3 − tR
⎯
ns
* + 95
⎯
ns
SCK
Internal clock
SCK, SOT
operation output pin :
SCK, SIN CL = 80 pF + 1 TTL.
SCK, SIN
SCK
SCK
SCK ↓ → SOT delay time
tSLOVE SCK, SOT
Valid SIN → SCK ↑
tIVSHE
SCK ↑ → valid SIN hold time
tSHIXE
External clock
SCK, SIN operation output pin :
CL = 80 pF + 1 TTL.
SCK, SIN
Unit
Min
t
* + 190
MCLK 3
MCLK 3
t
⎯
* + 95
MCLK 3
ns
190
⎯
ns
tMCLK*3 + 95
⎯
ns
2t
SCK fall time
tF
SCK
⎯
10
ns
SCK rise time
tR
SCK
⎯
10
ns
*1 : Provide switch function whether sampling of reception data is performed at rising edge or falling edge of the
serial clock.
*2 : Serial clock delay function is used to delay half clock for the output signal of serial clock.
*3 : Refer to “ (2) Source Clock/Machine Clock” for tMCLK.
43
MB95140 Series
• Internal shift clock mode
tSCYC
2.4 V
SCK
0.8 V
tSLOVI
2.4 V
SOT
0.8 V
tIVSHI
tSHIXI
0.8 VCC 0.8 VCC
SIN
0.2 VCC 0.2 VCC
• External shift clock mode
tSHSL
tSLSH
SCK
0.8 VCC
0.2 VCC
tF
SOT
0.2 VCC
tR
tSLOVE
2.4 V
0.8 V
tIVSHE
SIN
tSHIXE
0.8 VCC 0.8 VCC
0.2 VCC 0.2 VCC
44
0.8 VCC
MB95140 Series
Sampling at the falling edge of sampling clock*1 and prohibited serial clock delay*2
(ESCR register : SCES bit = 1, ECCR register : SCDE bit = 0)
(VCC = 3.3 V, AVSS = VSS = 0.0 V, TA = −40 °C to + 85 °C)
Symbol
Pin name
Serial clock cycle time
tSCYC
SCK
SCK ↑ → SOT delay time
tSHOVI
SCK, SOT
Parameter
Value
Conditions
Internal clock
operation output pin :
SCK, SIN CL = 80 pF + 1 TTL.
SCK, SIN
Unit
Min
Max
5 tMCLK*3
⎯
ns
−95
+ 95
ns
⎯
ns
0
⎯
ns
* + 190
Valid SIN → SCK ↓
tIVSLI
SCK ↓ → valid SIN hold time
tSLIXI
Serial clock “H” pulse width
tSHSL
SCK
3 tMCLK*3 − tR
⎯
ns
Serial clock “L” pulse width
tSLSH
SCK
tMCLK*3 + 95
⎯
ns
SCK, SOT
⎯
SCK ↑ → SOT delay time
tSHOVE
Valid SIN → SCK ↓
tIVSLE
SCK ↓ → valid SIN hold time
tSLIXE
External clock
SCK, SIN operation output pin :
SCK, SIN CL = 80 pF + 1 TTL.
t
MCLK 3
* + 95
MCLK 3
ns
190
⎯
ns
tMCLK*3 + 95
⎯
ns
2t
SCK fall time
tF
SCK
⎯
10
ns
SCK rise time
tR
SCK
⎯
10
ns
*1 : Provide switch function whether sampling of reception data is performed at rising edge or falling edge of the
serial clock.
*2 : Serial clock delay function is used to delay half clock for the output signal of serial clock.
*3 : Refer to “ (2) Source Clock/Machine Clock” for tMCLK.
45
MB95140 Series
• Internal shift clock mode
tSCYC
2.4 V
SCK
2.4 V
0.8 V
tSHOVI
2.4 V
SOT
0.8 V
tIVSLI
tSLIXI
0.8 VCC 0.8 VCC
SIN
0.2 VCC 0.2 VCC
• External shift clock mode
tSHSL
SCK
0.8 VCC
tSLSH
0.8 VCC
0.2 VCC
tR
SOT
tF
tSHOVE
2.4 V
0.8 V
tIVSLE
SIN
tSLIXE
0.8 VCC 0.8 VCC
0.2 VCC 0.2 VCC
46
0.2 VCC
MB95140 Series
Sampling at the rising edge of sampling clock*1 and enabled serial clock delay*2
(ESCR register : SCES bit = 0, ECCR register : SCDE bit = 1)
(VCC = 3.3 V, AVSS = VSS = 0.0 V, TA = −40 °C to + 85 °C)
Symbol
Pin name
Serial clock cycle time
tSCYC
SCK
SCK ↑ → SOT delay time
tSHOVI
SCK, SOT
Parameter
Value
Conditions
Valid SIN → SCK ↓
tIVSLI
SCK, SIN
SCK ↓ → valid SIN hold time
tSLIXI
SCK, SIN
SOT → SCK ↓ delay time
tSOVLI
SCK, SOT
Internal clock
operation output pin :
CL = 80 pF + 1 TTL.
Unit
Min
Max
5 tMCLK*3
⎯
ns
−95
+ 95
ns
⎯
ns
0
⎯
ns
⎯
4 tMCLK*3
ns
* + 190
MCLK 3
t
*1 : Provide switch function whether sampling of reception data is performed at rising edge or falling edge of
the serial clock.
*2 : Serial clock delay function is used to delay half clock for the output signal of serial clock.
*3 : Refer to “ (2) Source Clock/Machine Clock” for tMCLK.
tSCYC
2.4 V
SCK
0.8 V
SOT
2.4 V
0.8 V
2.4 V
0.8 V
tIVSLI
SIN
0.8 V
tSHOVI
tSOVLI
0.8 VCC
0.2 VCC
tSLIXI
0.8 VCC
0.2 VCC
47
MB95140 Series
Sampling at the falling edge of sampling clock*1 and enabled serial clock delay*2
(ESCR register : SCES bit = 1, ECCR register : SCDE bit = 1)
(VCC = 3.3 V, AVSS = VSS = 0.0 V, TA = −40 °C to + 85 °C)
Symbol
Pin name
Serial clock cycle time
tSCYC
SCK ↓ → SOT delay time
tSLOVI
Parameter
Value
Conditions
Unit
Min
Max
SCK
5 tMCLK*3
⎯
ns
SCK, SOT
−95
+ 95
ns
⎯
ns
0
⎯
ns
⎯
4 tMCLK*3
ns
Valid SIN → SCK ↑
tIVSHI
SCK ↑ → valid SIN hold time
tSHIXI
Internal clock
SCK, SIN operating output pin :
CL = 80 pF + 1 TTL.
SCK, SIN
SOT → SCK ↑ delay time
tSOVHI
SCK, SOT
t
* + 190
MCLK 3
*1 : Provide switch function whether sampling of reception data is performed at rising edge or falling edge of the
serial clock.
*2 : Serial clock delay function is used to delay half clock for the output signal of serial clock.
*3 : Refer to “ (2) Source Clock/Machine Clock” for tMCLK.
tSCYC
2.4 V
SCK
2.4 V
0.8 V
tSOVHI
SOT
2.4 V
0.8 V
2.4 V
0.8 V
tIVSHI
SIN
48
tSLOVI
0.8 VCC
0.2 VCC
tSHIXI
0.8 VCC
0.2 VCC
MB95140 Series
5. A/D Converter
(1) A/D Converter Electrical Characteristics
(AVCC = VCC = 1.8 V to 3.3 V, AVSS = VSS = 0.0 V, TA = − 40 °C to + 85 °C)
Parameter
Symbol
Value
Unit
Min
Typ
Max
Resolution
⎯
⎯
10
bit
Total error
− 3.0
⎯
+ 3.0
LSB
− 2.5
⎯
+ 2.5
LSB
− 1.9
⎯
+ 1.9
LSB
Linearity error
⎯
Differential linear
error
Zero transition
voltage
VOT
Full-scale transition
voltage
VFST
Compare time
Sampling time
⎯
Remarks
AVSS − 1.5 LSB AVSS + 0.5 LSB AVSS + 2.5 LSB
V
2.7 V ≤ AVCC ≤ 3.3 V
AVSS − 0.5 LSB AVSS + 1.5 LSB AVSS + 3.5 LSB
V
1.8 V ≤ AVCC < 2.7 V
AVCC − 3.5 LSB AVCC − 1.5 LSB AVCC + 0.5 LSB
V
2.7 V ≤ AVCC ≤ 3.3 V
AVCC − 2.5 LSB AVCC − 0.5 LSB AVCC + 1.5 LSB
V
1.8 V ≤ AVCC < 2.7 V
0.6
⎯
140
µs
2.7 V ≤ AVCC ≤ 3.3 V
20
⎯
140
µs
1.8 V ≤ AVCC < 2.7 V
0.4
⎯
∞
µs
2.7 V ≤ AVCC ≤ 3.3 V
external impedance <
at 1.8 kΩ
30
⎯
∞
µs
1.8 V ≤ AVCC < 2.7 V
external impedance <
at 14.8 kΩ
⎯
Analog input current
IAIN
−0.3
⎯
+ 0.3
µA
Analog input voltage
VAIN
AVSS
⎯
AVCC
V
⎯
AVSS + 1.8
⎯
AVCC
V
AVCC pin
IR
⎯
400
600
µA
AVCC pin,
During A/D operation
IRH
⎯
⎯
5
µA
AVCC pin,
At stop mode
Reference voltage
Reference voltage
supply current
49
MB95140 Series
(2) Notes on Using A/D Converter
• About the external impedance of analog input and its sampling time
• A/D converter with sample and hold circuit. If the external impedance is too high to keep sufficient sampling
time, the analog voltage charged to the internal sample and hold capacitor is insufficient, adversely affecting
A/D conversion precision. Therefore, to satisfy the A/D conversion precision standard, consider the relationship
between the external impedance and minimum sampling time and either adjust the register value and operating
frequency or decrease the external impedance so that the sampling time is longer than the minimum value.
Also, if the sampling time cannot be sufficient, connect a capacitor of about 0.1 µF to the analog input pin.
• Analog input equivalent circuit
R
Analog input
Comparator
C
During sampling : ON
2.7 V ≤ AVCC ≤ 3.6 V
1.8 V ≤ AVCC < 2.7 V
R
1.7 kΩ (Max)
84 kΩ (Max)
C
14.5 pF (Max)
25.2 pF (Max)
Note : The values are reference values.
• The relationship between external impedance and minimum sampling time
(External impedance = 0 kΩ to 20 kΩ)
(External impedance = 0 kΩ to 100 kΩ)
AVCC ≥ 2.7 V
AVCC ≥ 1.8 V
0
5
10
15
20
25
30
35
Minimum sampling time [µs]
40
External impedance [kΩ]
External impedance [kΩ]
AVCC ≥ 2.7 V
100
90
80
70
60
50
40
30
20
10
0
20
18
16
14
12
10
8
6
4
2
0
0
1
3
Minimum sampling time [µs]
• About errors
As |AVCC − AVSS| becomes smaller, values of relative errors grow larger.
50
2
4
MB95140 Series
(3) Definition of A/D Converter Terms
• Resolution
The level of analog variation that can be distinguished by the A/D converter.
When the number of bits is 10, analog voltage can be divided into 210 = 1024.
• Linearity error (unit : LSB)
The deviation between the value along a straight line connecting the zero transition point
(“00 0000 0000” ← → “00 0000 0001”) of a device and the full-scale transition point
(“11 1111 1111” ← → “11 1111 1110”) compared with the actual conversion values obtained.
• Differential linear error (Unit : LSB)
Deviation of input voltage, which is required for changing output code by 1 LSB, from an ideal value.
• Total error (unit: LSB)
Difference between actual and theoretical values, caused by a zero transition error, full-scale transition error,
linearity error, quantum error, and noise.
Ideal I/O characteristics
Total error
VFST
3FFH
3FFH
3FEH
1.5 LSB
3FDH
004H
003H
002H
VOT
Digital output
Digital output
3FEH
3FDH
Actual conversion
characteristic
{1 LSB × (N − 1) + 0.5 LSB}
004H
003H
002H
1 LSB
VNT
Actual conversion
characteristic
Ideal characteristics
001H
001H
0.5 LSB
AVSS
AVCC
Analog input
1 LSB =
AVCC − AVSS
1024
(V)
AVSS
AVCC
Analog input
VNT − {1 LSB × (N − 1) + 0.5 LSB}
Total error of
=
[LSB]
digital output N
1 LSB
N : A/D converter digital output value
VNT : A voltage at which digital output transits from (N − 1) to N.
(Continued)
51
MB95140 Series
(Continued)
Full-scale transition error
Zero transition error
Ideal characteristics
004H
3FFH
Digital output
Digital output
Actual conversion
characteristic
003H
Ideal
characteristics
002H
Actual conversion
characteristic
Actual conversion
characteristic
3FEH
VFST
(measurement
value)
3FDH
001H
Actual conversion
characteristic
3FCH
VOT (measurement value)
AVSS
AVCC
AVSS
AVCC
Analog input
Analog input
Differential linear error
Linearity error
Actual conversion
characteristic
3FFH
3FEH
Actual conversion
characteristic
VFST
(measurement
value)
VNT
004H
Actual conversion
characteristic
003H
Digital output
{1 LSB × N + VOT}
3FDH
Digital output
Ideal characteristics
N+1H
NH
N-1H
Actual conversion
characteristic
N-2H
001H
VOT (measurement value)
AVSS
AVCC
AVSS
Analog input
Linear error in = VNT − {1 LSB × N + VOT}
1 LSB
digital output N
N
VNT
VOT
VFST
52
VNT
Ideal characteristics
002H
V (N+1)T
Analog input
Differential linear error =
in digital output N
: A/D converter digital output value
: A voltage at which digital output transits from (N − 1) to N.
(Ideal value) = AVSS + 0.5 LSB [V]
(Ideal value) = AVCC − 1.5 LSB [V]
V (N + 1) T − VNT
1 LSB
AVCC
−1
MB95140 Series
6. Flash Memory Program/Erase Characteristics
Parameter
Value
Unit
Remarks
1.5*2
s
Excludes 00H programming prior erasure.
32
3600*2
µs
Excludes system-level overhead time.
10000
⎯
⎯
cycle
Power supply voltage at
program/erase
2.7
⎯
3.3
V
Flash memory data retention
time
20*3
⎯
⎯
year
Min
Typ
Max
Chip erase time
⎯
1*1
Byte programming time
⎯
Program/erase cycle
Average TA = +85 °C
*1 : TA = + 25 °C, VCC = 3.0 V, 10000 cycles
*2 : TA = + 85 °C, VCC = 2.7 V, 10000 cycles
*3 : This value comes from the technology qualification (using Arrhenius equation to translate high temperature
measurements into normalized value at +85 °C) .
53
MB95140 Series
■ MASK OPTION
No.
Part number
MB95F146S
MB95F146W
MB95FV100D-101
Specifying procedure
Setting disabled
Setting disabled
Setting disabled
Single-system
clock mode
Dual-system
clock mode
Changing by the
switch on MCU board
1
Clock mode select*
• Single-system clock mode
• Dual-system clock mode
2
Low voltage detection reset*
• With low voltage detection reset
• Without low voltage
detection reset
No
No
No
3
Clock supervisor*
• With clock supervisor
• Without clock supervisor
No
No
No
4
Selection of oscillation
stabilization wait time
• Selectable the initial value of
main clock oscillation stabilization
wait time
Fixed to oscillation
Fixed to oscillation
Fixed to oscillation
stabilization wait
stabilization wait time
stabilization wait
time of (214 − 2) /FCH time of (214 − 2) /FCH of (214 − 2) /FCH
* : Low voltage detection reset and clock supervisor are options of 5-V products.
54
MB95140 Series
■ ORDERING INFORMATION
Part number
Package
MB95F146SPFM
MB95F146WPFM
MB2146-301A
(MB95FV100D-101PBT)
32-pin plastic LQFP
(FPT-32P-M21)
(
MCU board
224-pin plastic PFBGA
(BGA-224P-M08)
)
55
MB95140 Series
■ PACKAGE DIMENSIONS
32-pin plastic LQFP
Lead pitch
0.80 mm
Package width ×
package length
7 × 7 mm
Lead shape
Gullwing
Sealing method
Plastic mold
Mounting height
1.70 mm MAX
Code
(Reference)
P-LQFP32-7×7-0.80
(FPT-32P-M21)
32-pin plastic LQFP
(FPT-32P-M21)
Note 1) * : These dimensions do not include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
9.00±0.20(.354±.008)SQ
* 7.00±0.10(.276±.004)SQ
24
0.145±0.055
(.0057±.0022)
17
25
16
Details of "A" part
+0.20
0.10(.004)
1.50 –0.10
+.008
.059 –.004
(Mounting height)
0.25(.010)
INDEX
0~8˚
32
9
1
0.80(.031)
C
"A"
8
0.32±0.05
(.013±.002)
0.20(.008)
0.10±0.10
(.004±.004)
(Stand off)
M
2002 FUJITSU LIMITED F32032S-c-3-5
Please confirm the latest Package dimension by following URL.
http://edevice.fujitsu.com/fj/DATASHEET/ef-ovpklv.html
56
0.50±0.20
(.020±.008)
0.60±0.15
(.024±.006)
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
MB95140 Series
■ MAIN CHANGES IN THIS EDITION
Page
Section
⎯
⎯
Preliminary Data Sheet→Data Sheet
⎯
⎯
Changed the part number
MB95FV100B-101→MB95FV100D-101
3
■ PRODUCT LINEUP
4
Change Results
CPU functions
Minimum instruction execution time : 0.1 µs
(at machine clock frequency 10 MHz)
→Minimum instruction execution time : 61.5 ns
(at machine clock frequency 16.25 MHz)
Interrupt processing time : 0.9 µs
(at machine clock frequency 10 MHz)
→Interrupt processing time : 0.6 µs
(at machine clock frequency 16.25 MHz)
Added the description Flash memory
27
■ ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
Changed under the table*3;
VI1→VI
28
2. Recommended Operating Conditions
Changed the Min value of power supply voltage VCC, AVCC.
TA = − 10 °C to + 85 °C 1.8→2.3
TA = − 40 °C to + 85 °C 2.0→2.4
Moved “H” level input voltage and “L” level input voltage from
the section "2. Recommended Operating Conditions".
29, 30 3. DC Characteristics
Added to FMP = 16 MHz in the section of ICC, ICCS, ICCMPLL of
power supply voltage.
Changed the Typ and Max values of ICTS
0.4 → 0.64 (Typ value)
0.5 → 0.80 (Max value)
32
4. AC Characteristics
(1) Clock Timing
Changed the Max values of clock frequency X0, X1.
When using main oscillation circuit 10→16.25
When using external clock 20→32.50
Main PLL multiplied by 2 : 5→8.13
Main PLL multiplied by 2.5 : 4 →6.50
Added the Main PLL multiplied by 4
Changed source clock cycle time (when using main clock)
Min : FCH = 10 MHz, PLL multiplied by 1
→Min : FCH = 8.125 MHz, PLL multiplied by 2
34
(2) Source Clock/Machine Clock
Changed the Max value of source clock frequency FSP.
10→16.25
Changed machine clock cycle time (when using main clock)
Min : FSP = 10 MHz→Min : FSP = 16.25 MHz
Changed the Max value of machine clock frequency FMP.
10 .000→16.250
(Continued)
57
MB95140 Series
(Continued)
Page
Section
Changed the diagram of • Outline of Clock Generation
Block
35
36, 37
Change Results
4. AC Characteristics
(2) Source Clock/Machine Clock
Changed the diagram of • Operating voltage - Operating
frequency
Changed the diagram of • Main PLL operation frequency
range.
38
49
Changed the pin name in the value section of full-scale
5. A/D Converter
transition voltage;
(1) A/D Converter Electrical Characteristics
AVR→AVCC
55
■ ORDERING INFORMATION
The part number is revised as follows;
MB2146-301 MB2146-301A
The vertical lines marked in the left side of the page show the changes.
58
MB95140 Series
The information for microcontroller supports is shown in the following homepage.
http://www.fujitsu.com/global/services/microelectronics/product/micom/support/index.html
FUJITSU LIMITED
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Edited
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F0701