GENNUM GS1511

HD-LINX ™ GS1511
HDTV Serial Digital Formatter
DATA SHEET
DESCRIPTION
• SMPTE 292M compliant
The GS1511 HDTV Serial Digital Formatter formats the
HDTV Luma and Chroma data according to SMPTE 292M
prior to serialization by the GS1522 HDTV Serializer. The
GS1511 optionally inserts TRS and line number signals
based on externally supplied H, V and F signals. The
device also allows the insertion of CRCs based on TRS
signals embedded in the input data streams, should the
user choose not to supply external HVF signals.
• NRZ(I) encoding
• SMPTE 292M scrambler with BYPASS option
• selectable TRS insertion
• selectable line number insertion
• selectable line based CRC insertion
• selectable active picture illegal code re-mapping
Following the insertion of TRS, Line Number, and CRC,
protected words of 000-003 and 3FC to 3FF occurring
during the active video period are optionally re-mapped to
004 and 3FB respectively. Prior to exiting the device SMPTE
292M compliant NRZ(I) encoding and scrambling may be
performed on the data stream.
• 20 bit 3.3V CMOS compatible input data bus
• optimized output interface to GS1522
• Pb-free and Green
• single +3.3V power supply
• 5V tolerant I/O
APPLICATIONS
• SMPTE 292M Serial Digital Interfaces
TRS_Y/C
DET_TRS
2
CODE
PROTECT
TRS_INS
LN_INS
CRC_INS
BP_SC
3
DATA_IN
[19:10]
(LUMA)
DATA_IN
[9:0]
INPUT
BUFFER
and
BLANKER
TRS
and
LINE NUMBER
DETECTION
TRS
INSERTION
ILLEGAL CODE
REMAPPING
LINE NUMBER
INSERTION
DATA_OUT
NRZI
ENCODER
[19:0]
SMPTE
SCAMBLER
CRC INSERTION
(CHROMA)
PCLK_IN
BLANK
3
[H:V:F]
RSTLN
SRST
OEN
GS1511 FUNCTIONAL BLOCK DIAGRAM
Revision Date: June 2004
Document No. 52248 - 5
GENNUM CORPORATION P.O. Box 489, Stn. A, Burlington, Ontario, Canada L7R 3Y3
Tel. +1 (905) 632-2996 Fax. +1 (905) 632-5946 E-mail: [email protected]
www.gennum.com
GS1511
KEY FEATURES
TABLE OF CONTENTS
1. PIN OUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.1 PIN ASSIGNMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.2 PIN DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6
2. ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
GS1511
2.1 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.2 DC ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.3 AC ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3. DETAILED DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4. REFERENCES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
5. PACKAGE & ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
5.1 PACKAGE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
5.2 ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
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GENNUM CORPORATION
VDD
GND
VDD
GND
DATA_IN[9]
DATA_IN[8]
DATA_IN[7]
DATA_IN[6]
DATA_IN[5]
DATA_IN[4]
DATA_IN[3]
DATA_IN[2]
DATA_IN[1]
DATA_IN[0]
VDD
GND
DATA_IN[13]
DATA_IN[12]
DATA_IN[11]
DATA_IN[10]
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
NC
65
38
VDD
NC
66
37
GND
NC
67
36
OEN
VDD
68
35
TN
GND
69
34
NC
TEST
70
33
NC
NC
71
32
NC
NC
72
31
NC
NC
73
30
NC
NC
74
29
NC
NC
75
28
NC
VDD
76
27
NC
VDD
77
26
NC
VDD
78
25
VDD
GND
79
24
GND
VDD
80
23
F
VDD
81
22
V
GND
82
21
H
VDD
83
20
VDD
VDD
84
19
GND
VDD
85
18
VDD
VDD
86
17
GND
VDD
87
16
CRC_INS
VDD
88
15
LN_INS
VDD
89
14
GND
VDD
90
13
TRS_INS
GND
91
12
TRS Y/C
VDD
92
11
SRST
VDD
93
10
BP_SC
GND
94
9
RSTLN
GND
95
8
CODE_PROTECT
VDD
96
7
GND
VDD
97
6
BLANK
VDD
98
5
DET_TRS
VDD
99
4
GND
VDD
100
3
VDD
VDD
101
2
GND
VDD
102
1
PCLK_IN
GS1511
TOP
VIEW
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
VDD
GND
DATA_OUT[6]
DATA_OUT[5]
DATA_OUT[4]
DATA_OUT[3]
DATA_OUT[2]
DATA_OUT[1]
DATA_OUT[0]
VDD
GND
DATA_OUT[8]
DATA_OUT[7]
VDD
GND
DATA_OUT[14]
DATA_OUT[13]
DATA_OUT[12]
DATA_OUT[11]
DATA_OUT[10]
DATA_OUT[9]
DATA_OUT[19]
DATA_OUT[18]
DATA_OUT[17]
DATA_OUT[16]
DATA_OUT[15]
GS1511
DATA_IN[19]
DATA_IN[18]
DATA_IN[17]
DATA_IN[16]
DATA_IN[15]
DATA_IN[14]
1. PIN OUT
1.1 PIN ASSIGNMENT
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1.2 PIN DESCRIPTIONS
PIN NUMBER
NAME
TIMING
TYPE
DESCRIPTION
1
PCLK_IN
Synchronous
Input
2, 4, 14, 19, 24,
37, 46, 50, 58,
69, 79, 82, 91,
94, 110, 116,
128
GND
N/A
Ground
Ground. Ground power supply connections.
3, 20, 25, 38, 47,
51, 59, 68, 78,
81, 90, 93, 99,
102, 109, 115,
127
VDD
N/A
Power
Power. Positive power supply connections.
5
DET_TRS
Nonsynchronous
Input
Control Signal Input. Used to enable or disable the detection of
the TRS signals embedded in the video stream. When DET
_TRS is high, the device detects the TRS signals embedded in
the input video stream and uses the detected HVF signals
instead of the external HVF signals. When DET _TRS is low,
TRS detection is disabled. The device uses the external
supplied HVF signals.
6
BLANK
Synchronous
wrt PCLK_IN
Input
Control Signal Input. When BLANK is low, the device sets the
accompanying LUMA and CHROMA data to their appropriate
blanking levels. When BLANK is high, the LUMA and CHROMA
data streams pass through this stage of the device unaltered.
See timing diagram Figure 3.
7, 17, 95
GND
N/A
8
CODE_PROTECT
Nonsynchronous
Input
Control Signal Input. Used to enable or disable re-mapping of
out-of-range words contained in the active portion of the video
signal. When this signal is high, the device re-maps out-ofrange words contained within the active portion of the video
signal into CCIR-601 compliant words. Values between 000-003
are re-mapped to 004. Values between 3FC and 3FF are remapped to 3FB. When this signal is low, out-of-range words in
the active video region pass through the device unaltered.
9
RSTLN
Synchronous
wrt PCLK_IN
Input
Control Signal Input. Line number reset signal which must be
asserted once per frame at the beginning of the frame (for
example, on the falling edge of the F signal). A high to low
transition will reset the line number counter of the device to one
(1). See Figure 2 for timing.
10
BP_SC
Nonsynchronous
Input
Control Signal Input. Used to enable or bypass the SMPTE292M
scrambler and NRZ(I) encoder. When BP_SC is low, the video
stream is scrambled according to SMPTE 292M and NRZ(I)
encoded. When BP_SC is high, the scrambler and NRZ(I)
encoder are by-passed.
11
SRST
Nonsynchronous
Input
Control Signal Input. Used to reset the SMPTE292M scrambler
and NRZI encoder. When SRST is low, the scrambler and
encoder operate normally. A low to high transition on SRST
causes the scrambler and encoder to reset.
12
TRS_Y/C
Nonsynchronous
Input
Control Signal Input. Only used when DET_TRS is high. When
TRS_Y/C is high, the device detects and uses TRS signals
embedded in the LUMA (DATA_IN[19:10]) channel. When
TRS_Y/C is low, the device detects and uses TRS signals
embedded in the CHROMA (DATA_IN[9:0]) channel.
Parallel Data Clock input. 74.25MHz or 74.25/1.001MHz.
GS1511
Ground. This pin must be connected to GND for normal
operation.
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1.2 PIN DESCRIPTIONS (Continued)
NAME
TIMING
TYPE
DESCRIPTION
13
TRS_INS
Nonsynchronous
Input
Control Signal Input. Used to enable or disable insertion of TRS
into the video streams. When TRS_INS is high, the device
inserts SMPTE 292M compliant TRS signals into the input LUMA
and CHROMA data streams based on the supplied HVF
signals. When TRS_INS is low, the device does not insert TRS
signals.
15
LN_INS
Nonsynchronous
Input
Control Signal Input. Used to enable or disable insertion of line
numbers into the video stream. When LN_INS is high, the
device inserts SMPTE 292M compliant line number information
into the LUMA and CHROMA channels. When LN_INS is low,
the device does not insert the line number information into the
LUMA and CHROMA channels. Line number insertion is only
available when user supplied external FVH data is used
(DET_TRS set LOW).
16
CRC_INS
Nonsynchronous
Input
Control Signal Input. Used to enable or disable insertion of
CRCs into the video stream. When CRC_INS is high, the device
calculates and inserts line based CRCs. When CRC_INS is low,
this feature is disabled.
18, 99, 102, 76,
77, 80, 83-89,
92, 96-98, 100,
101
VDD
N/A
21
H
Synchronous
wrt PCLK_IN
Input
Control Signal Input. This signal indicates the Horizontal
blanking period of the input video data stream. The device
inserts HDTV TRS based on the supplied HVF signals. Refer to
Figure 4 for required timing of H relative to LUMA
(DATA_IN[19:10]) and CHROMA (DATA_IN[9:0]).
22
V
Synchronous
wrt PCLK_IN
Input
Control Signal Input. This signal indicates the Vertical blanking
period of the input video data streams. Refer to Figure 4 for
required timing of V relative to LUMA (DATA_IN[19:10]) and
CHROMA (DATA_IN[9:0]).
This pin must be connected to VDD for normal operation.
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GS1511
PIN NUMBER
1.2 PIN DESCRIPTIONS (Continued)
PIN NUMBER
NAME
TIMING
TYPE
DESCRIPTION
23
F
Synchronous
wrt PCLK_IN
Input
26, 27, 28, 29,
NC
N/A
35
TN
N/A
TEST
Test pin. Used for test purposes only. This pin must be
connected to VDD for normal operation.
36
OEN
Nonsynchronous
Input
Control Signal Input. Used to enable the DATA_OUT[19:0]
output bus or set it to a high Z state. When OEN is low, the
DATA_OUT[19:0] bus is enabled. When OEN is high, the
DATA_OUT[19:0] bus is disabled and in a high Z state.
64, 63, 62, 61,
60, 57 56, 55,
54, 53, 52, 49,
48, 45, 44, 43,
42, 41, 40, 39
DATA_OUT[19:0]
Synchronous
wrt PCLK_IN
Outputs
70
TEST
N/A
TEST
Test Pin. Used for test purposes only. This pin must be
connected to GND for normal operation.
103,104,105,
106, 107, 108,
111, 112, 113,
114
DATA_IN [19:10]
Synchronous
wrt PCLK_IN
Input
Input Data Bus. LUMA CHANNEL. DATA_IN [19] is the MSB of
the LUMA input signal (pin 103). DATA_IN [10] is the LSB of the
LUMA input signal (pin 114).
Synchronous
wrt PCLK_IN
Input
CHROMA Input Data Bus. CHROMA CHANNEL DATA_IN [9] is
the MSB of the CHROMA signal (pin 117). DATA_IN [0] is the
LSB of the CHROMA signal (pin 126).
Control Signal Input. This signal indicates the ODD/EVEN field
of the input video data streams. Refer to Figure 4 for required
timing of F relative to LUMA (DATA_IN[19:10]) and CHROMA
(DATA_IN[9:0]). When the input video format is progressive
scan, F should remain low at all times.
GS1511
No Connect. Do not connect these pins.
30-34, 65, 66,
67,
71-75,
117, 118, 119,
120, 121, 122,
123, 124, 125,
126
(LUMA channel)
DATA_IN [9:0]
(CHROMA channel)
Output Data Bus. The device generates a 20 bit wide data
stream running at 74.25 (or 74.25/1.001) MHz. DATA_OUT[19]
is the MSB and DATA_OUT[0] is the LSB.
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2. ELECTRICAL CHARACTERISTICS
2.1 ABSOLUTE MAXIUMUM RATINGS
PARAMETER
VALUE
Supply Voltage
-0.5V to +4.6V
Input Voltage Range (any input)
-0.5V < VIN < 5.5V
GS1511
0°C ≤ TA ≤ 70°C
Operating Temperature Range
-40°C ≤ TS ≤
125°C
Storage Temperature Range
Lead Temperature (soldering 10
seconds)
260°C
2.2 DC ELECTRICAL CHARACTERISTICS
VDD = 3.0 to 3.6V, TA = 0°C to 70°C, unless otherwise shown
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
3.0
3.3
3.6
V
Positive Supply Voltage
VDD
Supply Current
ΙDD
ƒ = 74.25MHz, TA
= 25°C
-
413
480
mA
Input Logic LOW Voltage
VIL
ILEAKAGE < 10µA
-
-
0.8
V
Input Logic HIGH Voltage
VIH
ILEAKAGE < 10µA
2.1
3.3
5.0
V
Output Logic LOW Voltage
VOL
VDD = 3.0 to 3.6V,
IOL= 4mA
-
0.3
0.4
V
Output Logic HIGH Voltage
VOH
VDD = 3.0 to 3.6V,
IOH = -4mA
2.6
-
-
V
NOTES
2.3 AC ELECTRICAL CHARACTERISTICS
VDD = 3.0 to 3.6V, TA = 0°C to 70°C, unless otherwise shown
MIN
TYP
MAX
UNITS
Clock Input Frequency
PARAMETER
SYMBOL
FHSCI
CONDITIONS
-
74.25
80
MHz
Input Data Setup Time
tSU
2.5
-
-
ns
50% levels
Input Data Hold Time
tIH
1.5
-
-
ns
50% levels
Input Clock Duty Cycle
40
-
60
%
Output Data Hold Time
tOH
With 15pF load
2.0
-
-
ns
Output Enable Time
toen
With 15pF load
-
-
8
ns
Output Disable Time
todis
With 15pF load
-
-
10
ns
tOD
With 15pF load
-
-
10
ns
With 15pF load
-
-
2.75
ns
Output Data Delay Time
Output Data Rise/Fall Time
NOTES
Also supports 74.25/
1.001MHz
20% to 80% levels
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3. DETAILED DESCRIPTION
3.2 INPUT BLANKER
Data words entering the GS1511 can be dynamically set to
Luma and Chroma blanking levels if desired as shown in
Figure 3. Blanking is applied to both the LUMA and
CHROMA channels simultaneously.
3.1 DATA INPUT AND OUTPUTS
Data enters and exits the device synchronous to the rising
edge of PCLK_IN as shown in Figure 1.
GS1511
PCLK_IN
DATA_IN
DATA
DATA
DATA
DATA_OUT
tSU
DATA
DATA
DATA
DATA
tIH
tOH
tOD
Fig. 1 Synchronous I/O Timing
PCLK_IN
DATA_IN[19:0]
3FF
000
n Frames
000
XYZ
(EAV ID)
LN0
LN1
Line#1 Inserted
Here
EAV For Line#1
RSTLN
Transistion From Low To High Can Happen at Any Point
Fig. 2 RSTLN Timing
PCLK_IN
WORD
X
DATA_IN[19:0]
WORD
X+1
WORD
X+2
WORD
X+3
WORD
X+4
WORD
X+6
WORD
X+7
WORD
X+8
Data To Be Blanked
BLANK
Fig. 3 Timing of Dynamic Data Blanking
PCLK_IN
DATA_IN[19:10]
(LUMA)
3FF
000
000
XYZ
(EAV ID)
YLN 0
3FF
000
000
XYZ
(SAV ID)
DATA_IN[9:0]
(CHROMA)
3FF
000
000
XYZ
(EAV ID)
CLN0
3FF
000
000
XYZ
(SAV ID)
H
V
F
Fig. 4 HVF Input Timing
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4. REFERENCES
Compliant with SMPTE 292M.
5. PACKAGE & ORDERING INFORMATION
5.1 PACKAGE DIMENSIONS
GS1511
23.20 ±0.25
20.0 ±0.10
18.50 REF
12 TYP
0.75 MIN
17.20 ±0.25
12.50 REF
0 -7
0.30 MAX RADIUS
14.0 ±0.10
0-7
0.13 MIN.
RADIUS
0.88
±0.15
1.6
REF
3.00 MAX
128 pin MQFP
0.50 BSC
0.27 ±0.08
All dimensions in millimetres
2.80 ±0.25
5.2 ORDERING INFORMATION
PART NUMBER
PACKAGE
TEMPERATURE RANGE
Pb-FREE AND GREEN
GS1511-CQR
128 pin MQFP
0°C to 70°C
No
GS1511-CQRE3
128 pin MQFP
0°C to 70°C
Yes
CAUTION
ELECTROSTATIC
SENSITIVE DEVICES
DO NOT OPEN PACKAGES OR HANDLE
EXCEPT AT A STATIC-FREE WORKSTATION
REVISION NOTES:
Added Pb-free and green information.
DOCUMENT IDENTIFICATION
DATA SHEET
The product is in production. Gennum reserves the right to make
changes at any time to improve reliability, function or design, in order to
provide the best product possible.
GENNUM CORPORATION
MAILING ADDRESS:
P.O. Box 489, Stn. A, Burlington, Ontario, Canada L7R 3Y3
Tel. +1 (905) 632-2996 Fax. +1 (905) 632-5946
SHIPPING ADDRESS:
970 Fraser Drive, Burlington, Ontario, Canada L7L 5P5
For latest product information, visit www.gennum.com
GENNUM JAPAN CORPORATION
Shinjuku Green Tower Building 27F 6-14-1, Nishi Shinjuku Shinjuku-ku,
Tokyo 160-0023 Japan
Tel: +81 (03) 3349-5501 Fax: +81 (03) 3349-5505
GENNUM UK LIMITED
25 Long Garden Walk, Farnham, Surrey, England GU9 7HX
Tel. +44 (0)1252 747 000 Fax +44 (0)1252 726 523
Gennum Corporation assumes no responsibility for the use of any circuits described herein and makes no representations that they are free from patent infringement.
© Copyright May 2002 Gennum Corporation. All rights reserved. Printed in Canada.
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