G2996 Global Mixed-mode Technology Inc. DDR I/II Termination Regulator Features General Description The G2996 is a linear regulator designed to meet the JEDEC SSTL-18 ,SSTL-2 and SSTL-3 (Series Stub Termination Logic) specifications for termination of DDR-SDRAM. It contains a high-speed operational amplifier that provides excellent response to the load transients. This device can deliver 1.5A/0.9A continuous current and transient peaks up to 3A/1.8A in the application as required for DDRI/II-SDRAM termination. With an independent VSENSE pin, the G2996 can provide superior load regulation. The G2996 provides a VREF output as the reference for the applications of the chipset and DIMMs. Operation Supply Voltage: 1.6V to 5.5V Low Supply Current: 280µA @ 2.5V Low Output Offset Source and Sink Current Low External Component Count No Inductor Required No external Resistors Required Thermal Shutdown Protection Suspend to RAM (STR) function SOP-8 with Power-Pad package Applications DDR-SDRAM Termination Voltage DDR-I / DDR-II Termination Voltage SSTL-2 SSTL-3 The G2996 can easily provide the accurate VTT and VREF voltages without external resistors that PCB areas can be reduced. The quiescent current is as low as 280µA @ 2.5V. So the power consumption can meet the low power consumption applications. The G2996 also has an active low shutdown ( SD ) pin that provides Suspend to RAM (STR) functionality. When SD is pulled low, the VTT output will be tri-state providing a high impendence, but VREF will remain active. A power saving advantage can be obtained in this mode through lowering the quiescent current to180µA @ 2.5V. Ordering Information ORDER NUMBER ORDER NUMBER (Pb free) MARKING TEMP. RANGE PACKAGE G2996P1U G2996F1U G2996P1Uf G2996F1Uf G2996 G2996 -40°C to 85°C -40°C to 85°C SOP-8 SOP-8 (FD) Note: P1:SOP-8 U: Tape & Reel F1:SOP-8(FD) (FD): Thermal Pad Pin Configuration Typical Application Circuit G2996 GND 8 1 VTT SD 2 7 PVIN VSENSE 3 6 AVIN VREF 4 5 SD SD Thermal Pad VREF VDD=2.5V AVIN 47µF + VREF=1.25V 0.01µF VSENSE PVIN VDDQ + VDDQ VDDQ=2.5V VTT GND VTT=1.25V + 220µF SOP-8 Ver: 2.3 May 16, 2006 TEL: 886-3-5788833 http://www.gmt.com.tw 1 G2996 Global Mixed-mode Technology Inc. Absolute Maximum Ratings Recommend Operation Range (1) Supply Voltage PVIN, AVIN, VDDQ to GND . . . . . . . . . . . -0.3V to +6V Operating Ambient Temperature Range TA . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +125°C Maximum Junction Temperature, TJ . . . . . . . . ..150°C Storage Temperature Range, TSTG . . -65°C to+150°C Reflow Temperature (soldering, 10 sec) . . . . . .260°C Electrostatic Discharge, VESD Human body mode . . . . . . . . . . . . . . . . . . . . .2000V(2) Thermal Resistance Junction to Ambient, (θJA) SOP-8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .130°C/W SOP-8 (FD) . . . . . . . . . . . . . . . . . . . . . . . . 110°C/W(3) SOP-8 (FD) . . . . . . . . . . . . . . . . . . . . . . . . . 50°C/W(4) SOP-8 (FD) . . . . . . . . . . . . . . . . . . . . . . . . . 41°C/W(5) Thermal Resistance Junction to Case, (θJC) SOP-8 (FD) . . . . . . . . . . . . . . . . . . . . . . . . . ..12°C/W Operating Ambient Temperature Range TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C AVIN to GND . . . . . . . . . . . . . . . . . . . . . 1.6V to +5.5V PVIN, SD, VDDQ to GND . . . . . . . . . . . . 1.6V to AVIN Note: (1) : Absolute maximum rating indicates limits beyond which damage to the device may occurs. (2) : Human body model : C = 100pF, R = 1500Ω, 3 positive pulses plus 3 negative pulses : The package is placed on a 2-layer PCB (1oz/1oz) with minimum footprint. (3) (4) : The package is placed on a 2-layer PCB (2oz/2oz) with 6 vias. Please refer the evaluation board manual (EV2996-10) for pcb layout. (5) : The package is placed on a 2-layer PCB (2oz/2oz) with 6 vias. The airflow is used. Please refer the evaluation board manual (EV2996-10) for pcb layout. Electrical Characteristics Specifications with standard typeface are for TA=25°C. unless otherwise specified, AVIN=PVIN=2.5V, VDDQ=2.5V for DDR I, AVIN=PVIN=VDDQ=1.8V for DDRII. PARAMETER SYMBOL VREF Voltage VREF VREF Voltage VREF VREF Output impendence ZREF VTT Output voltage VTT Output voltage VTT VTT CONDITION VDDQ=1.7V VDDQ=1.8V VDDQ=1.9V VDDQ=2.3V VDDQ=2.5V VDDQ=2.7V IREF =-30µA to + 30µA IOUT=0A VDDQ=1.7V VDDQ=1.8V VDDQ=1.9V IOUT=±0.9A VDDQ=1.7V VDDQ=1.8V VDDQ=1.9V IOUT=0A VDDQ=2.3V VDDQ=2.5V VDDQ=2.7V IOUT=±1.5A VDDQ=2.3V VDDQ=2.5V VDDQ=2.7V Ver: 2.3 May 16, 2006 MIN TYP MAX UNIT 0.810 0.860 0.910 1.11 1.21 1.31 --- 0.849 0.898 0.949 1.145 1.245 1.345 1.15 0.890 0.940 0.990 1.19 1.29 1.39 --- V V V V V V kΩ 0.810 0.860 0.910 0.847 0.896 0.947 0.890 0.940 0.990 V V V 0.810 0.860 0.910 0.847 0.896 0.947 0.890 0.940 0.990 V V V 1.11 1.21 1.31 1.152 1.252 1.352 1.19 1.29 1.39 V V V 1.11 1.21 1.31 1.152 1.252 1.352 1.19 1.29 1.39 V V V TEL: 886-3-5788833 http://www.gmt.com.tw 2 G2996 Global Mixed-mode Technology Inc. Electrical Characteristics Specifications with standard typeface are for TA=25°C. unless otherwise specified, AVIN=PVIN=2.5V, VDDQ=2.5V for DDR I, AVIN=PVIN=VDDQ=1.8V for DDRII. PARAMETER SYMBOL MIN TYP MAX UNIT IOUT=0A IOUT=-0.9A IOUT=+0.9A IOUT=0A IOUT=-1.5A IOUT=+1.5A CONDITION -40 -40 -40 0 0 0 40 40 40 mV mV mV -40 -40 -40 0 0 0 40 40 40 mV mV mV 280 100 500 --- µA kΩ VTT Output Voltage Offset (VREF- VTT) VosVtt VTT Output Voltage Offset (VREF- VTT) VosVtt Quiescent Current VDDQ input Impedence IQ ZVDDQ IOUT=0A ----- Quiescent Current in shutdown ISD SD =0 --- 180 300 µA Shutdown leakage current VSENSE input current VTT leakage current in shutdown IQ_SD ISENSE IV ----- 0.01 20 ----- µA nA --- 0.01 --- µA Minimum Shutdown High Level VIH 1.6 --- --- V Maximum Shutdown Low Level Thermal Shutdown VIL TSD ----- --150 0.8 --- V °C Thermal Shutdown Hystersis THsy --- 25 --- °C SD =0, VTT =1.25V Ver: 2.3 May 16, 2006 TEL: 886-3-5788833 http://www.gmt.com.tw 3 Global Mixed-mode Technology Inc. G2996 Typical Performance Characteristics AVIN=2.5V, PVIN=2.5V, VDDQ=2.5V, CAVIN=0.1µF/Ceramic X7R/0603/6.3V/TDK, CPVIN=68µF/6.3V POSCAP Series/SANYO, CVTT=330µF*2/6.3V POSCAP Series/SANYO, TA=25°C, unless otherwise noted. ILoad=0.5A Transient (Sinking) ILoad=0.5A Transient (Sourcing) ILoad=1A Transient (Sinking) ILoad=1A Transient (Sourcing) ILoad=1.5A Transient (Sinking) ILoad=1.5A Transient (Sourcing) Ver: 2.3 May 16, 2006 TEL: 886-3-5788833 http://www.gmt.com.tw 4 G2996 Global Mixed-mode Technology Inc. Typical Performance Characteristics AVIN=2.5V, PVIN=2.5V, VDDQ=2.5V, CAVIN=0.1µF, CPVIN=47µF, CVREF=0.01µF, VSD=2.5V, CVTT=220µF, TA=25°C, unless otherwise noted. IQ vs AVIN 270 150 250 140 230 IQ(µA) IQ(µA) IQ vs AVIN in SD 160 130 210 120 190 110 170 100 150 2 2.5 3 3.5 4 4.5 5 5.5 2 2.5 3 3.5 AVIN(V) 4 4.5 5 5.5 AVIN(V) VREF vs IREF VIH and VIL 2 1.3 1.8 1.28 IO=200m 1.26 VIH VREF(V) VSD(V) 1.6 1.4 VIL 1.24 1.2 1.22 1 1.2 0.8 1.18 2 2.5 3 3.5 4 4.5 5 5.5 -30 -20 -10 0 10 20 30 IREF(µA) AVIN(V) VTT vs IOUT Temperature VREF vs VDDQ 3 1.252 2.5 1.248 1.244 VTT(V) VREF(V) 2 1.5 0°C 1.24 1 25°C 1.236 0.5 85°C 0 2 2.5 3 3.5 4 4.5 5 1.232 -100 5.5 VDDQ(V) -75 -50 -25 0 25 50 75 100 IOUT(mA) Ver: 2.3 May 16, 2006 TEL: 886-3-5788833 http://www.gmt.com.tw 5 G2996 Global Mixed-mode Technology Inc. Typical Performance Characteristics (continued) AVIN=2.5V, PVIN=2.5V, VDDQ=2.5V, CAVIN=0.1µF, CPVIN=47µF, CVREF=0.01µF, VSD=2.5V, CVTT=220µF, TA=25°C, unless otherwise noted. VTT vs VDDQ IQ vs AVIN in SD Temperature 3 160 2.5 150 2 140 IQ(µA) VTT(V) 25° 1.5 85° 130 0°C 1 120 0.5 110 0 100 2 2.5 3 3.5 4 4.5 5 5.5 2 2.5 3 3.5 4 4.5 5 5.5 VDDQ(V) AVIN(V) IQ vs AVIN Temperature Maximum Sourcing Current vs AVIN (VDDQ=2.5V, PVIN=1.8V) 270 1.4 25°C IO=200m 1.2 250 Output Current(A) 85°C IQ(µA) 230 0°C 210 190 170 1 0.8 0.6 0.4 0.2 150 0 2 2.5 3 3.5 4 4.5 5 5.5 2 2.5 3 3.5 4 4.5 5 5.5 AVIN(V) AVIN(V) Maximum Sourcing Current vs AVIN (VDDQ=2.5V, PVIN=2.5V) Maximum Sourcing Current vs AVIN (VDDQ=2.5V, PVIN=3.3V) 1.8 3 1.7 Output Current(A) Output Current(A) 2.8 1.6 1.5 1.4 1.3 2.6 2.4 2.2 1.2 2 1.1 2 2.5 3 3.5 4 4.5 5 2 5.5 AVIN(V) 2.5 3 3.5 4 4.5 5 5.5 AVIN(V) Ver: 2.3 May 16, 2006 TEL: 886-3-5788833 http://www.gmt.com.tw 6 G2996 Global Mixed-mode Technology Inc. Typical Performance Characteristics (continued) AVIN=2.5V, PVIN=2.5V, VDDQ=2.5V, CAVIN=0.1µF, CPVIN=47µF, CVREF=0.01µF, VSD=2.5V, CVTT=220µF, TA=25°C, unless otherwise noted. Maximum Sourcing Current vs AVIN (VDDQ=1.8V, PVIN=1.8V) 3 1.4 2.8 1.2 2.6 Output Current(A) Output Current(A) Maximum Sinking Current vs AVIN (VDDQ=2.5V) 2.4 2.2 2 1.8 1 0.8 0.6 0.4 0.2 1.6 0 1.4 2 2.5 3 3.5 4 4.5 5 2 5.5 2.5 3 3.5 4 4.5 5 5.5 AVIN(V) AVIN(V) Maximum Sourcing Current vs AVIN (VDDQ=1.8V, PVIN=3.3V) Maximum Sinking Current vs AVIN (VDDQ=1.8V) 2.8 3 IO=200m 2.6 2.8 Output Current(A) Output Current(A) 2.4 2.2 2 1.8 1.6 1.4 2.6 2.4 2.2 1.2 2 1 2 2.5 3 3.5 4 4.5 5 2 5.5 AVIN(V) 3 3.5 4 4.5 5 5.5 AVIN(V) Recommended Minimum Footprint VOSVTT vs Temperature(VDDQ=2.5V) SOP-8, SOP-8 (FD) 30 Sourcing 1.5A 20 VOSVTT(mV) 2.5 10 No Load 0 -10 Sinking 1.5A -20 -30 0 25 50 75 100 125 Temperature(°C) Ver: 2.3 May 16, 2006 TEL: 886-3-5788833 http://www.gmt.com.tw 7 G2996 Global Mixed-mode Technology Inc. Pin Description NUMBER NAME 1 2 GND FUNCTION 3 4 VSENSE VREF 5 6 7 VDDQ AVIN PVIN 8 VTT Ground Active low shutdown control pin SD Feedback pin for regulating VTT Buffered output that is a reference output of VDDQ/2 Power Input for internal reference Analog input pin Power input pin Output voltage for connection to termination resistors, equal to VDDQ/2 Block Diagram VDDQ SD AVIN PVIN 50k VREF + - + VTT - 50k VSENSE GND Description VTT VDD The G2996 is a linear bus termination regulator designed to meet the JEDEC SSTL-2 and SSTL-3 (Series Stub Termination Logic) specifications for termination of DDR-SDRAM. The output, VTT, is capable of sinking and sourcing current while regulating the output voltage equal to VDDQ/2. The G2996 is designed to maintain the excellent load regulation and with fast response time to minimum the transition preventing shoot-through. The G2996 also incorporates two distinct power rails that separates the analog circuitry (AVIN) from the power output stage (PVIN). This power rails split can be utilized to reduce the internal power dissipation. And this also permits G2996 to provide a termination solution for the next generation of DDR-SDRAM (DDR II). RT RS MENORY CHIPSET VREF Figure 1. SSTL-Termination Scheme AVIN, PVIN AVIN and PVIN are two independent input supply pins for the G2996. AVIN is used to supply all the internal analog circuits. PVIN is only used to supply the output stage to create the regulated VTT. To keep the regulation successfully, AVIN should be equal to or larger than PVIN. Using a higher PVIN voltage will produce a larger sourcing capability from VTT. But the internal power loss will also increase and then the heat increases. If the junction temperature exceeds the thermal shutdown threshold than the G2996 will enter the shutdown state that is the same as manual shutdown, where VTT is tri-state and VREF remains active. For SSTL-2 applications, the AVIN and PVIN can be short together at 2.5V to minimize the PCB complexity and to reduce the bypassing capacitors for the two supply pins separately. Series Stub Termination Logic (SSTL) was created to improve signal integrity of the data transmission across the memory bus. This termination scheme is essential to prevent data error from signal reflections while transmitting at high frequencies encountered with DDR-SDRAM. The most common form of termination is Class II single parallel termination. This involves one RS series resistor from the chipset to the memory and one RT termination resistor, both 25Ω typically. The resistors can be changed to scale the current requirements from the G2996. This implementation can be seen below in Figure 1. Ver: 2.3 May 16, 2006 TEL: 886-3-5788833 http://www.gmt.com.tw 8 Global Mixed-mode Technology Inc. VDDQ A voltage divider of two 50kΩ is connected between VDDQ and ground, to create the internal reference voltage (VDDQ/2). This guarantees that VTT will track VDDQ/2 precisely. The optimal implementation of VDDQ is as a remote sensing. This can be achieved by connecting VDDQ directly to the 2.5V rail (SSTL-2 applications) at the DIMM instead of AVIN and PVIN. This will ensure that the reference voltage tracks the DDR memory rails precisely without a large voltage drop from the power lines. G2996 PCB is strongly recommended to have a better thermal performance. The RDS of MOS will increase when the junction temperature increases. If the heat is not dealt with well, the maximum output current will be degraded. When the temperature exceeds the junction temperature, the thermal shutdown protection is activated. That will drive the VTT output into tri-state until the temperature returns below the hysteretic trigger point. Capacitors The G2996 does not require the capacitors for input stability, but it is recommended for improving the performance during large load transition to prevent the input power rail from dropping, especially for PVIN. The input capacitor for PVIN should be as close as possible. The typical recommended value is 50µF for AL electrolytic capacitors, 10µF with X5R for the ceramic capacitors. To prevent the excessive noise coupling into this device, an additional 0.1µF ceramic capacitor can be placed on the AVIN power rail for the better performance. Vsense The VSENSE pin is the feedback sensing pin of the operation amplifier which regulates the VTT voltage. In most motherboard applications, the termination resistors will connect VTT in a long plane. If using the remote sensing pin – VSENSE to the middle of the bus, the significant long-trace IR drop resulting in a termination voltage which is lower at one end than the other can be avoided. This will provide a better distribution across the entire termination bus. If the remote load regulation is not used, the VSENSE pin must still be connected to VTT for correct regulation. Care should be taken when a long VSENSE trace is implemented in close proximity to the memory. Noise pickup in the VSENSE trace can cause problems with precise regulation of VTT. A small 0.1µF ceramic capacitor placed next to the VSENSE pin can help to filter any high frequency signals and preventing errors. The output capacitor of the G2996 is suggested to use the capacitors with low ESR. Using the capacitors with low ESR (as ceramic, OS-CON, tantalum) will have the better transition performance which is with smaller voltage drop when the peak current occurring at the transition. As a general recommendation the output capacitor should be sized above 220µF with the low ESR for SSTL applications with DDR-SDRAM. VREF VREF provides a buffered output of the internal reference voltage (VDDQ/2). It can support the reference voltage of Northbridge chipset and memory. This output remains active during the shutdown state and thermal shutdown events to support the suspend to RAM (STR) functionality. For better performance, using an output bypass capacitor close this pin is more helpful for the noise. A ceramic capacitor in the range of 0.1µF to 0.01µF is recommended. Thermal Dissipation When the current is sinking to or sourcing from VTT, the G2996 will generate internal power dissipation resulting in the heat. Care should be taken to prevent the device from damages caused by the junction temperature exceeding the maximum rating. The maximum allowable internal temperature rise (TRMAX) can be calculated under the given maximum ambient temperature (TAMAX) of the application and the maximum allowable junction temperature (TJMAX). VTT VTT is the regulated output that is used to terminate the bus resistors of DDR-SDRAM. It can precisely track the VDDQ/2 voltage with the sinking and sourcing current capability. The G2996 is designed to deliver 1.5A continuous current and peak current up to 3A with a fast transient response @ 2.5V supply rail. The maximum continuous current sourcing from VTT is a function of PVIN. Using a higher PVIN will increase the source current from VTT, but it also increase the internal power dissipation and reduce the efficiency. Although the G2996 can deliver the larger current, care should be taken for the thermal dissipation when larger current is required. The G2996 is packaged with Power-Pad to increase the power dissipation capability. When driving larger current, the larger heat-sink in the TRMAX= TJMAX - TAMAX From this equation, the maximum power dissipation (PDMAX) of the G2996 can be calculated: PDMAX = TRMAX /θJA θJA of the G2996 will be dependent on several variables: the packages used, the thickness and size of the copper, the number of vias and the airflow. In the package, the G2996 use the SOP-8 with Power-PAD to improve the θJA . If the layout of the PCB can put a larger size of copper to contact the Power-PAD of this device, the θJA will be further improved. The better θJA is not only protecting the device well, but also increasing the maximum current capability at the same ambient temperature. Ver: 2.3 May 16, 2006 TEL: 886-3-5788833 http://www.gmt.com.tw 9 G2996 Global Mixed-mode Technology Inc. Typical Application Circuits There are several application circuits shown in Figure 2 through 8 to illustrate some of the possible configurations of the G2996. Figure 2~4 are the SSTL-2 applications. For the majority of applications that imple- ment the SSTL-2 termination scheme, it is recommended to connect all the input rails to 2.5V rail, as seen in Figure 2. This provides an optimal trade-off between power dissipation and component count. SD SD VREF CREF VDDQ=2.5V VDDQ VDD=2.5V AVIN VSENSE PVIN VTT CIN + VREF=1.25V + VTT=1.25V + GND COUT Figure 2. Recommended SSTL-2 Implementation In Figure 3, the power rails are split. The power rail of the output stage (PVIN) can be as low as 1.8V, the power rail of the analog circuit (AVIN) is operated above 2V. The lower output stage power rail can lower the internal power dissipation when sourcing from the device and improve the efficiency, but the disadvantage is the maximum continuous current sourcing from VTT is reduced. This configuration is applied when the power dissipation and efficiency are concerned. SD SD VREF VDDQ=2.5V AVIN=1.8V or 5.5V AVIN VSENSE PVIN=1.8V PVIN VTT CIN + VREF=1.25V + CREF VDDQ VTT=1.25V + GND COUT Figure 3. Lower Power Dissipation SSTL-2 Implementation In Figure 4, the power rail of the output stage (PVIN) is connected to 3.3V to increase the maximum continuous current sourcing from VTT. AVIN should be always equal to or larger than PVIN. This configuration can increase the source capability of this device, but the power dissipation increases at the same time. It should be more careful to prevent the junction temperature from exceeding the maximum rating. Because of this risk, it is not recommended to supply the output stage power rail (PVIN) with a voltage higher than a nominal 3.3V rail. SD SD VREF VDDQ=2.5V VDDQ AVIN=3.3V or 5V AVIN VSENSE PVIN VTT PVIN=3.3V CIN + GND + VREF=1.25V CREF VTT=1.25V + COUT Figure 4. SSTL-2 Implementation with higher voltage rails Ver: 2.3 May 16, 2006 TEL: 886-3-5788833 http://www.gmt.com.tw 10 G2996 Global Mixed-mode Technology Inc. In Figure 5 & 6, they are the application configurations of DDR-II SDRAM bus terminations. Figure 5 is the typical application scheme of DDR-II SDRAM. With the separate VDDQ pin and an internal resistor divider, it is possible to use the G2996 in applications utilizing DDR-II memory. Figure 6 is used to increase the driving capability. The risk is the same as figure 4. SD SD VREF VDDQ=1.8V VDDQ AVIN=1.8V or 5.5V AVIN VSENSE PVIN=1.8V PVIN VTT CIN + + VREF=0.9V CREF VTT=0.9V + GND COUT Figure 5. Recommended DDR-II Termination SD SD VREF VDDQ=1.8V VDDQ AVIN=3.3V or 5.5V AVIN VSENSE PVIN=3.3V PVIN VTT CIN + + VTT=0.9V + GND VREF=0.9V CREF COUT Figure 6. DDR-II Termination with higher voltage rails Figure 7 & 8 are used to scale the VTT to the wanted value when the standard voltages of SSTL-2 do not meet the requirements. Using R1 & R2, figure 7 can shift VTT up to VDDQ/2 * (1+R1/R2) and figure 8 can shift VTT down to VDDQ/2 * (1-R1/R2). VDDQ VDDQ VDD AVIN PVIN CIN + VTT VTT VSENSE R1 + COUT R2 GND Figure 7. Increasing VTT by Level Shifting R2 VDDQ VDDQ VDD AVIN VSENSE R1 PVIN VTT VTT + CIN + GND COUT Figure 8. Decreasing VTT by Level Shifting Ver: 2.3 May 16, 2006 TEL: 886-3-5788833 http://www.gmt.com.tw 11 G2996 Global Mixed-mode Technology Inc. Package Information C E H L D θ 7 ° (4X) A2 A A1 y e B SOP-8 Package Note: 1. Package body sizes exclude mold flash and gate burrs 2. Dimension L is measured in gage plane 3. Tolerance 0.10mm unless otherwise specified 4. Controlling dimension is millimeter converted inch dimensions are not necessarily exact. 5. Followed from JEDEC MS-012 SYMBOL MIN. DIMENSION IN MM NOM. MAX. MIN. DIMENSION IN INCH NOM. MAX. A 1.35 1.60 1.75 0.053 0.063 0.069 A1 A2 0.10 ----- ----1.45 0.25 ----- 0.004 ----- ----0.057 0.010 ----- B C D E e 0.33 0.19 4.80 3.80 ----- ----------------1.27 0.51 0.25 5.00 4.00 ----- 0.013 0.007 0.189 0.150 ----- ----------------0.050 0.020 0.010 0.197 0.157 ----- H L 5.80 0.40 --------- 6.20 1.27 0.228 0.016 --------- 0.244 0.050 y θ ----- ----- 0.10 ----- ----- 0.004 0° ----- 8° 0° ----- 8° Ver: 2.3 May 16, 2006 TEL: 886-3-5788833 http://www.gmt.com.tw 12 G2996 Global Mixed-mode Technology Inc. C E1 E H D1 L D θ 7 °(4X) A2 A A1 y e B SOP- 8 (FD) Package Note: 1. Package body sizes exclude mold flash and gate burrs 2. Dimension L is measured in gage plane 3. Tolerance 0.10mm unless otherwise specified 4. Controlling dimension is millimeter converted inch dimensions are not necessarily exact. 5. Followed from JEDEC MS-012 MIN. DIMENSION IN MM NOM. MAX. MIN. DIMENSION IN INCH NOM. A 1.45 1.50 1.55 0.057 0.059 0.061 A1 0.00 ----- 0.10 0.000 ----- 0.004 A2 B C D E e H ----0.33 0.19 4.80 3.80 ----5.80 1.45 ----------------1.27 ----- ----0.51 0.25 5.00 4.00 ----6.20 ----0.013 0.007 0.189 0.150 ----0.228 0.057 ----------------0.050 ----- ----0.020 0.010 0.197 0.157 ----0.244 L 0.40 ----- 1.27 0.016 ----- 0.050 y θ ----- ----- 0.10 ----- ----- 0.004 0° 2.22 2.60 ------------- 8° 2.60 2.98 0° 0.087 0.102 ------------- 8° 0.102 0.117 SYMBOL D1 E1 MAX. Taping Specification PACKAGE Q’TY/REEL SOP-8 SOP-8 (FD) 2,500 ea 2,500 ea F e e d D ir e c tio n T y p ic a l S O P P a c k a g e O r ie n ta tio n GMT Inc. does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and GMT Inc. reserves the right at any time without notice to change said circuitry and specifications. Ver: 2.3 May 16, 2006 TEL: 886-3-5788833 http://www.gmt.com.tw 13