Agilent HCPL-0708 High Speed CMOS Optocoupler Data Sheet Description Available in SO-8 package, the HCPL-0708 optocoupler utilizes the latest CMOS IC technology to achieve outstanding performance with very low power consumption. Basic building blocks of the HCPL- 0708 are a high speed LED and a CMOS detector IC. The detector incorporates an integrated photodiode, a high-speed transimpedance amplifier, and a voltage comparator with an output driver. Functional Diagram NC 1 8 VDD ANODE 2 7 NC CATHODE 3 6 VO NC 4 5 GND TRUTH TABLE LED VO, OUTPUT OFF ON H L *A 0.1 µF bypass capacitor must be connected between pins 5 and 8. Features • +5 V CMOS compatibility • 15 ns typical pulse width distortion • 30 ns max. pulse width distortion • 40 ns max. propagation delay skew • High speed: 15 MBd • 60 ns max. propagation delay • 10 kV/µs minimum common mode rejection • –40 to 100°C temperature range • Safety and regulatory approvals pending – UL recognized 2500 V rms for 1 min. per UL 1577 for HCPL-0708 – CSA component acceptance Notice #5 – VDE 0884 (TUV) approved for HCPL-0708 Option 060 Applications • Scan drive in PDP • Digital field bus isolation: DeviceNet, SDS, Profibus • Multiplexed data transmission • Computer peripheral interface • Microprocessor system interface • DC/DC converter CAUTION: It is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/or degradation which may be induced by ESD. Ordering Information Specify Part Number followed by Option Number (if desired) Example HCPL-0708#XXX 060 = VDE0884 Option. 500 = Tape and Reel Packaging Option. Package Outline Drawing HCPL-0708 (Small Outline SO-8 Package) 8 7 6 5 5.842 ± 0.203 (0.236 ± 0.008) XXX YWW 3.937 ± 0.127 (0.155 ± 0.005) TYPE NUMBER (LAST 3 DIGITS) PIN 1 ONE 2 3 0.381 ± 0.076 (0.016 ± 0.003) DATE CODE 4 1.270 BSG (0.050) 5.080 ± 0.005 (0.200 ± 0.005) 3.175 ± 0.127 (0.125 ± 0.005) 7° 45° X 0.432 (0.017) 0.228 ± 0.025 (0.009 ± 0.001) 1.524 (0.060) 0.152 ± 0.051 (0.006 ± 0.002) 0.305 MIN. (0.012) DIMENSIONS IN MILLIMETERS AND (INCHES). LEAD COPLANARITY = 0.10 mm (0.004 INCHES). *OPTION 500 NOT MARKED. 2 Solder Reflow Thermal Profile 300 TEMPERATURE (°C) PREHEATING RATE 3°C + 1°C/–0.5°C/SEC. REFLOW HEATING RATE 2.5°C ± 0.5°C/SEC. PEAK TEMP. 245°C PEAK TEMP. 240°C PEAK TEMP. 230°C 200 2.5°C ± 0.5°C/SEC. 30 SEC. 160°C 150°C 140°C SOLDERING TIME 200°C 30 SEC. 3°C + 1°C/–0.5°C 100 PREHEATING TIME 150°C, 90 + 30 SEC. 50 SEC. TIGHT TYPICAL LOOSE ROOM TEMPERATURE 0 0 50 100 150 200 250 TIME (SECONDS) Regulatory Information The HCPL-0708 has been approved by the following organizations: CSA Approved under CSA Component Acceptance Notice #5, File CA88324. UL Recognized under UL 1577, component recognition program, File E55361. VDE Approved according to VDE 0884/06.92, File 6591-23-4880-1005. Insulation and Safety Related Specifications Parameter Symbol Minimum External Air L(I01) Gap (Clearance) Minimum External L(I02) Tracking (Creepage) Minimum Internal Plastic Gap (Internal Clearance) Tracking Resistance (Comparative Tracking Index) CTI Isolation Group All Agilent data sheets report the creepage and clearance inherent to the optocoupler component itself. These dimensions are needed as a starting point for the equipment designer when determining the circuit insulation requirements. However, once mounted on a printed circuit 3 Value 4.9 Units mm 4.8 mm 0.08 mm ≥175 Volts IIIa TUV Approved according to VDE 0884/06.92, Certificate R9650938. Conditions Measured from input terminals to output terminals, shortest distance through air. Measured from input terminals to output terminals, shortest distance path along body. Insulation thickness between emitter and detector; also known as distance through insulation. DIN IEC 112/VDE 0303 Part 1 Material Group (DIN VDE 0110, 1/89, Table 1) board, minimum creepage and clearance requirements must be met as specified for individual equipment standards. For creepage, the shortest distance path along the surface of a printed circuit board between the solder fillets of the input and output leads must be considered. There are recommended techniques such as grooves and ribs which may be used on a printed circuit board to achieve desired creepage and clearances. Creepage and clearance distances will also change depending on factors such as pollution degree and insulation level. VDE 0884 Insulation Related Characteristics (Option 060) Description Installation classification per DIN VDE 0110/1.89, Table 1 for rated mains voltage ≤150 V rms for rated mains voltage ≤300 V rms for rated mains voltage ≤450 V rms Climatic Classification Pollution Degree (DIN VDE 0110/1.89) Maximum Working Insulation Voltage Input to Output Test Voltage, Method b† VIORM x 1.875 = VPR, 100% Production Test with tm = 1 sec, Partial Discharge < 5 pC Input to Output Test Voltage, Method a† VIORM x 1.5 = VPR, Type and Sample Test, tm = 60 sec, Partial Discharge < 5 pC Highest Allowable Overvoltage† (Transient Overvoltage, tini = 10 sec) Safety Limiting Values (Maximum values allowed in the event of a failure, also see Thermal Derating curve, Figure 11.) Case Temperature Input Current Output Power Insulation Resistance at TS, V10 = 500 V Symbol HCPL-0708 Option 060 Units I-IV I-III VIORM VPR 55/85/21 2 560 1050 V peak V peak VPR 840 V peak VIOTM 4000 V peak TS IS,INPUT PS,OUTPUT RIO 150 150 600 ≥109 °C mA mW Ω †Refer to the front of the optocoupler section of the Isolation and Control Component Designer’s Catalog, under Product Safety Regulations section (VDE 0884), for a detailed description. Note: These optocouplers are suitable for “safe electrical isolation” only within the safety limit data. Maintenance of the safety data shall be ensured by means of protective circuits. Note: The surface mount classification is Class A in accordance with CECC 00802. Absolute Maximum Ratings Parameter Storage Temperature Ambient Operating Temperature[1] Supply Voltages Output Voltage Average Output Current Average Forward Input Current Lead Solder Temperature Solder Reflow Temperature Profile Recommended Operating Conditions Parameter Ambient Operating Temperature Supply Voltages Input Current (ON) 4 Symbol TS TA VDD VO IO IF Symbol TA VDD IF Min. –55 –40 0 –0.5 Max. Units 125 °C +100 °C 6 Volts VDD2 +0.5 Volts 2 mA 20 mA 260°C for 10 sec., 1.6 mm below seating plane See Solder Reflow Temperature Profile Section Min. –40 4.5 10 Max. +100 5.5 16 Units °C V mA Figure Figure 1, 2 Electrical Specifications Over recommended temperature (T A = –40°C to +100°C) and 4.5 V ≤ VDD ≤ 5.5 V. All typical specifications are at TA = 25°C, VDD = +5 V. Parameter Input Forward Voltage Input Reverse Breakdown Voltage Logic High Output Voltage Logic Low Output Voltage Input Threshold Current Logic Low Output Supply Current Logic High Output Supply Current Symbol VF BVR Min. 1.3 5 Typ. 1.5 VOH 4.0 4.8 Max. 1.8 Units V V Test Conditions IF = 12 mA IR = 10 µA V IF = 0, IO = –20 µA Fig. 1 0.01 0.1 V IF = 12 mA, IO = 20 µA ITH IDDL 6.0 8.2 14.0 mA mA IOL = 20 µA IF = 12 mA 2 4 IDDH 4.5 11.0 mA IF = 0 3 VOL Notes Switching Specifications Over recommended temperature (TA = –40°C to +100°C) and 4.5 V ≤ VDD ≤ 5.5 V. All typical specifications are at TA = 25°C, VDD = +5 V. Parameter Propagation Delay Time to Logic Low Output Propagation Delay Time to Logic High Output Pulse Width 5 Symbol tPHL Min. 20 Typ. 35 Max. 60 Units ns tPLH 13 21 60 ns Pulse Width Distortion PW |PWD| 100 0 30 ns ns Propagation Delay Skew tPSK 40 ns Output Rise Time (10 - 90%) Output Fall Time (90 - 10%) Common Mode Transient Immunity at Logic High Output Common Mode Transient Immunity at Logic Low Output tR 20 ns tF 25 ns 14 |CMH| 10 15 kV/µs |CML | 10 15 kV/µs Test Conditions IF = 12 mA, CL = 15 pF CMOS Signal Levels IF = 12 mA, CL = 15 pF CMOS Signal Levels Fig. 5 Notes 1 5 1 IF = 12 mA, CL = 15 pF CMOS Signal Levels IF = 12 mA, CL = 15 pF CMOS Signal Levels IF = 12 mA, CL = 15 pF CMOS Signal Levels IF = 12 mA, CL = 15 pF CMOS Signal Levels VCM = 1000 V, TA = 25°C, IF = 0 mA 2 2 3 3 4 4 VCM = 1000 V, TA = 25°C, IF = 12 mA 5 5 Package Characteristics All Typicals at TA = 25°C. Parameter Input-Output Insulation Symbol II-O Min. Input-Output Momentary Withstand Voltage Input-Output Resistance Input-Output Capacitance VISO 2500 RI-O CI-O Typ. Max. 1 Units µA Vrms 1012 0.6 Ω pF Test Conditions 45% RH, t = 5 s VI-O = 3 kV dc, TA = 25°C RH ≤ 50%, t = 1 min., TA = 25°C VI-O = 500 V dc f = 1 MHz, TA = 25°C Notes: 1. tPHL propagation delay is measured from the 50% level on the risiing edge of the input pulse to the 2.5 V level of the falling edge of the VO signal. t PLH propagation delay is measured from the 50% level on the falling edge of the input pulse to the 2.5 V level of the rising edge of the VO signal. 2. PWD is defined as |tPHL - tPLH|. 3. tPSK is equal to the magnitude of the worst case difference in tPHL and/or tPLH that will be seen between units at any given temperature within the recommended operating conditions. 4. CM H is the maximum tolerable rate of rise of the common mode voltage to assure that the output will remain in a high logic state. 5. CM L is the maximum tolerable rate of fall of the common mode voltage to assure that the output will remain in a low logic state. 6 IF TA = 25°C + VF – 10 1.0 0.1 0.01 0.001 1.1 1.2 1.3 1.5 1.4 1.6 8 VDD = 5.0 V IOL = 20 µA 7 6 5 4 3 2 tp – PROPAGATION DELAY – ns Iddl – LOGIC LOW OUTPUT SUPPLY CURRENT – mA 100 50 VDD = 5.0 V 7.0 6.5 6.0 5.5 5.0 4.5 4.0 85 Figure 2. Typical input threshold current vs. temperature. 8.0 7.5 25 TA – TEMPERATURE – °C VF – FORWARD VOLTAGE – V Figure 1. Typical input diode forward characteristic. 0 -40 -40 0 25 85 100 VDD = 5.0 V TA = 25 °C 45 40 Tphl 35 30 25 Tplh 20 15 PWD 10 5 0 5 6 7 8 9 10 11 12 13 14 TA – TEMPERATURE – °C IF – PULSE INPUT CURRENT – mA Figure 4. Typical logic low O/P supply current vs. temperature. Figure 5. Typical switching speed vs. pulse input current. 7 Iddh – LOGIC HIGH OUTPUT SUPPLY CURRENT – mA 100 Ith – INPUT THRESHOLD CURRENT – mA IF – FORWARD CURRENT – mA 1000 6.0 5.5 VDD = 5.0 V 5.0 4.5 4.0 3.5 3.0 2.5 2.0 -40 0 25 85 TA – TEMPERATURE – °C Figure 3. Typical logic high O/P supply current vs. temperature. 100 Application Information Bypassing and PC Board Layout to be connected directly to the inputs and outputs. The HCPL-0708 optocoupler is extremely easy to use. No external interface circuitry is required because the HCPL-0708 uses high-speed CMOS IC technology allowing CMOS logic As shown in Figure 6, the only external component required for proper operation is the bypass capacitor. Capacitor values should be between 0.01 µF and VDD 8 1 0.1 µF. For each capacitor, the total lead length between both ends of the capacitor and the power-supply pins should not exceed 20 mm. Figure 7 illustrates the recommended printed circuit board layout for the HPCL-0708. C VI XXX YWW 2 3 7 NC 6 5 4 VO GND C1, C2 = 0.01 µF TO 0.1 µF Figure 6. Recommended printed circuit board layout. VDD XXX YWW VI C2 VO GND C1, C2 = 0.01 µF TO 0.1 µF Figure 7. Recommended printed circuit board layout. Propagation Delay, Pulse-Width Distortion and Propagation Delay Skew Propagation Delay is a figure of merit which describes how quickly a logic signal propagates through a system. The propaga- tion delay from low to high (tPLH) is the amount of time required for an input signal to propagate to the output, causing the output to change from low to high. Similarly, the propagation delay from high to low (tPHL) is the INPUT VI 50% 5 V CMOS 0V tPLH OUTPUT VO Figure 8. 8 90% 10% tPHL 90% 10% VOH 2.5 V CMOS VOL amount of time required for the input signal to propagate to the output, causing the output to change from high to low. See Figure 8. Pulse-width distortion (PWD) is the difference between tPHL and tPLH and often determines the maximum data rate capability of a transmission system. PWD can be expressed in percent by dividing the PWD (in ns) by the minimum pulse width (in ns) being transmitted. Typically, PWD on the order of 20 - 30% of the minimum pulse width is tolerable; the exact figure depends on the particular application. Propagation delay skew, tPSK, is an important parameter to consider in parallel data applications where synchronization of signals on parallel data lines is a concern. If the parallel data is VI being sent through a group of optocouplers, differences in propagation delays will cause the data to arrive at the outputs of the optocouplers at different times. If this difference in propagation delay is large enough it will determine the maximum rate at which parallel data can be sent through the optocouplers. Propagation delay skew is defined as the difference between the minimum and maximum propagation delays, either tPLH or tPHL , for any given group of optocouplers which are operating under the same conditions (i.e., the same drive current, supply voltage, output load, and operating temperature). As illustrated in Figure 9, if the inputs of a group of optocouplers are switched either ON or OFF at the same time, tPSK is the difference between the shortest propagation delay, either tPLH or t PHL, and the longest propagation delay, either tPLH or tPHL. As mentioned earlier, tPSK can determine the maximum parallel data transmission rate. Figure 10 is the timing diagram of a typical parallel data application with both the clock and data lines being sent through the optocouplers. The figure shows data and clock signals at the inputs and outputs of the optocouplers. In this case the data is assumed to be clocked off of the rising edge of the clock. 50% DATA VO INPUTS 2.5 V, CMOS CLOCK tPSK VI 50% DATA OUTPUTS VO 2.5 V, CMOS tPSK CLOCK tPSK Figure 9. Propagation delay skew waveform. Propagation delay skew represents the uncertainty of where an edge might be after being sent through an optocoupler. Figure 10 shows that there will be uncertainty in both the data and clock lines. It is important that these two areas of uncertainty not overlap, otherwise the clock signal might arrive before all of the data outputs have settled, or some of the data outputs may 9 Figure 10. Parallel data transmission example. start to change before the clock signal has arrived. From these considerations, the absolute minimum pulse width that can be sent through optocouplers in a parallel application is twice tPSK. A cautious design should use a slightly longer pulse width to ensure that any additional uncertainty in the rest of the circuit does not cause a problem. The HCPL-0708 optocouplers offer the advantage of guaranteed specifications for propagation delays, pulse-width distortion, and propagation delay skew over the recommended temperature and power supply ranges. www.agilent.com/semiconductors For product information and a complete list of distributors, please go to our web site. For technical assistance call: Americas/Canada: +1 (800) 235-0312 or (408) 654-8675 Europe: +49 (0) 6441 92460 China: 10800 650 0017 Hong Kong: (+65) 6271 2451 India, Australia, New Zealand: (+65) 6271 2394 Japan: (+81 3) 3335-8152(Domestic/International), or 0120-61-1280(Domestic Only) Korea: (+65) 6271 2194 Malaysia, Singapore: (+65) 6271 2054 Taiwan: (+65) 6271 2654 Data subject to change. Copyright © 2002 Agilent Technologies, Inc. Obsoletes 5988-3611EN April 30, 2002 5988-6492EN