ISSUED DATE :2006/06/14 REVISED DATE : GSC93BC46/56/66 3-wire Serial EEPROMs 1K/2K/4K Description The GSC93BC family provides 1K, 2K and 4K of serial electrically erasable and programmable read-only memory (EEPROM). The wide Vdd range allows for low-voltage operation down to 1.8V and up to 5.5V. The device, fabricated using traditional CMOS EEPROM technology, is optimized for many industrial and commercial applications where low-voltage and low-power operation is essential. The device is accessed via a 3-wire serial interface. Features Internally organized as 128x8 or 64x16 (1K), 256x8 or 128x16 (2K), 512x8 or 256x16 (4K) Wide-voltage range operation: 1.8V~5.5V 3-wire serial interface bus Date retention: 100years High endurance: 1,000,000 Write Cycles 2MHz (5V) clock rate Sequential read operation Self-timed write cycle (10ms max) Package Dimensions REF. A B C D E F Figure 1. Pin Configurations Absolute Maximum Ratings Parameter Voltage on Any Pin with Respect to Ground Maximum Operating Voltage DC Output Current Operating Temperature Range Storage Temperature Range Millimeter Min. Max. 5.80 4.80 3.80 0° 0.40 0.19 Pin Name CS SK DI DO Gnd Vcc ORG NC 6.20 5.00 4.00 8° 0.90 0.25 REF. M H L J K G Millimeter Min. Max. 0.10 0.25 0.35 0.49 1.35 1.75 0.375 REF. 45° 1.27 TYP. Function Chip Select Serial Data Clock Serial Data Input Serial Data Output Ground Power Supply Internal Organization No Connect Ratings -1.0 to Vcc +7.0 6.25 5.0 -55 ~ +125 -65 ~ +150 Unit V V mA Note: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of these specifications are not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. GSC93BC46/56/66 Page: 1/8 ISSUED DATE :2006/06/14 REVISED DATE : Figure 2. Block Diagram Notes 1. The ORG pin is used to select between x8 and x16. When the pin is connected to Vcc, x16 mode is selected. Otherwise, the ORG pin should be grounded in order to select x8 mode. The interface foe the GSC93BC46/56/66 is accessed through four different signals: Chip Select (CS), Data Input (DI), Data Output (DO), and Serial Data Clock (SK). The Chip Select (CS) signal must be pulled high before issuing a command through the Data Input (DI) pin. The Serial Data Clock (SK) signal is used in conjunction with the Data Input (DI) pin. PIN Capacitance Applicable over recommended operating range from TA=25 , f=1.0MHz, Vcc=+5V Symbol Test Condition Max Unit COUT Output Capacitance (DO) 5 pF CIN Input Capacitance (CK, SK, DI) 5 pF Condition VOUT=0V VIN=0V Note: 1. This parameter is characterized and not 100% tested. DC Characteristics Applicable over recommended operating range from: TA=-40 ~ +85 , Vcc=+1.8 ~ +5V (unless otherwise noted) Parameter Symbol Test Condition Min TYP Max Unit Supply Voltage VCC1 1.8 5.5 V Supply Voltage VCC2 2.7 5.5 V Supply Voltage VCC3 4.5 5.5 V Supply Current VCC=5.0V ICC READ at 1MHz 0.5 2.0 mA Supply Current VCC=5.0V ICC WRITE at 1MHz 0.5 2.0 mA Standby Current VCC=1.8V ISB1 CS=0V 0 0.1 A Standby Current VCC=2.7V ISB2 CS=0V 6.0 10.0 A Standby Current VCC=5.0V ISB3 CS=0V 17 30 A Input Leakage Current ILI VIN=0V to VCC 0.1 3.0 A Output Leakage Current ILO VIN=0V to VCC 0.1 3.0 A -0.6 0.8 Input Low Level VIL1(1) 2.7V< VCC <5.5V V (1) 2.0 VCC+1 Input High Level VIH1 (1) -0.6 VCCx0.3 Input Low Level VIL2 1.8V< VCC <2.7V V VCCx0.7 Input High Level VIH2(1) VCC+1 0.4 Output Low Level VOL1(1) 2.7V< VCC <5.5V; IOL=2.1mA V (1) Output High Level 2.4 VOH1 IOH=-0.4mA (1) 0.2 Output Low Level VOL2 1.8V< VCC <2.7V; IOL=0.15mA V (1) Output High Level VOH2 IOH=-100uA VCC-2 Note 1: V IL and V IH max are reference only and are not tested. GSC93BC46/56/66 Page: 2/8 ISSUED DATE :2006/06/14 REVISED DATE : AC Characteristics Applicable over recommended operating range from: TA=-40 ~ +85 , Vcc=As specified, CL=1 TTL Gate & 100pF (unless otherwise noted) Parameter Symbol Test Condition Min TYP Max Unit Clock Frequency, SK f SK 4.5V< VCC <5.5V 2.7V< VCC <5.5V 1.8V< VCC <5.5V 0 0 0 - 2 1 0.25 MHz SK High Time tSKH 4.5V< VCC <5.5V 2.7V< VCC <5.5V 1.8V< VCC <5.5V 250 250 1000 - - ns SK Low Time tSKL 4.5V< VCC <5.5V 2.7V< VCC <5.5V 1.8V< VCC <5.5V 250 250 1000 - - ns Minimum CS Low Time tCS 4.5V< VCC <5.5V 2.7V< VCC <5.5V 1.8V< VCC <5.5V 250 250 1000 - - ns CS Setup Time tCSS Relative To SK 4.5V< VCC <5.5V 2.7V< VCC <5.5V 1.8V< VCC <5.5V 50 50 200 - - ns DI Setup Time tDIS Relative To SK 4.5V< VCC <5.5V 2.7V< VCC <5.5V 1.8V< VCC <5.5V 100 100 400 - - ns CS Hold Time tCSH Relative To SK 0 - - ns DI Hold Time tDIH Relative To SK 4.5V< VCC <5.5V 2.7V< VCC <5.5V 1.8V< VCC <5.5V 100 100 400 - - ns Output Delay to “1” tPD1 AC Test 4.5V< VCC <5.5V 2.7V< VCC <5.5V 1.8V< VCC <5.5V - - 250 250 1000 ns Output Delay to “0” tPD0 AC Test 4.5V< VCC <5.5V 2.7V< VCC <5.5V 1.8V< VCC <5.5V - - 250 250 1000 ns CS to Status Valid tSV AC Test 4.5V< VCC <5.5V 2.7V< VCC <5.5V 1.8V< VCC <5.5V - - 250 250 1000 ns CS to DO in High Impedance tDF AC Test CS=VIL 4.5V< VCC <5.5V 2.7V< VCC <5.5V 1.8V< VCC <5.5V - - 100 100 400 ns Write Cycle Time tWP 1.8V< VCC <5.5V - 3 10 ms 1M - - Write Cycles 5.0V, 25 Endurance (1) Note: 1. This parameter is characterized and not 100% tested. GSC93BC46/56/66 Page: 3/8 ISSUED DATE :2006/06/14 REVISED DATE : Instruction set for the GSC93BC46 Instruction SB Address OP Code X8 X16 READ 1 10 A6 ~ A0 A5 ~ A0 EWEN 1 00 11xxxxx 11xxxx ERASE WRITE 1 1 11 01 A6 ~ A0 A6 ~ A0 A5 ~ A0 A5 ~ A0 ERAL 1 00 10xxxxx 10xxxx WRAL 1 00 01xxxxx 01xxxx EWDS 1 00 00xxxxx 00xxxx Data X8 X16 D7 ~ D0 D15 ~ D0 D7 ~ D0 D15 ~ D0 Comment Reads data stored at specified memory location. Write enable command (must be issued before any erase or write operation). Erases memory location An~A0 Write to memory location An~A0 Erases all memory locations. Valid only at VCC=4.5V to 5.5V Write all memory locations. Valid only at VCC=4.5V to 5.5V Disables all erase or write instructions Note : The X’s in the address field represent don’t care values and must be clocked. Instruction set for the GSC93BC56/66 Instruction SB Address OP Code X8 X16 READ 1 10 A8 ~ A0 A7 ~ A0 EWEN 1 00 11xxxxxxx 11xxxxxx ERASE WRITE 1 1 11 01 A8 ~ A0 A8 ~ A0 ERAL 1 00 10xxxxxxx 10xxxxxx WRAL 1 00 01xxxxxxx 01xxxxxx EWDS 1 00 00xxxxxxx 00xxxxxx A7 ~ A0 A7 ~ A0 Data X8 X16 D7~D0 D15~D0 D7~D0 D15~D0 Comment Reads data stored at specified memory location. Write enable command (must be issued before any erase or write operation). Erases memory location An~A0 Write to memory location An~A0 Erases all memory locations. Valid only at VCC=4.5V to 5.5V Write all memory locations. Valid only at VCC=4.5V to 5.5V Disables all erase or write instructions Note : The X’s in the address field represent don’t care values and must be clocked. Function Description The GSC93BC46/56/66 support 7 different instructions, which must be clocked serially using the CS, SK and DI pins. Before sending each of these instructions, the CS pin must be pulled high followed by a START bit (logic ‘1’). The next sequence includes a 2-bit Op Code and usually an 8 or 16-bit address. The next description describes the various functions in the chip. READ (READ): The Read (READ) instruction includes the Op Code (“10”) followed by the memory address location to be read. After the instruction and address is sent, the data from the memory location can be clocked out using the serial output pin DO. The data changes on the rising edge of the clock, so the falling edge can be used to strobe the output. Note that during shifting the last address bit, the DO pin is a dummy bit (logic “0”). ERASE/WRITE (EWEN)): When the chip is first powered-on, no erase or write instructions can be issued. Only when the Erase/Write Enable (EWEN) instruction is sent will the system be allowed to write to the chip. The EWEN command only needs to be issued once after being powered-on. To disable the chip again, the Erase/Write Disable (EWDS) command can be used. GSC93BC46/56/66 Page: 4/8 ISSUED DATE :2006/06/14 REVISED DATE : ERASE (ERASE): The Erase (ERASE) instruction clears the designated memory location to a logic ‘1’ state. After the Op Code and address location is inputted, the chip will enter into an erase cycle. When the cycle completes, the chip will automatically enter into standby mode. WRITE (WRITE): The Write (WRITE) instruction is used to write to a specific memory location. If word mode (x16) is selected, then 16 bits of data will be written into the location. If byte mode (x8) is chosen, then 8 bits of data will be written into the location. The write cycle will begin automatically after the 8 or 16 bits are shifted into the chip. ERASE ALL (ERAL): The Erase All (ERAL) instruction is primarily used for testing purposes and only functions when VCC=4.5V to 5.5V. This instruction will clear the entire memory array to ‘1’. WRITE ALL (WRAL): The Write All (WRAL) instruction will program the entire memory array according to the 8 or 16-bit data pattern provided. The instruction will only be valid when VCC=4.5V to 5.5V. ERASE/WRITE DISABLE (EWDS): The Erase/Write Disable (EWDS) instruction blocks any kind of erase or program operations from modifying the contents of the memory array. This instruction should be executed after erasing or programming to prevent accidental data loss. Note also that the READ instruction will operate regardless of whether the chip is disabled from program and write operations. Ready/Busy To determine whether the chip has completed an erase or write operation, the CS signal can be pulled LOW for a minimum of 250ns (tCS) and then pulled back HIGH to enter Ready/Busy mode. If the chip is currently in the programming cycle, tWP, then the DO pin will go low (logical “0”). When the write cycle completes, the DO pin is pulled high (logical “1”) to indicate that the part can receive anther instruction. Note that the Ready/Busy polling cannot be done if the chip has already finished and returned back to standby mode. Timing Diagrams Synchronous Data Timing Note (1): This is the minimum SK period. Organization Key for TIMING Diagrams I/O AN DN X8 A6 D7 GSC93BC46(1K) X16 A5 D15 GSC93BC56(2K) X8 X16 (1) A8 A7(2) D7 D15 X8 A8 D7 GSC93BC66(4K) X16 A7 D15 Note: 1. A8 is a DON’T CARE value, but the extra clock is required. 2. A7 is a DON’T CARE value, but the extra clock is required. GSC93BC46/56/66 Page: 5/8 ISSUED DATE :2006/06/14 REVISED DATE : READ Timing EWEN Timing EWDS Timing WRITE Timing GSC93BC46/56/66 Page: 6/8 ISSUED DATE :2006/06/14 REVISED DATE : WRAL Timing (1) (1) Valid only at VCC=4.5V to 5.5V ERASE Timing ERAL Timing (1) (1) Valid only at VCC=4.5V to 5.5V GSC93BC46/56/66 Page: 7/8 ISSUED DATE :2006/06/14 REVISED DATE : GSC93BC46 Ordering Information Ordering Code GSC93BC46AI GSC93BC46BI Package SOP-8 Pin Type A B Operating Ranges Pin Type A B Operating Ranges Pin Type A B Operating Ranges Industrial (-40 ~ +85 ) GSC93BC56 Ordering Information Ordering Code GSC93BC56AI GSC93BC56BI Package SOP-8 GSC93BC66 Ordering Information Ordering Code GSC93BC66AI GSC93BC66BI Package SOP-8 Industrial (-40 ~ +85 ) Industrial (-40 ~ +85 ) Product Ordering Information GSC93BCXXYZ G=GTM SC=SOP-8 93=Device Type Supply Voltage BC=1.8V to 5.5V Device Function 46=1 Kbit (128x8 or 64x16) 56=2 Kbit (256x8 or 128x16) 66=4 Kbit (512x8 or 256x16) Pin Type A=A-Type B=B-Type Temperature I=Industrial (-40 ~ +85 Important Notice: All rights are reserved. Reproduction in whole or in part is prohibited without the prior written approval of GTM. GTM reserves the right to make changes to its products without notice. GTM semiconductor products are not warranted to be suitable for use in life-support Applications, or systems. GTM assumes no liability for any consequence of customer product design, infringement of patents, or application assistance. Head Office And Factory: Taiwan: No. 17-1 Tatung Rd. Fu Kou Hsin-Chu Industrial Park, Hsin-Chu, Taiwan, R. O. C. TEL : 886-3-597-7061 FAX : 886-3-597-9220, 597-0785 China: (201203) No.255, Jang-Jiang Tsai-Lueng RD. , Pu-Dung-Hsin District, Shang-Hai City, China TEL : 86-21-5895-7671 ~ 4 FAX : 86-21-38950165 GSC93BC46/56/66 Page: 8/8