HAMAMATSU S3902-256Q

IMAGE SENSOR
NMOS linear image sensor
S3902/S3903 series
Current output, high UV sensitivity, excellent linearity, low power consumption
NMOS linear image sensors are self-scanning photodiode arrays designed specifically as detectors for multichannel spectroscopy. The scanning
circuit is made up of N-channel MOS transistors, operates at low power consumption and is easy to handle. Each photodiode has a large active
area, high UV sensitivity yet very low noise, delivering a high S/N even at low light levels. NMOS linear image sensors also offer excellent output
linearity and wide dynamic range.
The photodiodes of S3902 series have a height of 0.5 mm and are arrayed in a row at a spacing of 50 µm. The photodiodes of S3903 series also
have a height of 0.5 mm but are arrayed at a spacing of 25 µm. The photodiodes are available in 3 different pixel quantities for each series: 128
(S3902-128Q), 256 (S3902-256Q, S3903-256Q), 512 (S3902-512Q, S3903-512Q) and 1024 (S3903-1024Q). Quartz glass is the standard window
material.
Features
Applications
l Wide active area
Pixel pitch: 50 µm (S3902 series)
25 µm (S3903 series)
Pixel height: 0.5 mm
l High UV sensitivity with good stability
l Low dark current and high saturation charge allow a long
integration time and a wide dynamic range at room temperature
l Excellent output linearity and sensitivity spatial uniformity
l Lower power consumption: 1 mW Max.
l Start pulse and clock pulses are CMOS logic compatible
Figure 1 Equivalent circuit
st
1
CLOCK
2
Figure 2 Active area structure
DEGITAL SHIFT REGISTER
(MOS SHIFT REGISTER)
END OF SCAN
0.5 mm
START
CLOCK
l Multichannel spectrophotometry
l Image readout system
ACTIVE VIDEO
ACTIVE
PHOTODIODE
Vss
b
SATURATION
CONTROL GATE
SATURATION
CONTROL DRAIN
1.0 µm
a
DUMMY VIDEO
OXIDATION SILICON
N TYPE SILICON
1.0 µm
KMPDC0020EA
400 µm
DUMMY DIODE
P TYPE SILICON
S3902 SERIES: a=50 µm, b=45 µm
S3903 SERIES: a=25 µm, b=20 µm
■ Absolute maximum ratings
Parameter
Input pulse (φ1, φ2, φst) voltage
Power consumption *1
Operating temperature *2
Storage temperature
*1: Vφ=5.0 V
*2: No condensation
Symbol
Vφ
P
Topr
Tstg
Value
15
1
-40 to +65
-40 to +85
KMPDA0107EA
Unit
V
mW
°C
°C
S3902/S3903 series
NMOS linear image sensor
■ Shape specifications
S3902S3902128Q
256Q
128
256
31.75
22
Quartz
3.0
Parameter
Number of pixels
Package length
Number of pin
Window material *3
Weight
*3: Fiber optic plate is available.
■ Specifications (Ta=25 °C)
Parameter
Symbol
Min.
-
S3902512Q
512
40.6
3.5
S3902 series
Typ.
Max.
50
0.5
-
Pixel pitch
Pixel height
Spectral response range
200 to 1000
λ
(10 % of peak)
Peak sensitivity wavelength
600
λp
Photodiode dark current *4
ID
0.08
Photodiode capacitance *4
Cph
4
Saturation exposure *4, *5
Esat
180
Saturation output charge *4
Qsat
10
Photo response non-uniformity *6
PRNU
*4: Vb=2.0 V, Vφ=5.0 V
*5: 2856 K, tungsten lamp
*6: 50 % of saturation, excluding the start pixel and last pixel
■ Electrical characteristics (Ta=25 °C)
Parameter
Symbol
High Vφ1, Vφ2 (H)
Low Vφ1, Vφ2 (L)
High
Vφs (H)
Start pulse (φst) voltage
Low
Vφs (L)
Video bias voltage *7
Vb
Saturation control gate voltage
Vscg
Saturation control drain voltage
Vscd
trφ1, trφ2
8
Clock pulse (φ1, φ2) rise / fall time *
tfφ1, tfφ2
Clock pulse (φ1, φ2) pulse width
tpwφ1, tpwφ2
Start pulse (φst) rise / fall time
trφs, tfφs
Start pulse (φ1, φ2) pulse width
tpwφs
Start pulse (φst) and clock pulse
tφov
(φ2) overlap
8
Clock pulse space *
X 1 , X2
Data rate *9
f
Clock pulse (φ1, φ2)
voltage
Video delay time
tvd
Clock pulse (φ1, φ2)
line capacitance
Cφ
Saturation control gate (Vscg)
line capacitance
Video line capacitance
Cscg
CV
Condition
S3903S3903256Q
512Q
256
512
31.75
22
Quartz
3.0
Min.
-
S39031024Q
1024
40.6
3.5
S3903 series
Typ.
Max.
25
0.5
200 to 1000
0.15
±3
-
S3902 series
Typ.
Max.
5
10
0.4
10
Vφ1
0.4
Vφ - 3.0 Vφ - 2.5
0
Vb
-
600
0.04
2
180
5
-
mm
g
Unit
µm
mm
nm
0.08
±3
S3903 series
Typ.
Max.
5
10
0.4
10
Vφ1
0.4
Vφ - 3.0 Vφ - 2.5
0
Vb
-
nm
pA
pF
mlx · s
pC
%
Unit
-
Min.
4.5
0
4.5
0
1.5
-
-
-
20
-
-
20
-
ns
-
200
200
20
-
-
200
200
20
-
-
ns
ns
ns
-
200
-
-
200
-
-
ns
trf - 20
0.1
-
80 (-256 Q)
120 (-512 Q)
160 (-1024 Q)
27 (-256 Q)
50 (-512 Q)
100 (-1024 Q)
12 (-256 Q)
24 (-512 Q)
45 (-1024 Q)
10 (-256 Q)
16 (-512 Q)
30 (-1024 Q)
2000
-
ns
kHz
ns
ns
ns
pF
pF
pF
pF
pF
pF
pF
pF
pF
trf - 20
0.1
50 % of
saturation
*9, *10
5 V bias
5 V bias
2 V bias
-
2000
70 (-128 Q)
110 (-256 Q)
140 (-512 Q)
21 (-128 Q)
36 (-256 Q)
67 (-512 Q)
12 (-128 Q)
20 (-256 Q)
35 (-512 Q)
7 (-128 Q)
11 (-256 Q)
20 (-512 Q)
Min.
4.5
0
4.5
0
1.5
-
Unit
V
V
V
V
V
V
V
*7: Vφ is input pulse voltage (refer to figure 8)
*8: trf is the clock pulse rise or fall time. A clock pulse space of “rise time/fall time - 20 ” ns (nanoseconds) or more should be
input if the clock pulse rise or fall time is longer than 20 ns. (refer to figure 7)
*9: Vb=2.0 V, Vφ=5.0 V
*10: Measured with C7883 driver circuit.
NMOS linear image sensor
S3902/S3903 series
Figure 3 Dimensional outlines (unit: mm)
ACTIVE AREA
12.8 × 0.5
5.2 ± 0.2
6.4 ± 0.3
31.75
1.3 ± 0.2*
5.2 ± 0.2
PHOTOSENSITIVE
SURFACE
PHOTOSENSITIVE
SURFACE
3.0
3.0
31.75
5.2 ± 0.2
10.4
10.4
3.2 ± 0.3
1.3 ± 0.2*
ACTIVE AREA
6.4 × 0.5
S3902-256Q, S3903-512Q
5.2 ± 0.2
S3902-128Q, S3903-256Q
0.51
0.25
0.51
0.25
2.54
25.4
2.54
10.16
25.4
10.16
* Optical distance from the outer surface
of the quartz window to the chip surface
* Optical distance from the outer surface
of the quartz window to the chip surface
KMPDA0108EA
Figure 4 Pin connection
S3902-512Q, S3903-1024Q
5.2 ± 0.2
ACTIVE AREA
25.6 × 0.5
10.4
12.8 ± 0.3
1.3 ± 0.2 *
5.2 ± 0.2
PHOTOSENSITIVE
SURFACE
3.0
40.6
KMPDA0109EA
0.51
2
1
22
NC
1
2
21
NC
st
3
20
NC
Vss
4
19
NC
Vscg
5
18
NC
NC
6
17
NC
Vscd
7
16
NC
Vss
8
15
NC
ACTIVE VIDEO
9
14
NC
DUMMY VIDEO
10
13
NC
Vsub
11
12
END OF SCAN
0.25
Vss, Vsub and NC should be grounded.
KMPDC0056EA
2.54
25.4
10.16
* Optical distance from the outer surface
of the quartz window to the chip surface
KMPDA0110EA
NMOS linear image sensor
Terminal
Input or output
φ1, φ2
Input
(CMOS logic compatible)
φst
Input
(CMOS logic compatible)
Vss
-
Vscg
Input
Vscd
Input
Active video
Output
Dummy video
Output
Vsub
Output
(CMOS logic compatible)
End of scan
NC
-
Description
Pulses for operating the MOS shift register. The video data rate is
equal to the clock pulse frequency since the video output signal is
obtained synchronously with the rise of φ2 pulse.
Pulse for starting the MOS shift register operation. The time interval
between start pulses is equal to the signal accumulation time.
Connected to the anode of each photodiode. This should be
grounded.
Used for restricting blooming. This should be grounded.
Used for restricting blooming. This should be biased at a voltage
equal to the video bias voltage.
Video output signal. Connects to photodiode cathodes when the
address is on. A positive voltage should be applied to the video
line in order to use photodiodes with a reverse voltage. When the
amplitude of φ1 and φ2 is 5 V, a video bias voltage of 2 V is
recommended.
This has the same structure as the active video, but is not
connected to photodiodes, so only spike noise is output. This
should be biased at a voltage equal to the active video or left as an
open-circuit when not needed.
Connected to the silicon substrate. This should be grounded.
This should be pulled up at 5 V by using a 10 kΩ resistor. This is a
negative going pulse that appears synchronously with the φ2
timing right after the last photodiode is addressed.
Should be grounded.
Figure 5 Spectral response (typical example)
102
(Typ. Vb=2 V, V =5 V, light source: 2856 K)
101
OUTPUT CHARGE (pC)
PHOTO SENSITIVITY (A/W)
Figure 6 Output charge vs. exposure
(Ta=25 ˚C)
0.3
S3902/S3903 series
0.2
0.1
10
SATURATION
CHARGE
0
S3902 SERIES
10
–1
S3903 SERIES
10–2
SATURATION EXPOSURE
0
200
400
600
800
1000
1200
10
–3
10–5
10–4
10–3
10–2
10–1
100
EXPOSURE (lx · s)
WAVELENGTH (nm)
KMPDB0149EA
KMPDB0117EA
■ Construction of image sensor
The NMOS image sensor consists of a scanning circuit made
up of MOS transistors, a photodiode array, and a switching
transistor array that addresses each photodiode, all integrated
onto a monolithic silicon chip. Figure 1 shows the circuit of a
NMOS linear image sensor.
The MOS scanning circuit operates at low power consumption and generates a scanning pulse train by using a start
pulse and 2-phase clock pulses in order to turn on each address sequentially. Each address switch is comprised of an
NMOS transistor using the photodiode as the source, the
video line as the drain and the scanning pulse input section
as the gate.
The photodiode array operates in charge integration mode
so that the output is proportional to the amount of light exposure (light intensity × integration time).
Each cell consists of an active photodiode and a dummy
photodiode, which are respectively connected to the active
video line and the dummy video line via a switching transistor. Each of the active photodiodes is also connected to the
saturation control drain via the saturation control transistor,
so that the photodiode blooming can be suppressed by
grounding the saturation control gate. Applying a pulse signal to the saturation control gate triggers all reset. (See “Auxiliary functions”.)
Figure 2 shows the schematic diagram of the photodiode
active area. This active area has a PN junction consisting of
an N-type diffusion layer formed on a P-type silicon substrate.
A signal charge generated by light input accumulates as a
capacitive charge in this PN junction. The N-type diffusion
layer provides high UV sensitivity but low dark current.
NMOS linear image sensor
S3902/S3903 series
■ Driver circuit
S3902/S3903 series do not require any DC voltage supply
for operation. However, the Vss, Vsub and all NC terminals
must be grounded. A start pulse φst and 2-phase clock pulses
φ1, φ2 are needed to drive the shift register. These start and
clock pulses are positive going pulses and CMOS logic compatible.
The 2-phase clock pulses φ1, φ2 can be either completely
separated or complementary. However, both pulses must not
be “High” at the same time.
A clock pulse space (X1 and X2 in Figure 7) of a “rise time/fall
time - 20” ns or more should be input if the rise and fall times
of φ1, φ2 are longer than 20 ns. The φ1 and φ2 clock pulses
must be held at “High” at least 200 ns. Since the photodiode
signal is obtained at the rise of each φ2 pulse, the clock pulse
frequency will equal the video data rate.
Figure 7 Timing chart for driver circuit
1
2
V s (H)
V s (L)
V
V
V
V
■ End of scan
The end of scan (EOS) signal appears in synchronization
with the φ2 timing right after the last photodiode is addressed,
and the EOS terminal should be pulled up at 5 V using a 10
kΩ resistor.
Figure 8 Video bias voltage margin
10
tpw s
tpw 1
1 (H)
1 (L)
2 (H)
2 (L)
tpw 2
VIDEO BIAS VOLTAGE (V)
st
The amplitude of start pulse φst is the same as the φ1 and φ2
pulses. The shift register starts the scanning at the “High”
level of φst, so the start pulse interval determines the length of
signal accumulation time. The φst pulse must be held “High”
at least 200 ns and overlap with φ2 at least for 200 ns. To
operate the shift register correctly, φ2 must change from the
“High” level to the “Low” level only once during “High” level of
φst. The timing chart for each pulse is shown in Figure 7.
tvd
ACTIVE VIDEO OUTPUT
END OF SCAN
tr s
st
tf s
tr 1
tf 1
1
X1
X2
8
X.
S
ED
6
MA
BIA
ND
E
MM
CO
RE
4
VIDEO BIAS RANGE
2
tf 2
MIN.
2
0
t ov
4
5
6
7
8
9
10
tr 2
CLOCK PULSE AMPLITUDE (V)
■ Signal readout circuit
There are two methods for reading out the signal from an NMOS
linear image sensor. One is a current detection method using
the load resistance and the other is a current integration method
using a charge amplifier. In either readout method, a positive
bias must be applied to the video line because photodiode
anodes of NMOS linear image sensors are set at 0 V (Vss).
Figure 8 shows a typical video bias voltage margin. As the clock
pulse amplitude is higher, the video bias voltage can be set
larger so the saturation charge can be increased. The rise and
fall times of the video output waveform can be shortened if the
video bias voltage is reduced while the clock pulse amplitude is
still higher. When the amplitude of φ1, φ2 and φst is 5 V, setting
the video bias voltage at 2 V is recommended.
To obtain good linearity, using the current integration method is
advised. In this method, the integration capacitance is reset to
the reference voltage level immediately before each photodiode
is addressed and the signal charge is then stored as an integration capacitive charge when the address switch turns on. Figures 9 and 10 show a typical current integration circuit and its
pulse timing chart. To ensure stable output, the rise of a reset
pulse must be delayed at least 50 ns from the fall of φ2.
KMPDC0022EA
KMPDB0043EA
Hamamatsu provides the following driver circuits and related
products (sold separately).
Product
name
Type No.
C7883
C7883G
Driver
circuit
C7884
C7884G
C7884-01
C7884G-01
Pulse
C8225-01
generator
Cable
A8226
Content
Feature
High-speed
driver circuit
C7883
+ C8225-01
Precision
driver circuit
C7884
+ C8225-01
High precision
driver circuit
C7884-01
+ C8225-01
C7883,
C7884 series
C7883 to
C7885 series
High-speed operation
Single power supply
(+15 V) operation
Compact
Low noise
Good output linearity
Boxcar waveform output
Ultra-low noise
Good output linearity
Boxcar waveform output
BNC, length 1 m
NMOS linear image sensor
S3902/S3903 series
Figure 9 Readout circuit example and timing chart
+5 V
50 ns MIN.
10 kΩ
st
st
EOS
1
1
2
2
DUMMY
VIDEO
st
EOS
RESET
1, Reset
OPEN
2
10 pF
Vscg
Vss
Vsub
ACTIVE
VIDEO
–
Vscd
+
KMPDC0024EA
NC
OP-AMP (JFET INPUT)
+
+2 V
KMPDC0023EA
Output voltage Vout is
Output charge [C]
Vout [V] =
10 × 10-12 [F]
shown in.
■ Anti-blooming function
If the incident light intensity is higher than the saturation charge level, even partially, a signal charge in excess of the saturation
charge cannot accumulate in the photodiode. This excessive charge flows out into the video line degrading the signal purity. To
avoid this problem and maintain the signal purity, applying the same voltage as the video bias voltage to the saturation control
drain and grounding the saturation control gate are effective. If the incident light intensity is extremely high, a positive bias should
be applied to the saturation control gate. The larger the voltage applied to the saturation control gate, the higher the function for
suppressing the excessive saturation charge will be. However, this voltage also lowers the amount of saturation charge, so an
optimum bias voltage should be selected.
■ Auxiliary functions
1) All reset
In normal operation, the accumulated charge in each photodiode is reset when the signal is read out. Besides this method that
uses the readout line, S3902/S3903 series can reset the photodiode charge by applying a pulse to the saturation control gate.
The amplitude of this pulse should be equal to the φ1, φ2 and φst pulses and the pulse width should be longer than 5 µs.
When the saturation control gate is set at the “High” level, all photodiodes are reset to the saturation control drain potential
(equal to video bias). Conversely, when the saturation control gate is set at the “Low” level (0 V), the signal charge accumulates
in each photodiode without being reset.
2) Dummy video
S3902/S3903 series have a dummy video line to eliminate spike noise contained in the video output waveform. Video signal
with lower spike noise can be obtained by differential amplification applied between the active video line and dummy video
line outputs. When not needed, leave this unconnected.
■ Handling precautions
1) Electrostatic countermeasures
NMOS linear image sensors are designed to resist static electrical charges. However, take sufficient cautions and countermeasures to prevent damage from static charges when handling the sensors.
2) Window
If dust or grime sticks to the surface of the light input window, it appears as a black blemish or smear on the image. Before using
the image sensor, the window surface should be cleaned. Wipe off the window surface with a soft cloth, cleaning paper or
cotton swab slightly moistened with organic solvent such as alcohol, and then lightly blow away with compressed air. Do not
rub the window with dry cloth or cotton swab as this may generate static electricity.
Information furnished by HAMAMATSU is believed to be reliable. However, no responsibility is assumed for possible inaccuracies or omissions.
Specifications are subject to change without notice. No patent rights are granted to any of the circuits described herein. ©2005 Hamamatsu Photonics K.K.
HAMAMATSU PHOTONICS K.K., Solid State Division
1126-1 Ichino-cho, Higashi-ku, Hamamatsu City, 435-8558 Japan, Telephone: (81) 53-434-3311, Fax: (81) 53-434-5184, www.hamamatsu.com
U.S.A.: Hamamatsu Corporation: 360 Foothill Road, P.O.Box 6910, Bridgewater, N.J. 08807-0910, U.S.A., Telephone: (1) 908-231-0960, Fax: (1) 908-231-1218
Germany: Hamamatsu Photonics Deutschland GmbH: Arzbergerstr. 10, D-82211 Herrsching am Ammersee, Germany, Telephone: (49) 08152-3750, Fax: (49) 08152-2658
France: Hamamatsu Photonics France S.A.R.L.: 19, Rue du Saule Trapu, Parc du Moulin de Massy, 91882 Massy Cedex, France, Telephone: 33-(1) 69 53 71 00, Fax: 33-(1) 69 53 71 10
United Kingdom: Hamamatsu Photonics UK Limited: 2 Howard Court, 10 Tewin Road, Welwyn Garden City, Hertfordshire AL7 1BW, United Kingdom, Telephone: (44) 1707-294888, Fax: (44) 1707-325777
North Europe: Hamamatsu Photonics Norden AB: Smidesvägen 12, SE-171 41 Solna, Sweden, Telephone: (46) 8-509-031-00, Fax: (46) 8-509-031-01
Italy: Hamamatsu Photonics Italia S.R.L.: Strada della Moia, 1/E, 20020 Arese, (Milano), Italy, Telephone: (39) 02-935-81-733, Fax: (39) 02-935-81-741
Cat. No. KMPD1043E01
Oct. 2005 DN