PHOTODIODE Photodiode array with amplifier S8865-256, S8865-256G Photodiode array combined with signal processing circuit chip S8865-256 and S8865-256G are Si photodiode arrays combined with a signal processing circuit chip. The signal processing circuit chip is formed by CMOS process and incorporates a timing generator, shift register, charge amplifier array, clamp circuit and hold circuit, making the external circuit configuration simple. A long, narrow image sensor can also be configured by arranging multiple arrays in a row. For X-ray detection applications, types with fluorescent paper affixed on the active area are also available. Features Applications l Element pitch: 0.2 mm pitch × 256 ch l 5 V power supply operation l Simultaneous integration by using a charge amplifier l Long line sensors l Line sensors for X-ray detection array l Sequential readout with a shift register (Data rate: 1 MHz Max.) l Low dark current due to zero-bias photodiode operation l Integrated clamp circuit allows low noise and wide dynamic range l Integrated timing generator allows operation at two different input pulse timings (reset, clock) l Types with phosphor screen affixed on the active area are available for X-ray detection: S8865-256G ■ Specifications of active area Parameter Element pitch Element width Element height Number of elements Active area length *1: Refer to following figure. Symbol *1 P W H - Value 0.2 0.1 0.3 256 51.2 Unit mm mm mm mm H ■ Enlarged view of active area W PHOTODIODE P KMPDC0072EB 1 Photodiode array with amplifier S8865-256, S8865-256G ■ Absolute maximum ratings Parameter Supply voltage Reference voltage Photodiode voltage Gain selection terminal voltage Master/slave selection voltage Clock pulse voltage Reset pulse voltage External start pulse voltage Operating temperature *2 Storage temperature *2: No condensation Symbol Vdd Vref Vpd Rated value -0.3 to +6 -0.3 to +6 -0.3 to +6 Unit V V V Vgain -0.3 to +6 V Vms -0.3 to +6 V V (CLK) V (RESET) -0.3 to +6 -0.3 to +6 V V V (EXTST) -0.3 to +6 V Topr Tstg -5 to +60 -10 to +70 °C °C ■ Recommended terminal voltage Parameter Supply voltage Reference voltage Photodiode voltage Gain selection terminal voltage Master/slave selection voltage Clock pulse voltage Reset pulse voltage Symbol Vdd Vref Vpd High gain Low gain High level *3 Low level *4 High level Low level High level Low level High level Low level External start pulse voltage *3: Parallel *4: Serial at 2nd or later stages Vgain Vms V (CLK) V (RESET) V (EXESP) Min. 4.75 4 Vdd-0.25 0 Vdd-0.25 0 Vdd-0.25 0 Vdd-0.25 0 Vdd-0.25 0 Typ. 5 4.5 Vref Vdd Vdd Vdd Vdd Vdd - Max. 5.25 4.75 Vdd+0.25 0.4 Vdd+0.25 0.4 Vdd+0.25 0.4 Vdd+0.25 0.4 Vdd+0.25 0.4 Unit V V V V V V V V V V V V V Max. 4000 - Unit kHz kΩ mW ■ Electrical characteristics [Ta=25 °C, Vdd=5 V, V (CLK)=V (RESET)=5 V] Parameter Symbol Clock pulse frequency *5 f (CLK) Output impedance Zo Power consumption P High gain Charge amp feedback Cf capacitance Low gain *5: Video data rate is 1/4 of clock pulse frequency f (CLK). 2 Min. 40 - Typ. 3 360 0.5 1 pF Photodiode array with amplifier S8865-256, S8865-256G ■ Electrical/optical characteristics [Ta=25 °C, Vdd=5 V, V (CLK)=V (RESET)=5 V, Vgain=5 V (High gain), 0 V (Low gain)] Parameter Spectral response range Peak sensitivity wavelength High gain Dark output voltage *6 Low gain Saturation output voltage High gain Saturation exposure *7 Low gain High gain Photo sensitivity Low gain Photo response non-uniformity *8 High gain Noise *9 Low gain Output offset voltage *10 Symbol λ λp Min. Typ. 200 to 1000 720 0.002 0.001 3.5 15 30 250 125 0.6 0.3 Vref 3 - Vd Vsat Esat S PRNU N Vos Max. Unit nm nm 0.02 0.01 ±10 - mV V mlx · s V/lx · s % mVrms V *6: Integration time ts=1 ms *7: Measured with a 2856 K tungsten lamp *8: When the photodiode array is exposed to uniform light which is 50 % of the saturation exposure, the Photo Response NonUniformity (PRNU) is defined as follows: PRNU = ∆X/X × 100 (%) where X is the average output of all elements and ∆X is the difference between the maximum and minimum outputs. *9: Measured with a video data rate of 50 kHz and Ts=1 ms in dark state *10: Video output is negative-going output with respect to the output offset voltage. ■ Output waveform of one element ■ Spectral response (measurement example) PHOTO SENSITIVITY (A/W) SATURATION OUTPUT VOLTAGE Vsat=3.5 V Typ. OUTPUT OFFSET VOLTAGE Vref=4.5 V Typ. SATURATION STATE (Ta=25 ˚C) 0.5 DARK STATE 1 V Typ. 0.4 0.3 0.2 0.1 GND KMPDC0152EA 0 200 400 ■ Block diagram RESET 1 CLK 2 600 800 1000 1200 WAVELENGTH (nm) KMPDB0220EA EXTSP Vms Vdd GND 4 5 6 7 3 TRIG SHIFT REGISTER 8 EOS 9 Video TIMING GENERATOR Vref 10 HOLD CIRCUIT Vgain 11 CHARGE AMP ARRAY Vpd 12 1 2 3 4 5 N-1 N PHOTODIODE ARRAY KMPDC0153EA 3 Photodiode array with amplifier S8865-256, S8865-256G ■ Timing chart 1 2 3 4 5 14 15 16 17 18 19 20 1 2 3 CLK tpw (RESET1) RESET tpw (RESET2) VIDEO OUTPUT PERIOD Video 1 2 n-1 n Trig EOS tf (CLK) tr (CLK) tpw (CLK1) tpw (CLK2) t1 tf (RESET) tpw (RESET1) t2 tpw (RESET2) tr (RESET) KMPDC0154EC Parameter Clock pulse width Clock pulse rise/fall times Reset pulse width 1 Reset pulse width 2 Reset pulse rise/fall times Clock pulse-reset pulse timing 1 Clock pulse-reset pulse timing 2 Symbol tpw (CLK1), tpw (CLK2) tr (CLK), tf (CLK) tpw (RESET1) tpw (RESET2) tr (RESET), tf (RESET) t1 t2 Min. 125 0 10 20 0 -20 -20 Typ. 20 20 0 0 Max. 12500 30 30 20 20 Unit ns ns µs µs ns ns ns 1. The internal timing circuit starts operation at a fall of CLK immediately after a RESET pulse sets to Low. 2. When a fall of CLK is counted as "1 clock", the video signal at the 1st channel appears between "18.5 clocks and 20 clocks". Then a video signal appears every 4 clocks. 3. Signal charge integration time equals the High period of a RESET pulse. However, the charge integration does not start at the rise of a RESET pulse but starts at the 8th clock after the rise of the RESET pulse and ends at the 8th clock after the fall of the RESET pulse. Signals integrated within this period are sequentially read out as time-series signals by the shift register operation when the RESET pulse next changes from High to Low. The rise and fall of a RESET pulse must be synchronized with the fall of a CLK pulse, but the rise of a RESET pulse must be set outside the video output period. One cycle of RESET pulses cannot be set shorter than the time equal to "(video signal readout period 16.5 + 4) × N (number of pixels)" clocks. 4 Photodiode array with amplifier S8865-256, S8865-256G ■ Dimensional outline (unit: mm) +0.2 51.2-0 (26 ×) 0.64 × 0.64 34.02 25 2 26 (× 4) 2.2 6.9 6.0 1 2.28 6.6 CMOS1 CMOS2 17.0 2.54 2.54 8.0 *11 40.0 ± 0.15 10.0 P2.54 × 12 = 30.48 3.0 PHOSPHOR SCREEN *12 40.0 1.6 PHOTODIODE 1 ch DIRECTION OF SCAN KMPDA0191EA *11: Distance from the bottom of the board to the center of active area Board: G10 glass epoxy Connector: JAE (Japan Aviation Electronics Industry, Limited) PS-26PE-D4LT1-PN1 *12:Photodiode array with phosphor screen: S8865-256G only · Material Gd2O2S: Tb · Phosphor thickness 300 µm Typ. · Detectable energy range 30k to 100 keV ■ Pin connection Pin No. CMOS1 1 Vpd 2 RESET 3 CLK 4 Trig 5 EXTSP 6 Vms 7 Vdd 8 GND 9 EOS 10 Video 11 Vref 12 Vg 13 Vpd Pin No. 14 15 16 17 18 19 20 21 22 23 24 25 26 CMOS2 Vpd RESET CLK Trig EXTSP Vms Vdd GND EOS Video Vref Vg Vpd Name Photodiode voltage Reset pulse Clock pulse Trigger pulse External start pulse M a ster/slave selection supply voltage Supply voltage Ground End of scan Video output Reference voltage Gain-selection terminal voltage Photodiode voltage Note Voltage input Pulse input Pulse input Positive-going pulse output Pulse input Voltage input Voltage input Negative-going pulse output Negative-going output with respect to Vref Voltage input Voltage input Voltage input 5 Photodiode array with amplifier S8865-256, S8865-256G ■ Gain selection terminal voltage setting Vdd: High gain (Cf: 0.5 pF) GND: Low gain (Cf: 1 pF) ■ Readout methods and settings Signals of channels 1 through 126 are output from CMOS1, while signals of channels 129 through 256 are output from CMOS2. The following two readout methods are available. (1) Serial readout method CMOS1 and CMOS2 are connected in serial and the signals of channels 1 through 256 are sequentially read out from one output line. Set CMOS1 as in “A” in the table below, and set CMOS2 as in “B”. CMOS1 and CMOS2 should be connected to the same CLK and RESET lines, and their video output terminals to one line. (2) Parallel readout method 128 channel signals are output in parallel respectively from the output lines of CMOS1 and CMOS2. Set both CMOS1 and CMOS2 as in “A” in the table below. ■ Connection example Serial readout method Parallel readout method CMOS1 CMOS1 1 Vpd RESET 1 RESET (1) RESET 2 RESET (1) CLK 2 CLK (1) CLK 3 CLK (1) Trig1 3 Trig (1) 4 EXTSP (1) 4 Trig (1) 5 Vms (1) 5 EXTSP (1) 6 Vms (1) Vdd 6 Vdd Vdd 7 Vdd GND 7 GND GND 8 GND EOS1 8 EOS (1) 9 EOS (1) Video1 9 Video (1) 10 Video (1) Vref 10 Vref Vref 11 Vref Vgain 11 Vgain Vgain 12 Vgain 12 Vpd 13 Vpd CMOS2 CMOS2 14 Vpd Trig 1 RESET (2) 2 CLK (2) 15 RESET (2) Trig2 16 CLK (2) OR Logic IC 74HC32 3 Trig (2) 17 Trig (2) 4 EXTSP (2) 18 EXTSP (2) 5 Vms (2) 19 Vms (2) 6 Vdd 7 GND 20 Vdd 21 GND EOS2 EOS 22 EOS (2) Video2 8 EOS (2) Video 23 Video (2) 10 Vref 24 Vref 11 Vgain 25 Vgain 12 Vpd 9 Video (2) 26 Vpd KMPDC0222EA Type A B Vms Vdd GND KMPDC0223EA EXTSP Vdd Preceding sensor EOS should be input ■ Readout circuit Check that pulse signals meet the required pulse conditions before supplying them to the input terminals. Video output should be amplified by an operational amplifier that is connected close to the sensor. ■ Cautions during use (1) The signal processing circuit chips of S8865 series are protected against static electricity. However, in order to prevent possible damage to the chip, implement electrostatic countermeasures such as grounding of the operator, work table and tools. Furthermore, the devices must be protected against surge voltages from external equipment. (2) Since the photodiode array chip is not protected, handle it carefully so it will not become contaminated or scratched. Photodiode array performance may deteriorate if operated at high temperatures and humidity, so the housing should be designed to be airtight. The signal processing circuit chip and its wire bonding are covered with a resin coating for protection, but never touch these portions. In addition, take care when installing the board so that it does not warp. (3) S8865-256G Signal processing IC chip performance will drop if subjected to X-rays. Protect the IC chip from X-rays by installing a lead shield. Information furnished by HAMAMATSU is believed to be reliable. However, no responsibility is assumed for possible inaccuracies or omissions. Specifications are subject to change without notice. No patent rights are granted to any of the circuits described herein. ©2006 Hamamatsu Photonics K.K. HAMAMATSU PHOTONICS K.K., Solid State Division 1126-1 Ichino-cho, Higashi-ku, Hamamatsu City, 435-8558 Japan, Telephone: (81) 53-434-3311, Fax: (81) 53-434-5184, www.hamamatsu.com U.S.A.: Hamamatsu Corporation: 360 Foothill Road, P.O.Box 6910, Bridgewater, N.J. 08807-0910, U.S.A., Telephone: (1) 908-231-0960, Fax: (1) 908-231-1218 Germany: Hamamatsu Photonics Deutschland GmbH: Arzbergerstr. 10, D-82211 Herrsching am Ammersee, Germany, Telephone: (49) 08152-3750, Fax: (49) 08152-2658 France: Hamamatsu Photonics France S.A.R.L.: 19, Rue du Saule Trapu, Parc du Moulin de Massy, 91882 Massy Cedex, France, Telephone: 33-(1) 69 53 71 00, Fax: 33-(1) 69 53 71 10 United Kingdom: Hamamatsu Photonics UK Limited: 2 Howard Court, 10 Tewin Road, Welwyn Garden City, Hertfordshire AL7 1BW, United Kingdom, Telephone: (44) 1707-294888, Fax: (44) 1707-325777 North Europe: Hamamatsu Photonics Norden AB: Smidesvägen 12, SE-171 41 Solna, Sweden, Telephone: (46) 8-509-031-00, Fax: (46) 8-509-031-01 Italy: Hamamatsu Photonics Italia S.R.L.: Strada della Moia, 1/E, 20020 Arese, (Milano), Italy, Telephone: (39) 02-935-81-733, Fax: (39) 02-935-81-741 6 Cat. No. KMPD1087E01 Jul. 2006 DN