HANBIT HMF51232M4D-90

HANBit
HMF51232M4D
FLASH-ROM MODULE 2MByte (512K x 32-Bit)
Part No. HMF51232M4D
GENERAL DESCRIPTION
The HMF51232M4D is a high-speed flash read only memory (FROM) module containing 524,288 words organized in a x32bit
configuration. The module consists of four 512Kx 8 FROM mounted on a 72-pin, single-sided, FR4-printed circuit board.
Commands are written to the command register using standard microprocessor write timings.
Register contents serve as input to an internal state-machine, which controls the erase and programming circuitry. Write cycles
also internally latch addresses and data needed for the programming and erase operations. Reading data out of the device is
similar to reading from 12.0V flash or EPROM devices.
Four chip enable inputs, (/CE_UU2, /CE_UM2, /CE_LM2, /CE_LL2) are used to enable the module’s 4 bytes independently.
Output enable (/OE) and write enable (/WE) can set the memory input and output.
When FROM module is disable condition, the module is becoming power standby mode, system designer can get low-power
design.
All module components may be powered from a single +5V DC power supply and all inputs and outputs are TTL-compatible.
PIN ASSIGNMENT
FEATURES
PIN
SYMBOL
PIN
1
Vss
2
A3
3
A2
4
A1
5
A0
6
Vcc
7
8
w Minimum 1,000,000 write/erase cycle
w Sector erases architecture
w Sector group protection
w Temporary sector group unprotection
w Part Identification
w Access time : 55,70, 90 and 120ns
w High-density 2MByte design
w High-reliability, low-power design
w Single + 5V ± 0.5V power supply
w Easy memory expansion
wAll inputs and outputs are TTL- compatible
w FR4-PCB design
w Low profile 72-pin SIMM
HMF51232M4D : Gold Plate Lead
OPTIONS
MARKING
w Timing
55ns access
- 55
70ns access
- 70
90ns access
- 90
120ns access
- 120
SYMBOL
PIN
SYMBOL
25
Vcc
49
DQ17
26
DQ8
50
DQ18
27
DQ9
51
DQ22
28
DQ10
52
DQ21
29
NC
53
DQ20
30
Vcc
54
DQ19
A11
31
/CE_LM2
55
Vcc
/OE
32
DQ15
56
A15
9
A10
33
DQ14
57
A12
10
Vcc
34
DQ13
58
A7
11
NC
35
DQ12
59
Vcc
12
/CE_LL2
36
DQ11
60
A8
13
DQ7
37
A18
61
A9
14
DQ0
38
A16
62
DQ24
15
DQ1
39
Vss
63
DQ25
16
DQ2
40
A6
64
DQ26
17
DQ6
41
Vcc
65
NC
18
DQ5
42
A5
66
/CE_UU2
19
DQ4
43
A4
67
DQ31
20
DQ3
44
Vcc
68
DQ30
21
/WE
45
NC
69
DQ29
22
A17
46
/CE_UM2
70
DQ28
23
A14
47
DQ23
71
DQ27
24
A13
48
DQ16
72
Vss
w Package
72-pin SIMM
72-PIN SIMM
TOP VIEW
M
FUNCTIONAL BLOCK DIAGRAM
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REV.02(August,2002)
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HANBit Electronics co., Ltd.
HANBit
HMF51232M4D
DQ0 - DQ31
A0 - A18
32
19
A0-18
/WE
DQ 0-7
U1
/OE
/CE
/CE_LL2
A0-18
/WE
DQ 8-15
U2
/OE
/CE
/CE_LM2
A0-18
/WE
DQ16-23
U3
/OE
/CE
/CE_UM2
A0-18
/WE
/WE
/OE
/OE
DQ24-31
U4
/CE
/CE_UU2
TRUTH TABLE
MODE
/OE
/CE
/WE
DQ
POWER
STANDBY
X
H
X
HIGH-Z
STANDBY
NOT SELECTED
H
L
H
HIGH-Z
ACTIVE
READ
L
L
H
Dout
ACTIVE
WRITE
X
L
L
Din
ACTIVE
Note : X means don't care
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REV.02(August,2002)
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HMF51232M4D
ABSOLUTE MAXIMUM RATINGS
PARAMETER
SYMBOL
RATING
VIN,OUT
-2.0V to +7.0V
Voltage with respect to ground Vcc
VCC
-2.0V to +7.0V
Power Dissipation
Po
4W
TSTG
-65oC to +125oC
Voltage with respect to ground all other pins
Storage Temperature
Operating Temperature
TA
-55oC to +125oC
w Stresses greater than those listed under " Absolute Maximum Ratings" may cause permanent damage to the device.
This is a stress rating only and functional operation of the device at these or any other conditions above those indicated
in the operating section of this specification is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS
SYMBOL
MIN
Vcc for ±5% device Supply Voltages
VCC
4.75V
5.25V
Vcc for ± 10% device Supply Voltages
Vcc
4.5V
5.5V
Ground
VSS
0
PARAMETER
TYP.
MAX
0
0
DC AND OPERATING CHARACTERISTICS (0oC ≤ TA ≤ 70 oC ; Vcc = 5V ± 0.5V )
PARAMETER
TEST CONDITIONS
SYMBOL
MI
N
TYP
MAX
UNITS
Input Load Current
Vin=Vss to, VCC, Vcc= Vcc Max
IL1
±1.0
µA
A9 Input Lodad Current
Vcc= Vcc Max, A9= 12.5V
IL1T
50
µA
Output Leakage Current
VOUT= VSS to VCC, VCC= VCC Max
IL0
±1.0
µA
Vcc Active Read Current(Note1,2)
/CE = VIL, /OE=VIH,
ICC1
80
120
mA
/CE = VIL, /OE=VIH
ICC2
120
160
mA
/CE= VIH
ICC3
4
20
mA
Vcc Active Write(Program/Erase)
Current(Note 2,3,4)
Vcc Standby Current(Note2)
Input Low Level
VIL
-0.5
0.8
V
Input High Level
VIH
2.0
Vcc+0.
V
5
Voltage for Autoselect
Vcc= 5.25V
VID
And Sector Protect
10.
12.5
V
0.45
V
5
Output Low Voltage
IOL = 12mA, Vcc =Vcc Min
VOL
Output High Voltage
IOH = -2.5mA, Vcc = Vcc Min
VOH
2.4
VLKO
3.2
Low Vcc Lock-Out Voltage
V
4.2
V
Notes:
1. The Icc current listed is typically less than 2mA/MHz, with /OE at VIH.
2. Icc active while embedded algorithm (program or erase) is in progress
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REV.02(August,2002)
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HMF51232M4D
3. Maximum Icc current specifications are tested with Vcc=Vcc max
ERASE AND PROGRAMMING PERFORMANCE
LIMITS
PARAMETER
MIN.
Sector Erase Time
-
Chip Erase Time
TYP.
UNIT
COMMENTS
MAX.
1
8
sec
Excludes 00H programming
8
64
sec
prior to erasure
Excludes system-level
Byte Programming Time
-
7
300
us
Chip Programming Time
-
3.6
10.8
sec
overhead
Notes:
1.
Typical program and erase times assume the follwing conditions:25°,5.0Vcc,1,000,000cycles.
Additionally,programming typicals assume checkerboard pattern.
2.
Under worst case conditions of 90°C, Vcc=4.5V(4.75V for-55), 1,000,000 cycles.
3.
The typical chip programming time is considerably less than the maximum chip programming time listed, since most
bytes program faster than the maximum byte program time listed. If the maximum byte program time given is
exceeded, only then does the device set DQ5= 1. See the section os DQ5for further information.
4.
In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.
5.
System-level overhead is the time required to execute the four-bus-cycle command sequence for programming. See
Table 4 for further in formation on command definitions.
6.
The device has a guaranteed minimum erase and program cycle endurance of 1,000,000cycles.
CAPACITANCE
PARAMETER
PARAMETER
SYMBOL
CIN
TEST SETUP
TYP.
MAX
UNIT
VIN = 0
6
7.5
pF
VOUT = 0
8.5
12
pF
VIN = 0
7.5
9
pF
DESCRIPTION
Input Capacitance
COUT
Output Capacitance
CIN2
Control Pin Capacitance
o
Notes : Test conditions TA = 25 C, f=1.0 MHz.
TEST CONDITIONS
TEST CONDITION
-55
Output load
ALL OTHERS
UNIT
1 TTL gate
Output load Capacitance, CL
30
100
pF
Input Rise and Fall Times
5
20
ns
0~3
0.45~2.4
V
Input Pulse Levels
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REV.02(August,2002)
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HANBit
HMF51232M4D
Input timing measurement reference levels
1.5
0.8
V
Output timing measurement reference levels
1.5
2.0
V
AC CHARACTERISTICS
u Read Only Operations Characteristics
PARAMETE
-55
-70
-90
-120
UNIT
TEST
DESCRIPTION
R
MIN
SETUP
MAX
MIN
MAX
MIN
MAX
MIN
MAX
SYMBOLS
tRC
Read Cycle Time
55
tACC
/CE = VIL
70
55
90
120
ns
70
Address to Output Delay
90
120
ns
/OE = VIL
tCE
Chip Enable to Output Delay
tOE
Chip Enable to Output Delay
tDF
Chip Enable to Output High-Z
tDF
Output Enable to Output High-Z
/OE = VIL
55
70
90
120
ns
30
30
35
50
ns
0
0
18
Output Hold Time From
0
20
0
20
ns
35
ns
0
ns
0
Addresses,
tQH
0
0
/CE or /OE, Whichever Occurs
First
5.0V
2.7kΩ
IN3064
or Equivalent
Device
Under
Test
CL
6.2kΩ
Diodes = IN3064
or Equivalent
Note : CL = 100pF including jig capacitance
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REV.02(August,2002)
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HMF51232M4D
u Erase/Program Operations
PARAMETE
-55
DESCRIPTION
R
MIN
-70
TYP
MIN
-90
MAX
MIN
-120
MAX
MIN
MAX
UNIT
SYMBOLS
tWC
Write Cycle Time
tAS
Address Setup Time
tAH
Address Hold Time
40
45
45
50
ns
tDS
Data Setup Time
25
30
45
50
ns
tDH
Data Hold Time
0
ns
tOES
Output Enable Setup Time
0
ns
Read Recover Time Before Write
0
ns
tCS
/CE Setup Time
0
ns
tCH
/CE Hold Time
0
ns
tWP
Write Pulse Width
tWPH
Write Pulse Width High
20
ns
tWHWH1
Byte Programming Operation
7
µs
tWHWH2
Sector Erase Operation (Note1)
1
sec
Vcc set up time
50
µs
tGHWL
tVCS
55
70
90
120
ns
0
30
35
ns
45
50
ns
Notes :
1. This does not include the preprogramming time
2. This timing is only for Sector Protect operations
u Erase/Program Operations
Alternate /CE Controlled Writes
PARAMETE
-55
DESCRIPTION
R
-70
MIN
TYP
MIN
55
ns
70
-90
MAX
MIN
-120
MAX
MIN
MAX
UNIT
SYMBOLS
tWC
Write Cycle Time
tAS
Address Setup Time
tAH
Address Hold Time
40
ns
45
45
50
ns
tDS
Data Setup Time
25
ns
30
45
50
ns
tDH
Data Hold Time
0
ns
Read Recover Time Before Write
0
ns
tWS
/WE Setup Time
0
ns
tWH
/WE Hold Time
0
ns
tGHEL
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REV.02(August,2002)
90
120
0
6
ns
ns
HANBit Electronics co., Ltd.
HANBit
HMF51232M4D
tCP
/CE Pulse Width
30
ns
35
45
50
ns
tCPH
/CE Pulse Width High
20
ns
tWHWH1
Byte Programming Operation
7
µs
tWHWH2
Sector Erase Operation (Note)
1
sec
Notes : This does not include the preprogramming time.
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REV.02(August,2002)
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HMF51232M4D
u READ OPERATIONS TIMING
u RESET TIMING
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REV.02(August,2002)
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HMF51232M4D
u PROGRAM OPERATIONS TIMING
u CHIP/SECTOR ERASE OPERATION TIMINGS
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REV.02(August,2002)
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HMF51232M4D
u DATA# POLLING TIMES(DURING EMBEDDED ALGORITHMS)
u TOGGLE# BIT TIMINGS (DURING EMBEDDED ALGORITHMS)
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REV.02(August,2002)
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HMF51232M4D
u SECTOR PROTECT UNPROTECT TIMEING DIAGRAM
u ALTERNATE CE# CONTROLLED WRITE OPERATING TIMINGS
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REV.02(August,2002)
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HMF51232M4D
PACKAGE DIMENSIONS
2.54
mm
MIN
0.25 mm MAX
1.27±0.08mm
Gold: 1.04±0.10 mm
Solder: 0.914±0.10 mm
1.27
(Solder & Gold Plating)
ODERING INFORMATION
Part Number
Density
Org.
Package
HMF51232M4D-55
2MByte
512K×32bit
72 Pin-SIMM
HMF51232M4D-70
2MByte
512K×32bit
HMF51232M4D-90
2MByte
HMF51232M4D-120
2MByte
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REV.02(August,2002)
Component
Vcc
SPEED
4EA
5.0V
55ns
72 Pin-SIMM
4EA
5.0V
70ns
512K×32bit
72 Pin-SIMM
4EA
5.0V
90ns
512K×32bit
72 Pin-SIMM
4EA
5.0V
120ns
12
Number
HANBit Electronics co., Ltd.