HANBit HMNR28D(V) 5.0 or 3.3V, 16K bit (2 Kbit x 8) TIMEKEEPER NVSRAM Part No. HMNR28D(V) GENERAL DESCRIPTION The HMNR28D(V) TIMEKEEPER SRAM is a 2Kb x 8 non-volatile static RAM and real time clock organized as 2,048 words by 8 bits. The special DIP package provides a fully integrated battery back-up memory and real time clock solution. The HMNR28D(V) directly replaces industry standard 2Kbit x 8 SRAMs. It also provides the non-volatility of Flash without any requirement for special WRITE timing or limitations on the number of WRITEs that can be performed. FEATURES ■ INTEGRATED LOW POWER SRAM, REAL TIME CLOCK, POWER-FAIL CONTROL CIRCUIT, BATTERY and CRYSTAL ■ BCD CODED YEAR, MONTH, DAY, DATE, HOURS, MINUTES, and SECONDS ■ AUTOMATIC POWER-FAIL CHIP DESELECT and WRITE PROTECTION VOLTAGES : (VPFD = Power-fail Deselect Voltage) – HMNR28D : VCC = 4.5 to 5.5V 4.2V ≤ VPFD ≤ 4.5V – HMNR28DV: VCC = 3.0 to 3.6V 2.7V ≤ VPFD ≤ 3.0V ■ CONVENTIONAL SRAM OPERATION : UNLIMITED WRITE CYCLES ■ SOFTWARE CONTROLLED CLOCK CALIBRATION FOR HIGH ACCURACY APPLICATIONS ■ 10 YEARS OF DATA RETENTION and CLOCK OPERATION IN THE ABSENCE OF POWER PIN and FUNCTION COMPATIBLE WITH INDUSTRY STANDARD 2K x 8 SRAMS ■ SELF-CONTAINED BATTERY and CRYSTAL IN DIP PACKAGE OPTIONS MARKING PIN ASSIGNMENT w Timing 70 ns -70 85 ns -85 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 Vss 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 Vcc A8 A9 /WE /OE A10 /CE DQ7 DQ6 DQ5 DQ4 DQ3 24-pin Encapsulated Package URL : www.hbe.co.kr Rev. 0.0 (March, 2002) 1 HANBit Electronics Co.,Ltd. HANBit HMNR28D(V) FUNCTIONAL DESCRIPTION The HMNR28D(V) is a full function, year 2000 compliant (Y2KC), real– time clock/calendar (RTC) and 2k x 8 non-volatile static RAM. User access to all registers within the HMNR28D(V) is accomplished with a bytewide interface . The Realtime clock (RTC) information and control bits reside in the sixteen upper most RAM locations. The RTC registers contain century, year, month, date, day, hours, minutes, and seconds data in 24-hour BCD format. Corrections for the date of each month and leap year are made automatically. The RTC clock registers are double buffered to avoid access of incorrect data that can occur during clock update cycles. The double buffered system also prevents time loss as the timekeeping countdown continues unabated by access to time register data. The HMNR28D(V) also contains its own power-fail circuitry which deselects the device when the VCC supply is in an out of tolerance condition. This feature prevents loss of data from unpredictable system operation brought on by low VCC as errant access and update cycles are avoided. BLOCK DIAGRAM 16 x 8 TIMEKEEPER REGISTER OSCILLATOR AND CLOCK CHAIN 32.768KHz CRYSTAL A0 ~ A10 POWER 2,032 x 8 SRAM ARRAY LITHIUM CELL VPFD /CE VOLTAGE SENSE AND SWITCHING CIRCURITY /WE /OE Vcc Vss A0-A10 : Address Input /WE : Write Enable /CE : Chip Enable /OE : Output Enable Vss : Ground VCC : Power (+5V or +3.3V) DQ0-DQ7 : Data In / Data Out NC : No Connection URL : www.hbe.co.kr Rev. 0.0 (March, 2002) DQ0 ~ DQ7 2 HANBit Electronics Co.,Ltd. HANBit HMNR28D(V) Absolute Maximum Ratings Symbol Parameter Value Unit TA AmbientOperatingTemperature 0 to 70 °C TSTG Storage Temperature(Vcc Off, Oscillator Off) -40 to 70 °C Lead Solder Temperature for 10 seconds 260 °C Input or Output Voltage TSLD (1) VIO VCC Supply Voltage -0.3 to Vcc+0.3 V HMNR28D 4.5 to 5.5 V HMNR28DV 3.0 to 3.6 V IO Output Current 20 mA PD Power Dissipation 1 W Note : Permanent device damage may occur if Absolute Maximum Ratings are exceeded. Functional operation should be restricted to the Recommended DC Operating Conditions detailed in this data sheet. Exposure to higher than recommended voltage for extended periods of time could affect device reliability. (1) Soldering temperature not to exceed 260° C for 10 seconds (Total thermal budget not to exceed 150° C for longer than 30 seconds). Caution : Negative undershoots below – 0.3V are not allowed on any pin while in the Battery Back-up mode. Operating and AC Measurement Conditions Parameter HMNR28D HMNR28DV Unit VCC Supply Voltage 4.5 to 5.5 3.0 to 3.6 V Ambient Operating Temperature 0 to 70 0 to 70 °C Load Capacitance (CL ) 100 50 pS Input Rise and Fall Times ≤ 5 ≤ 5 nS Input Pulse Voltages 0 to 3 0 to 3 V Input and Output Timing Ref. Voltages 1.5 1.5 V AC Measurement Load Circuit Note : 50pF for HMNR28DV URL : www.hbe.co.kr Rev. 0.0 (March, 2002) 3 HANBit Electronics Co.,Ltd. HANBit HMNR28D(V) Capacitance Symbol Parameter Max Unit Input Capacitance 10 pF Input/Output Capacitance 10 pF CIN (3) COUT (1,2) Min Note : 1. Effective capacitance measured with power supply at 5V (HMNR28D) or 3.3V (HMNR28DV). Sampled only, not 100% tested. 2. At 25° C, f = 1MHz. 3. Outputs deselected. DC Characteristics HMNR28D HMNR28DV Parameter ILI Input Leakage Current 0V ≤ VIN ≤ VCC ± 1 ± 1 uA Output Leakage Current 0V ≤ VOUT ≤ VCC ± 1 ± 1 uA Supply Current Outputs open 10 mA ILO (2) ICC ICC1 ICC2 Supply Current (Standby) TTL Supply Current (Standby) CMOS Test Condition (1) Symbol Min 8 3 2 mA 800 nA 100 nA 0.8 V 575 VIH Input High Voltage 2.2 Output High Voltage 800 575 100 -0.3 VOH Unit /CE=VCC-0.2 Input Low Voltage (open drain) (4) 4 Max mA VIL Output Low Voltage 15 Typ 3 OFF VOL Min 5 Battery Current OSC Output Low Voltage Max /CE=VIH Battery Current OSC ON IBAT Typ 0.8 VCC +0.3 -0.3 VCC 2.0 +0.3 V IOL=2.1mA 0.4 0.4 V IOL=10mA 0.4 0.4 V IOH=-1.0mA 2.4 2.0 2.4 VOHB VOH Battery Back-up IOUT2=-1.0uA 3.6 V IOUT1 VOUT Current (Active) VOUT1 > VCC-0.3 100 70 mA VOUT2>VBAT-0.3 100 100 uA 3.0 V IOUT2 VPFD VSO VBAT VOUT Current (Battery Back-up) Power-fail Deselect 4.1 Voltage 3.6 V 4.35 4.5 2.0 2.7 2.9 VPFD- Battery Back-up 3.0 Switchover Voltage 100 V mV Battery Voltage 3.0 3.0 V Note: 1. Valid for Ambient Operating Temperature: TA =0 to 70° C or 40 to 85°C ; VCC = 4.5 to 5.5V or 3.0 to 3.6V (except where noted). 2. Outputs deselected. URL : www.hbe.co.kr Rev. 0.0 (March, 2002) 4 HANBit Electronics Co.,Ltd. HANBit HMNR28D(V) OPERATING MODES The 24-pin, 600mil DIP Hybrid houses a controller chip, SRAM, quartz crystal, and a long life lithium button cell in a single package. The clock locations contain the year, month, date, day, hour, minute, and second in 24 hour BCD format. Corrections for 28, 29 (leap year-compliant until the year 2100), 30, and 31 day months are made automatically. Byte 7F8h is the clock control register. This byte controls user access to the clock information and also stores the clock calibration setting. The seven clock bytes (7FFh-7F9h) are not the actual clock counters, they are memory locations consisting of READ/WRITE memory cells within the static RAM array. The HMNR28D includes a clock control circuit which updates the clock bytes with current information once per second. The information can be accessed by the user in the same manner as any other location in the static memory array. The HMNR28D(V) also has its own Power-Fail Detect circuit. This control circuitry constantly monitors the supply voltage for an out of tolerance condition. When VCC is out of tolerance, the circuit write protects the TIMEKEEPER register data and SRAM, providing data security in the midst of unpredictable system operation. As VCC falls, the control circuitry automatically switches to the battery, maintaining data and clock operation until valid power is restored. Operating Modes Mode Deselect WRITE READ READ Deselect Deselect VCC 4.5V to 5.5V or 3.0V to 3.6V VSO to VPFD (min) ≤ VSO (1) /CE /OE /WE DQ7 – DQ0 Power VIH X X High-Z Standby VIL X VIL DIN Active VIL VIL VIH DOUT Active VIL VIH VIH High X X X X X X High High Active CMOS Standby Battery Backup Note : X = VIH or VIL; VSO = Battery Back-up Switchover Voltage. URL : www.hbe.co.kr Rev. 0.0 (March, 2002) 5 HANBit Electronics Co.,Ltd. HANBit HMNR28D(V) READ Mode The HMNR28D(V) is in the READ Mode whenever /WE (WRITE Enable) is high and /CE (Chip Enable) is low. The unique address specified by the 15 Address Inputs defines which one of the 32,768 bytes of data is to be accessed. Valid data will be available at the Data I/O pins within Address Access Time (tAVQV) after the last address input signal is stable, providing the /CE and /OE access times are also satisfied. If the /CE and /OE access times are not met, valid data will be available after the latter of the Chip Enable Access Times (tELQV) or Output Enable Access Time (tGLQV). The state of the eight three-state Data I/O signals is controlled by /CE and /OE. If the outputs are activated before tAVQV, the data lines will be driven to an indeterminate state until tAVQV. If the Address Inputs are changed while /CE and /OE remain active, output data will remain valid for Output Data Hold Time (tAXQX) but will go indeterminate until the next Address Access. READ Mode AC Waveforms A0-A10 /CE /OE Note : /WE = High. READ Mode AC Characteristics HMNR28D Symbol Parameter HMNR28DV -70 Min Unit -85 Max Max tAVAV READ Cycle Time tAVQV Address Valid to Output Valid 70 85 nS tELQV Chip Enable Low to Output Valid 70 85 nS tGLQV Output Enable Low to Output Valid 25 35 nS (2) tELQX 70 Min 85 nS Chip Enable Low to Output Transition 5 5 nS tGLQX (2) Output Enable Low to Output Transition 0 0 nS tEHQZ (2) Chip Enable High to Output Hi-Z tGHQZ (2) tAXQX 20 Output Enable High to Output Hi-Z 20 Address Transition to Output Transition 5 5 25 nS 25 nS nS Note: 1.Valid for Ambient Operating Temperature: TA = 0 to 70° C; VCC = 4.5 to 5.5V or 3.0 to 3.6V (except where noted). 2. CL = 5pF. URL : www.hbe.co.kr Rev. 0.0 (March, 2002) 6 HANBit Electronics Co.,Ltd. HANBit HMNR28D(V) WRITE Mode The HMNR28D(V) is in the WRITE Mode whenever /WE (WRITE Enable) and /CE (Chip Enable) are low state after the address inputs are stable. The start of a WRITE is referenced from the latter occurring falling edge of /WE or /CE. A WRITE is terminated by the earlier rising edge of /WE or /CE. The addresses must be held valid throughout the cycle. /CE or /WE must return high for a minimum of tEHAX from Chip Enable or tWHAX from WRITE Enable prior to the initiation of another READ or WRITE cycle. Data-in must be valid tDVWH prior to the end of WRITE and remain valid for tWHDX afterward. /OE should be kept high during WRITE cycles to avoid bus contention; although, if the output bus has been activated by a low on /CE and /OE a low on /WE will disable the outputs tWLQZ after /WE falls. WRITE AC Waveforms, WRITE Enable Controlled A0-A10 WRITE AC Waveforms, Chip Enable Controlled A0-A10 URL : www.hbe.co.kr Rev. 0.0 (March, 2002) 7 HANBit Electronics Co.,Ltd. HANBit HMNR28D(V) WRITE Mode AC Characteristics Parameter Symbol HMNR28D HMNR28DV -70 -85 (1) Min Max Min Unit Max tAVAV WRITE Cycle Time 70 85 nS tAVWL Address Valid to WRITE Enable Low 0 0 nS tAVEL Address Valid to Chip Enable Low 0 0 nS tWLWH WRITE Enable Pulse Width 45 55 nS tELEH Chip Enable Low to Chip Enable High 50 60 nS tWHAX WRITE Enable High to Address Transition 0 0 nS tEHAX Chip Enable High to Address Transition 0 0 nS tDVWH Input Valid to WRITE Enable High 25 30 nS tDVEH Input Valid to Chip Enable High 25 30 nS tWHDX WRITE Enable High to Input Transition 0 0 nS tEHDX Chip Enable High to Input Transition 0 0 nS tWLQZ (2,3) WRITE Enable Low to Output High-Z 20 25 nS tAVWH Address Valid to WRITE Enable High 55 65 nS tAVEH Address Valid to Chip Enable High 55 65 nS WRITE Enable High to Output Transition 5 5 nS tWHQX (2,3) Note : 1. Valid for Ambient Operating Temperature: TA = 0 to 70° C; VCC = 4.5 to 5.5V or 3.0 to 3.6V (except where noted). 2. CL = 5pF. 3. If /CE goes low simultaneously with /WE going low, the outputs remain in the high impedance state. Data Retention Mode With valid VCC applied, the HMNR28D(V) operates as a conventional Bytewide static RAM. Should the supply voltage decay, the RAM will automatically deselect, write protecting itself when VCC falls between VPFD (max), VPFD (min) window. All outputs become high impedance and all inputs are treated as “Don't care.” Note : A power failure during a WRITE cycle may corrupt data at the current addressed location, but does not jeopardize the rest of the RAM's content. At voltages below VPFD (min), the memory will be in a write protected state, provided the VCC fall time is not less than tF. The HMNR28D(V) may respond to transient noise spikes on VCC that cross into the deselect window during the time the device is sampling VCC. Therefore, decoupling of the power supply lines is recommended. When VCC drops below VSO, the control circuit switches power to the internal battery, preserving data and powering the clock. The internal energy source will maintain data in the HMNR28D(V) for an accumulated period of at least 10 years at room temperature. As system power rises above VSO, the battery is disconnected, and the power supply is switched to external VCC . Write protection continues until VCC reaches VPFD (min) plus tREC (min). Normal RAM operation can resume tREC after VCC exceeds VPFD (max). URL : www.hbe.co.kr Rev. 0.0 (March, 2002) 8 HANBit Electronics Co.,Ltd. HANBit HMNR28D(V) Power Down/Up Mode AC Waveforms Power Down/Up AC Characteristics Symbol Parameter Min (2) tF VPFD (max) to VPFD (min) VCC Fall Time 300 uS HMNR28D 10 uS HMNR28DV (3) tFB VPFD (min) to VSS VCC Fall Time tR tREC Unit 150 uS VPFD (min) to VPFD (max) VCC Rise Time 10 uS VPFD (max) to RST High 40 VSS to VPFD (min) VCC Rise Time 5 (4) tRB Max 200 uS uS Note : 1. Valid for Ambient Operating Temperature: TA = 0 to 70° C; VCC = 4.5 to 5.5V or 3.0 to 3.6V (except where noted). 2. VPFD (max) to VPFD (min) fall time of less than tF may result in deselection/write protection not occurring until 200µs after VCC passes VPFD (min). 3. VPFD (min) to VSS fall time of less than tFB may cause corruption of RAM data. Power Down/Up Trip Points DC Characteristics Parameter Symbol VPFD VSO Power-fail Deselect Voltage (1,2) Min Typ Max Unit HMNR28D 4.2 4.35 4.5 V HMNR28DV 2.7 2.9 3.0 V Battery Back-up Switchover HMNR28D 3.0 V Voltage HMNR28DV VPFD-100mV V TDR(3) Expected Data Retention Time 10 YEARS Note: 1. All voltages referenced to VSS . 2. Valid for Ambient Operating Temperature: TA = 0 to 70° C; VCC = 4.5 to 5.5V or 3.0 to 3.6V (except where noted). 3. At 25° C. URL : www.hbe.co.kr Rev. 0.0 (March, 2002) 9 HANBit Electronics Co.,Ltd. HANBit HMNR28D(V) Register Map Address Funtion / Data D7 D6 7FE 0 0 7FD 0 0 7FC 0 FT 7FB 0 0 7FA 0 7F9 ST 7F8 W R S 7F7 0 0 0 0 0 0 0 0 7F6 0 0 0 0 0 0 0 0 7F5 0 0 0 0 0 0 0 0 7F4 0 0 0 0 0 0 0 0 7F3 0 0 0 0 0 0 0 0 7F2 0 0 0 0 0 0 0 0 BL 0 7FF D4 D3 D2 10Years 7F1 7F0 D5 0 0 0 Year Year 00-99 Month 01-12 Date : Day of Month Date 01-31 0 10 Hours Day 01-07 Hours(24 Hour Format) Day Hours 00-23 Minutes Minutes 00-59 Seconds Seconds 00-59 10 Minutes 10 Seconds Calibration 1000 Years 0 0 0 D0 Month 10M 10 Date D1 Range BCD Format Control 100 Years 0 0 Century 0 00-99 Flag Keys : R = READ Bit W = WRITE Bit ST = Stop Bit 0 = Must be set to ’0’ BL = Battery Low Flag S = Sign Bit CLOCK OPERATIONS The HMNR28D(V) offers 16 internal registers which contain TIMEKEEPER, and Control data. These registers are memory locations which contain external (user accessible) and internal copies of the data. The external copies are independent of internal functions except that they are updated periodically by the simultaneous transfer of the incremented internal copy. TIMEKEEPER Registers store data in BCD. Control Registers store data in Binary Format. Reading the Clock Updates to the TIMEKEEPER registers should be halted before clock data is read to prevent reading data in transition. The TIMEKEEPER cells in the RAM array are only data registers and not the actual clock counters, so updating the registers can be halted without disturbing the clock itself. Updating is halted when a ’1’is written to the READ Bit, D6 in the Control Register (7F8h). As long as a ’1’remains in that position, updating is halted. After a halt is issued, the registers reflect the count; that is, the day, date, and time that were current at the moment the halt command was is-sued. All of the TIMEKEEPER registers are updated simultaneously. A halt will not interrupt an update in progress. Updating occurs approximately 1 second after the READ Bit is reset to a ’0.’ URL : www.hbe.co.kr Rev. 0.0 (March, 2002) 10 HANBit Electronics Co.,Ltd. HANBit HMNR28D(V) Setting the Clock Bit D7 of the Control Register (7F8h) is the WRITE Bit. Setting the WRITE Bit to a ’1,’like the READ Bit, halts updates to the TIMEKEEPER reg-isters. The user can then load them with the correct day, date, and time data in 24-hour BCD format. Resetting the WRITE Bit to a ’0’then transfers the values of all time registers (7Fh-7F9h, 7F1h) to the actual TIMEKEEPER counters and allows normal operation to resume. After the WRITE Bit is reset, the next clock update will occur approximately one second later. Note: Upon power-up following a power failure, both the WRITE Bit and the READ Bit will be reset to ’0.’ Stopping and Starting the Oscillator The oscillator may be stopped at any time. If the device is going to spend a significant amount of time on the shelf, the oscillator can be turned off to minimize current drain on the battery. The STOP Bit is located at Bit D7 within the Seconds Register (7F9h). Setting it to a ’1’stops the oscillator. When reset to a ’0,’the HMNR28D oscillator starts within one second. Note : It is not necessary to set the WRITE Bit when setting or resetting the STOP Bit (ST). Calibrating the Clock The HMNR28D(V) is driven by a quartz controlled oscillator with a nominal frequency of 32,768Hz. The devices are factory calibrated at 25° C and tested for accuracy. Clock accuracy will not exceed 35 ppm (parts per million) oscillator frequency error at 25° C, which equates to about ± 1.53 minutes per month. When the Calibration circuit is properly employed, accuracy improves to better than +1/-2 ppm at 25° C. The oscillation rate of crystals changes with temperature. The HMNR28D design employs periodic counter correction. The calibration circuit adds or subtracts counts from the oscillator divider circuit at the divide by 256 stage. The number of times pulses are blanked (subtracted, negative calibration) or split (added, positive calibration) depends upon the value loaded into the five Calibration bits found in the Control Register. Adding counts speeds the clock up, subtracting counts slows the clock down. The Calibration bits occupy the five lower order bits (D4-D0) in the Control Register 7F8h. These bits can be set to represent any value between 0 and 31 in binary form. Bit D5 is a Sign bit; '1' indicates positive calibration, '0' indicates negative calibration. Calibration occurs within a 64 minute cycle. The first 62 minutes in the cycle may, once per minute, have one second either shortened by 128 or lengthened by 256 oscillator cycles. If a binary '1' is loaded into the register, only the first 2 minutes in the 64 minute cycle will be modified; if a binary 6 is loaded, the first 12 will be affected, and so on. Therefore, each calibration step has the effect of adding 512 or subtracting 256 oscillator cycles for every 125, 829, 120 actual oscillator cycles; that is, +4.068 or 2.034 ppm of adjustment per calibration step in the calibration register. Assuming that the oscillator is running at exactly 32,768Hz, each of the 31 increments in the Calibration byte would represent +10.7 or -5.35 seconds per month which corresponds to a total range of +5.5 or -2.75 minutes per month. One method for ascertaining how much calibration a given HMNR28D(V) may require involves setting the clock, letting it run for a month and comparing it to a known accurate reference and recording deviation over a fixed period of time. This allows the designer to give the end user the ability to calibrate the clock as the environment requires, even if the final product is packaged in a nonuser serviceable enclosure. The designer could provide a simple utility that accesses the Calibration bits. URL : www.hbe.co.kr Rev. 0.0 (March, 2002) 11 HANBit Electronics Co.,Ltd. HANBit HMNR28D(V) Battery Low Warning The HMNR28D(V) automatically performs battery voltage monitoring upon power-up and at factory-programmed time intervals of approximately 24 hours. The Battery Low (BL) Bit, Bit D4 of Flags Register 7F0h, will be asserted if the battery voltage is found to be less than approximately 2.5V. The BL Bit will remain asserted until completion of battery replacement and subsequent battery low monitoring tests, either during the next power-up sequence or the next scheduled 24hour interval. If a battery low is generated during a power-up sequence, this indicates that the battery is below approximately 2.5V and may not be able to maintain data integrity in the SRAM. Data should be considered suspect and verified as correct. A fresh battery should be installed. If a battery low indication is generated during the 24-hour interval check, this indicates that the battery is near end of life. However, data is not compromised due to the fact that a nominal VCC is supplied. In order to insure data integrity during Power Supply Decoupling and Undershoot Protection Note: ICC transients, including those produced by output switching, can produce voltage fluctuations, resulting in spikes on the VCC bus. These transients can be reduced if capacitors are used to store energy which stabilizes the VCC bus. The energy stored in the bypass capacitors will be released as low going spikes are generated or energy will be absorbed when overshoots occur. A ceramic bypass capacitor value of 0.1uF is recommended in order to provide the needed filtering. In addition to transients that are caused by normal SRAM operation, power cycling can generate negative voltage spikes on VCC that drive it to values below VSS by as much as one volt. These negative spikes can cause data corruption in the SRAM while in battery backup mode. To protect from these voltage spikes, ST recommends connecting a schottky diode from VCC to VSS (cathode connected to VCC, anode to VSS). (Schottky diode 1N5817 is recommended for through hole and MBRS120T3 is recommended for surface mount). URL : www.hbe.co.kr Rev. 0.0 (March, 2002) 12 HANBit Electronics Co.,Ltd. HANBit HMNR28D(V) PACKAGE DIMENSION Dimension Min Max A 1.470 1.500 B 0.710 0.740 C 0.365 0.375 D 0.012 - E 0.008 0.013 F 0.590 0.630 G 0.017 0.023 H 0.090 0.110 I 0.075 0.110 J 0.120 0.150 J A I H G B C D E F ORDERING INFORMATION H M N R 2 8 D V – 70 I Operating Temperature : I = Industrial Temp. (-40~85 °C ) Blank = Commercial Temp. (0~70°C) Speed options : 70 = 70 ns 85 = 85 ns Operating Voltage : Blank = 5V V = 3.3V Dip type package Device : 2K x 8 Nonvolatile Timekeeping SRAM HANBit Memory Module URL : www.hbe.co.kr Rev. 0.0 (March, 2002) 13 HANBit Electronics Co.,Ltd.