HANBIT HSD16M32D4-10

HANBit
HSD16M32D4
Synchronous DRAM Module 64Mbyte(16Mx32-Bit), 100pin DIMM,
4Banks, 8K Ref., 3.3V
Part No. HSD16M32D4
GENERAL DESCRIPTION
The HSD16M32D4 is a 16M x 32 bit Synchronous Dynamic RAM high density memory module. The module consists of
four CMOS 2M x 16 bit x 4banks Synchronous DRAMs in TSOP-II 400mil packages on a 100-pin glass-epoxy substrate.
Two 0.1uF decoupling capacitors are mounted on the printed circuit board in parallel for each SDRAM. The HSD16M32D4
is a DIMM( Dual in line Memory Module) and is intended for mounting into 100-pin edge connector sockets. Synchronous
design allows precise cycle control with the use of system clock. I/O transactions are possible on every clock cycle. Range
of operating frequencies, programmable latencies allows the same device to be useful for a variety of high bandwidth, high
performance memory system applications All module components may be powered from a single 3.3V DC power supply
and all inputs and outputs are LVTTL-compatible.
FEATURES
• Part Identification
HSD16M32D4-10 : 100MHz (CL=2)
HSD16M32D4-10L : 100MHz (CL=3)
HSD16M32D4-12 : 125MHz (CL=3)
HSD16M32D4-13 : 133MHz (CL=3)
• Burst mode operation
• Auto & self refresh capability (8192 Cycles/64ms)
• LVTTL compatible inputs and outputs
• Single 3.3V ±0.3V power supply
• MRS cycle with address key programs
- Latency (Access from column address)
- Burst length (1, 2, 4, 8 & Full page)
- Data scramble (Sequential & Interleave)
• All inputs are sampled at the positive going edge of the system clock
• The used device is 4M x 16bit x 4Banks SDRAM
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HSD16M32D4
PIN ASSIGNMENT
PIN
Symbol
PIN
Symbol
PIN
Symbol
PIN
Symbol
1
Vss
26
VSS
51
VSS
76
VSS
2
DQ0
27
CKE0
52
DQ8
77
CKE1
3
DQ1
28
/WE
53
DQ9
78
NC
4
DQ2
29
/CS0
54
DQ10
79
/CS1
5
DQ3
30
/CS2
55
DQ11
80
/CS3
6
Vcc
31
VCC
56
VCC
81
VCC
7
DQ4
32
NC
57
DQ12
82
NC
8
DQ5
33
NC
58
DQ13
83
NC
9
DQ6
34
NC
59
DQ14
84
NC
10
DQ7
35
NC
60
DQ15
85
NC
11
DQM0
36
VSS
61
DQM1
86
VSS
12
Vss
37
DQM2
62
VSS
87
DQM3
13
A0
38
DQ16
63
A1
88
DQ24
14
A2
39
DQ17
64
A3
89
DQ25
15
A4
40
DQ18
65
A5
90
DQ26
16
A6
41
DQ19
66
A7
91
DQ27
17
A8
42
VCC
67
A9
92
VCC
18
A10
43
DQ20
68
BA0
93
DQ28
19
BA1
44
DQ21
69
A11
94
DQ29
20
NC
45
DQ22
70
NC
95
DQ30
21
VCC
46
DQ23
71
VCC
96
DQ31
22
NC
47
VSS
72
/RAS
97
VSS
23
NC
48
SDA
73
/CAS
98
SA0
24
NC
49
SCL
74
NC
99
SA1
25
CLK0
50
VCC
75
CLK1
100
SA2
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HANBit
HSD16M32D4
FUNCTIONAL BLOCK DIAGRAM
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HSD16M32D4
PIN FUNCTION DESCRIPTION
PIN
NAME
INPUT FUNCTION
CLK
System clock
Active on the positive going edge to sample all inputs.
/CS 0~3
Chip enable
Disables or enables device operation by masking or enabling all inputs except
CLK, CKE and DQM
CKE
Clock enable
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one cycle prior to new command.
Disable input buffers for power down in standby.
CKE should be enabled 1CLK+tSS prior to valid command.
A0 ~ A11
Address
Row/column addresses are multiplexed on the same pins.
Row address : RA0 ~ RA11, Column address : CA0 ~ CA8
BA0 ~ BA1
Bank select address
Selects bank to be activated during row address latch time.
Selects bank for read/write during column address latch time.
/RAS
Row address strobe
Latches row addresses on the positive going edge of the CLK with RAS low.
Enables row access & precharge.
/CAS
Column address strobe
Latches column addresses on the positive going edge of the CLK with CAS low.
Enables column access.
/WE
Write enable
Enables write operation and row precharge.
Latches data in starting from CAS, WE active.
DQM0 ~ 3
Data input/output mask
Makes data output Hi-Z, tSHZ after the clock and masks the output.
Blocks data input when DQM active. (Byte masking)
DQ0 ~DQ 32
Data input/output
Data inputs/outputs are multiplexed on the same pins.
VDD/VSS
Power supply/ground
Power and ground for the input buffers and the core logic.
ABSOLUTE MAXIMUM RATINGS
PARAMETER
SYMBOL
RATING
VIN ,OUT
-1V to 4.6V
Voltage on Vcc Supply Relative to Vss
Vcc
-1V to 4.6V
Power Dissipation
PD
4W
TSTG
-55oC to 150oC
Voltage on Any Pin Relative to Vss
Storage Temperature
Short Circuit Output Current
IOS
400mA
Notes:
Permanent device damage may occur if " Absolute Maximum Ratings" are exceeded. Functional operation should be
restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
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HSD16M32D4
DC OPERATING CONDITIONS
(Recommended operating conditions (Voltage referenced to VSS = 0V, TA = 0 to 70° C) )
PARAMETER
SYMBOL
MIN
TYP.
MAX
UNIT
NOTE
Supply Voltage
Vcc
3.0
3.3
3.6
V
Input High Voltage
VIH
2.0
3.0
Vcc+0.3
V
1
Input Low Voltage
VIL
-0.3
0
0.8
V
2
Output High Voltage
VOH
2.4
-
-
V
IOH = -2mA
Output Low Voltage
VOL
-
-
0.4
V
IOL = 2mA
Input leakage current
I LI
-12
12
uA
Notes :
1. VIH (max) = 5.6V AC. The overshoot voltage duration is ≤ 3ns.
2. VIL (min) = -2.0V AC. The undershoot voltage duration is ≤ 3ns.
3. Any input 0V ≤ VIN ≤ VDDQ.
Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs.
3
CAPACITANCE
(VCC = 3.3V, TA = 23° C, f = 1MHz, VREF =1.4V ± 200 mV)
DESCRIPTION
SYMBOL
MIN
MAX
UNITS
CCLK
20
32
pF
CIN
20
40
pF
Address
CADD
20
40
pF
DQ (DQ0 ~ DQ63)
COUT
32
52
pF
Clock
/RAS, /CAS,/WE,/CS, CKE, DQM
DC CHARACTERISTICS
(Recommended operating condition unless otherwise noted, TA = 0 to 70° C)
TEST
PARAMETER
VERSION
SYMBOL
CONDITION
-13
-12
-10
-10L
600
600
560
560
UNIT
NOTE
mA
1
Burst length = 1
Operating current
(One bank active)
ICC1
tRC ≥ tRC(min)
IO = 0mA
Precharge standby current in
ICC2P
power-down mode
ICC2PS
CKE ≤ VIL(max)
8
mA
8
mA
64
mA
tCC=10ns
CKE & CLK ≤ VIL(max)
tCC=∞
CKE ≥ VIH(min)
Precharge standby current in
non power-down mode
ICC2N
CS* ≥ VIH(min),
tCC=10ns
Input signals are changed
one time during 20ns
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HSD16M32D4
CKE ≥ VIH(min)
ICC2NS
CLK ≤ VIL(max),
tCC=∞
56
Input signals are stable
Active
standby
current
power-down mode
in
ICC3P
ICC3PS
CKE ≤ VIL(max), tCC=10ns
24
CKE&CLK ≤ VIL(max)
mA
24
tCC=∞
CKE≥VIH(min),
Active standby current in
ICC3N
CS*≥VIH(min),
tCC=10ns
non power-down mode
one time during 20ns
(One bank active)
CKE≥VIH(min)
ICC3NS
240
Input signals are changed
CLK ≤VIL(max),
mA
tCC=∞
140
Input signals are stable
IO = 0 mA
Operating current
Page burst
ICC4
(Burst mode)
720
720
560
560
mA
1
840
840
800
800
mA
2
4Banks Activated
tCCD = 2CLKs
Refresh current
ICC5
Self refresh current
ICC6
tRC ≥ tRC(min)
CKE ≤ 0.2V
20
mA
8
mA
Notes :
1. Measured with outputs open.
2. Refresh period is 64ms.
3. Unless otherwise noticed, input swing level is CMOS(VIH/VIL=VDDQ/VSSQ).
AC OPERATING TEST CONDITIONS
(vcc = 3.3V ± 0.3V, TA = 0 to 70° C)
PARAMETER
AC Input levels (Vih/Vil)
Input timing measurement reference level
Input rise and fall time
Output timing measurement reference level
Output load condition
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Value
UNIT
2.4/0.4
V
1.4
V
tr/tf = 1/1
Ns
1.4
V
See Fig. 2
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HANBit
HSD16M32D4
Vtt=1.4V
3.3V
1200Ω
50Ω
DOUT
870Ω
DOUT
Z0=50Ω
50pF*
50pF
VOH (DC) = 2.4V, IOH = -2mA
VOL (DC) = 0.4V, IOL = 2mA
(Fig. 2) AC output load circuit
(Fig. 1) DC output load
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted)
VERSION
PARAMETER
SYMBOL
-13
-12
-10
-10L
UNIT
NOTE
Row active to row active delay
tRRD(min)
15
16
20
20
ns
1
RAS to CAS delay
tRP(min)
20
20
20
20
ns
1
Row precharge time
tRP(min)
20
20
20
20
ns
1
tRAS(min)
45
48
50
50
ns
1
Row active time
Row cycle time
tRAS(max)
100
tRC(min)
65
68
ns
70
70
2
ns
1
CLK
2.5
Last data in to row precharge
tRDL(min)
Last data in to Active delay
tDAL(min)
Last data in to new col. address delay
tCDL(min)
1
CLK
2
Last data in to burst stop
tBDL(min)
1
CLK
2
Col. address to col. address delay
tCCD(min)
1
CLK
3
ea
4
2 CLK + 20 ns
CAS latency=3
2
Number of valid output data
CAS latency=2
-
1
Notes :
1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and
then rounding off to the next higher integer.
2. Minimum delay is required to complete write.
3. All parts allow every cycle column address change.
4. In case of row precharge interrupt, auto precharge and read burst stop.
.
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HSD16M32D4
AC CHARACTERISTICS
(AC operating conditions unless otherwise noted)
-13
PARAMETER
-12
-10
-10L
SYMBOL
MIN
MAX
MIN
MAX
MIN
MAX
MIN
UNIT
NOTE
ns
1
ns
1,2
ns
2
MAX
CAS
7.5
8
10
10
latency=3
CLK cycle time
tCC
1000
1000
1000
1000
CAS
-
-
10
12
latency=2
CAS
5.4
CLK to valid
latency=3
output delay
CAS
6
6
6
tSAC
-
-
6
7
latency=2
CAS
2.7
Output data
latency=3
hold time
CAS
3
3
3
tOH
-
-
3
3
latency=2
CLK high pulse width
tCH
2.5
3
3
3
ns
3
CLK low pulse width
tCL
2.5
3
3
3
ns
3
Input setup time
tSS
1.5
2
2
2
ns
3
Input hold time
tSH
0.8
1
1
1
ns
3
CLK to output in Low-Z
tSLZ
1
1
1
1
ns
3
2
CAS
CLK to output
latency=3
in Hi-Z
CAS
5.4
6
6
6
ns
-
-
6
7
ns
tSHZ
latency=2
Notes :
1. Parameters depend on programmed CAS latency.
2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter.
3. Assumed input rise and fall time (tr & tf) = 1ns.
If tr & tf is longer than 1ns, transient time compensation should be considered, ie., [(tr + tf)/2-1]ns should be added to
the parameter.
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HSD16M32D4
SIMPLIFIED TRUTH TABLE
COMMAND
Register
Mode register set
Auto refresh
Refresh
Entry
Self
refresh
Exit
Bank active & row addr.
Read &
column
address
Auto
CKE
n-1
CKE
n
/C
S
/R
A
S
/C
A
S
/W
E
D
Q
M
H
X
L
L
L
L
X
OP code
L
L
L
H
X
X
L
H
H
H
H
X
X
X
L
L
H
H
H
H
L
L
H
H
X
BA
0,1
X
X
Auto
precharge
X
L
H
L
H
X
NOT
1,2
3
3
3
X
V
Column
Address
V
(A0 ~
H
disable
3
Row address
L
H
A11
A9~A0
E
precharge
disable
A10/
AP
A8)
4
4,5
Column
Write &
column
address
Auto
precharge
disable
L
H
Auto
X
L
H
L
L
X
H
Bank selection
e
All banks
Clock suspend or
active power down
Precharge power
down mode
X
H
X
Entry
H
L
Exit
L
H
Entry
Exit
H
L
DQM
H
No operation command
H
L
H
L
L
L
H
L
H
L
L
H
X
X
X
L
V
V
V
X
X
X
X
H
X
X
X
L
H
H
H
H
X
X
X
L
V
V
V
X
X
H
X
X
X
L
H
H
H
X
X
X
4
A8)
H
disable
Precharg
(A0 ~
V
precharge
Burst Stop
Address
4,5
X
V
L
X
H
6
X
X
X
X
X
X
V
X
X
X
7
(V=Valid, X=Don't care, H=Logic high, L=Logic low)
Notes :
1. OP Code : Operand code
A0 ~ A12& BA0 ~ BA1 : Program keys. (@ MRS)
2. MRS can be issued only at all banks precharge state.
A new command can be issued after 2 CLK cycles of MRS.
3. Auto refresh functions are as same as CBR refresh of DRAM.
The automatical precharge without row precharge command is meant by "Auto".
Auto/self refresh can be issued only at all banks precharge state.
4. BA0 ~ BA1 : Bank select addresses.
If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected.
If both BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank B is selected.
If both BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank C is selected.
If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected.
If A10/AP is "High" at row precharge, BA0 and BA1 is ignored and all banks are selected.
5. During burst read or write with auto precharge, new read/write command can not be issued.
Another bank read/write command can be issued after the end of burst.
New row active of the associated bank can be issued at tRP after the end of burst.
6. Burst stop command is valid at every burst length.
7. DQM sampled at positive going edge of a CLK and masks the data-in at the very CLK (Write DQM latency is 0),
but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2)
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HSD16M32D4
PACKAGING INFORMATION
Unit : mm
Tolerances : ± 0.20 mm
PCB Thickness: 1.27mm ± 0.10mm
ORDERING INFORMATION
Part Number
Density
Org.
Package
Ref.
Vcc
MODE
HSD16M32D4-10
64MByte
16M x 32
100 Pin-DIMM
8K
3.3V
SDRAM
HSD16M32D4-10L
64MByte
16M x 32
100 Pin
8K
3.3V
SDRAM
HSD16M32D4-12
64MByte
16M x 32
100 Pin
8K
3.3V
SDRAM
HSD16M32D4-13
64MByte
16M x 32
100 Pin
8K
3.3V
SDRAM
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MAX. frq
CL2
100MHz
CL3
100MHz
CL3
125MHz
CL 3
133MHz
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