2SJ389 L , 2SJ389 S Silicon P Channel MOS FET Application DPAK–2 4 High speed power switching 4 Features • • • • Low on–resistance High speed switching Low drive current 4 V gate drive device can be driven from 5 V source • Suitable for Switching regulator, DC – DC converter • Avalanche Ratings 12 2, 4 12 3 3 1 1. Gate 2. Drain 3. Source 4. Drain 3 Table 1 Absolute Maximum Ratings (Ta = 25°C) Item Symbol Ratings Unit ——————————————————————————————————————————— Drain to source voltage VDSS –60 V ——————————————————————————————————————————— Gate to source voltage VGSS ±20 V ——————————————————————————————————————————— Drain current ID –10 A ——————————————————————————————————————————— Drain peak current ID(pulse)* –40 A ——————————————————————————————————————————— Body–drain diode reverse drain current IDR –10 A ——————————————————————————————————————————— Avalanche current IAP*** –10 A ——————————————————————————————————————————— Avalanche energy EAR*** 8.5 mJ ——————————————————————————————————————————— Channel dissipation Pch** 30 W ——————————————————————————————————————————— Channel temperature Tch 150 °C ——————————————————————————————————————————— Storage temperature Tstg –55 to +150 °C ——————————————————————————————————————————— * PW ≤ 10 µs, duty cycle ≤ 1 % ** Value at Tc = 25 °C *** Value at Tch = 25 °C, Rg ≥ 50 Ω 2SJ389 L , 2SJ389 S Table 2 Electrical Characteristics (Ta = 25°C) Item Symbol Min Typ Max Unit Test conditions ——————————————————————————————————————————— Drain to source breakdown voltage V(BR)DSS –60 — — V ID = –10 mA, VGS = 0 ——————————————————————————————————————————— Gate to source breakdown voltage V(BR)GSS ±20 — — V IG = ±100 µA, VDS = 0 ——————————————————————————————————————————— Gate to source leak current IGSS — — ±10 µA VGS = ±16 V, VDS = 0 ——————————————————————————————————————————— Zero gate voltage drain current IDSS — — –100 µA VDS = –50 V, VGS = 0 ——————————————————————————————————————————— Gate to source cutoff voltage VGS(off) –1.0 — –2.25 V ID = –1 mA, VDS = –10 V ——————————————————————————————————————————— Static drain to source on state resistance RDS(on) — 0.1 0.135 Ω ID = –5 A VGS = –10 V * ———————————————————————— — 0.14 0.2 Ω ID = –5 A VGS = –4 V * ——————————————————————————————————————————— Forward transfer admittance |yfs| 4 8 — S ID = –5 A VDS = –10 V * ——————————————————————————————————————————— Input capacitance Ciss — 910 — pF VDS = –10 V ———————————————————————————————— Output capacitance Coss — 440 — pF VGS = 0 ———————————————————————————————— Reverse transfer capacitance Crss — 170 — pF f = 1 MHz ——————————————————————————————————————————— Turn–on delay time td(on) — 15 — ns ID = –5 A ———————————————————————————————— Rise time tr — 85 — ns ———————————————————————————————— Turn–off delay time td(off) — 220 — ns VGS = –10 V RL = 6 Ω ———————————————————————————————— Fall time tf — 145 — ns ——————————————————————————————————————————— Body–drain diode forward voltage VDF — –1.0 — V IF = –10 A, VGS = 0 ——————————————————————————————————————————— Body–drain diode reverse recovery time trr — 170 — µs IF = –10 A, VGS = 0, diF / dt = 50 A / µs ——————————————————————————————————————————— * Pulse Test 2SJ389 L , 2SJ389 S Power vs. Temperature Derating Maximum Safe Operation Area 30 20 10 I D (A) –200 –100 –50 Drain Current Channel Dissipation Pch (W) 40 –10 50 100 Case Temperature DC –5 PW Op era s 1m =1 µs s 0m s( tio 1s Operation in n( ho Tc –2 this area is = 2 t) 5° limited by R DS(on) C) –1 150 Ta = 25 °C –0.2 –1 –2 –5 –10 –20 –50 –100 Drain to Source Voltage V DS (V) 200 Tc (°C) Typical Output Characteristics Pulse Test –10 V (A) –12 –8 –3.5 V –3 V –4 VGS = –2.5 V 0 V DS = –10 V Pulse Test –4 V –5 V –4.5 V ID –16 Typical Transfer Characteristics –10 Drain Current –20 I D (A) 0µ –20 –0.5 0 Drain Current 10 10 –4 –8 –12 Drain to Source Voltage –16 –20 V DS (V) –8 –6 –4 –2 75 °C Tc = –25 °C 25 °C 0 –1 –2 –3 Gate to Source Voltage –4 –5 V GS (V) 2SJ389 L , 2SJ389 S Pulse Test -0.8 –0.6 I D = –5 A -0.4 Pulse Test 2 1 0.2 –2 A –0.2 –1 A 0 Static Drain to Source on State Resistance R DS(on) ( Ω) Static Drain to Source on State Resistance vs. Drain Current 5 0.5 –4 –8 12 Gate to Source Voltage 0.4 0.3 –2, –1 A I D = –5 A 0.2 V GS = –4 V –5, –2, –1 A 0.1 –10 V 0 –40 0 40 80 120 160 Case Temperature Tc (°C) –10 V 0.05 –1 –16 –20 V GS (V) Static Drain to Source on State Resistance vs. Temperature 0.5 Pulse Test VGS = –4 V 0.1 –2 –5 –10 –20 –50 –100 Drain Current I D (A) Forward Transfer Admittance vs. Drain Current Forward Transfer Admittance |y fs | (S) Drain to Source Saturation Voltage V DS(on) (V) –1.0 Drain to Source On State Resistance R DS(on) ( Ω ) Drain to Source Saturation Voltage vs. Gate to Source Voltage 50 20 V DS = –10 V Pulse Test 10 Tc = –25 °C 5 2 25 °C 75 °C 1 0.5 –0.1 –0.2 –0.5 –1 –2 –5 Drain Current I D (A) –10 2SJ389 L , 2SJ389 S 1000 10000 500 Capacitance C (pF) Reverse Recovery Time trr (ns) Typical Capacitance vs. Drain to Source Voltage Body–Drain Diode Reverse Recovery Time 200 100 50 20 V DD = –50 V –25 V –10 V –100 0 V GS 80 20 40 60 Gate Charge Qg (nc) –10 –20 –30 -40 –50 Drain to Source Voltage V DS (V) –8 V GS (V) 1000 –12 –16 –20 100 500 Switching Time t (ns) V DS –60 –80 –4 I D = –10 A VGS = 0 f = 1 MHz Switching Characteristics 0 Gate to Source Voltage V DS (V) Drain to Source Voltage –40 Crss 100 0 Dynamic Input Characteristics –20 Coss 300 100 10 –0.1 –0.3 –1 –3 –10 –30 –100 Reverse Drain Current I DR (A) V DD = –10 V –25 V –50 V Ciss 1000 300 di / dt = 50 A / µs VGS = 0, Ta = 25 °C 0 3000 V GS = –10 V, V DD = –30 V PW = 5 µs, duty < 1 % t d(off) 200 100 tf 50 tr 20 10 –0.1 –0.2 t d(on) –0.5 –1 –2 –5 Drain Current I D (A) –10 2SJ389 L , 2SJ389 S Reverse Drain Current vs. Source to Drain Voltage Maximun Avalanche Energy vs. Channel Temperature Derating Repetive Avalanche Energy E AR (mJ) –20 Reverse Drain Current I DR (A) Pulse Test –16 –12 –8 V GS = –10 V –5 V 0, 5 V -4 0 –0.4 –0.8 –1.2 Source to Drain Voltage –1.6 10 –2.0 I AP = –10 A V DD = –25 V duty < 0.1 % Rg > 50 Ω 8 6 4 2 0 25 50 V SD (V) 75 100 125 150 Channel Temperature Tch (°C) Avalanche Test Circuit and Waveform V DS Monitor EAR = L 1 2 • L • I AP • 2 I AP Monitor VDSS VDSS – V DD V (BR)DSS I AP Rg D. U. T V DS VDD ID Vin –15 V 50Ω 0 VDD 2SJ389 L , 2SJ389 S Normalized Transient Thermal Impedance vs. Pulse Width Normalized Transient Thermal Impedance γ s (t) 3 Tc = 25°C 1 D=1 0.5 0.3 0.1 0.2 0.1 0.05 θ ch – c(t) = γ s (t) • θ ch – c θ ch – c = 4.17 °C/W, Tc = 25 °C 0.02 e uls 1 0.03 0.0 PDM P ot D= h 1s PW T PW T 0.01 10 µ 100 µ 1m 10 m Pulse Width 100 m 10 PW (S) Switching Time Test Circuit Waveforms Vout Monitor Vin Monitor 1 Vin 10% D.U.T. RL 90% Vin –10 V 50Ω V DD = 30 V 90% 90% Vout td(on) 10% 10% tr td(off) tf