HT0610 33´120 LCD Driver Features · Operating voltage: 2.4V~3.5V · External contrast control · 33 common/120 segment LCD driver output · Low power icon mode driven by com32 · 33´120=3960 bits capacity of built-in graphic display · Four static icon driver circuit · High accuracy voltage regulator with temperature co- data RAM (BGDRAM) · Master and slave mode available for multi-chip efficient (0.00%, -0.18%, -0.22%, -0.35%) operation · Low power consumption - Read/write mode 170mA (Typical) - Display mode 160mA (Typical) · 8-bit Parallel interface with general MCU · On-chip oscillator circuit for display clock, external - Standby mode 15mA (Typical; Display off; internal clock can also be used · Selectable multiplex ratio: 1/16, 1/32, 1/33 oscillator enable) - Standby mode < 1mA (Typical; Display off; external · Selectable bias ratio: 1/5 or 1/7 oscillator enable) · External driving circuit for external bias supply · CMOS process · On-chip selectable voltage doublers and tripler · TCP available · Wide range of operating temperature: -30°C to 85°C · S/W controlled electronic contrast control function (16 levels) General Description The HT0610 is a driver and controller LSI for graphic dot-matrix liquid crystal display systems. It has 33 common and 120 segment driver circuits. This chip is connected directly to an MCU, accepts 8-bit parallel display data and stores an on-chip graphic display data RAM (BGDRAM) of 33´120 bits. It provides a high-flexible display section due to the one-to-one correspondence Rev. 1.00 between BGDRAM bits and LCD panel pixels. It performs BGDRAM read/write operation with no externally operating clock to minimize power consumption. In addition, because it contains power supply circuits necessary to drive an LCD, it is possible to make a display system with minimal components. 1 February 24, 2004 HT0610 Block Diagram IB P S E G 0 ~ S E G 1 1 9 IC O N 0 ~ IC O N 3 S ta tic Ic o n C o n tr o l C ir c u it C O M 0 ~ C O M 3 2 L e v e l S e le c to r H ig h V o lta g e C e ll L e v e l S h ifte r V L L 2 V L L 6 V C C A 1 1 5 5 B its L a tc h ( 3 3 B its & 1 2 0 B its ) O S C 1 O S C 2 L C D D r iv in g V o lta g e G e n e r a to r D o u b le r & T r ip le r V o lta g e R e g u la to r , V o lta g e D iv id e r , C o n tr a s t C o n tr o l, T e m p e ra tu re C o m p e n s a tio n C ir c u it T im in g G e n e r a to r fo r D is p la y B G D R A M 1 2 0 ´ 3 3 B its V D D V S S V R V F C 2 C 2 C 1 C 1 D U D U C + C V D P N N P M 2 M 1 D A C o m m a n d D e c o d e r C ir c u it P a r a lle l In te r fa c e C o m m a n d In te rfa c e C S (C L K ) D C O M C E R E S R W D 0 ~ D 7 Operation of LCD Driver Description of block diagram module Block Description This module determines whether the input data is interpreted as data or command. Data is directed to this module based upon the input of the DCOM pin. If DCOM High, then data is written to BGDRAM ( Built-in Graphic Display data RAM) . DCOM pin Low indicates that the input at D0~D7 is interpreted as a Command. Command Decoder and CE is the master chip selection signal . A High input enable the input lines ready to samCommand Interface ple signals. RES pin of same function as Power On Reset (POR). Once RES received the reset signal, all internal circuitry will back to its initial status. Refer to Command Description section for more information. Parallel Interface The parallel interface consists of 8 bi-directional data lines (D0~D7),RW, and CS. The RW input High indicates a read operation from the BGDRAM . RW input Low indicates a write to BGDRAM or Internal Command Registers depending on the status of DCOM pin input. The CS input serves as data latch signal (clock). The BGDRAM is a bit mapped static RAM holding the bit pattern to be displayed. The Built-in Graphic Display size of the BGDRAM is determined by number of row times the number of column data RAM (BGDRAM) (120´33 =3960 bits). Figure as follow is a description of the BGDRAM address map. For mechanical flexibility, re-mapping on both Segment and Common outputs are provided Display Timing Generator Rev. 1.00 This module is an on chip low power RC oscillator circuitry. The oscillator frequency can be selected in the range of 15kHz to 50kHz by external resistor. One can enable the circuitry by software command. For external clock provided, feed the clock to OSC2 and leave OSC1 open. 2 February 24, 2004 HT0610 Block Description Static Icon Control Circuit This module generates the LCD waveform of the 4 annunciators and IBP signal. The four independent static icons are enabled by software command. Icon signals are also controlled by oscillator circuit, too. This module generates the LCD voltage needed for display output. It takes a single supply input and generates necessary bias voltages. It consists of: · Voltage doubler and voltage tripler To generate the VCCA1 voltage. Either doubler or tripler can be enabled. · Voltage regulator Feedback gain control for initial LCD voltage. It can also be used with external contrast control. · Voltage divider LCD Driving Voltage Generator Divide the LCD display voltage (VLL2~VLL6) from the regulator output. This is low power consumption circuit, which can save the most display current compare with traditional resistor ladder method. · Bias Ratio Selection circuitry Software control of 1/5 and 1/7 bias ratios to match the characteristic of LCD panel. · Self adjust temperature compensation circuitry Provide 4 different compensation grade selections to satisfy the various liquid crystal temperature grades. The grading can be selected by software control. · Contrast Control Block Software control of 16 voltage levels of LCD voltage. · External Contrast Control By adjusting the gain control resistors connected externally, the contrast can be varied. All blocks can be individually turned off if external voltage generator is employed. 120 Bit Latch/33 Bit Latch 153 bit long registers, which carry the display signal information. First 33 bits are Common driving signals and other 120 bits are Segment driving signals. Data will be input to the HV-buffer Cell for bumping up to the required level. Level Selector Level selector is a control of the display synchronization. Display voltage can be separated into two sets and used with different cycles. Synchronization is important since it selects the required LCD voltage level to the HV Buffer Cell for output signal voltage pump. HV Buffer Cell (Level Shifter) HV Buffer Cell works as a level shifter that translates the low voltage output signal to the required driving voltage. The output is shifted out with an internal FRM clock, which comes from the Display Timing Generator. The voltage levels are given by the level selector which is synchronized with the internal M signal. Rev. 1.00 3 February 24, 2004 HT0610 Pin Assignment D U M M Y D U M M Y V S O S C V S V S R S 1 C O M C O M C O M C O M C O M C O M 3 2 1 8 4 1 8 3 1 8 2 1 8 1 1 8 0 1 7 9 1 7 8 1 7 7 1 7 6 C O M C O M C O M C O M S E G S E G S E G S E G S E G 0 1 2 1 3 1 4 1 5 6 3 S E G S E G S E G C O M C O M C O M C O M C O M 1 1 7 1 1 8 1 1 9 3 2 3 1 3 0 2 9 2 8 C O M C O M C O M C O M IC O N IC O N IC O N IC O N IB P 1 9 0 1 2 3 4 2 1 V F V C C A 1 C C + D U M 2 O S C 2 D U M 1 V L L 6 V L L 5 V L L 4 V L L 3 V L L 2 C 2 N C 2 P C 1 N C 1 P V D D A V S S C E D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 V S S C S (C L K ) R W D C O M V S S R E S V D D 1 9 7 1 9 6 1 9 5 1 9 4 1 9 3 1 9 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 2 3 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 6 2 2 5 6 1 2 6 6 0 2 7 5 9 2 8 5 8 2 9 5 7 3 0 5 6 3 1 3 2 3 3 3 4 3 5 4 7 3 6 4 6 3 7 4 5 3 8 4 4 4 3 D U M M Y 4 2 4 1 4 0 3 9 1 8 1 7 1 6 0 1 2 3 D U M M Y Rev. 1.00 4 February 24, 2004 HT0610 Pin Description Pin Name I/O Description VDD I VDD is the positive supply to the digital control circuit and other circuitry in LCD bias voltage generator (Must have same voltage level with VDDA) RES I Active low reset pin; reset all internal status of circuit (Same as power on reset) VSS I VSS is ground DCOM I If pull this pin ²High² then D0~D7 bi-direction bus is used for data transferring; If DCOM pin is ²Low² then D0~D7 bi-direction bus is used for command transferring. RW I If pull this pin high: Indicate we want to read the display data RAM or the internal state. If we force this to Low: Indicate we want to write data to display data RAM or write some internal state to registers. CS I This pin is normal low clock input. Data on D0~D7 bi-direction data bus are latched at the falling edge of CS D0~D7 B Those bi-direction pins are used for DATA or command transferring. CE I High input to this pin to enable the control pins on the driver. OSC1 I Oscillator input pin. For internal oscillator mode, this is an input for the internal low power RC oscillator circuit. In this mode, an external resistor of certain value is placed between the OSC1 and OSC2 pins. For external oscillator mode, OSC1 pin should be left open OSC2 Oscillator output pin For internal oscillator mode, this is an output for the internal low power RC oscillator circuit. O External Oscillator input For external oscillator mode, OSC2 will be an input pin for external clock and no external resistor is needed. C1P, C1N ¾ If internal DC/DC converter is enabled, a capacitor is required to connect these two pins. C2P, C2N ¾ VLL2~VLL6 Group of voltage level pins for driving the LCD panel. They can either be connected to external O driving circuit for external bias supply or connected internally to built-in divider circuit. For internal voltage divider enable, a 0.1mF capacitor to VSS is required on each pin. DUM1, DUM2 O C+, C- ¾ If internal divider circuit is enable, a capacitor is required to connect between these two pin VCCA1 O VF, VR This is a feedback path for the gain control (external contrast control) of VLL1 to VLL6. For adjusting the LCD driving voltage, it requires a feedback resistor placed between VR and VF, a ¾ gain control resistor placed between VF and VSS, a 10uF capacitor placed between VR and VSS. COM0~COM32 O These pins provide the row driving signal to LCD panel VDDA I ICON1~ICON4 O There are four independent annunciator driving outputs IBP O This pin combines with ICON1~ICON4 pins to form annunciator driving part. SEG0~SEG119 O These 120 pins provide LCD column driving signal to LCD panel. Rev. 1.00 If internal tripler is enabled, a capacitor is required to connect these two pins. Otherwise, leave these pin open. If internal voltage divider is enable with 1/7 bias selected, a capacitor to VSS is required on each pin. Otherwise, pull these two pin to VSS If internal DC/DC Converter is enabled, a 0.1mF capacitor from this pin to VSS is required. It can also be an external bias input pin if internal DC/DC converter is not used VDDA is the positive supply to the noise sensitive circuitry and must have same voltage level with VDD 5 February 24, 2004 HT0610 Absolute Maximum Ratings Supply Voltage ........................................-0.3V to 4.0V Storage Temperature ...........................-65°C to 150°C Input Voltage .............................VSS-0.3V to VDD+0.3V Operating Temperature ..........................-30°C to 85°C LCD Input Voltage ..................................-0.3V to 10.5V Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maximum Ratings² may cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability. HT0610 contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precaution to be taken to avoid application of any voltage higher than maximum rated voltages to this high impedance circuit . For proper operation it is recommended that VIN and Vout be constrained to the range VSS < or = (VIN or VOUT) < or = VDD. Reliability of operation is enhanced if unused inputs are connected to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open. This device may be light sensitive? caution should be taken to avoid exposure of this device to any light source during normal operation. This device is not radiation protected. Electrical Characteristics Ta=25°C Test Conditions Min. Typ. Max. Unit 2.4 3.15 3.5 V IRW Measure with VDD fixed at 3.15V Internal DC/DC converter on, Read/write Mode 2.4V~ display on, tripler enable, Supply Current Drain from Pin VDDA 120 3.5V read/write accessing, and VDD tCYC=1MHz, Osc freq.=50kHz, 1/33 duty, 1/7 bias 170 200 mA ION1 Internal DC/DC converter on, display on, tripler enable, Display on Mode 2.4V~ read/write HALT, Supply Current Drain from Pin VDDA 3.5V Osc freq.=50kHz, 1/33 duty, and VDD 1/7 bias 130 110 140 mA ION2 Internal DC/DC converter on, display on, tripler enable, Display on Mode 2.4V~ 140 read/write HALT, Supply Current Drain from Pin VDDA 3.5V Osc freq.=38.4kHz, 1/33 duty, and VDD 1/7 bias 100 120 mA ISTB1 Standby Mode Supply Current Drain 2.4V~ Display off, oscillator disabled, from Pin VDDA and VDD 3.5V read/write HALT ¾ 300 500 nA ISTB2 Display off, oscillator enabled, Standby Mode Supply Current Drain 2.4V~ read/write HALT, external osfrom Pin VDDA and VDD 3.5V cillator and frequency=50kHz ¾ 0.6 1 mA ISTB3 Display off, oscillator enabled, Standby Mode Supply Current Drain 2.4V~ read/write HALT, internal oscilfrom Pin VDDA and VDD 3.5V lator and frequency=50kHz ¾ 23 30 mA IICON Low power ICON mode, oscillaStandby Mode Supply Current Drain 2.4V~ tor enable, read/write HALT, from Pin VDDA and VDD 3.5V internal oscillator and frequency=50kHz ¾ 25 30 mA Symbol Parameter VDD Conditions Supply voltage VDD Operating Voltage 2.4V~ VDDA=VDD 3.5V Supply Current Rev. 1.00 6 February 24, 2004 HT0610 Symbol Parameter Test Conditions Min. Typ. Max. Unit VLCC1 Display on, internal DC/DC converter enable, tripler enLCD Driving Voltage 2.4V~ a b l e , o sci l l a t o r a n d f r eGenerator Output Voltage at Pin 3.5V quency=50kHz, regulator VCCA1 e n a b l e , d i vi d e r e n a b l e IOUT£100mA ¾ 3´VDD 10.5 V VLCC2 Display on, internal DC/DC converter enable, doubler enLCD Driving Voltage 2.4V~ a b l e , o sci l l a t o r a n d f r eGenerator Output Voltage at Pin 3.5V quency=50kHz, regulator VCCA1 e n a b l e , d i vi d e r e n a b l e IOUT£100mA ¾ 2´VDD 7 V VLCD LCD Driving Voltage Input at Pin 2.4V~ Internal DC/DC converter disVCCA1 3.5V able 5 ¾ 10.5 V 0.8´ VDD ¾ VDD V 0 ¾ 0.2´ VDD V Conditions VDD VLCD voltage (Absolute value referenced to VSS) Output voltage VOH1 Output High Voltage at Pin D0~D7, 2.4V~ IOUT=100mA ICON1~ICON4, IBP and OSC2 3.5V VOL1 Output Low Voltage at Pin D0~D7, ICON1~ICON4, IBP and OSC2 VR1 LCD Driving Voltage Source at Pin 2.4V~ Regulator enable, IOUT=50mA VR 3.5V 0 ¾ VCCA1 V VR2 LCD Driving Voltage Source at Pin 2.4V~ Regulator disable VR 3.5V ¾ Floating ¾ V 2.4V~ IOUT=100mA 3.5V Input voltage VIH1 Input High Voltage at Pin RES, CE, 2.4V~ CS, D0~D7, RW, DCOM, OSC1 and 3.5V OSC2 ¾ 0.8´ VDD ¾ VDD V VIL1 Input Low Voltage at Pin RES, CE, 2.4V~ CS, D0~D7, RW, DCOM, OSC1 and 3.5V OSC2 ¾ 0 ¾ 0.2´ VDD V LCD display voltage VLL6 2.4V~ 3.5V ¾ VR ¾ V VLL5 2.4V~ 3.5V ¾ 0.8´VR ¾ V ¾ 0.6´VR ¾ V VLL4 LCD Driving Voltage Output from Pin 2.4V~ 1/5 bias ratio, voltage divider VLL6~VLL2 3.5V enable, regulator enable VLL3 2.4V~ 3.5V ¾ 0.4´VR ¾ V VLL2 2.4V~ 3.5V ¾ 0.2´VR ¾ V Rev. 1.00 7 February 24, 2004 HT0610 Symbol Parameter Test Conditions Conditions VDD Min. Typ. Max. Unit VLL6 2.4V~ 3.5V ¾ VR ¾ V VLL5 2.4V~ 3.5V ¾ 6/7´VR ¾ V VLL4 2.4V~ 3.5V ¾ 5/7´VR ¾ V DUM2 2.4V~ 1/7 bias ratio, voltage divider 3.5V enable, regulator enable ¾ 4/7´VR ¾ V DUM1 2.4V~ 3.5V ¾ 3/7´VR ¾ V VLL3 2.4V~ 3.5V ¾ 2/7´VR ¾ V VLL2 2.4V~ 3.5V ¾ 1/7´VR ¾ V VLL6 2.4V~ 3.5V 0.5´ VCCA1 ¾ VCCA1 VLL5 2.4V~ 3.5V VCCA1 ¾ VCCA1 VLL4 2.4V~ External voltage generator, 0.5´ 3.5V internal voltage divider disable VCCA1 ¾ VCCA1 VLL3 2.4V~ 3.5V vss ¾ VLL2 2.4V~ 3.5V vss ¾ 0.5´ 0.5´ VCCA1 0.5´ VCCA1 Output Current IOH Output High Current Source from 2.4V~ VOUT=VDD-0.1V Pins D0~D7, ICON1~ICON4, IBP 3.5V and OSC2 ¾ 1.5 ¾ mA IOL Output Low Current Drain by Pins 2.4V~ VOUT=0.1V D0~D7, ICON1~ICON4, IBP and 3.5V OSC2 ¾ 5 ¾ mA IOZ Output Tri-state Current Drain 2.4V~ Source at Pins D0~D7 and OSC2 3.5V ¾ -1 ¾ 1 mA IIL/IIH Input Current at Pins RES, CE, CS, 2.4V~ D0~D7, RW, DCOM, OSC1 and 3.5V OSC2 ¾ -1 ¾ 1 mA On resistance RON During display on, 0.1V apply Channel Resistance between LCD Driving Signal Pins (Segment and 2.4V~ b e t w e e n t w o t e r m i n a l s, Common) and Driving Voltage Input 3.5V VCCA1 within operating voltage range Pins (VLL2 to VLL6) ¾ ¾ 5 kW VMR Memory Retention Voltage (VDD) 2.4V~ Standby Mode, Retained All Internal 3.5V Configuration and BGDRAM Data ¾ 1.8 ¾ ¾ V CIN Input Capacitance All Control Pins 2.4V~ 3.5V ¾ ¾ 5 7.5 pF Rev. 1.00 8 February 24, 2004 HT0610 Symbol Parameter Test Conditions Conditions VDD Min. Typ. Max. Unit Temperature coefficient compensation PTC0 Flat Temperature 2.4V~ TC1=0, TC2=0, 3.5V regulator disable ¾ 0 ¾ % PTC1 Coefficient 2.4V~ TC1=0, TC2=1, 3.5V regulator enable ¾ -0.18 ¾ % PTC2 Temperature Coefficient 1* 2.4V~ TC1=1, TC2=0, 3.5V regulator enable ¾ -0.22 ¾ % PTC3 Temperature Coefficient 2* Temperature Coefficient 3* 2.4V~ TC1=1, TC2=1, 3.5V regulator enable ¾ -0.35 ¾ % VCON Internal Contrast Control VR Output Voltage with Internal Contrast ConInternal regulator enabled, trol Selected 2.4V~ internal contrast control en16 Voltage Levels Controlled by Soft3.5V abled ware Each Level is Typical of 2.25% of the Regulator Output Voltage ¾ ±18 ¾ % Oscillator frequency FOSC1 Oscillator Frequency of Display Tim2.4V~ ing Generator with 60Hz Frame FreSet clock frequency to slow 3.5V quency ¾ 38.4 ¾ kHz FOSC2 Oscillator Frequency of Display Tim2.4V~ Set clock frequency to normal ing Generator with 60Hz Frame Fre3.5V quency ¾ 50 ¾ kHz FICON1 Four Static ICON Display (50% Duty 2.4V~ Cycle) from Pins ICON1~ICON4 and 3.5V IBP ¾ ¾ 18.75 ¾ Hz FICON2 Four Static ICON Display (50% Duty 2.4V~ Cycle) from Pins ICON1~ICON4 and 3.5V IBP ¾ ¾ 24.4 ¾ Hz FFRAME1 LCD Driving Signal Frame Frequency Either external clock input or 2.4V~ internal oscillator enable, ei3.5V ther 1/32 or 1/16 duty cycle, graphic display mode ¾ 66 ¾ Hz FFRAME2 LCD Driving Signal Frame Frequency Either external clock input or 2.4V~ internal oscillator enable, ei3.5V ther 1/32 or 1/16 duty cycle ¾ 65 ¾ Hz FCON1 LCD Driving Signal Frame Frequency Either external clock input or 2.4V~ internal oscillator enable, 1/33 3.5V duty cycle, graphic display mode ¾ 64 ¾ Hz FCON2 LCD Driving Signal Frame Frequency Either external clock input or 2.4V~ internal oscillator enable, 1/33 3.5V duty cycle ¾ 63 ¾ Hz Internal oscillation frequency OSC Internal OSC Oscillation Frequency 2.4V~ Internal oscillator enable with Different Value of Feedback Re3.5V within operation range sistor See the figure as follow Note: * The formula for the temperature coefficient is: TC (%)= Rev. 1.00 VR at 50o C - VR at 0o C 1 ´ ´100% 50o C - 0o C VR at 25o C 9 February 24, 2004 HT0610 Total variation of VR D VRT is affected by the following factors: Process variation of regulator D VR External VDD variation contributed to regulator D VVDD External resistor pair Ra/Rf contributed to regulator D VRES Where D VRT = DVR 2 DVVDD 2 DVRES 2 Assume external VDD variation is ±6% at 3.15V and 1% variation resistor used at application TC Level D VVDD (%) TC0 ±6.0 TC1 ±4.0 TC2 ±2.5 TC3 ±1.4 Reference Generator D VR (%) D VRT (%) ±6.652 ±2.5 ±4.924 ±1.414 ±3.805 ±3.195 Parallel timing characteristics (Write cycle) Symbol D VRES (%) Ta=30°C~85°C, DVDD=2.4V~3.5V, VSS=0V Parameter Min. Typ. Max. Unit tCYCLE Enable Cycle Time 620 ¾ ¾ ns tEH Enable Pulse Width 300 ¾ ¾ ns tAS Address Setup Time 10 ¾ ¾ ns tDS Data Setup Time 300 ¾ ¾ ns tDH Data Hold Time 30 ¾ ¾ ns tAH Address Hold Time 30 ¾ ¾ ns C E tC Y C L E C S (C L K ) tE H R W tA tA S H D C O M tD D 0 ~ D 7 S tD H V a lid D a ta Timing characteristics (Write cycle) Rev. 1.00 10 February 24, 2004 HT0610 Parallel timing characteristics (Read cycle) Symbol Ta=30°C~85°C, DVDD=2.4V~3.5V, VSS=0V Parameter Min. Typ. Max. Unit tCYCLE Enable Cycle Time 620 ¾ ¾ ns tEH Enable Pulse Width 300 ¾ ¾ ns tAS Address Setup Time 10 ¾ ¾ ns tDS Data Setup Time ¾ ¾ 300 ns tDH Data Hold Time 10 ¾ ¾ ns tAH Address Hold Time 30 ¾ ¾ ns C E tC Y C L E C S (C L K ) tE H R W tA tA S H D C O M tD D 0 ~ D 7 tD S H V a lid D a ta Timing characteristics (Read cycle) Rev. 1.00 11 February 24, 2004 HT0610 Functional Description 3 0 0 O s c illa to r F r e q u e n c y (k H z ) 2 5 0 2 0 0 1 5 0 1 0 0 5 0 0 1 0 0 K 1 5 0 K 2 0 0 K 2 4 0 K 3 0 0 K 3 6 0 K 4 3 0 K 5 1 0 K 5 6 0 K 6 2 0 K 6 8 0 K 7 5 0 K 8 2 0 K 9 1 0 K 1 M 1 .5 M 2 .0 M R e s is to r v a lu e o n O S C 1 & O S C 2 (W ) Internal oscillator frequency relationship with different external resistor value · Set clock frequency to slow: FFRAME1=FOSC1/576 · Set clock frequency to normal: FFRAME2=FOSC2/768 C o lu m n a d d r e s s 0 0 H ( o r c lo u m n a d d r e s s 7 7 H ) L S B C o lu m n a d d r e s s 7 7 H ( o r c lo u m n a d d r e s s 0 0 H ) C O M 0 (C O M 3 1 ) P a g e 1 M S B P a g e 2 P a g e 3 P a g e 4 S E G 0 P a g e 5 S E G 1 1 9 C O M 0 (C O M 3 1 ) C O M 3 2 Built-in graphic display data RAM (BGDRAM) address map Rev. 1.00 12 February 24, 2004 HT0610 Command Description The display on command turns the LCD common and segment outputs on and has no effect to the static icons output. This command causes the conversion of data in BGDRAM to necessary waveforms on the common and segment driving outputs. The on-chip bias generator is also turned on by this command. (Note: ²oscillator on² command should be sent before ²display on² is selected.) The display off command turns the display off and the states of the LCD driver are as follow during display off: Set Display On/Off (Display Mode/Standby Mode) · The common and segment outputs are fixed at VLL1(VSS) · The bias voltage generator is turned off. · The RAM and content of all register are retained. · IC will accept new commands and data. · The status of the static Icons and oscillator are not affected by display off com- mand. Set BGDRAM Page Address This command positions the row address to 1 of 5 possible positions in BGDRAM. Master Clear BGDRAM This command is to clear the 480 byte BGDRAM by setting the RAM data to zero. Issue this command followed by a dummy writes command. The RAM for icon line will not be affected by this command. Master Clear Icons This command is used to clear the data in page 5 of BGDRAM, which stores the icon line data. Before using this command, set the page address to page 5 by the command ²set BGDRAM page address². A dummy write data is also needed after this ²master clear Icons² command to make the clear icon action effective. Set Display with Icon Line If 1/32 Mux selected, use this command change to 1/33 Mux for using the Icon line. This command can also change Icon display mode to normal display mode (1/32 or 1/33 MUX). Set Icon Display Mode This command forces the output to the icon display mode. Display on row 0 to row 31 will be disabled. Set Icon Line/Static Icon Contrast Level The contrast of the icon line and static icon in icon mode can be set by this command. There are four levels to select from. Set Vertical Scroll Value This command is used to scroll the screen vertically with scroll value 0 to 31. With scroll value equals to 0, row 0 of BGDRAM is mapped to com 0 and row 1 through row 31 are mapped to com 1 through com 31 respectively. With scroll value equal to 1, row 1 of BGDRAM is mapped to com 0, then row 2 through row 31 will be mapped to com 1 through com 30 respectively and row 0 will be mapped to com 31. Com 32 is not affected by this command. Save/Restore BGDRAM Column Address With bit option=1 in this command, the save/restore column address command saves a copy of the column address of BGDRAM. With a bit option=0, this command restores the copy obtained from the previous execution of saving column address. This instruction is very useful for writing full graphics characters that are larger than 8 pixels vertically. This instruction selects the mapping of BGDRAM to segment drivers for mechanical flexibility. There are 2 mappings to select: Set Column Mapping · Column 0~column 119 of BGDRAM mapped to SEG0~SEG119 respectively · Column 0~column 119 of BGDRAM mapped to SEG119~SEG0 respectively COM 32 will not be affected by this command. Detailed information please refer to section ²display output description². This instruction selects the mapping of BGDRAM to common drivers for mechanical flexibility. There are 2 mappings to select: Set Row Mapping · Row 0~Row 31 of BGDRAM mapped to COM 0~COM 31 respectively. · Row 0~Row 31 of BGDRAM mapped to COM 31~COM 0 respectively. COM 32 will not be affected by this command. Detail information please refer to section ²display output description². Rev. 1.00 13 February 24, 2004 HT0610 Command Description Set Static Icon Control Signal This command is used to control the active states of the 4 stand-alone icons drivers. Set Oscillator Disable/Enable This command is used to either disable or enable the oscillator. For using internal or external oscillator, this command should be executed. The setting for this command is not affected by command ²set display on/off² and ²set static Icon control signal². Refer to command ²set internal/external oscillator² for more information. This command is used to select either internal or external oscillator. When internal Set Internal/External Oscillator oscillator is selected, feedback resistor between OSC1 and OSC2 is needed. For external oscillation circuit, feed clock input signal to OSC2 and leaves OSC1 open. Set Clock Frequency Use this command to choose from two different oscillation frequency (50kHz or 38.4kHz) to get the 60Hz frame frequency. With frequency high, 50kHz clock frequency is preferred. 38.4kHz clock frequency (low frequency) enable for power saving purpose. Set DC/DC Converter On/Off Use this command selects the internal DC/DC converter to generate the VDDA1 from VDD. Disable the internal DC/DC converter if external VCCA1 is provided. Set Voltage Doubler/Tripler Use this command to choose doubler or tripler when the internal DC/DC converter is enabled. Set Internal Regulator On/Off Choose bit option 0 to disable the internal regulator. Choose bit option 1 to enable internal regulator, which consists of the internal contrast control and temperature compensation circuits. If the internal voltage divider is disabled, external bias can be used for VLL6 to Set Internal Voltage Divider VLL2. If the internal voltage divider is enabled, the internal circuit will automatically select the correct bias level according to the number of multiplex. Refer to comOn/Off mand ²bias ratio select². Set Duty Cycle This command is to select 16 mux or 32 mux display. When 16 mux is enabled, the unused 16 common outputs will be swinging between VLL2 and VLL5 for dummy scan purpose and doubler will be used. Set Bias Ratio This command sets the 1/5 bias or 1/7 bias for the divider output. The selection should match the characteristic of LCD panel. This command is used to turn on or off the internal control of delta voltage of the Set Internal Contrast Control bias voltages. With bit option=1, the software selection for delta bias voltage conOn/Off trol is enabled. With bit option=0, internal contrast control is disabled. If the internal contrast control is enabled, this command is used to increase or deIncrease/Decrease Contrast crease the contrast level within the 16 contrast levels. The contrast level starts from Level lowest value after power on reset. Set Contrast Level This command is to select one of the 16 contrast levels when internal contrast control circuitry is in use. Read Contrast Value This command allows the user to read the current contrast level value. With RW input HIGH (READ), DCOM input LOW (Command) and D7, D6, D5 and D4 are equal to 0001, the value if the internal contrast value can be read on D0~D3 at the falling edge of CS. Set Temperature Coefficient This command can select 4 different LCD driving voltage temperature coefficients to match various liquid crystal temperature grades. Those temperature coefficients are specified in electrical characteristics table. S e t I D D R educ t i on M o d e By using this command to reduce the display clock frequency by HALT. Use in Icon On/Off mode to reduce standby current Rev. 1.00 14 February 24, 2004 HT0610 Command table Bit Pattern (D7~D0) 00000X2X1X0 Command Comment Set BGDRAM page address using X2X1X0 as address bits. X2X1X0=000: page 1 (POR; initial state) X2X1X0=001: page 2 Set BGDRAM Page Address X2X1X0=010: page 3 X2X1X0=011: page 4 X2X1X0=100: page 5 000011X1X0 Set Icon Line/Annunciator Contrast Level Set one of the 4 available values to the icon and annunciator contrast, using X1X0 as data bits. X1X0=00 (Von=0.87VDD) X1X0=01 (Von=0.71VDD) X1X0=10 (Von=0.61VDD) (POR initial state) X1X0=11 (Von=0.55VDD) 0001X3X2X1X0 Set Contrast Level Set one of the 16 available values to the internal contrast register, using X3X2X1X0 as data bits. The contrast register is reset to 0000 during POR 0001X3X2X1X0 Read Contrast Value With DCOM pin input low, RW pin input high, and D7~d4 pins equal to 0001 at the rising edge of CS, the value of the internal contrast register will be latched out at D3, D2, D1 and D0 pins, i.e. X3X2X1X0 at the rising edge of CS. 0010000X0 Set Voltage Doubler/Tripler X0=0: Select voltage tripler (POR initial state) X0=1: Select voltage doubler 0010001X0 Set Column Mapping X0=0: COL0 to SEG0 (POR initial state) X0=1: COL0 to SEG119 0010010X0 Set Row Mapping X0=0: ROW0 to COM0 (POR initial state) X0=1: ROW0 to COM31 0010011X0 Reserved 0010100X0 Set Display On/Off X0=0: Display off (POR initial state) X0=1: Display on 0010101X0 Set DC/DC Converter On/Off X0=0: DC/DC converter off (POR initial state) X0=1: DC/DC converter on 0010110X0 X0=0: Internal regulator off (POR initial state) X0=1: Internal regulator on Set Internal Regulator On/Off When the application employs external contrast control, the internal contrast control, temperature compensation and the regulator must be enabled. 0010111X0 X0=0: Internal voltage divider off (POR initial state) Set Internal Voltage Divider X0=1: Internal voltage divider on On/Off When an external bias network is preferred, the voltage divider should be disabled. 0011000X0 X0=0: Internal contrast control off (POR initial state) Set Internal Contrast Control X0=1: Internal contrast control on On/Off Internal contrast circuits can be disabled if external contrast circuit is preferred. 0011001X0 Set Clock Frequency 0011010X0 Save/Restore RAM Column X0=0: Restore address Address X0=1: Save address 00110110 Master Clear RAM Master clear BGDRAM page 1 to 4 00110111 Master Clear Icons Master clear of BGDRAM page 5 Rev. 1.00 X0=0: Low frequency (38.4kHz) (POR initial state) X0=1: High frequency (50kHz) 15 February 24, 2004 HT0610 Bit Pattern (D7~D0) Command Comment 0011100X0 Set Bias Ratio X0=0: Set 1/7 bias (POR initial state) X0=1: Set 1/5 bias 0011101X0 Reserved X0=0: Normal operation (POR initial state) X0=1: Test mode (Note: make sure to set X0=0: during application) 0011110X0 Set Display with Icon Line X0=0: Set display mode without Icon line (POR initial state) X0=1: Set display mode with Icon line 00111110 Set Icon Display Mode Power saving icon display mode, COM 0 to COM 31 will be disabled. 010X4X3X2X1X0 Set Vertical Scroll Value Use X4X3X2X1 as number for lines to scroll. Scroll value=0 upon POR 01100A1A0X0 A1A0=00: Select Icon 1 (POR initial state) A1A0=01: Select Icon 2 Set Static Icon Control Sig- A1A0=10: Select Icon 3 nals A1A0=11: Select Icon 4 X0=0: Turned selected Icon off (POR state) X0=1: Turned selected Icon on 0110100X0 Set Duty Cycle X0=0: 1/32 duty and triple enabled (POR initial state) X0=1: 1/16 duty and doubler enabled 0110101X0 Set IDD Reduction Mode X0=0: Normal mode X0=1: IDD reduction mode 011011X1X0 X0=00: 0.00% (POR initial state) X0=01: -0.18% Set Temperature Coefficient X0=10: -0.22% X0=11: -0.35% 0111000X0 X0=0: Decrease by one level (POR initial state) Increase/Decrease Contrast X0=1: Increase by one level Value (Note: increment/decrement wraps round among the 16 contrast levels. Start at the lowest level when POR. 0111001X0 Reserved 0111010X0 Reserved 0111011X0 Reserved 0111100X0 Reserved 0111101X0 Set Internal/External Oscillator 0111110X0 Reserved 0111111X0 X0=0: Oscillator disable (POR initial state) X0=1: Oscillator enable Set Oscillator Disable/Enable This is the master control for oscillator circuitry. This command should be issued after the ²external/internal oscillator² command. 1X6X5X4X3X2X1X0 Set BGDRAM Address Rev. 1.00 X0=0: Normal operation (POR initial state) X0=1: Test mode select (Note: make sure to set X0=0 during application) X0=0: Internal oscillator (POR initial state) X0=1: External oscillator If resistors are placed at OSC1 and OSC2. For external oscillator, simply feed clock in OSC2. Set BGDRAM column address. Use X6X5X4X3X2X1X0 as address bits 16 February 24, 2004 HT0610 Data read write · To read data from the BGDRAM, input high to RW pin and DCOM pin. Data is valid at the falling edge of CS. And the BGDRAM column address pointer will be increased by one automatically. · To write data to the BGDRAM, input low to RW pin and high to DCOM pin. Data is latched at the falling edge of CS. And the BGDRAM column address pointer will be increased by one automatically. · No auto address pointer increment will be performed for the dummy write data after ²master clear BGDRAM² Address increment table (Automatic) DCOM RW Comment Address Increment 0 0 Write command 0 1 Read command 1 0 Write data Ö 1 1 Read data Ö Note *1 *2 Address increment is done automatically data read write. The column address pointer of BGDRAM*3 is affected. Note: ²*1² Refer to the command read contrast value ²*2² If write data is issued after command clear RAM, address increase is not applied ²*3² Column address will be wrapped around when overflow Power up sequence (Command required) Command Required POR Status Note Set Clock Frequency Low *1 Set Oscillator Enable Disable *1 Set Static Icon Control Signals Static Icon off *1 Set Duty Cycle 1/32 duty *1 Set Bias Ratio 1/7 bias *1 Set Internal DC/DC Converter On Off *1 Set Internal Regulator On Off *1 Set Temperature Coefficient TC=0% *1, *3 Set Internal Contrast Control On Off *1, *3 Increase Contrast Level Contrast level=0 *1, *2, *3 Set Internal Voltage Divider On Off *1 Set Segment Mapping SEG0=COLUMN0 Set Common Mapping COM0=ROW0 Set Vertical Scroll Value Scroll value=0 Set Display On Off Note: ²*1² Required only if desired status differ from power on reset ²*2² Effective only if internal contrast control is enabled. ²*3² Effective only if the regulator is enabled. Rev. 1.00 17 February 24, 2004 HT0610 Command Required for Display Mode Setup Display Mode Command Required Display Mode Set external/internal oscillator* Set oscillator enable* Set display on* Static Icon Display Set external/internal oscillator* Set oscillator enable* Set static Icon control signal* Standby Mode 1 Set display off* Set oscillator disable* Standby Mode 2 Set external oscillator* Set static Icon control signal* Set display off* Set oscillator enable* Standby Mode 3 Set internal oscillator* Set static Icon control signal* Set display off* Set oscillator enable* Other related command with display mode: set duty cycle, set column mapping, set row mapping, set vertical scroll value. Command Related to Internal DC/DC Converter Set oscillator disable/enable, set internal regulator on/off, set duty cycle, set temperature coefficient, set internal contrast control on/off, increase contrast level, set internal voltage divider on/off, set bias ratio, set display on/off, set internal/external oscillator, set contrast level, set voltage doubler/tripler, set 33 mux display mode, set Icon display mode. * You do not need to resend the command again if it is set previously. Command Required for R/W Actions on RAM R/W Actions on RAM Command Required Read data from BGDRAM Write data to BGDRAM Set BGDRAM page address* Set BGDRAM column address* Read/write data Save or restore BGDRAM column address Save or restore BGDRAM column address Increase BGDRAM address by one Dummy read data Master clear BGDRAM Master clear BGDRAM Dummy write data * You do not need to resend the command again if it is set previously. Rev. 1.00 18 February 24, 2004 HT0610 Note: Film: UPILEX-S 75±5mm thickness Copper: FQ-VLP 25±5mm thickness Adhesive: Toray #7100, 12±2mm thickness Solder resist: AE-70-M11, 26±14mm thickness Flex coating: FS-100L Min. 10mm Plating: Sn 0.21±0.05mm thickness All corner radii of base film are less than 0.2mm unless otherwise noted Other specs than display in this drawing are based on the standard spec lists All dimensional tolerances of ²SR² & ²Flex² are ±0.2mm & 0.3mm unless otherwise noted All dimensional tolerances of ²base film² are ±0.05mm unless otherwise noted Inner lead accumulative pitch: Output side: 9.359±0.008mm Input side: 9.077±0.008mm Reel size: F405mm Rev. 1.00 19 February 24, 2004 HT0610 Application Circuits 32/33 MUX display with analog circuitry enabled, tripler enabled and 1/7 bias T o L C D M P U /M C U w ith P a r a lle l In te rfa c e P a n e l C O M 0 ~ C O M 3 2 S E G 0 ~ S E G 1 1 9 A N N 1 ~ A N N 4 , B P R E S C S C E R W D C O M V D D V S S V D D A V L L 2 V L L 3 D 0 ~ D 7 H T 0 6 1 0 D U M 2 D U M 1 V L L 4 V L L 5 E P R O M D D 0 .1 m F 0 .1 m F 0 .1 m F 0 .1 m F 0 .1 m F 0 .1 m F 0 .1 m F 0 .1 m F 0 .1 m F V R V C C A 1 V F C 2 P C 1 N C 1 P C 2 N C 2 C 1 O S C 1 V L L 6 O S C 2 R A M V 0 .1 m F 1 5 0 k W 9 1 0 k W 0 .1 m F 0 .1 m F 0 .1 m F 5 6 0 p F 4 .7 m F 3 0 0 k W N o te : V R a n d V F c a n b e le ft o p e n w h e n R e g u la to r is d is a b le d . 16 MUX display with analog circuitry enabled, tripler enabled and 1/5 bias T o L C D P a n e l M P U /M C U w ith P a r a lle l In te rfa c e C O M 0 ~ C O M 3 2 S E G 0 ~ S E G 1 1 9 A N N 1 ~ A N N 4 , B P R E S C S C E R W D C O M V D D V S S V D D A V L L 2 V L L 3 D 0 ~ D 7 H T 0 6 1 0 V L L 4 V L L 5 E P R O M D D 0 .1 m F 0 .1 m F 0 .1 m F 0 .1 m F 0 .1 m F 0 .1 m F 0 .1 m F V R V C C A 1 V F C 2 N C 2 P C 1 P C 1 N C 2 C 1 O S C 1 V L L 6 O S C 2 V D U M 2 D U M 1 R A M 0 .1 m F 1 5 0 k W E x te rn a l C lo c k 0 .1 m F 0 .1 m F 5 6 0 p F 3 0 0 k W 4 .7 m F N o te : V R a n d V F c a n b e le ft o p e n w h e n R e g u la to r is d is a b le d . Rev. 1.00 20 February 24, 2004 HT0610 16/32/33 MUX display with analog circuitry disabled T o L C D R E S C S C E R W D C O M 0 .1 m F V S S V D D 0 .1 m F V L L 2 D 0 ~ D 7 V L L D U M D U M V L L H T 0 6 1 0 3 2 1 4 V L L 5 V F V R C 2 P C 2 N C 2 C 1 O S C 1 E P R O M O S C 2 R A M V D D V D D A C 1 N /M C U ith r a lle l rfa c e C O M 0 ~ C O M 3 2 S E G 0 ~ S E G 1 1 9 A N N 1 ~ A N N 4 , B P C 1 P M P U w P a In te P a n e l V L L 6 V C C A 1 V C C E x te rn a l C lo c k N o te : V R a n d V F c a n b e le ft o p e n w h e n R e g u la to r is d is a b le d . Rev. 1.00 21 February 24, 2004 HT0610 Holtek Semiconductor Inc. (Headquarters) No.3, Creation Rd. II, Science Park, Hsinchu, Taiwan Tel: 886-3-563-1999 Fax: 886-3-563-1189 http://www.holtek.com.tw Holtek Semiconductor Inc. (Sales Office) 4F-2, No. 3-2, YuanQu St., Nankang Software Park, Taipei 115, Taiwan Tel: 886-2-2655-7070 Fax: 886-2-2655-7373 Fax: 886-2-2655-7383 (International sales hotline) Holtek Semiconductor (Shanghai) Inc. 7th Floor, Building 2, No.889, Yi Shan Rd., Shanghai, China Tel: 021-6485-5560 Fax: 021-6485-0313 http://www.holtek.com.cn Holtek Semiconductor (Hong Kong) Ltd. Block A, 3/F, Tin On Industrial Building, 777-779 Cheung Sha Wan Rd., Kowloon, Hong Kong Tel: 852-2-745-8288 Fax: 852-2-742-8657 Holmate Semiconductor, Inc. 46712 Fremont Blvd., Fremont, CA 94538 Tel: 510-252-9880 Fax: 510-252-9885 http://www.holmate.com Copyright Ó 2004 by HOLTEK SEMICONDUCTOR INC. The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. Holtek¢s products are not authorized for use as critical components in life support devices or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw. Rev. 1.00 22 February 24, 2004