HT36F2 Music Synthesizer 8-Bit MCU Technical Document · Tools Information · FAQs · Application Note Features · Operating voltage: 2.4V~5.0V · Oscillation modes: XTAL/RCOSC · Operating frequency: · Low voltage reset Xtal: 6MHz~8MHz ROSC: typ. 6MHz · Eight-level subroutine nesting · Watchdog timer · Built-in 32K´16-bit (0.5M-bit) ROM for program/data · Supports 8-bit table read instruction (TBLP) shared · HALT function and wake-up feature reduce power · Built-in 8 bit MCU with 208´8 bits RAM consumption · Two 8 bit programmable timer with 8 stage prescaler · Bit manipulation instructions · 16 bidirectional I/O lines · 63 powerful instructions · Four polyphonic synthesizer · All instructions in 1 or 2 machine cycles · Mono 16-bit DAC · 16/28-pin SOP package General Description microprocessor which controls the synthesizer to generate the melody by setting the special register. A HALT feature is provided to reduce power consumption. The HT36F2 is an 8-bit high performance RISC architecture microcontroller specifically designed for various music applications. It provides an 8-bit MCU and a 4-channel Wavetable synthesizer. It has a built-in 8-bit Block Diagram 3 2 K ´ 1 6 - b it R O M P A 0 ~ P A 7 P B 0 ~ P B 7 O S C 1 O S C 2 R E S Rev. 1.00 8 - B it M C U V D V S V D V S 2 0 8 ´ 8 R A M M u ltip lie r /P h a s e G e n e ra l 1 1 6 - B it D A C D S D A S A A U D August 15, 2005 HT36F2 Pin Assignment P B 1 1 2 8 P B 2 P B 0 2 2 7 P B 3 A U D 3 2 6 P B 4 T E S T 4 2 5 P B 5 V D D A 5 2 4 P B 6 V S S A 6 2 3 P B 7 A U D 1 1 6 P A 7 O S C 2 7 2 2 P A 7 V D D A 2 1 5 P A 6 O S C 1 8 2 1 P A 6 V S S A 3 1 4 P A 5 V S S 9 2 0 P A 5 O S C 2 4 1 3 P A 4 V D D 1 0 1 9 P A 4 O S C 1 5 1 2 P A 3 R E S 1 1 1 8 P A 3 V S S 6 1 1 P A 2 N C 1 2 1 7 P A 2 V D D 7 1 0 P A 1 N C 1 3 1 6 P A 1 R E S 8 9 P A 0 N C 1 4 1 5 P A 0 H T 3 6 F 2 2 8 S O P -A H T 3 6 F 2 1 6 S O P -A Pad Assignment 4 2 5 2 4 2 3 2 2 P B 5 P B 4 3 V S S A P B 2 2 P B 3 T E S T V D D A P B 0 1 P B 1 A U D 1 9 2 1 2 0 1 8 1 7 1 6 P B 6 P B 7 P A 7 1 5 1 4 P A 6 P A 5 P A 4 1 3 P A 3 (0 , 0 ) O S C 2 5 O S C 1 6 V S S 7 V D D 8 R E S 9 1 0 1 1 1 2 P A 1 P A 2 P A 0 Chip size: 2135 ´ 2385 (mm)2 * The IC substrate should be connected to VSS in the PCB layout artwork. Rev. 1.00 2 August 15, 2005 HT36F2 Pad Coordinates Unit: mm Pad No. X Y Pad No. X Y 1 -876.150 1043.000 14 916.350 514.500 2 -876.150 931.200 15 916.350 625.100 3 -876.150 817.560 16 916.350 725.100 4 -876.150 715.600 17 916.350 835.700 5 -916.350 -63.124 18 916.350 935.700 6 -916.350 -740.976 19 916.350 1046.300 7 -916.350 -842.650 20 704.250 1041.550 8 -916.350 -942.650 21 593.650 1041.550 9 -1044.324 22 493.650 1041.550 10 -916.350 710.500 -1041.350 23 383.050 1041.550 11 810.500 -1041.350 24 283.050 1041.550 12 13 921.100 916.350 -1041.350 414.500 25 172.450 1041.550 Pad Description Pad No. Pad Name I/O Internal Connection Function 8, 7 VDD, VSS ¾ ¾ Digital power supply, ground 3,4 VDDA, VSSA ¾ ¾ DAC power supply 10~17 PA0~PA7 I/O Wake-up, Pull-high or None Bidirectional 8-bit I/O port, wake-up by mask option 25~18 PB0~PB7 I/O Pull-high or None Bidirectional 8-bit I/O port 9 RESET I ¾ 6 OSC1 I X¢tal/Resistor 5 OSC2 O ¾ XOUT or T1 1 AUD O ¾ DAC output interface Reset input, active low XIN for X¢tal or ROSCIN for resistor by mask option Absolute Maximum Ratings Supply Voltage ..........................VSS-0.3V to VSS+5.5V Storage Temperature ...........................-50°C to 125°C Input Voltage .............................VSS-0.3V to VDD+0.3V Operating Temperature ..........................-25°C to 70°C Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maximum Ratings² may cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability. Rev. 1.00 3 August 15, 2005 HT36F2 Electrical Characteristics Symbol Parameter VDD Operating Voltage IDD Operating Current Ta=25°C Test Conditions Min. Typ. Max. Unit 2.4 4.5 5 V ¾ 2 8 ¾ 8 10 ¾ 1 ¾ ¾ 1 3 ¾ 5 ¾ ¾ mA ¾ 5 ¾ ¾ mA VDD Conditions ¾ ¾ 3V No load (OSC= 6MHz) 4.5V ISTB 3V ¾ Standby Current 4.5V 3V mA mA IOH Flag Source Current IOL Flag Sink Current VIH Input High Voltage for I/O Ports ¾ ¾ 0.8VDD ¾ VDD V VIL Input Low Voltage for I/O Ports ¾ ¾ 0 ¾ 0.2VDD V Rev. 1.00 4.5V 3V 4.5V 4 August 15, 2005 HT36F2 Function Description When executing a jump instruction, conditional skip execution, loading PCL register, subroutine call, initial reset, internal interrupt, external interrupt or return from subroutine, the PC manipulates the program transfer by loading the address corresponding to each instruction. Execution Flow The system clock for the HT36F2 is derived from either a crystal or an RC oscillator. The oscillator frequency divided by 2 is the system clock for the MCU and it is internally divided into four non-overlapping clocks. One instruction cycle consists of four system clock cycles. The conditional skip is activated by instruction. Once the condition is met, the next instruction, fetched during the current instruction execution, is discarded and a dummy cycle replaces it to retrieve the proper instruction. Otherwise proceed with the next instruction. Instruction fetching and execution are pipelined in such a way that a fetch takes one instruction cycle while decoding and execution takes the next instruction cycle. However, the pipelining scheme causes each instruction to effectively execute in one cycle. If an instruction changes the program counter, two cycles are required to complete the instruction. The lower byte of the program counter (PCL) is a readable and writeable register (06H). Moving data into the PCL performs a short jump. The destination will be within 256 locations. Program Counter - PC Once a control transfer takes place, an additional dummy cycle is required. The 13-bit program counter (PC) controls the sequence in which the instructions stored in program ROM are executed and its contents specify a maximum of 8192 addresses for each bank. Program ROM HT36F2 provides 16 address lines WA15~WA0 to read the Program ROM which is up to 0.5M bits, and is commonly used for the wavetable voice codes and the program memory. It provides two address types, one type is for program ROM, which is addressed by a bank pointer PF1~PF0 and a 13-bit program counter PC12~PC0; After accessing a program memory word to fetch an instruction code, the contents of the program counter are incremented by one. The program counter then points to the memory word containing the next instruction code. S y s te m C lo c k o f M C U ( S y s te m C lo c k /2 ) T 1 T 2 T 3 T 4 T 1 T 2 P C P C T 3 T 4 T 1 T 2 P C + 1 F e tc h IN S T (P C ) E x e c u te IN S T (P C -1 ) T 3 T 4 P C + 2 F e tc h IN S T (P C + 1 ) E x e c u te IN S T (P C ) F e tc h IN S T (P C + 2 ) E x e c u te IN S T (P C + 1 ) Execution Flow Mode Initial Reset Program Counter *14 *13 *12 *11 *10 0 0 *9 *8 *7 *6 *5 *4 *3 *2 *1 *0 0 0 0 0 0 0 0 0 0 0 0 0 0 Timer/Event Counter 0 Overflow PF1 PF0 0 0 0 0 0 0 0 0 0 1 0 0 0 Timer/Event Counter 1 Overflow PF1 PF0 0 0 0 0 0 0 0 0 0 1 1 0 0 Skip Program Counter+2 Loading PCL PF1 PF0 *12 *11 *10 *9 *8 @7 @6 @5 @4 @3 @2 @1 @0 Jump, Call Branch PF1 PF0 #12 #11 #10 #9 #8 #7 #6 #5 #4 #3 #2 #1 #0 Return From Subroutine PF1 PF0 S12 S11 S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 S0 Program Counter Note: *12~*0: Bits of Program Counter S12~S0: Bits of Stack Register @7~@0: Bits of PCL @7~@0: Bits of PCL #12~#0: Bits of Instruction Code PF1~PF0: Bits of Bank Register Rev. 1.00 5 August 15, 2005 HT36F2 0 0 0 0 H and the other type is for wavetable code, which is addressed by the start address ST15~ST0. On the program type, WA15~WA0=PF1~PF0´213+PC12~PC0. On t h e w a v e t a b l e R O M t y pe, W A 1 5 ~W A 0 = ST15~ST0´25. D e v ic e in itia liz a tio n p r o g r a m 0 0 0 8 H T im e r C o u n te r 0 in te r r u p t s u b r o u tin e 0 0 0 C H Program Memory - ROM n 0 0 H The program memory is used to store the program instructions which are to be executed. It also contains data, table, and interrupt entries, and is organized into 8192´16 bits, addressed by the bank pointer, program counter and table pointer. n F F H T im e r C o u n te r 1 in te r r u p t s u b r o u tin e L o o k - u p ta b le ( 2 5 6 w o r d s ) 1 F F F H 1 6 b its Certain locations in the program memory of each bank are reserved for special usage: N o te : n ra n g e s fro m 0 0 to 3 F . Program Memory for Each Bank · Location 000H on bank0 This area is reserved for the initialization program. After chip reset, the program always begins execution at location 000H on bank0. be placed in TBLP. The TBLH is read only and cannot be restored. If the main routine and the ISR (Interrupt Service Routine) both employ the table read instruction, the contents of the TBLH in the main routine are likely to be changed by the table read instruction used in the ISR. Errors can occur. In this case, using the table read instruction in the main routine and the ISR simultaneously should be avoided. However, if the table read instruction has to be applied in both the main routine and the ISR, the interrupt should be disabled prior to the table read instruction. It will not be enabled until the TBLH has been backed up. All table related instructions need 2 cycles to complete the operation. These areas may function as normal program memory depending upon user requirements. · Location 008H This area is reserved for the Timer Counter 0 interrupt service program on each bank. If timer interrupt results from a timer counter 0 overflow, and if the interrupt is enabled and the stack is not full, the program begins execution at location 008H corresponding to its bank. · Location 00CH This area is reserved for the Timer Counter 1 interrupt service program on each bank. If a timer interrupt results from a Timer Counter 1 overflow, and if the interrupt is enabled and the stack is not full, the program begins execution at location 00CH corresponding to its bank. · Bank pointer The program memory is organized into 4 banks and each bank into 8192´16 bits of program ROM. PF1~PF0 is used as the bank pointer. After an instruction has been executed to write data to the PF register to select a different bank, note that the new bank will not be selected immediately. It is not until the following instruction has completed execution that the bank will be actually selected. It should be note that the PF register has to be cleared before setting to output mode. · Table location Any location in the ROM space can be used as look-up tables. The instructions ²TABRDC [m]² (the current page, 1 page=256 words) and ²TABRDL [m]² (the last page) transfer the contents of the lower-order byte to the specified data memory, and the higher-order byte to TBLH (08H). Only the destination of the lower-order byte in the table is well-defined, the higher-order byte of the table word are transferred to the TBLH. The Table Higher-order byte register (TBLH) is read only. The Table Pointer (TBLP) is a read/write register (07H), which indicates the table location. Before accessing the table, the location must Instruction (s) P ro g ra m R O M L o o k - u p ta b le ( 2 5 6 w o r d s ) Wavetable ROM The ST15~ST0 is used to defined the start address of each sample on the wavetable and read the waveform data from the location. HT36F2 provides 16 output adTable Location *14 *13 *12 *11 *10 *9 *8 *7 *6 *5 *4 *3 *2 *1 *0 TABRDC [m] P14 P13 P12 P11 P10 P9 P8 @7 @6 @5 @4 @3 @2 @1 @0 TABRDL [m] P14 P13 1 1 1 1 1 @7 @6 @5 @4 @3 @2 @1 @0 Table Location Note: *12~*0: Bits of table location P12~P8: Bits of current Program Counter @7~@0: Bits of table pointer P14~P13: Bits of Bank PF1~PF0 Rev. 1.00 6 August 15, 2005 HT36F2 0 0 H dress lines from WA15~WA0, the ST15~ST0 is used to locate the major 11 bits i.e. WA15~WA5 and the undefined data from WA4~WA0 is always set to 00000b. So the start address of each sample have to be located at a multiple of 32. Otherwise, the sample will not be read out correctly because it has a wrong starting code. M P 0 0 2 H In d ir e c t A d d r e s s in g R e g is te r 1 0 3 H M P 1 0 4 H 0 5 H Stack Register - Stack This is a special part of the memory which is used to save the contents of the program counter only. The stack is organized into 8 levels and is neither part of the data nor part of the program space, and is neither readable nor writeable. The activated level is indexed by the stack pointer (SP) and is neither readable nor writeable. At a subroutine call or interrupt acknowledgment, the contents of the program counter are pushed onto the stack. At the end of a subroutine or an interrupt routine, signaled by a return instruction (RET or RETI), the program counter is restored to its previous value from the stack. After a chip reset, the SP will point to the top of the stack. A C C 0 6 H P C L 0 7 H T B L P 0 8 H T B L H 0 9 H W D T S 0 A H S T A T U S 0 B H IN T C 0 C H 0 D H T M R 0 L 0 E H T M R 0 C S p e c ia l P u r p o s e D A T A M E M O R Y 0 F H T M R 1 L T M R 1 C 1 0 H 1 1 H 1 2 H P A 1 3 H P A C 1 4 H P B 1 5 H P B C 1 6 H 1 7 H 1 8 H If the stack is full and a non-masked interrupt takes place, the interrupt request flag will be recorded but the acknowledgment will be inhibited. When the stack pointer is decremented (by RET or RETI), the interrupt will be serviced. This feature prevents stack overflow allowing the programmer to use the structure more easily. In a similar case, if the stack is full and a CALL is subsequently executed, a stack overflow occurs and the first entry will be lost (only the most recent eight return address are stored). 1 9 H 1 A H 1 B H P F 1 C H 1 D H 1 E H 1 F H Data Memory - RAM The data memory is designed with 256 ´ 8 bits. The data memory is divided into three functional groups: special function registers, wavetable function register, and general purpose data memory (208´8). Most of them are read/write, but some are read only. D A C H ig h B y te ( D A H ) D A C L o w D A C B y te (D A L ) C o n tro l (D A C ) 2 0 H C h a n n e l N u m b e r S e le c t ( C H A N ) 2 1 H F r e q u e n c y N u m b e r H ig h B y te ( F r e q N H ) 2 2 H F re q u e n c y N u m b e r L o w B y te (F re q N L ) 2 3 H S ta r t A d d r e s s H ig h B y te ( A d d r H ) 2 4 H S ta rt A d d re s s L o w 2 5 H R e p e a t N u m b e r H ig h B y te ( R e H ) 2 6 H R e p e a t N u m b e r L o w B y te (R e L ) 2 7 H V o lu m e C o n tr o l H ig h ( V o lH ) B y te (A d d rL ) W a v e ta b le F u n c tio n R e g is te r 2 8 H 2 9 H 2 A H 2 B H The special function registers include the Indirect Addressing register 0 (00H), the Memory Pointer register 0 (MP0;01H), the Indirect Addressing register 1 (02H), the Memory Pointer register 1 (MP1;03H), the Accumulator (ACC;05H), the Program Counter Lower-byte register (PCL;06H), the Table Pointer (TBLP;07H), the Table Higher-order byte register (TBLH;08H), the Watchdog Timer option Setting register (WDTS;09H), the Status register (STATUS;0AH), the Interrupt Control register (INTC;0BH), the Timer Counter 0 Lower-order byte register (TMR0L;0DH), the Timer Counter 0 Control register (TMR0C;0EH), the Timer Counter 1 Lower-order byte register (TMR1L;10H), the Timer Counter 1 Control register (TMR1C;11H), the I/O registers (PA;12H, PB;14H) and the I/O control registers (PAC;13H, PBC;15H, PCC;17H). The program ROM bank select (PF;1CH). The DAC High byte (DAH;1DH). The DAC low byte (DAL;1EH). The DAC control (DAC;1FH). The Rev. 1.00 In d ir e c t A d d r e s s in g R e g is te r 0 0 1 H V o lu m C o n tr o l ( V o lL ) 2 F H 3 0 H : U n u s e d . R e a d a s "0 0 " G e n e ra l P u rp o s e D A T A M E M O R Y (2 0 8 B y te s ) F F H RAM Mapping wavetable function registers is defined between 20H~2AH. The remaining space before the 30H is reserved for future expanded usage and reading these locations will return the result 00H. The general purpose data memory, addressed from 30H to FFH, is used for data and control information under instruction command. 7 August 15, 2005 HT36F2 Status Register - STATUS All data memory areas can handle arithmetic, logic, increment, decrement and rotate operations directly. Except for some dedicated bits, each bit in the data memory can be set and reset by the ²SET [m].i² and ²CLR [m].i² instructions, respectively. They are also indirectly accessible through Memory pointer registers (MP0:01H, MP1:03H). This 8-bit register (0AH) contains the zero flag (Z), carry flag (C), auxiliary carry flag (AC), overflow flag (OV), power down flag (PDF) and Watchdog time-out flag (TO). It also records the status information and controls the operation sequence. With the exception of the TO and PDF flags, bits in the status register can be altered by instructions like any other register. Any data written into the status register will not change the TO or PDF flags. In addition it should be noted that operations related to the status register may give different results from those intended. The TO and PDF flags can only be changed by system power up, Watchdog Timer overflow, executing the ²HALT² instruction and clearing the Watchdog Timer. Indirect Addressing Register Location 00H and 02H are indirect addressing registers that are not physically implemented. Any read/write operation of [00H] and [02H] access data memory pointed to by MP0 (01H) and MP1 (03H) respectively. Reading location 00H or 02H directly will return the result 00H. And writing directly results in no operation. The function of data movement between two indirect addressing registers, is not supported. The memory pointer registers, MP0 and MP1, are 8-bit register which can be used to access the data memory by combining corresponding indirect addressing registers. The Z, OV, AC and C flags generally reflect the status of the latest operations. In addition, on entering the interrupt sequence or executing a subroutine call, the status register will not be automatically pushed onto the stack. If the contents of status are important and the subroutine can corrupt the status register, the programmer must take precautions to save it properly. Accumulator The accumulator closely relates to ALU operations. It is mapped to location 05H of the data memory and it can operate with immediate data. The data movement between two data memory locations must pass through the accumulator. Interrupt The HT36F2 provides two internal timer counter interrupts on each bank. The Interrupt Control register (INTC;0BH) contains the interrupt control bits that sets the enable/disable and the interrupt request flags. Arithmetic and Logic Unit - ALU This circuit performs 8-bit arithmetic and logic operation. The ALU provides the following functions: Once an interrupt subroutine is serviced, all other interrupts will be blocked (by clearing the EMI bit). This scheme may prevent any further interrupt nesting. Other interrupt requests may occur during this interval but only the interrupt request flag is recorded. If a certain interrupt needs servicing within the service routine, the programmer may set the EMI bit and the corresponding bit of the INTC to allow interrupt nesting. If the stack is full, the interrupt request will not be acknowledged, even if · Arithmetic operations (ADD, ADC, SUB, SBC, DAA) · Logic operations (AND, OR, XOR, CPL) · Rotation (RL, RR, RLC, RRC) · Increment & Decrement (INC, DEC) · Branch decision (SZ, SNZ, SIZ, SDZ ....) The ALU not only saves the results of a data operation but can also change the status register. Bit No. Label Function 0 C C is set if an operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation; otherwise C is cleared. Also it is affected by a rotate through carry instruction. 1 AC AC is set if an operation results in a carry out of the low nibbles in addition or no borrow from the high nibble into the low nibble in subtraction; otherwise AC is cleared. 2 Z Z is set if the result of an arithmetic or logical operation is zero; otherwise Z is cleared. 3 OV OV is set if an operation results in a carry into the highest-order bit but not a carry out of the highest-order bit, or vice versa; otherwise OV is cleared. 4 PDF PDF is cleared by either a system power-up or executing the ²CLR WDT² instruction. PDF is set by executing the ²HALT² instruction. 5 TO TO is cleared by a system power-up or executing the ²CLR WDT² or ²HALT² instruction. TO is set by a WDT time-out. 6~7 ¾ Unused bit, read as ²0² Status (0AH) Register Rev. 1.00 8 August 15, 2005 HT36F2 the related interrupt is enabled, until the SP is decremented. If immediate service is desired, the stack must be prevented from becoming full. The Timer Counter 0/1 interrupt request flag (T0F/T1F), Enable Timer Counter 0/1 bit (ET0I/ET1I) and Enable Master Interrupt bit (EMI) constitute an interrupt control register (INTC) which is located at 0BH in the data memory. EMI, ET0I, ET1I are used to control the enabling/disabling of interrupts. These bits prevent the requested interrupt from being serviced. Once the interrupt request flags (T0F, T1F) are set, they will remain in the INTC register until the interrupts are serviced or cleared by a software instruction. All these kinds of interrupt have a wake-up capability. As an interrupt is serviced, a control transfer occurs by pushing the program counter onto the stack and then branching to subroutines at specified locations in the program memory. Only the program counter is pushed onto the stack. If the contents of the register and Status register (STATUS) are altered by the interrupt service program which may corrupt the desired control sequence, then the programmer must save the contents first. It is recommended that a program does not use the ²CALL subroutine² within the interrupt subroutine. Because interrupts often occur in an unpredictable manner or need to be serviced immediately in some applications, if only one stack is left and enabling the interrupt is not well controlled, once the ²CALL subroutine² operates in the interrupt subroutine, it may damage the original control sequence. The internal Timer Counter 0 interrupt is initialized by setting the Timer Counter 0 interrupt request flag (T0F; bit 5 of INTC), caused by a Timer Counter 0 overflow. When the interrupt is enabled, and the stack is not full and the T0F bit is set, a subroutine call to location 08H will occur. The related interrupt request flag (T0F) will be reset and the EMI bit cleared to disable further interrupts. Oscillator Configuration The HT36F2 provides two types of oscillator circuit for the system clock, i.e., RC oscillator and crystal oscillator. No matter what type of oscillator, the signal divided by 2 is used for the system clock. The HALT mode stops the system oscillator and ignores external signal to conserve power. If the RC oscillator is used, an external resistor between OSC1 and VSS is required. The system clock, divided by 4, is available on OSC2 with pull-high resistor, which can be used to synchronize external logic. The RC oscillator provides the most cost effective solution. However, the frequency of the oscillation may vary with VDD, temperature, and the chip itself due to process variations. It is therefore, not suitable for timing sensitive operations where accurate oscillator frequency is desired. The Timer Counter 1 interrupt is operated in the same manner as Timer Counter 0. The related interrupt control bits ET1I and T1F of the Timer Counter 1 are bit 3 and bit 6 of the INTC respectively. During the execution of an interrupt subroutine, other interrupt acknowledgments are held until the ²RETI² instruction is executed or the EMI bit and the related interrupt control bit are set to 1 (if the stack is not full). To return from the interrupt subroutine, the ²RET² or ²RETI² instruction may be invoked. RETI will set the EMI bit to enable an interrupt service, but RET will not. Interrupts occurring in the interval between the rising edges of two consecutive T2 pulses, will be serviced on the latter of the two T2 pulses, if the corresponding interrupts are enabled. In the case of simultaneous requests the priorities in the following table apply. These can be masked by resetting the EMI bit. Interrupt Source Priority Vector Timer Counter 0 overflow 1 08H Timer Counter 1 overflow 2 0CH O S C 1 V fS O S C 2 Y S O S C 1 D D /8 C r y s ta l O s c illa to r O S C 2 R C O s c illa to r System Oscillator Bit No. Label Function 0 EMI 1, 4, 7 ¾ 2 ET0I Controls the Timer Counter 0 interrupt (1=enabled; 0=disabled) 3 ET1I Controls the Timer Counter 1 interrupt (1=enabled; 0=disabled) 5 T0F Internal Timer Counter 0 request flag (1=active; 0=inactive) 6 T1F Internal Timer Counter 1 request flag (1=active; 0=inactive) Controls the Master (Global) interrupt (1=enabled; 0=disabled) Unused bit, read as ²0² INTC (0BH) Register Rev. 1.00 9 August 15, 2005 HT36F2 the logic can only be restarted by external logic. The high nibble and bit 3 of the WDTS are reserved for user defined flags, and the programmer may use these flags to indicate some specified status. On the other hand, if the crystal oscillator is selected, a crystal across OSC1 and OSC2 is needed to provide the feedback and phase shift required for the oscillator, and no other external components are required. A resonator may be connected between OSC1 and OSC2 to replace the crystal and to get a frequency reference, but two external capacitors in OSC1 and OSC2 are required. The WDT oscillator is a free running on-chip RC oscillator, and no external components are required. Even if the system enters the Power Down Mode, the system clock is stopped, but the WDT oscillator still works with a period of approximately 78ms. The WDT oscillator can be disabled by mask option to conserve power. Watchdog Timer - WDT The WDT clock source is implemented by a dedicated RC oscillator (WDT oscillator) or instruction clock (system clock of the MCU divided by 4), determined by mask options. This timer is designed to prevent a software malfunction or sequence jumping to an unknown location with unpredictable results. The Watchdog Timer can be disabled by mask option. If the Watchdog Timer is disabled, all the executions related to the WDT result in no operation. WS1 WS0 Division Ratio 0 0 0 1:1 0 0 1 1:2 0 1 0 1:4 0 1 1 1:8 1 0 0 1:16 1 0 1 1:32 1 1 0 1:64 1 1 1 1:128 If the device operates in a noisy environment, using the on-chip RC oscillator (WDT OSC) is strongly recommended, since the HALT will stop the system clock. The WDT overflow under normal operation will initialize a ²chip reset² and set the status bit TO. Whereas in the HALT mode, the overflow will initialize a ²warm reset² only the Program Counter and SP are reset to zero. To clear the WDT contents (including the WDT prescaler ), 3 methods are implemented; external reset (a low level to RES), software instructions, or a ²HALT² instruction. The software instructions include ²CLR WDT² and the other set - ²CLR WDT1² and ²CLR WDT2². Of these two types of instructions, only one can be active depending on the mask option - ²CLR WDT times selection option². If the ²CLR WDT² is selected (i.e. CLRWDT times equal one), any execution of the ²CLR WDT² instruction will clear the WDT. In case ²CLR WDT1² and ²CLR WDT2² are chosen (i.e. CLRWDT times equal two), these two instructions must be executed to clear the WDT; otherwise, the WDT may reset the chip because of time-out. Once the internal WDT oscillator (RC oscillator with a period of 78ms normally) is selected, it is first divided by 256 (8-stages) to get the nominal time-out period of approximately 20ms. This time-out period may vary with temperature, VDD and process variations. By invoking the WDT prescaler, longer time-out periods can be realized. Writing data to WS2, WS1, WS0 (bit 2,1,0 of the WDTS) can give different time-out periods. If WS2, WS1, WS0 all equal to 1, the division ratio is up to 1:128, and the maximum time-out period is 2.6 seconds. If the WDT oscillator is disabled, the WDT clock may still come from the instruction clock and operate in the same manner except that in the HALT state the WDT may stop counting and lose its protecting purpose. In this situation S y s te m WS2 C lo c k /8 W D T O S C M a s k O p tio n S e le c t W D T P r e s c a le r 8 - b it C o u n te r 7 - b it C o u n te r 8 -to -1 M U X W S 0 ~ W S 2 W D T T im e - o u t Watchdog Timer Rev. 1.00 10 August 15, 2005 HT36F2 Power Down Operation - HALT Reset The HALT mode is initialized by a ²HALT² instruction and results in the following... There are 3 ways in which a reset can occur: · The system oscillator will turn off but the WDT oscilla- · RES reset during HALT · RES reset during normal operation tor keeps running (If the WDT oscillator is selected). Watchdog Timer - WDT · WDT time-out reset during normal operation The WDT time-out during HALT is different from other chip reset conditions, since it can perform a ²warm re set² that just resets the Program Counter and SP, leaving the other circuits to maintain their state. Some registers remain unchanged during any other reset conditions. Most registers are reset to the ²initial condition² when the reset conditions are met. By examining the PDF and TO flags, the program can distinguish between different ²chip resets². · The contents of the on-chip RAM and registers remain unchanged · The WDT and WDT prescaler will be cleared and starts to count again (if the clock comes from the WDT oscillator). · All I/O ports maintain their original status. · The PDF flag is set and the TO flag is cleared. · The HALT pin will output a high level signal to disable the external ROM. The system can leave the HALT mode by means of an external reset, an interrupt, an external falling edge signal on port A or a WDT overflow. An external reset causes a device initialization and the WDT overflow performs a ²warm reset². By examining the TO and PDF flags, the cause for a chip reset can be determined. The PDF flag is cleared when there is a system power-up or by executing the ²CLR WDT² instruction and it is set when a ²HALT² instruction is executed. The TO flag is set if the WDT time-out occurs, and causes a wake-up that only resets the Program Counter and SP, the others remain in their original status. TO PDF RESET Conditions 0 0 RES reset during power-up u u RES reset during normal operation 0 1 RES wake-up HALT 1 u WDT time-out during normal operation 1 1 WDT wake-up HALT Note: ²u² stands for ²unchanged² To guarantee that the system oscillator has started and stabilized, the SST (System Start-up Timer) provides an extra-delay of 1024 system clock pulses during system power up or when the system awakes from a HALT state. The port A wake-up and interrupt methods can be considered as a continuation of normal execution. Each bit in port A can be independently selected to wake-up the device by mask option. Awakening from an I/O port stimulus, the program will resume execution of the next instruction. If awakening from an interrupt, two sequences may occur. If the related interrupts is disabled or the interrupts is enabled but the stack is full, the program will resume execution at the next instruction. If the interrupt is enabled and the stack is not full, a regular interrupt response takes place. When a system power-up occurs, the SST delay is added during the reset period. But when the reset comes from the RES pin, the SST delay is disabled. Any wake-up from HALT will enable the SST delay. The functional units chip reset status are shown below. Once a wake-up event occurs, it takes 1024 tSYS (system clock period) to resume to normal operation. In other words, a dummy cycle period will be inserted after the wake-up. If the wake-up results from an interrupt acknowledge, the actual interrupt subroutine will be delayed by one more cycle. If the wake-up results in next instruction execution, this will execute immediately after a dummy period has finished. If an interrupt request flag is set to ²1² before entering the HALT mode, the wake-up function of the related interrupt will be disabled. Program Counter 000H Interrupt Disable Prescaler Clear WDT Clear. After master reset, WDT begins counting Timer Counter (0/1) Off Input/output ports Input mode Stack Pointer Points to the top of stack V D D R E S tS S T S S T T im e - o u t To minimize power consumption, all I/O pins should be carefully managed before entering the HALT status. C h ip R e s e t Reset Timing Chart Rev. 1.00 11 August 15, 2005 HT36F2 V D D H A L T W D T R E S W a rm W D T R e s e t T im e - o u t R e s e t R E S O S C I Reset Circuit C o ld R e s e t S S T 1 0 -s ta g e R ip p le C o u n te r P o w e r - o n D e te c tin g Reset Configuration The registers status is summarized in the following table: Reset (Power On) WDT Time-out (Normal Operation) RES Reset (Normal Operation) RES Reset (HALT) WDT Time-out (HALT)* MP0 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu MP1 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu ACC xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu Register Program Counter TBLP 0000H 0000H 0000H 0000H 0000H xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu TBLH xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu WDTS 0000 0111 0000 0111 0000 0111 0000 0111 uuuu uuuu STATUS --00 xxxx --1u uuuu --uu uuuu --01 uuuu --11 uuuu INTC -000 0000 -000 0000 -000 0000 -000 0000 -uuu uuuu TMR0L xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu TMR0C 00-0 1000 00-0 1000 00-0 1000 00-0 1000 uu-u 1uuu TMR1L xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu TMR1C 00-0 1000 00-0 1000 00-0 1000 00-0 1000 uu-u 1uuu PA 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu PAC 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu PB 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu PBC 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu PF ---- --00 ---- --00 ---- --00 ---- --00 ---- --uu DAH xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu DAL xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu DAC ---- --00 ---- --00 ---- --00 ---- --00 ---- --uu CHAN 00-- --00 uu-- --uu uu-- --uu uu-- --uu uu-- --uu FreqNH xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu FreqNL xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu AddrH ---x xxxx ---u uuuu ---u uuuu ---u uuuu ---u uuuu AddrL xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu ReH x--x xxxx u--u uuuu u--u uuuu u--u uuuu u--u uuuu ReL xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu VolH x--- xxxx u--- uuuu u--- uuuu u--- uuuu u--- uuuu VolL xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu Note: ²*² stands for warm reset ²u² stands for unchanged ²x² stands for unknown ²-² stands for unused Rev. 1.00 12 August 15, 2005 HT36F2 D a ta B u s Timer 0/1 Timer 0 is an 8-bit counter, and its clock source comes from the system clock divided by an 8-stage prescaler. There are two registers related to Timer 0; TMR0L(0DH) and TMR0C(0EH). One physical registers are mapped to TMR0L location; writing TMR0L makes the starting value be placed in the Timer 0 preload register and reading the TMR0 gets the contents of the Timer 0 counter. The TMR0C is a control register, which defines the division ration of the prescaler and counting enable or disable. S y s te m C lo c k /8 T O N 0 0 0 SYS CLK/16 0 0 1 SYS CLK/32 0 1 0 SYS CLK/64 0 1 1 SYS CLK/128 1 0 0 SYS CLK/256 1 0 1 SYS CLK/512 1 1 0 SYS CLK/1024 1 1 1 SYS CLK/2048 Each I/O line has its own control register (PAC, PBC, PCC0~3) to control the input/output configuration. With this control register, CMOS output or Schmitt trigger input with or without pull-high resistor (mask option) structures can be reconfigured dynamically under software control. To function as an input, the corresponding latch of the control register must write a ²1². The pull-high resistance will exhibit automatically if the pull-high option is selected. The input source also depends on the control register. If the control register bit is ²1², input will read the pad state. If the control register bit is ²0², the contents of the latches will move to the internal bus. The latter is possible in ²read-modify-write² instruction. For output function, CMOS is the only configuration. These control registers are mapped to locations 13H, 15H and 17H. After a chip reset, these input/output lines remain at high levels or floating (mask option). Each bit of these input/output latches can be set or cleared by the ²SET [m].i² or ²CLR [m].i² (m=12H, 14H or 16H) instruction. TMR0C Bit 4 to enable/disable timer counting (1=enable; 0=disable) Some instructions first input data and then follow the output operations. For example, the ²SET [m].i², ²CLR [m].i², ²CPL [m]² and ²CPLA [m]² instructions read the entire port states into the CPU, execute the defined operations (bit-operation), and then write the results back to the latches or the accumulator. Each line of port A has the capability to wake-up the device. TMR0C Bit 3, always write ²0². TMR0C Bit 5, always write ²0². TMR0C Bit 6, always write ²0². TMR0C Bit 7, always write ²1². Rev. 1.00 O v e r flo w There are 20 bidirectional input/output lines labeled from PA to PC0~3, which are mapped to the data memory of [12H], [14H], [16H] respectively. All these I/O ports can be used for input and output operations. For input operation, these ports are non-latching, that is, the inputs must be ready at the T2 rising edge of instruction ²MOV A,[m]² (m=12H, 14H or 16H). For output operation, all data is latched and remains unchanged until the output latch is rewritten. T0F B0 T im e r 0 /1 Input/Output Ports There are two registers related to the Timer Counter1; TMR1L(10H), TMR1C(11H). The Timer Counter 1 operates in the same manner as Timer Counter 0. B1 R e lo a d Timer 0/1 One the Timer 0 starts counting, it will count from the current contents in the counter to FFH. Once an overflow occurs, the counter is reloaded from a preload register, and generates an interrupt request flag (T0F; bit 2 of INTCH). To enable the counting operation, the timer On bit (TON; bit 4 of TMR0C) should be set to ²1². For proper operation, bit 7 of TMR0C should be set to ²1² and bit 3, bit 6 should be set to ²0². TMR0C/TMR1C T im e r 0 /1 P r e lo a d R e g is te r T 0 F Writing data to B2, B1 and B0 (bits 2, 1, 0 of TMR0C) can yield various clock sources. B2 8 -s ta g e P r e s c a le r 13 August 15, 2005 HT36F2 D a ta B u s W r ite C o n tr o l R e g is te r V Q D C K Q S V D D W e a k P u ll- u p D D C h ip R e s e t M a s k O p tio n R e a d C o n tr o l R e g is te r W r ite I/O I/O Q D C K S Q M R e a d I/O S y s te m L in e U X W a k e -U p M a s k O p tio n Input/Output Ports Channel Wavetable Synthesizer Name Function D7 D6 D5 D4 D3 D2 D1 D0 1DH DAC high byte (no default value) DA15 DA14 DA13 DA12 DA11 DA10 DA9 DA8 1EH DAC low byte (no default value) DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0 1FH DAON=1: DAC ON DAON=0: DAC OFF (default) SELW=1: DAC data from wavetable SELW=0: DAC data from MCU ¾ ¾ ¾ ¾ ¾ ¾ 20H Channel number selection VM FR CH2 CH1 CH0 21H High byte frequency number BL3 BL2 BL1 BL0 FR11 FR10 FR9 FR8 22H Low byte frequency number FR7 FR6 FR5 FR0 23H High byte start address 24H Low byte start address ST7 25H Wave bit select, High byte repeat number WBS 26H Low byte repeat number RE7 27H Envelope control, Volume control A_R ST6 28H~29H 2AH FR4 FR3 FR2 FR1 ST12 ST11 ST10 ST9 ST8 ST4 ST3 ST2 ST1 ST0 RE12 RE11 RE10 RE9 RE8 RE4 RE3 RE2 RE1 RE0 ENV1 ENV0 VR9 VR8 VR3 VR2 VR1 VR0 ST5 RE6 DAON SELW RE5 Unused Volume control VR7 VR6 2BH~2FH VR5 VR4 Unused 30H~FFH Data memory (RAM) General purpose data memory (same as 8-Bit MCU) Memory Map (20H~FFH) Register Note: ²¾² No function, read only, read as ²0². Unused: No function, read only, read as ²0². · CH1~CH0 channel number selection register will be updated on this selected channel. There are two modes that can be selected to reduce the process of setting the register. Please refer to the statements of the following table: The HT36F2 has a built-in 8 output channels and CH1~CH0 is used to define which channel is selected. When this register is written to, the wavetable synthesizer will automatically output the dedicated PCM code. So this register is also used as a start playing key and it has to be written to after all the other wavetable function registers are already defined. · Change parameter selection VM FR Function 0 0 Update all the parameter 0 1 Only update the frequency number 1 0 Only update the volume These two bits, VM and FR, are used to define which Rev. 1.00 14 August 15, 2005 HT36F2 · Output frequency definition · Repeat number definition The repeat number is used to define the address which is the repeat point of the sample. When the repeat number is defined, it will be output from the start code to the end code once and always output the range between the repeat address to the end code (80H) until the volume become close. The RE12~RE0 is used to calculate the repeat address of the PCM code. The process for setting the RE12~RE0 is to write the 2¢s complement of the repeat length to RE12~RE0, with the highest carry ignored. The HT36F2 will get the repeat address by adding the RE12~RE0 to the address of the end code, then jump to the address to repeat this range. The data on BL3~BL0 and FR11~FR0 are used to define the output speed of the PCM file, i.e. it can be used to generate the tone scale. When the FR11~FR0 is 800H and BL3~BL0 is 6H, each sample data of the PCM code will be sent out sequentially. When the fOSC is 6.4MHz, the formula of a tone frequency is: 25kHz FR11 ~ FR0 fOUT= fRECORD x x (17 -BL3~BL0) SR 2 where fOUT is the output signal frequency, fRECORD and SR is the frequency and sampling rate on the sample code, respectively. So if a voice code of C3 has been recorded which has the fRECORD of 261Hz and the SR of 11025Hz, the tone frequency (fOUT) of G3: fOUT=98Hz. Can be obtained by using the fomula: 25kHz FR11 ~ FR0 98Hz= 261Hz x x 11025Hz 2 (17 -BL3~BL0) A pair of the values FR11~FR0 and BL3~BL0 can be determined when the fOSC is 6.4MHz. · Volume control The HT36F2 provides the volume control independently. The volume are controlled by VR9~VR0 respectively. The chip provides 1024 levels of controllable volume, the 000H is the maximum and 3FFH is the minimum output volume. · The PCM code definition · Start address definition The HT36F2 can only solve the voice format of the signed 8-bit or 12-bit raw PCM. And the MCU will take the voice code 80H as the end code. So each PCM code section must be ended with the end code 80H. The HT36F2 provides two address types for extended use, one is the program ROM address which is program counter corresponding with PF value, the other is the start address of the PCM code. The ST15~ST0 is used to define the start address of each PCM code and reads the waveform data from this location. The HT36F2 provides 16 input data lines from WA15~WA0, the ST15~ST0 is used to locate the major 12 bits i.e. WA15~WA5 and the undefined data from WA4~WA0 is always set as 00000b. In other words, the WA15~WA0=ST15~ST0´25. So each PCM code has to be located at a multiple of 32. Otherwise, the PCM code will not be read out correctly because it has a wrong start code. · Digital to Analog Converter - DAC The HT36F2 provides one 16-bit voltage type DAC device controlled by the MCU or Wavetable Synthesizer for driving the external speaker through an external NPN transistor. It is in fact an optional object used for Wavetable Synthesizer DAC or general DAC, this is chosen by Mask Option and DAC control register. If the general DAC is chosen for application, then the Wavetable Synthesizer is disabled since the DAC is taken up and controlled by the MCU. If general DAC is selected, the programmer must write the voice data to register DAL and DAH to get the corresponding analog data. If Mask Option enables the DAC register and the SELW, then the following table comes useful. · Waveform format definition The HT36F2 accepts two waveform formats to ensure a more economical data space. WBS is used to define the sample format of each PCM code. ¨ WBS=0 means the sample format is 8-bit ¨ WBS=1 means the sample format is 12-bit The 12-bit sample format allocates location to each sample data. Please refer to the waveform format statement as shown below. 8 - B it 1 B 2 B 3 B 4 B 5 B 6 B 7 B 1 H 1 M 1 L 2 L 2 H 2 M 3 H Label Bit7~Bit3 ¾ Bit1 DAON 8 B Bit0 A s a m p lin g d a ta c o d e ; B m e a n s o n e d a ta b y te . 1 2 - B it Bit No. 3 M 3 L Function No used DAON=1: DAC ON DAON=0: DAC OFF (Default) SELWR=1, Right Channel DAC data from Wavetable SELWR SELWR=0, Right Channel DAC data from MCU (Default) A s a m p lin g d a ta c o d e N o te : " 1 H " H ig h N ib b le " 1 M " M id d le N ib b le " 1 L " L o w N ib b le Waveform Format Rev. 1.00 15 August 15, 2005 HT36F2 Mask Option No. Mask Option Function 1 WDT source On-chip RC/Instruction clock/ disable WDT 2 CLRWDT times One time, two times (CLR WDT1/WDT2) 3 Wake-up PA only 4 Pull-High PA, PB, PC input 5 OSC mode Crystal or Resistor type 6 LVR Enable/disable 7 LVD 2.2V/3.3V Application Circuit V D D 1 0 W V D D 4 7 m F V D D A 0 .1 m F O S C 1 O S C 2 V V D D 4 7 m F D D A U D 2 0 k W 1 0 0 k W R E S V S S A 0 .1 m F 1 0 m F V S S 0 .1 m F 2 IN V re f 3 8 V D D H T 8 2 V 7 3 3 V S S 4 5 O U T N 1 S P K 8 W 7 O U T P C E H T 3 6 F 2 V D D 1 0 W V D D 4 7 m F V D D A 0 .1 m F O S C 1 6 M H z V O S C 2 V D D 1 0 0 k W R E S 0 .1 m F S P K 8 W R 1 1 k W A U D D D R 2 7 5 0 W V S S A V S S H T 3 6 F 2 N o te : R 1 > R 2 Rev. 1.00 16 August 15, 2005 HT36F2 Instruction Set Summary Description Instruction Cycle Flag Affected Add data memory to ACC Add ACC to data memory Add immediate data to ACC Add data memory to ACC with carry Add ACC to data memory with carry Subtract immediate data from ACC Subtract data memory from ACC Subtract data memory from ACC with result in data memory Subtract data memory from ACC with carry Subtract data memory from ACC with carry and result in data memory Decimal adjust ACC for addition with result in data memory 1 1(1) 1 1 1(1) 1 1 1(1) 1 1(1) 1(1) Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV C 1 1 1 1(1) 1(1) 1(1) 1 1 1 1(1) 1 Z Z Z Z Z Z Z Z Z Z Z Increment data memory with result in ACC Increment data memory Decrement data memory with result in ACC Decrement data memory 1 1(1) 1 1(1) Z Z Z Z Rotate data memory right with result in ACC Rotate data memory right Rotate data memory right through carry with result in ACC Rotate data memory right through carry Rotate data memory left with result in ACC Rotate data memory left Rotate data memory left through carry with result in ACC Rotate data memory left through carry 1 1(1) 1 1(1) 1 1(1) 1 1(1) None None C C None None C C Move data memory to ACC Move ACC to data memory Move immediate data to ACC 1 1(1) 1 None None None Clear bit of data memory Set bit of data memory 1(1) 1(1) None None Mnemonic Arithmetic ADD A,[m] ADDM A,[m] ADD A,x ADC A,[m] ADCM A,[m] SUB A,x SUB A,[m] SUBM A,[m] SBC A,[m] SBCM A,[m] DAA [m] Logic Operation AND A,[m] OR A,[m] XOR A,[m] ANDM A,[m] ORM A,[m] XORM A,[m] AND A,x OR A,x XOR A,x CPL [m] CPLA [m] AND data memory to ACC OR data memory to ACC Exclusive-OR data memory to ACC AND ACC to data memory OR ACC to data memory Exclusive-OR ACC to data memory AND immediate data to ACC OR immediate data to ACC Exclusive-OR immediate data to ACC Complement data memory Complement data memory with result in ACC Increment & Decrement INCA [m] INC [m] DECA [m] DEC [m] Rotate RRA [m] RR [m] RRCA [m] RRC [m] RLA [m] RL [m] RLCA [m] RLC [m] Data Move MOV A,[m] MOV [m],A MOV A,x Bit Operation CLR [m].i SET [m].i Rev. 1.00 17 August 15, 2005 HT36F2 Instruction Cycle Flag Affected Jump unconditionally Skip if data memory is zero Skip if data memory is zero with data movement to ACC Skip if bit i of data memory is zero Skip if bit i of data memory is not zero Skip if increment data memory is zero Skip if decrement data memory is zero Skip if increment data memory is zero with result in ACC Skip if decrement data memory is zero with result in ACC Subroutine call Return from subroutine Return from subroutine and load immediate data to ACC Return from interrupt 2 1(2) 1(2) 1(2) 1(2) 1(3) 1(3) 1(2) 1(2) 2 2 2 2 None None None None None None None None None None None None None Read ROM code (current page) to data memory and TBLH Read ROM code (last page) to data memory and TBLH 2(1) 2(1) None None No operation Clear data memory Set data memory Clear Watchdog Timer Pre-clear Watchdog Timer Pre-clear Watchdog Timer Swap nibbles of data memory Swap nibbles of data memory with result in ACC Enter Power Down Mode 1 1(1) 1(1) 1 1 1 1(1) 1 1 None None None TO,PDF TO(4),PDF(4) TO(4),PDF(4) None None TO,PDF Mnemonic Description Branch JMP addr SZ [m] SZA [m] SZ [m].i SNZ [m].i SIZ [m] SDZ [m] SIZA [m] SDZA [m] CALL addr RET RET A,x RETI Table Read TABRDC [m] TABRDL [m] Miscellaneous NOP CLR [m] SET [m] CLR WDT CLR WDT1 CLR WDT2 SWAP [m] SWAPA [m] HALT Note: x: Immediate data m: Data memory address A: Accumulator i: 0~7 number of bits addr: Program memory address Ö: Flag is affected -: Flag is not affected (1) : If a loading to the PCL register occurs, the execution cycle of instructions will be delayed for one more cycle (four system clocks). (2) : If a skipping to the next instruction occurs, the execution cycle of instructions will be delayed for one more cycle (four system clocks). Otherwise the original instruction cycle is unchanged. (3) (1) : (4) Rev. 1.00 and (2) : The flags may be affected by the execution status. If the Watchdog Timer is cleared by executing the ²CLR WDT1² or ²CLR WDT2² instruction, the TO and PDF are cleared. Otherwise the TO and PDF flags remain unchanged. 18 August 15, 2005 HT36F2 Instruction Definition ADC A,[m] Add data memory and carry to the accumulator Description The contents of the specified data memory, accumulator and the carry flag are added simultaneously, leaving the result in the accumulator. Operation ACC ¬ ACC+[m]+C Affected flag(s) TO PDF OV Z AC C ¾ ¾ Ö Ö Ö Ö ADCM A,[m] Add the accumulator and carry to data memory Description The contents of the specified data memory, accumulator and the carry flag are added simultaneously, leaving the result in the specified data memory. Operation [m] ¬ ACC+[m]+C Affected flag(s) TO PDF OV Z AC C ¾ ¾ Ö Ö Ö Ö ADD A,[m] Add data memory to the accumulator Description The contents of the specified data memory and the accumulator are added. The result is stored in the accumulator. Operation ACC ¬ ACC+[m] Affected flag(s) TO PDF OV Z AC C ¾ ¾ Ö Ö Ö Ö ADD A,x Add immediate data to the accumulator Description The contents of the accumulator and the specified data are added, leaving the result in the accumulator. Operation ACC ¬ ACC+x Affected flag(s) TO PDF OV Z AC C ¾ ¾ Ö Ö Ö Ö ADDM A,[m] Add the accumulator to the data memory Description The contents of the specified data memory and the accumulator are added. The result is stored in the data memory. Operation [m] ¬ ACC+[m] Affected flag(s) Rev. 1.00 TO PDF OV Z AC C ¾ ¾ Ö Ö Ö Ö 19 August 15, 2005 HT36F2 AND A,[m] Logical AND accumulator with data memory Description Data in the accumulator and the specified data memory perform a bitwise logical_AND operation. The result is stored in the accumulator. Operation ACC ¬ ACC ²AND² [m] Affected flag(s) TO PDF OV Z AC C ¾ ¾ ¾ Ö ¾ ¾ AND A,x Logical AND immediate data to the accumulator Description Data in the accumulator and the specified data perform a bitwise logical_AND operation. The result is stored in the accumulator. Operation ACC ¬ ACC ²AND² x Affected flag(s) TO PDF OV Z AC C ¾ ¾ ¾ Ö ¾ ¾ ANDM A,[m] Logical AND data memory with the accumulator Description Data in the specified data memory and the accumulator perform a bitwise logical_AND operation. The result is stored in the data memory. Operation [m] ¬ ACC ²AND² [m] Affected flag(s) TO PDF OV Z AC C ¾ ¾ ¾ Ö ¾ ¾ CALL addr Subroutine call Description The instruction unconditionally calls a subroutine located at the indicated address. The program counter increments once to obtain the address of the next instruction, and pushes this onto the stack. The indicated address is then loaded. Program execution continues with the instruction at this address. Operation Stack ¬ Program Counter+1 Program Counter ¬ addr Affected flag(s) TO PDF OV Z AC C ¾ ¾ ¾ ¾ ¾ ¾ CLR [m] Clear data memory Description The contents of the specified data memory are cleared to 0. Operation [m] ¬ 00H Affected flag(s) Rev. 1.00 TO PDF OV Z AC C ¾ ¾ ¾ ¾ ¾ ¾ 20 August 15, 2005 HT36F2 CLR [m].i Clear bit of data memory Description The bit i of the specified data memory is cleared to 0. Operation [m].i ¬ 0 Affected flag(s) TO PDF OV Z AC C ¾ ¾ ¾ ¾ ¾ ¾ CLR WDT Clear Watchdog Timer Description The WDT is cleared (clears the WDT). The power down bit (PDF) and time-out bit (TO) are cleared. Operation WDT ¬ 00H PDF and TO ¬ 0 Affected flag(s) TO PDF OV Z AC C 0 0 ¾ ¾ ¾ ¾ CLR WDT1 Preclear Watchdog Timer Description Together with CLR WDT2, clears the WDT. PDF and TO are also cleared. Only execution of this instruction without the other preclear instruction just sets the indicated flag which implies this instruction has been executed and the TO and PDF flags remain unchanged. Operation WDT ¬ 00H* PDF and TO ¬ 0* Affected flag(s) TO PDF OV Z AC C 0* 0* ¾ ¾ ¾ ¾ CLR WDT2 Preclear Watchdog Timer Description Together with CLR WDT1, clears the WDT. PDF and TO are also cleared. Only execution of this instruction without the other preclear instruction, sets the indicated flag which implies this instruction has been executed and the TO and PDF flags remain unchanged. Operation WDT ¬ 00H* PDF and TO ¬ 0* Affected flag(s) TO PDF OV Z AC C 0* 0* ¾ ¾ ¾ ¾ CPL [m] Complement data memory Description Each bit of the specified data memory is logically complemented (1¢s complement). Bits which previously contained a 1 are changed to 0 and vice-versa. Operation [m] ¬ [m] Affected flag(s) Rev. 1.00 TO PDF OV Z AC C ¾ ¾ ¾ Ö ¾ ¾ 21 August 15, 2005 HT36F2 CPLA [m] Complement data memory and place result in the accumulator Description Each bit of the specified data memory is logically complemented (1¢s complement). Bits which previously contained a 1 are changed to 0 and vice-versa. The complemented result is stored in the accumulator and the contents of the data memory remain unchanged. Operation ACC ¬ [m] Affected flag(s) TO PDF OV Z AC C ¾ ¾ ¾ Ö ¾ ¾ DAA [m] Decimal-Adjust accumulator for addition Description The accumulator value is adjusted to the BCD (Binary Coded Decimal) code. The accumulator is divided into two nibbles. Each nibble is adjusted to the BCD code and an internal carry (AC1) will be done if the low nibble of the accumulator is greater than 9. The BCD adjustment is done by adding 6 to the original value if the original value is greater than 9 or a carry (AC or C) is set; otherwise the original value remains unchanged. The result is stored in the data memory and only the carry flag (C) may be affected. Operation If ACC.3~ACC.0 >9 or AC=1 then [m].3~[m].0 ¬ (ACC.3~ACC.0)+6, AC1=AC else [m].3~[m].0 ¬ (ACC.3~ACC.0), AC1=0 and If ACC.7~ACC.4+AC1 >9 or C=1 then [m].7~[m].4 ¬ ACC.7~ACC.4+6+AC1,C=1 else [m].7~[m].4 ¬ ACC.7~ACC.4+AC1,C=C Affected flag(s) TO PDF OV Z AC C ¾ ¾ ¾ ¾ ¾ Ö DEC [m] Decrement data memory Description Data in the specified data memory is decremented by 1. Operation [m] ¬ [m]-1 Affected flag(s) TO PDF OV Z AC C ¾ ¾ ¾ Ö ¾ ¾ DECA [m] Decrement data memory and place result in the accumulator Description Data in the specified data memory is decremented by 1, leaving the result in the accumulator. The contents of the data memory remain unchanged. Operation ACC ¬ [m]-1 Affected flag(s) Rev. 1.00 TO PDF OV Z AC C ¾ ¾ ¾ Ö ¾ ¾ 22 August 15, 2005 HT36F2 HALT Enter Power Down Mode Description This instruction stops program execution and turns off the system clock. The contents of the RAM and registers are retained. The WDT and prescaler are cleared. The power down bit (PDF) is set and the WDT time-out bit (TO) is cleared. Operation Program Counter ¬ Program Counter+1 PDF ¬ 1 TO ¬ 0 Affected flag(s) TO PDF OV Z AC C 0 1 ¾ ¾ ¾ ¾ INC [m] Increment data memory Description Data in the specified data memory is incremented by 1 Operation [m] ¬ [m]+1 Affected flag(s) TO PDF OV Z AC C ¾ ¾ ¾ Ö ¾ ¾ INCA [m] Increment data memory and place result in the accumulator Description Data in the specified data memory is incremented by 1, leaving the result in the accumulator. The contents of the data memory remain unchanged. Operation ACC ¬ [m]+1 Affected flag(s) TO PDF OV Z AC C ¾ ¾ ¾ Ö ¾ ¾ JMP addr Directly jump Description The program counter are replaced with the directly-specified address unconditionally, and control is passed to this destination. Operation Program Counter ¬addr Affected flag(s) TO PDF OV Z AC C ¾ ¾ ¾ ¾ ¾ ¾ MOV A,[m] Move data memory to the accumulator Description The contents of the specified data memory are copied to the accumulator. Operation ACC ¬ [m] Affected flag(s) Rev. 1.00 TO PDF OV Z AC C ¾ ¾ ¾ ¾ ¾ ¾ 23 August 15, 2005 HT36F2 MOV A,x Move immediate data to the accumulator Description The 8-bit data specified by the code is loaded into the accumulator. Operation ACC ¬ x Affected flag(s) TO PDF OV Z AC C ¾ ¾ ¾ ¾ ¾ ¾ MOV [m],A Move the accumulator to data memory Description The contents of the accumulator are copied to the specified data memory (one of the data memories). Operation [m] ¬ACC Affected flag(s) TO PDF OV Z AC C ¾ ¾ ¾ ¾ ¾ ¾ NOP No operation Description No operation is performed. Execution continues with the next instruction. Operation Program Counter ¬ Program Counter+1 Affected flag(s) TO PDF OV Z AC C ¾ ¾ ¾ ¾ ¾ ¾ OR A,[m] Logical OR accumulator with data memory Description Data in the accumulator and the specified data memory (one of the data memories) perform a bitwise logical_OR operation. The result is stored in the accumulator. Operation ACC ¬ ACC ²OR² [m] Affected flag(s) TO PDF OV Z AC C ¾ ¾ ¾ Ö ¾ ¾ OR A,x Logical OR immediate data to the accumulator Description Data in the accumulator and the specified data perform a bitwise logical_OR operation. The result is stored in the accumulator. Operation ACC ¬ ACC ²OR² x Affected flag(s) TO PDF OV Z AC C ¾ ¾ ¾ Ö ¾ ¾ ORM A,[m] Logical OR data memory with the accumulator Description Data in the data memory (one of the data memories) and the accumulator perform a bitwise logical_OR operation. The result is stored in the data memory. Operation [m] ¬ACC ²OR² [m] Affected flag(s) Rev. 1.00 TO PDF OV Z AC C ¾ ¾ ¾ Ö ¾ ¾ 24 August 15, 2005 HT36F2 RET Return from subroutine Description The program counter is restored from the stack. This is a 2-cycle instruction. Operation Program Counter ¬ Stack Affected flag(s) TO PDF OV Z AC C ¾ ¾ ¾ ¾ ¾ ¾ RET A,x Return and place immediate data in the accumulator Description The program counter is restored from the stack and the accumulator loaded with the specified 8-bit immediate data. Operation Program Counter ¬ Stack ACC ¬ x Affected flag(s) TO PDF OV Z AC C ¾ ¾ ¾ ¾ ¾ ¾ RETI Return from interrupt Description The program counter is restored from the stack, and interrupts are enabled by setting the EMI bit. EMI is the enable master (global) interrupt bit. Operation Program Counter ¬ Stack EMI ¬ 1 Affected flag(s) TO PDF OV Z AC C ¾ ¾ ¾ ¾ ¾ ¾ RL [m] Rotate data memory left Description The contents of the specified data memory are rotated 1 bit left with bit 7 rotated into bit 0. Operation [m].(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6) [m].0 ¬ [m].7 Affected flag(s) TO PDF OV Z AC C ¾ ¾ ¾ ¾ ¾ ¾ RLA [m] Rotate data memory left and place result in the accumulator Description Data in the specified data memory is rotated 1 bit left with bit 7 rotated into bit 0, leaving the rotated result in the accumulator. The contents of the data memory remain unchanged. Operation ACC.(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6) ACC.0 ¬ [m].7 Affected flag(s) Rev. 1.00 TO PDF OV Z AC C ¾ ¾ ¾ ¾ ¾ ¾ 25 August 15, 2005 HT36F2 RLC [m] Rotate data memory left through carry Description The contents of the specified data memory and the carry flag are rotated 1 bit left. Bit 7 replaces the carry bit; the original carry flag is rotated into the bit 0 position. Operation [m].(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6) [m].0 ¬ C C ¬ [m].7 Affected flag(s) TO PDF OV Z AC C ¾ ¾ ¾ ¾ ¾ Ö RLCA [m] Rotate left through carry and place result in the accumulator Description Data in the specified data memory and the carry flag are rotated 1 bit left. Bit 7 replaces the carry bit and the original carry flag is rotated into bit 0 position. The rotated result is stored in the accumulator but the contents of the data memory remain unchanged. Operation ACC.(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6) ACC.0 ¬ C C ¬ [m].7 Affected flag(s) TO PDF OV Z AC C ¾ ¾ ¾ ¾ ¾ Ö RR [m] Rotate data memory right Description The contents of the specified data memory are rotated 1 bit right with bit 0 rotated to bit 7. Operation [m].i ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6) [m].7 ¬ [m].0 Affected flag(s) TO PDF OV Z AC C ¾ ¾ ¾ ¾ ¾ ¾ RRA [m] Rotate right and place result in the accumulator Description Data in the specified data memory is rotated 1 bit right with bit 0 rotated into bit 7, leaving the rotated result in the accumulator. The contents of the data memory remain unchanged. Operation ACC.(i) ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6) ACC.7 ¬ [m].0 Affected flag(s) TO PDF OV Z AC C ¾ ¾ ¾ ¾ ¾ ¾ RRC [m] Rotate data memory right through carry Description The contents of the specified data memory and the carry flag are together rotated 1 bit right. Bit 0 replaces the carry bit; the original carry flag is rotated into the bit 7 position. Operation [m].i ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6) [m].7 ¬ C C ¬ [m].0 Affected flag(s) Rev. 1.00 TO PDF OV Z AC C ¾ ¾ ¾ ¾ ¾ Ö 26 August 15, 2005 HT36F2 RRCA [m] Rotate right through carry and place result in the accumulator Description Data of the specified data memory and the carry flag are rotated 1 bit right. Bit 0 replaces the carry bit and the original carry flag is rotated into the bit 7 position. The rotated result is stored in the accumulator. The contents of the data memory remain unchanged. Operation ACC.i ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6) ACC.7 ¬ C C ¬ [m].0 Affected flag(s) TO PDF OV Z AC C ¾ ¾ ¾ ¾ ¾ Ö SBC A,[m] Subtract data memory and carry from the accumulator Description The contents of the specified data memory and the complement of the carry flag are subtracted from the accumulator, leaving the result in the accumulator. Operation ACC ¬ ACC+[m]+C Affected flag(s) TO PDF OV Z AC C ¾ ¾ Ö Ö Ö Ö SBCM A,[m] Subtract data memory and carry from the accumulator Description The contents of the specified data memory and the complement of the carry flag are subtracted from the accumulator, leaving the result in the data memory. Operation [m] ¬ ACC+[m]+C Affected flag(s) TO PDF OV Z AC C ¾ ¾ Ö Ö Ö Ö SDZ [m] Skip if decrement data memory is 0 Description The contents of the specified data memory are decremented by 1. If the result is 0, the next instruction is skipped. If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Operation Skip if ([m]-1)=0, [m] ¬ ([m]-1) Affected flag(s) TO PDF OV Z AC C ¾ ¾ ¾ ¾ ¾ ¾ SDZA [m] Decrement data memory and place result in ACC, skip if 0 Description The contents of the specified data memory are decremented by 1. If the result is 0, the next instruction is skipped. The result is stored in the accumulator but the data memory remains unchanged. If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Operation Skip if ([m]-1)=0, ACC ¬ ([m]-1) Affected flag(s) Rev. 1.00 TO PDF OV Z AC C ¾ ¾ ¾ ¾ ¾ ¾ 27 August 15, 2005 HT36F2 SET [m] Set data memory Description Each bit of the specified data memory is set to 1. Operation [m] ¬ FFH Affected flag(s) TO PDF OV Z AC C ¾ ¾ ¾ ¾ ¾ ¾ SET [m]. i Set bit of data memory Description Bit i of the specified data memory is set to 1. Operation [m].i ¬ 1 Affected flag(s) TO PDF OV Z AC C ¾ ¾ ¾ ¾ ¾ ¾ SIZ [m] Skip if increment data memory is 0 Description The contents of the specified data memory are incremented by 1. If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Operation Skip if ([m]+1)=0, [m] ¬ ([m]+1) Affected flag(s) TO PDF OV Z AC C ¾ ¾ ¾ ¾ ¾ ¾ SIZA [m] Increment data memory and place result in ACC, skip if 0 Description The contents of the specified data memory are incremented by 1. If the result is 0, the next instruction is skipped and the result is stored in the accumulator. The data memory remains unchanged. If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Operation Skip if ([m]+1)=0, ACC ¬ ([m]+1) Affected flag(s) TO PDF OV Z AC C ¾ ¾ ¾ ¾ ¾ ¾ SNZ [m].i Skip if bit i of the data memory is not 0 Description If bit i of the specified data memory is not 0, the next instruction is skipped. If bit i of the data memory is not 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Operation Skip if [m].i¹0 Affected flag(s) Rev. 1.00 TO PDF OV Z AC C ¾ ¾ ¾ ¾ ¾ ¾ 28 August 15, 2005 HT36F2 SUB A,[m] Subtract data memory from the accumulator Description The specified data memory is subtracted from the contents of the accumulator, leaving the result in the accumulator. Operation ACC ¬ ACC+[m]+1 Affected flag(s) TO PDF OV Z AC C ¾ ¾ Ö Ö Ö Ö SUBM A,[m] Subtract data memory from the accumulator Description The specified data memory is subtracted from the contents of the accumulator, leaving the result in the data memory. Operation [m] ¬ ACC+[m]+1 Affected flag(s) TO PDF OV Z AC C ¾ ¾ Ö Ö Ö Ö SUB A,x Subtract immediate data from the accumulator Description The immediate data specified by the code is subtracted from the contents of the accumulator, leaving the result in the accumulator. Operation ACC ¬ ACC+x+1 Affected flag(s) TO PDF OV Z AC C ¾ ¾ Ö Ö Ö Ö SWAP [m] Swap nibbles within the data memory Description The low-order and high-order nibbles of the specified data memory (1 of the data memories) are interchanged. Operation [m].3~[m].0 « [m].7~[m].4 Affected flag(s) TO PDF OV Z AC C ¾ ¾ ¾ ¾ ¾ ¾ SWAPA [m] Swap data memory and place result in the accumulator Description The low-order and high-order nibbles of the specified data memory are interchanged, writing the result to the accumulator. The contents of the data memory remain unchanged. Operation ACC.3~ACC.0 ¬ [m].7~[m].4 ACC.7~ACC.4 ¬ [m].3~[m].0 Affected flag(s) Rev. 1.00 TO PDF OV Z AC C ¾ ¾ ¾ ¾ ¾ ¾ 29 August 15, 2005 HT36F2 SZ [m] Skip if data memory is 0 Description If the contents of the specified data memory are 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Operation Skip if [m]=0 Affected flag(s) TO PDF OV Z AC C ¾ ¾ ¾ ¾ ¾ ¾ SZA [m] Move data memory to ACC, skip if 0 Description The contents of the specified data memory are copied to the accumulator. If the contents is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Operation Skip if [m]=0 Affected flag(s) TO PDF OV Z AC C ¾ ¾ ¾ ¾ ¾ ¾ SZ [m].i Skip if bit i of the data memory is 0 Description If bit i of the specified data memory is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Operation Skip if [m].i=0 Affected flag(s) TO PDF OV Z AC C ¾ ¾ ¾ ¾ ¾ ¾ TABRDC [m] Move the ROM code (current page) to TBLH and data memory Description The low byte of ROM code (current page) addressed by the table pointer (TBLP) is moved to the specified data memory and the high byte transferred to TBLH directly. Operation [m] ¬ ROM code (low byte) TBLH ¬ ROM code (high byte) Affected flag(s) TO PDF OV Z AC C ¾ ¾ ¾ ¾ ¾ ¾ TABRDL [m] Move the ROM code (last page) to TBLH and data memory Description The low byte of ROM code (last page) addressed by the table pointer (TBLP) is moved to the data memory and the high byte transferred to TBLH directly. Operation [m] ¬ ROM code (low byte) TBLH ¬ ROM code (high byte) Affected flag(s) Rev. 1.00 TO PDF OV Z AC C ¾ ¾ ¾ ¾ ¾ ¾ 30 August 15, 2005 HT36F2 XOR A,[m] Logical XOR accumulator with data memory Description Data in the accumulator and the indicated data memory perform a bitwise logical Exclusive_OR operation and the result is stored in the accumulator. Operation ACC ¬ ACC ²XOR² [m] Affected flag(s) TO PDF OV Z AC C ¾ ¾ ¾ Ö ¾ ¾ XORM A,[m] Logical XOR data memory with the accumulator Description Data in the indicated data memory and the accumulator perform a bitwise logical Exclusive_OR operation. The result is stored in the data memory. The 0 flag is affected. Operation [m] ¬ ACC ²XOR² [m] Affected flag(s) TO PDF OV Z AC C ¾ ¾ ¾ Ö ¾ ¾ XOR A,x Logical XOR immediate data to the accumulator Description Data in the accumulator and the specified data perform a bitwise logical Exclusive_OR operation. The result is stored in the accumulator. The 0 flag is affected. Operation ACC ¬ ACC ²XOR² x Affected flag(s) Rev. 1.00 TO PDF OV Z AC C ¾ ¾ ¾ Ö ¾ ¾ 31 August 15, 2005 HT36F2 Package Information 16-pin SOP (300mil) Outline Dimensions 1 6 9 A B 1 8 C C ' G H D E Symbol Rev. 1.00 a F Dimensions in mil Min. Nom. Max. A 394 ¾ 419 B 290 ¾ 300 C 14 ¾ 20 C¢ 390 ¾ 413 D 92 ¾ 104 E ¾ 50 ¾ F 4 ¾ ¾ G 32 ¾ 38 H 4 ¾ 12 a 0° ¾ 10° 32 August 15, 2005 HT36F2 28-pin SOP (300mil) Outline Dimensions 2 8 1 5 A B 1 1 4 C C ' G H D E Symbol Rev. 1.00 a F Dimensions in mil Min. Nom. Max. A 394 ¾ 419 B 290 ¾ 300 C 14 ¾ 20 C¢ 697 ¾ 713 D 92 ¾ 104 E ¾ 50 ¾ F 4 ¾ ¾ G 32 ¾ 38 H 4 ¾ 12 a 0° ¾ 10° 33 August 15, 2005 HT36F2 Product Tape and Reel Specifications Reel Dimensions D T 2 A C B T 1 SOP 16W (300mil) Symbol Description Dimensions in mm A Reel Outer Diameter 330±1 B Reel Inner Diameter 62±1.5 C Spindle Hole Diameter 13±0.5 -0.2 D Key Slit Width 2±0.5 T1 Space Between Flange 16.8+0.3 -0.2 T2 Reel Thickness 22.2±0.2 SOP 28W (300mil) Symbol Description Dimensions in mm A Reel Outer Diameter 330±1 B Reel Inner Diameter 62±1.5 C Spindle Hole Diameter 13+0.5 -0.2 D Key Slit Width 2±0.5 T1 Space Between Flange 24.8+0.3 -0.2 T2 Reel Thickness 30.2±0.2 Rev. 1.00 34 August 15, 2005 HT36F2 Carrier Tape Dimensions P 0 D P 1 t E F W C D 1 B 0 P K 0 A 0 SOP 16W (300mil) Symbol Description Dimensions in mm W Carrier Tape Width 16±0.2 P Cavity Pitch 12±0.1 E Perforation Position 1.75±0.1 F Cavity to Perforation (Width Direction) 7.5±0.1 D Perforation Diameter 1.5+0.1 D1 Cavity Hole Diameter 1.5+0.25 P0 Perforation Pitch 4±0.1 P1 Cavity to Perforation (Length Direction) A0 Cavity Length 10.9±0.1 B0 Cavity Width 10.8±0.1 K0 Cavity Depth 3±0.1 t Carrier Tape Thickness C Cover Tape Width 2±0.1 0.3±0.05 13.3 SOP 28W (300mil) Symbol Description Dimensions in mm W Carrier Tape Width P Cavity Pitch E Perforation Position 1.75±0.1 F Cavity to Perforation (Width Direction) 11.5±0.1 24±0.3 12±0.1 D Perforation Diameter 1.5+0.1 D1 Cavity Hole Diameter 1.5+0.25 P0 Perforation Pitch 4±0.1 P1 Cavity to Perforation (Length Direction) 2±0.1 A0 Cavity Length 10.85±0.1 B0 Cavity Width 18.34±0.1 K0 Cavity Depth 2.97±0.1 t Carrier Tape Thickness 0.35±0.01 C Cover Tape Width Rev. 1.00 21.3 35 August 15, 2005 HT36F2 Holtek Semiconductor Inc. (Headquarters) No.3, Creation Rd. II, Science Park, Hsinchu, Taiwan Tel: 886-3-563-1999 Fax: 886-3-563-1189 http://www.holtek.com.tw Holtek Semiconductor Inc. (Taipei Sales Office) 4F-2, No. 3-2, YuanQu St., Nankang Software Park, Taipei 115, Taiwan Tel: 886-2-2655-7070 Fax: 886-2-2655-7373 Fax: 886-2-2655-7383 (International sales hotline) Holtek Semiconductor Inc. (Shanghai Sales Office) 7th Floor, Building 2, No.889, Yi Shan Rd., Shanghai, China 200233 Tel: 021-6485-5560 Fax: 021-6485-0313 http://www.holtek.com.cn Holtek Semiconductor Inc. (Shenzhen Sales Office) 43F, SEG Plaza, Shen Nan Zhong Road, Shenzhen, China 518031 Tel: 0755-8346-5589 Fax: 0755-8346-5590 ISDN: 0755-8346-5591 Holtek Semiconductor Inc. (Beijing Sales Office) Suite 1721, Jinyu Tower, A129 West Xuan Wu Men Street, Xicheng District, Beijing, China 100031 Tel: 010-6641-0030, 6641-7751, 6641-7752 Fax: 010-6641-0125 Holmate Semiconductor, Inc. (North America Sales Office) 46712 Fremont Blvd., Fremont, CA 94538 Tel: 510-252-9880 Fax: 510-252-9885 http://www.holmate.com Copyright Ó 2005 by HOLTEK SEMICONDUCTOR INC. The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. Holtek¢s products are not authorized for use as critical components in life support devices or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw. Rev. 1.00 36 August 15, 2005