HOLTEK HT46R652

HT46R652
A/D with LCD Type 8-Bit OTP MCU
Technical Document
· Tools Information
· FAQs
· Application Note
- HA0003E Communicating between the HT48 & HT46 Series MCUs and the HT93LC46 EEPROM
- HA0004E HT48 & HT46 MCU UART Software Implementation Method
- HA0005E Controlling the I2C bus with the HT48 & HT46 MCU Series
- HA0047E An PWM application example using the HT46 series of MCUs
Features
· Operating voltage:
· Buzzer output
fSYS=4MHz: 2.2V~5.5V
fSYS=12MHz: 3.3V~5.5V
· On-chip crystal, RC and 32768Hz crystal oscillator
· Power-down function and wake-up features reduce
· 32 bidirectional I/O lines
power consumption
· Two external interrupt inputs
· 16-level subroutine nesting
· Two 16-bit programmable timer/event counters with
· 8-channel 12-bit resolution A/D converter
PFD (programmable frequency divider) function
· 16-channel 8-bit PWM output shared with 16 I/O lines
· LCD driver with 41´3 or 40´4 segments
· Bit manipulation instruction
(logical output option for SEG0~SEG23)
· 16-bit table read instruction
· 8K´16 program memory
· Up to 0.33ms instruction cycle with 12MHz system
· 384´8 data memory RAM
clock
· PFD for sound generation
· 63 powerful instructions
· Real Time Clock (RTC)
· All instructions in 1 or 2 machine cycles
· 8-bit RTC prescaler
· Low voltage reset/detector function
· Watchdog Timer
· 100-pin QFP package
General Description
The HT46R652 is an 8-bit, high performance, RISC architecture microcontroller devices specifically designed
for A/D product applications that interface directly to analog signals and which require an LCD Interface.
Power-down and wake-up functions, in addition to a
flexible and configurable LCD interface enhance the
versatility of these devices to control a wide range of applications requiring analog signal processing and LCD
interfacing, such as electronic metering, environmental
monitoring, handheld measurement tools, motor driving, etc. for both the industrial and home appliance application areas.
The advantages of low power consumption, I/O flexibility, timer functions, oscillator options, multi-channel A/D
Converter, Pulse Width Modulation function,
Rev. 1.00
1
December 19, 2006
HT46R652
Block Diagram
In te rru p t
C ir c u it
P ro g ra m
E P R O M
IN T C
In s tr u c tio n
R e g is te r
M
M P
U
P r e s c a le r
X
M
T M R 1 C
T M R 1
P F D 1
U
U
X
X
3 2 7 6 8 H z
fS
M
W D T
U
M U X
O S
R E
V D
A V
P C
P D
V S
P C
P D
O S
O S C 3
O S C 4
P C 0 /P W M 0 ~ P C 7 /P W M 7
P D 0 /P W M 8 ~ P D 7 /P W M 1 5
S h ifte r
8 -C h a n n e l
A /D C o n v e rte r
P B C
D
S
A C C
C 1
D D
V D
V D
S /A
V S
V S
C 3
S
D
S
D
L C D
M e m o ry
V S S
P o rt B
P B
/V R E F
P A C
P o rt A
P A
L C D D r iv e r
H A L T
C O M 0 ~
C O M 2
Rev. 1.00
P o rt C
P o rt D
P C , P D
B P
O S C 2
O S C 4
O S C
W D T O S C
P C C , P D C
T im in g
G e n e r a tio n
/4
P W M
S T A T U S
A L U
Y S
R T C
X
T im e B a s e
In s tr u c tio n
D e c o d e r
Y S
P A 7 /T M R 1
fS Y S /4
R T C
D A T A
M e m o ry
fS
P A 4 /T M R 0
P F D 0
S T A C K
P ro g ra m
C o u n te r
M
T M R 0 C
T M R 0
C O M 3 /
S E G 4 0
E N /D IS
P B 0 /A N 0 ~ P B 7 /A N 7
P A 0
P A 1
P A 2
P A 3
P A 4
P A 5
P A 6
P A 7
/B Z
/B Z
/P
/T
/IN
/IN
/T
F D
M R 0
T 0
T 1
M R 1
L V D /L V R
S E G 0 ~
S E G 3 9
2
December 19, 2006
HT46R652
Pin Assignment
S E G 8
S E G 7
S E G 6
S E G 5
S E G 4
S E G 3
S E G 2
S E G 1
S E G 0
O S C 4
O S C 3
V D D
O S C 2
O S C 1
R E S
P A 0 /B Z
P A 1 /B Z
P A 2
P A 3 /P F D
P A 4 /T M R 0
P A
P B
P B
P B
P B
P B
P A
P A 7
P B
P B
P B
P
P
P
P
P
P
5 /IN
0 /A
1 /A
2 /A
3 /A
4 /A
6 /IN
/T M
5 /A
6 /A
7 /A
V R
A V
A V
P D
P D
D 2
D 3
D 4
D 5
D 6
D 7
0 /P
1 /P
/P W
/P W
/P W
/P W
/P W
/P W
P D
P D
P C
P C
P C 0 /P
W
V
W
W
V
M
V
V
V
M
M
M
M
M
T 0
N 0
N 1
N 2
N 3
N 4
T 1
R 1
N 5
N 6
N 7
E F
D D
S S
N C
N C
S S
M 8
M 9
1 0
1 1
1 2
1 3
1 4
1 5
D D
S S
S S
D D
M 0
1 0 0 9 9 9 8 9 7 9 6 9 5 9 4 9 3 9 2 9 1 9 0 8 9 8 8 8 7 8 6 8 5 8 4 8 3 8 2 8 1
1
8 0
2
7 9
3
7 8
4
7 7
5
7 6
6
7 5
7
7 4
8
7 3
9
7 2
1 0
7 1
1 1
7 0
1 2
6 9
1 3
6 8
1 4
6 7
H T 4 6 R 6 5 2
1 0 0 Q F P -A
1 5
1 6
1 7
6 6
6 5
6 4
1 8
6 3
1 9
6 2
2 0
6 1
2 1
6 0
2 2
5 9
2 3
5 8
2 4
5 7
2 5
5 6
2 6
5 5
2 7
5 4
2 8
5 3
2 9
3 0
5 2
3 1 3 2 3 3 3 4 3 5 3 6 3 7 3 8 3 9 4 0 4 1 4 2 4 3 4 4 4 5 4 6 4 7 4 8 4 9 5 0
5 1
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
9
1 0
1 1
1 2
1 3
1 4
1 5
1 6
1 7
1 8
1 9
2 0
2 1
2 2
2 3
2 4
2 5
2 6
2 7
2 8
2 9
3 0
3 1
3 2
3 3
3 4
3 5
3 6
3 7
3 8
S E G
C O M
C O M
C O M
C O M
C 2
C 1
V 2
V 1
V M A
V L C
N C
N C
P C 7
P C 6
P C 5
P C 4
P C 3
P C 2
P C 1
D
2
1
0
M 7
M 6
M 5
M 4
M 3
M 2
M 1
3
3 9
3 /S E G 4 0
X
/P W
/P W
/P W
/P W
/P W
/P W
/P W
Rev. 1.00
December 19, 2006
HT46R652
Pin Description
Pin Name
Options
Description
Wake-up
Pull-high
Buzzer
PFD
Bidirectional 8-bit input/output port. Each individual pin on this port can be
configured as a wake-up input by a configuration option. Software instructions determine if the pin is a CMOS output or Schmitt trigger input. Configuration options determine which pins on the port have pull-high resistors. Pins
PA0, PA1 and PA3 are pin-shared with BZ, BZ and PFD respectively. Pins
PA5, PA6, PA4 and PA7 are pin-shared with INT0, INT1, TMR0 and TMR1
respectively.
Pull-high
Bidirectional 8-bit input/output port. Software instructions determine if the pin
is a CMOS output or Schmitt trigger input. Configuration options determine
which pins on the port have pull-high resistors. PB is pin-shared with the A/D
input pins. The A/D inputs are selected via software instructions. Once a PB
line is selected as an A/D input, the I/O function and pull-high resistor
functions are disabled automatically.
I/O
Pull-high
PWM
Bidirectional 8-bit input/output port. Software instructions determine if the pin
is a CMOS output or Schmitt trigger input. Configuration options determine if
all pins on the port have pull-high resistors. A configuration option determines if all of the pins on this port are to be used as PWM outputs. Individual
pins cannot be selected to have a PWM function.
I/O
Pull-high
PWM
Bidirectional 8-bit input/output port. Software instructions determine if the pin
is a CMOS output or Schmitt trigger input. Configuration options determine
which pins on the port have pull-high resistors. A configuration option for
each pin on this port determines if each pin is to be used as a PWM output.
VLCD
I
¾
LCD power supply
VMAX
I
¾
IC maximum voltage connect to VDD, VLCD or V1
V1, V2, C1, C2
I
¾
Voltage pump
COM0~COM2
COM3/SEG40
O
1/3 or 1/4 Duty
SEG40 can be set as a segment or as a common output driver for LCD panel
by options. COM0~COM2 are outputs for the LCD panel.
SEG0~SEG39
O
Logical Output
LCD driver outputs for the the LCD panel segments. SEG0~SEG23 can be
configured as logical outputs via a configuration option.
PA0/BZ
PA1/BZ
PA2
PA3/PFD
PA4/TMR0
PA5/INT0
PA6/INT1
PA7/TMR1
PB0/AN0~
PB7/AN7
PC0/PWM0~
PC7/PWM7
PD0/PWM8~
PD7/PWM15
I/O
I/O
I/O
OSC1
OSC2
I
O
Crystal or RC
OSC1 and OSC2 are connected to an RC network or external crystal (determined by a configuration option) for the internal system clock. If the RC system clock is selected, OSC2 can be used to measure the system clock at 1/4
frequency. The system clock may also be sourced from the RTC oscillator, in
which case these two pins can be left floating.
OSC3
OSC4
I
O
RTC or
System Clock
Real time clock oscillator. OSC3 and OSC4 are connected to a 32768Hz
crystal oscillator for timing purposes or to form a system clock source, depending on configuration options.
RES
I
¾
Schmitt trigger reset input, active low
VDD
¾
¾
Positive power supply
AVDD/VREF
Analog positive power supply and A/D converter reference input voltage.
PCVDD
¾
¾
Port C positive power supply
PDVDD
¾
¾
Port D positive power supply
VSS/AVSS
¾
¾
Negative power supply and analog negative power supply, ground
PCVSS
¾
¾
Port C negative power supply, ground
PDVSS
¾
¾
Port D negative power supply, ground
Note:
Individual pins on PC cannot be selected as a PWM output, if the PWM configuration option is selected for this
port then all pins on PC will be setup as PWM outputs.
Rev. 1.00
4
December 19, 2006
HT46R652
Absolute Maximum Ratings
Supply Voltage ...........................VSS-0.3V to VSS+6.0V
Storage Temperature ............................-50°C to 125°C
Input Voltage..............................VSS-0.3V to VDD+0.3V
IOL Total ..............................................................300mA
Total Power Dissipation .....................................500mW
Operating Temperature...........................-40°C to 85°C
IOH Total............................................................-200mA
Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maximum Ratings² may
cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed
in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability.
D.C. Characteristics
Ta=25°C
Test Conditions
Symbol
Parameter
VDD
Operating Voltage
Min.
Typ.
Max.
Unit
Conditions
VDD
¾
fSYS=4MHz
2.2
¾
5.5
V
¾
fSYS=12MHz
3.3
¾
5.5
V
AVDD
Analog Operating Voltage*
¾
VREF=AVDD
3.0
¾
5.5
V
IDD1
Operating Current
(Crystal OSC)
3V
No load, ADC off
fSYS=4MHz
¾
1
2
mA
¾
3
5
mA
¾
1
2
mA
¾
3
5
mA
¾
4
8
mA
¾
0.3
0.6
mA
¾
0.6
1
mA
¾
¾
1
mA
¾
¾
2
mA
¾
2.5
5
mA
¾
10
20
mA
¾
2
5
mA
¾
6
10
mA
¾
17
30
mA
¾
34
60
mA
¾
13
25
mA
¾
28
50
mA
¾
14
25
mA
¾
26
50
mA
¾
10
20
mA
¾
19
40
mA
IDD2
Operating Current
(RC OSC)
5V
3V
5V
IDD3
Operating Current
(Crystal OSC, RC OSC)
IDD4
Operating Current
(fSYS=32768Hz)
3V
Standby Current
(*fS=T1)
3V
ISTB1
ISTB2
ISTB3
ISTB4
ISTB5
ISTB6
ISTB7
Rev. 1.00
Standby Current
(*fS=32.768kHz OSC)
Standby Current
(*fS=WDT RC OSC)
Standby Current
(*fS=32.768kHz OSC)
Standby Current
(*fS=32.768kHz OSC)
Standby Current
(*fS=WDT RC OSC)
Standby Current
(*fS=WDT RC OSC)
5V
No load, ADC off
fSYS=4MHz
No load, ADC off
fSYS=12MHz
No load, ADC off
5V
5V
3V
5V
3V
5V
3V
5V
3V
5V
3V
5V
3V
5V
No load, system HALT
LCD off at HALT
No load, system HALT
LCD on at HALT, C type
No load, system HALT
LCD on at HALT, C type
No load, system HALT
LCD on at HALT, R type,
1/2 bias, VLCD=VDD
(Low bias current option)
No load, system HALT
LCD on at HALT, R type,
1/3 bias, VLCD=VDD
(Low bias current option)
No load, system HALT
LCD on at HALT, R type,
1/2 bias, VLCD=VDD
(Low bias current option)
No load, system HALT
LCD on at HALT, R type,
1/3 bias, VLCD=VDD
(Low bias current option)
5
December 19, 2006
HT46R652
Symbol
Parameter
Test Conditions
VDD
Conditions
Min.
Typ.
Max.
Unit
VIL1
Input Low Voltage for I/O Ports,
TMR and INT
¾
¾
0
¾
0.3VDD
V
VIH1
Input High Voltage for I/O Ports,
TMR and INT
¾
¾
0.7VDD
¾
VDD
V
VIL2
Input Low Voltage (RES)
¾
¾
0
¾
0.4VDD
V
VIH2
Input High Voltage (RES)
¾
¾
0.9VDD
¾
VDD
V
VLVR
Low Voltage Reset Voltage
¾
¾
2.7
3.0
3.3
V
VLVD
Low Voltage Detector Voltage
¾
¾
3.0
3.3
3.6
V
IOL1
I/O Port (PA, PB) and Segment
Logic Output Sink Current
3V
6
12
¾
mA
10
25
¾
mA
I/O Port (PA, PB) and Segment
Logic Output Source Current
3V
-2
-4
¾
mA
-5
-8
¾
mA
10
20
¾
mA
25
40
¾
mA
-10
-20
¾
mA
-25
-40
¾
mA
210
420
¾
mA
350
700
¾
mA
-80
-160
¾
mA
-180
-360
¾
mA
IOH1
5V
VOH=0.9VDD
5V
3V
IOL2
VOL=0.1VDD
I/O Port (PC, PD) Sink Current
VOL=0.1VDD
5V
3V
IOH2
I/O Port (PC, PD) Source Current
VOH=0.9VDD
5V
LCD Common and Segment
Current
IOL3
LCD Common and Segment
Current
IOH3
RPH
3V
VOL=0.1VDD
5V
3V
VOH=0.9VDD
5V
3V
¾
20
60
100
kW
5V
¾
10
30
50
kW
¾
0
¾
VREF
V
AVDD=3V
1.3
¾
AVDD
V
AVDD=5V
1.5
¾
AVDD
V
Pull-high Resistance of I/O Ports
VAD
A/D Input Voltage
¾
VREF
ADC Input Reference Voltage
Range
¾
DNL
ADC Differential Non-Linear
¾
¾
¾
¾
±2
LSB
INL
ADC Integral Non-Linear
¾
¾
¾
±2.5
±4
LSB
¾
¾
¾
¾
12
Bits
¾
0.5
1
mA
¾
1.5
3
mA
RESOLU Resolution
Additional Power Consumption
if A/D Converter is Used
IADC
Note:
3V
¾
5V
²*fS² please refer to clock option of WDT
²*² Voltage level of AVDD and VDD must be the same.
Rev. 1.00
6
December 19, 2006
HT46R652
A.C. Characteristics
Ta=25°C
Test Conditions
Symbol
Parameter
VDD
fSYS1
System Clock
Typ.
Max.
Unit
¾
2.2V~5.5V
400
¾
4000
kHz
¾
3.3V~5.5V
400
¾
12000
kHz
2.2V~5.5V
¾
32768
¾
Hz
¾
32768
¾
Hz
fSYS2
System Clock
(32768Hz Crystal OSC)
¾
fRTCOSC
RTC Frequency
¾
fTIMER
Timer I/P Frequency
(TMR0/TMR1)
tWDTOSC
Min.
Conditions
¾
¾
2.2V~5.5V
0
¾
4000
kHz
¾
3.3V~5.5V
0
¾
12000
kHz
3V
¾
45
90
180
ms
5V
¾
32
65
130
ms
Watchdog Oscillator Period
tRES
External Reset Low Pulse Width
¾
¾
1
¾
¾
ms
tSST
System Start-up Timer Period
¾
Power-up or wake-up
from HALT
¾
1024
¾
*tSYS
tLVR
Low Voltage Width to Reset
¾
¾
0.25
1
2
ms
tINT
Interrupt Pulse Width
¾
¾
1
¾
¾
ms
tAD
A/D Clock Period
¾
¾
1
¾
¾
ms
tADC
A/D Conversion Time
¾
¾
¾
80
¾
tAD
tADCS
A/D Sampling Time
¾
¾
¾
32
¾
tAD
Note:
*tSYS= 1/fSYS1 or 1/fSYS2
Rev. 1.00
7
December 19, 2006
HT46R652
Functional Description
Execution Flow
After accessing a program memory word to fetch an instruction code, the value of the PC is incremented by 1.
The PC then points to the memory word containing the
next instruction code.
The system clock is derived from either a crystal or an
RC oscillator or a 32768Hz crystal oscillator. It is internally divided into four non-overlapping clocks. One instruction cycle consists of four system clock cycles.
When executing a jump instruction, conditional skip execution, loading a PCL register, a subroutine call, an initial reset, an internal interrupt, an external interrupt, or
returning from a subroutine, the PC manipulates the
program transfer by loading the address corresponding
to each instruction.
Instruction fetching and execution are pipelined in such
a way that a fetch takes one instruction cycle while decoding and execution takes the next instruction cycle.
The pipelining scheme makes it possible for each instruction to be effectively executed in a cycle. If an instruction changes the value of the program counter, two
cycles are required to complete the instruction.
The conditional skip is activated by instructions. Once
the condition is met, the next instruction, fetched during
the current instruction execution, is discarded and a
dummy cycle replaces it to get a proper instruction; otherwise proceed to the next instruction.
Program Counter - PC
The program counter, PC, is 13 bits wide and it controls
the sequence in which the instructions stored in the
Program Memory are executed. The contents of the PC
can specify a maximum of 8192 addresses.
S y s te m
O S C 2 (R C
C lo c k
T 1
T 2
T 3
T 4
T 1
T 2
T 3
T 4
T 1
T 2
T 3
T 4
o n ly )
P C
P C
P C + 1
F e tc h IN S T (P C )
E x e c u te IN S T (P C -1 )
P C + 2
F e tc h IN S T (P C + 1 )
E x e c u te IN S T (P C )
F e tc h IN S T (P C + 2 )
E x e c u te IN S T (P C + 1 )
Execution Flow
Mode
Program Counter
*12
*11
*10
*9
*8
*7
*6
*5
*4
*3
*2
*1
*0
Initial Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
External Interrupt 0
0
0
0
0
0
0
0
0
0
0
1
0
0
External Interrupt 1
0
0
0
0
0
0
0
0
0
1
0
0
0
Timer/Event Counter 0 Overflow
0
0
0
0
0
0
0
0
0
1
1
0
0
Timer/Event Counter 1 Overflow
0
0
0
0
0
0
0
0
1
0
0
0
0
Time Base Interrupt
0
0
0
0
0
0
0
0
1
0
1
0
0
RTC Interrupt
0
0
0
0
0
0
0
0
1
1
0
0
0
Loading PCL
*12
*11
*10
*9
*8
@7
@6
@5
@4
@3
@2
@1
@0
Jump, Call Branch
#12
#11
#10
#9
#8
#7
#6
#5
#4
#3
#2
#1
#0
Return from Subroutine
S12 S11 S10
S9
S8
S7
S6
S5
S4
S3
S2
S1
S0
Skip
Program Counter+2
Program Counter
Note:
*12~*0: Program counter bits
#12~#0: Instruction code bits
Rev. 1.00
S12~S0: Stack register bits
@7~@0: PCL bits
8
December 19, 2006
HT46R652
· Location 008H
The lower byte of the PC, known as PCL is a readable
and writeable register. Moving data into the PCL performs a short jump. The destination is within 256 locations.
Location 008H is reserved for the external interrupt
service program also. If the INT1 input pin is activated,
and the interrupt is enabled, and the stack is not full,
the program begins execution at location 008H.
When a control transfer takes place, an additional
dummy cycle is required.
· Location 00CH
Location 00CH is reserved for the Timer/Event Counter 0 interrupt service program. If a timer interrupt results from a Timer/Event Counter 0 overflow, and if the
interrupt is enabled and the stack is not full, the program begins execution at location 00CH.
Program Memory
The program memory is used to store the program instructions which are to be executed. It also contains
data, table, and interrupt entries, and is organized into
8192´16 bits which are addressed by the program
counter and table pointer.
· Location 010H
Location 010H is reserved for the Timer/Event Counter 1 interrupt service program. If a timer interrupt results from a Timer/Event Counter 1 overflow, and if the
interrupt is enabled and the stack is not full, the program begins execution at location 010H.
Certain locations in the ROM are reserved for special
usage:
· Location 000H
· Location 014H
Location 000H is reserved for program initialization.
After a device reset, the program always begins execution at this location.
Location 014H is reserved for the Time Base interrupt
service program. If a Time Base interrupt occurs, and
the interrupt is enabled, and the stack is not full, the
program begins execution at location 014H.
· Location 004H
Location 004H is reserved for the external interrupt
service program. If the INT0 input pin is activated, and
the interrupt is enabled, and the stack is not full, the
program begins execution at location 004H.
0 0 0 H
· Table location
E x te r n a l in te r r u p t 0 s u b r o u tin e
0 0 8 H
0 1 0 H
Location 018H is reserved for the real time clock interrupt service program. If a real time clock interrupt occurs, and the interrupt is enabled, and the stack is not
full, the program begins execution at location 018H.
D e v ic e in itia liz a tio n p r o g r a m
0 0 4 H
0 0 C H
· Location 018H
Any location in the Program Memory can be used as a
look-up table. The instructions ²TABRDC [m]² (the
current page, 1 page=256 words) and ²TABRDL [m]²
(the last page) transfer the contents of the lower-order
byte to the specified data memory, and the contents of
the higher-order byte to TBLH which is the Table
Higher-order byte register. Only the destination of the
lower-order byte in the table is well-defined; the other
bits of the table word are all transferred to the lower
portion of TBLH. The TBLH register is read only, and
the table pointer, TBLP, is a read/write register, indicating the table location. Before accessing the table,
the location should be placed in TBLP. All the table related instructions require 2 cycles to complete the operation. These areas may function as a normal
Program Memory depending upon the user¢s requirements.
E x te r n a l in te r r u p t 1 s u b r o u tin e
T im e r /e v e n t c o u n te r 0 in te r r u p t s u b r o u tin e
T im e r /e v e n t c o u n te r 1 in te r r u p t s u b r o u tin e
0 1 4 H
P ro g ra m
M e m o ry
T im e B a s e In te r r u p t
0 1 8 H
R T C In te rru p t
n 0 0 H
L o o k - u p ta b le ( 2 5 6 w o r d s )
n F F H
L o o k - u p ta b le ( 2 5 6 w o r d s )
1 F F F H
1 6 b its
N o te : n ra n g e s fro m
0 to 1 F
Program Memory
Instruction(s)
Table Location
*12
*11
*10
*9
*8
*7
*6
*5
*4
*3
*2
*1
*0
TABRDC [m]
P12
P11
P10
P9
P8
@7
@6
@5
@4
@3
@2
@1
@0
TABRDL [m]
1
1
1
1
1
@7
@6
@5
@4
@3
@2
@1
@0
Table Location
Note:
*12~*0: Table location bits
@7~@0: Table pointer bits
Rev. 1.00
P12~P8: Current program counter bits
9
December 19, 2006
HT46R652
0 0 H
Stack Register - STACK
The stack register is a special part of the memory used
to save the contents of the program counter. The stack
is organized into 16 levels and is neither part of the data
nor part of the program, and is neither readable nor
writeable. Its activated level is indexed by a stack
pointer, SP, which is neither readable nor writeable. At
the start of a subroutine call or an interrupt acknowledgment, the contents of the program counter is pushed
onto the stack. At the end of the subroutine or interrupt
routine, signaled by a return instruction, RET or RETI,
the contents of the program counter is restored to its
previous value from the stack. After a device reset, the
SP will point to the top of the stack.
If the stack is full and a non-masked interrupt takes
place, the interrupt request flag is recorded but the acknowledgment is still inhibited. Once the SP is decremented, by RET or RETI, the interrupt will be serviced.
This feature prevents a stack overflow, allowing the programmer to use the structure easily. Likewise, if the
stack is full, and a ²CALL² is subsequently executed, a
stack overflow occurs and the first entry is lost as only
the most recent sixteen return addresses are stored.
Data Memory - RAM
The data memory has a structure of 431´8 bits, and is
divided into two functional groups, namely the special
function registers, 47´8 bits, and the general purpose
data memory, Bank0: 192´8 bits and Bank2: 192´8 bits
most of which are readable/writeable, although some
are read only. The special function registers are overlapped in every bank.
M P 0
0 2 H
In d ir e c t A d d r e s s in g R e g is te r 1
0 3 H
M P 1
0 4 H
B P
0 5 H
A C C
0 6 H
P C L
0 7 H
T B L P
0 8 H
T B L H
0 9 H
R T C C
0 A H
S T A T U S
0 B H
IN T C 0
0 C H
T M R 0 H
0 D H
T M R 0 L
0 E H
T M R 0 C
0 F H
T M R 1 H
1 0 H
T M R 1 L
1 1 H
T M R 1 C
1 2 H
P A
1 3 H
P A C
1 4 H
P B
1 5 H
P B C
1 6 H
P C
1 7 H
P C C
1 8 H
P D
1 9 H
P D C
1 A H
P W M 0
1 B H
P W M 1
1 C H
P W M 2
1 D H
P W M 3
1 E H
IN T C 1
S p e c ia l P u r p o s e
D a ta M e m o ry
1 F H
Any unused remaining space before 40H is reserved for
future expanded usage and if read will return a ²00H²
value. The Data Memory space before 40H will overlap
in each bank.
The general purpose data memory, addressed from 40H
to FFH (Bank0; BP=0 or Bank2; BP=2), is used for data
and control information under instruction commands. All
of the data memory areas can handle arithmetic, logic,
increment, decrement and rotate operations directly.
Except for some dedicated bits, each bit in the data
memory can be set and reset by ²SET [m].i² and ²CLR
[m].i². They are also indirectly accessible through memory pointer registers, MP0 and MP1.
After first setting up BP to the value of ²01H² or ²02H² to
access either bank 1 or bank 2 respectively, these banks
must then be accessed indirectly using the Memory
Pointer MP1. With BP set to a value of either ²01H² or
²02H², using MP1 to indirectly read or write to the data
memory areas with addresses from 40H~FFH, will result in operations to either bank 1 or bank 2. Directly addressing the Data Memory will always result in Bank 0
being accessed irrespective of the value of BP.
Rev. 1.00
In d ir e c t A d d r e s s in g R e g is te r 0
0 1 H
2 0 H
P W M 4
2 1 H
P W M 5
2 2 H
P W M 6
2 3 H
P W M 7
2 4 H
A D R L
2 5 H
A D R H
2 6 H
A D C R
2 7 H
A C S R
2 8 H
P W M 8
2 9 H
P W M 9
2 A H
P W M 1 0
2 B H
P W M 1 1
2 C H
P W M 1 2
2 D H
P W M 1 3
2 E H
P W M 1 4
2 F H
P W M 1 5
3 F H
4 0 H
F F H
G e n e ra l P u rp o s e
D a ta M e m o ry
(3 8 4 B y te s )
: U n u s e d
R e a d a s "0 0 "
RAM Mapping
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December 19, 2006
HT46R652
Indirect Addressing Register
Status Register - STATUS
Locations 00H and 02H are for indirect addressing registers that are not physically implemented. Any
read/write operation to locations [00H] and [02H] accesses the Data Memory locations pointed to by MP0
and MP1 respectively. Reading location 00H or 02H indirectly will return a result of 00H. Writing indirectly will
lead to no operation.
The status register is 8 bits wide and contains, a carry
flag (C), an auxiliary carry flag (AC), a zero flag (Z), an
overflow flag (OV), a power down flag (PDF), and a
watchdog time-out flag (TO). It also records the status
information and controls the operation sequence.
Except for the TO and PDF flags, bits in the status register can be altered by instructions similar to other registers. Data written into the status register does not alter
the TO or PDF flags. Operations related to the status
register, however, may yield different results from those
intended. The TO and PDF flags can only be changed
by a Watchdog Timer overflow, a device power-up, or
clearing the Watchdog Timer and executing the ²HALT²
instruction. The Z, OV, AC, and C flags reflect the status
of the latest operations.
The function of data movement between two indirect addressing registers is not supported. The memory pointer
registers, MP0 and MP1, are both 8-bit registers used to
access the Data Memory by combining corresponding
indirect addressing registers. MP0 can only be applied
to the data memory, while MP1 can be applied to both
the data memory and the LCD display memory.
Accumulator - ACC
The accumulator, ACC, is related to the ALU operations.
It is also mapped to location 05H in the Data Memory
and is capable of operating with immediate data. The
data movement between two data memory locations
must pass through the ACC.
On entering the interrupt sequence or executing a subroutine call, the status register will not be automatically
pushed onto the stack. If the contents of the status is important, and if the subroutine is likely to corrupt the status register, the precautions should be taken to save it
properly.
Arithmetic and Logic Unit - ALU
Interrupts
This circuit performs 8-bit arithmetic and logic operations and provides the following functions:
The device provides two external interrupts, two internal
timer/event counter interrupts, an internal time base interrupt and an internal real time clock interrupt. The interrupt control register 0, INTC0, and the interrupt
control register 1, INTC1, both contain the interrupt control bits that are used to set the enable/disable status
and interrupt request flags.
· Arithmetic operations - ADD, ADC, SUB, SBC, DAA
· Logic operations - AND, OR, XOR, CPL
· Rotation - RL, RR, RLC, RRC
· Increment and Decrement - INC, DEC
· Branch decision - SZ, SNZ, SIZ, SDZ etc.
Once an interrupt subroutine is serviced, other interrupts are all blocked as the EMI bit is automatically
cleared, which may prevent any further interrupt nesting. Other interrupt requests may take place during this
interval, but only the interrupt request flag will be recorded. If a certain interrupt requires servicing within the
The ALU not only saves the results of a data operation
but also changes the status register.
Bit No.
Label
Function
0
C
C is set if an operation results in a carry during an addition operation or if a borrow does not
take place during a subtraction operation; otherwise C is cleared. C is also affected by a rotate through carry instruction.
1
AC
AC is set if an operation results in a carry out of the low nibbles in addition or no borrow from
the high nibble into the low nibble in subtraction; otherwise AC is cleared.
2
Z
3
OV
OV is set if an operation results in a carry into the highest-order bit but not a carry out of the
highest-order bit, or vice versa; otherwise OV is cleared.
4
PDF
PDF is cleared by either a system power-up or executing the ²CLR WDT² instruction. PDF is
set by executing the ²HALT² instruction.
5
TO
TO is cleared by a system power-up or executing the ²CLR WDT² or ²HALT² instruction. TO
is set by a WDT time-out.
6, 7
¾
Unused bit, read as ²0²
Z is set if the result of an arithmetic or logic operation is zero; otherwise Z is cleared.
Status (0AH) Register
Rev. 1.00
11
December 19, 2006
HT46R652
The internal Timer/Event Counter 0 interrupt is initialised by setting the Timer/Event Counter 0 interrupt request flag, T0F; bit 6 of INTC0, which is normally caused
by a timer overflow. After the interrupt is enabled, and if
the stack is not full, and the T0F bit is set, a subroutine
call to location 0CH occurs. The related interrupt request flag, T0F, is reset, and the EMI bit is cleared to disable other maskable interrupts. Timer/Event Counter 1
is operated in the same manner but its related interrupt
request flag is T1F, bit 4 of INTC1, and its subroutine call
location is 10H.
service routine, the EMI bit and the corresponding bit of
INTC0 or of INTC1 may be set in order to allow interrupt
nesting. If the stack is full, the interrupt request will not
be acknowledged, even if the related interrupt is enabled, until the stack pointer is decremented. If immediate service is desired, the stack should be prevented
from becoming full.
All these interrupts will generate a wake-up function. As
an interrupt is serviced, a control transfer occurs by
pushing the contents of the program counter onto the
stack followed by a branch to a subroutine at the specified location in the Program Memory. Only the contents
of the program counter is pushed onto the stack. If the
contents of the register or of the status register is altered
by the interrupt service program which corrupts the desired control sequence, the contents should be saved in
advance.
The time base interrupt is initialised by setting the time
base interrupt request flag, TBF; bit 5 of INTC1, that is
caused by a regular time base signal. After the interrupt
is enabled, and the stack is not full, and the TBF bit is
set, a subroutine call to location 14H occurs. The related
interrupt request flag, TBF, is reset and the EMI bit is
cleared to disable further maskable interrupts.
External interrupts are triggered by a an edge transition
on INT0 or INT1, when the related interrupt request flag,
EIF0; bit 4 of INTC0, EIF1; bit 5 of INTC0, is set. The
trigger edge type, high to low, low to high, or both low to
high and or high to low is determined by configuration
option. After the interrupt is enabled, if the stack is not
full, and the external interrupt is active, a subroutine call
to location 04H or 08H occurs. The interrupt request
flag, EIF0 or EIF1, and EMI bits are all cleared to disable
other maskable interrupts.
The real time clock interrupt is initialised by setting the
real time clock interrupt request flag, RTF; bit 6 of INTC1,
that is caused by a regular real time clock signal. After the
interrupt is enabled, and the stack is not full, and the RTF
bit is set, a subroutine call to location 18H occurs. The related interrupt request flag, RTF, is reset and the EMI bit
is cleared to disable further maskable interrupts.
Bit No.
Label
Function
0
EMI
Controls the master (global) interrupt (1=enabled; 0=disabled)
1
EEI0
Controls the external interrupt 0 (1=enabled; 0=disabled)
2
EEI1
Controls the external interrupt 1 (1=enabled; 0=disabled)
3
ET0I
Controls the Timer/Event Counter 0 interrupt (1=enabled; 0=disabled)
4
EIF0
External interrupt 0 request flag (1=active; 0=inactive)
5
EIF1
External interrupt 1 request flag (1=active; 0=inactive)
6
T0F
Internal Timer/Event Counter 0 request flag (1=active; 0=inactive)
7
¾
For test mode used only.
Must be written as ²0²; otherwise may result in unpredictable operation.
INTC0 (0BH) Register
Bit No.
Label
Function
0
ET1I
Controls the Timer/Event Counter 1 interrupt (1=enabled; 0=disabled)
1
ETBI
Controls the time base interrupt (1=enabled; 0:disabled)
2
ERTI
Controls the real time clock interrupt (1=enabled; 0:disabled)
3, 7
¾
Unused bit, read as ²0²
4
T1F
Internal Timer/Event Counter 1 request flag (1=active; 0=inactive)
5
TBF
Time base request flag (1=active; 0=inactive)
6
RTF
Real time clock request flag (1=active; 0=inactive)
INTC1 (1EH) Register
Rev. 1.00
12
December 19, 2006
HT46R652
which is determined by configuration option. When the
device enters the Power Down mode, the RC or crystal
oscillator will cease running to conserve power. The
32768Hz crystal oscillator, however, will keep running
when the device is in the Power Down mode. If the
32768Hz crystal oscillator is selected as the system oscillator, when the device enters the Power Down mode,
the system oscillator keeps running, but instruction execution will cease. Since the 32768Hz oscillator is also
designed for timing purposes, the internal timing functions, RTC, time base and WDT, continue to operate
even when the system enters the Power Down mode.
During the execution of an interrupt subroutine, other
maskable interrupt acknowledgments are all held until
the ²RETI² instruction is executed or the EMI bit and the
related interrupt control bit are set both to 1 (if the stack
is not full). To return from the interrupt subroutine,a
²RET² or ²RETI² instruction may be executed. RETI sets
the EMI bit and enables an interrupt service, but RET
does not.
Interrupts occurring in the interval between the rising
edges of two consecutive T2 pulses are serviced on the
latter of the two T2 pulses if the corresponding interrupts
are enabled. In the case of simultaneous requests, the
priorities in the following table apply. These can be
masked by resetting the EMI bit.
Interrupt Source
External interrupt 0
Priority
Vector
1
04H
External interrupt 1
2
08H
Timer/Event Counter 0 overflow
3
0CH
Timer/Event Counter 1 overflow
4
10H
Time base interrupt
5
14H
Real time clock interrupt
6
18H
If the RC oscillator is used, an external resistor connected between pins OSC1 and VSS is required, whose
value should range from 24kW to 1MW. The system clock,
divided by 4, can be monitored on pin OSC2 if a pull-high
resistor is connected. This pin can be used to synchronise external logic. The RC oscillator provides the most
cost effective solution. However, as the frequency may
vary with VDD, temperature, and process variations, it is
therefore not suitable for timing sensitive operations
where an accurate oscillator frequency is desired.
If a crystal oscillator is selected, a crystal across OSC1
and OSC2 is needed to provide the feedback and phase
shift required for the oscillator, and no other external
components are required. A resonator may be connected
between OSC1 and OSC2 to replace the crystal and to
get a frequency reference, but two external capacitors
between OSC1 and OSC2 and ground are required.
The EMI, EEI0, EEI1, ET0I, ET1I, ETBI, and ERTI bits
are all used to control the enable/disable status of the interrupts. These bits prevent the requested interrupt from
being serviced. Once the interrupt request flags, RTF,
TBF, T0F, T1F, EIF1, EIF0 are set, they remain in the
INTC1 or INTC0 register respectively until the interrupts
are serviced or cleared by a software instruction.
The other oscillator circuit, which is a real time clock, requires a 32768Hz crystal oscillator to be connected between OSC3 and OSC4.
It is recommended that a program should not use a
²CALL² instruction within the interrupt subroutine. This is
because interrupts often occur in an unpredictable manner or require to be serviced immediately in some applications. During that period, if only one stack is left, and
enabling the interrupt is not well controlled, execution of
a ²CALL² in the interrupt subroutine may damage the
original control sequence.
The RTC oscillator circuit can be controlled to start-up
quickly by setting the ²QOSC² bit, which is bit 4 of
RTCC. It is recommended to turn on the quick start-up
function during power on, and then turn it off again after
2 seconds.
The WDT oscillator is a free running on-chip RC oscillator, which does not require external components. Although when the system enters the Power Down mode
and the system clock stops, the WDT oscillator still operates with a nominal period of approximately 65ms at 5V.
The WDT oscillator can be disabled by a configuration
option to conserve power.
Oscillator Configuration
The device provides three oscillator circuits for the system clock, namely an RC oscillator, a crystal oscillator
and an RTC 32768Hz crystal oscillator, the choice of
V
O S C 3
O S C 4
3 2 7 6 8 H z C r y s ta l/R T C O s c illa to r
O S C 1
O S C 2
C r y s ta l O s c illa to r
D D
4 7 0 p F
O S C 1
fS
Y S
/4
O S C 2
R C
O s c illa to r
System Oscillator
Note: *32768Hz crystal enable condition: for WDT clock source or for system clock source.
Rev. 1.00
13
December 19, 2006
HT46R652
Watchdog Timer - WDT
the pair of instructions, ²CLR WDT1² and ²CLR WDT2².
Of these two types of instruction, only one type of instruction can be active at a time depending on a configuration
option - ²CLR WDT² times selection option. If the ²CLR
WDT² is selected (i.e., CLR WDT times equal one), any
execution of the ²CLR WDT² instruction clears the WDT.
In the case where the two ²CLR WDT1² and ²CLR
WDT2² instruction are chosen (i.e., CLR WDT times
equal two), these two instructions have to be executed to
clear the WDT; otherwise, the WDT may reset the chip
due to a time-out.
The WDT clock source is implemented by a dedicated
RC oscillator (WDT oscillator) or an instruction clock
(system clock/4) or a real time clock oscillator (RTC oscillator). The timer is designed to prevent a software
malfunction or sequence from jumping to an unknown
location with unpredictable results. The WDT can be
disabled by options. But if the WDT is disabled, all executions related to the WDT lead to no operation.
If the internal WDT oscillator, which is an RC oscillator
with a nominal period of 65ms at 5V, is selected, it is divided by 212~215 , the actual ratio chosen by configuration option, to get the WDT time-out period. The
minimum period for the WDT time-out period is about
300ms~600ms. This time-out period may vary with temperature, VDD and process variations. By selection the
WDT configuration option, longer time-out periods can
be realised. If the WDT time-out is selected as 215, the
maximum time-out period is divided by 215~216 about
2.1s~4.3s. If the WDT oscillator is disabled, the WDT
clock may still come from the instruction clock and operate in the same manner except that in the Power Down
mode the WDT will stop counting and lose its protecting
function. If the device operates in a noisy environment,
using the WDT internal RC oscillator is strongly recommended, since the HALT instruction will stop the system
clock.
Multi-function Timer
The device provides a multi-function timer for the WDT,
time base and RTC but with different time-out periods.
The multi-function timer consists of an 8-stage divider
and a 7-bit prescaler, with the clock source coming from
the WDT OSC, the RTC OSC or the instruction clock,
which is the system clock divided by 4. The multi-function timer also provides a selectable frequency signal,
whose division ratio ranges from fS/22 to fS/28, for LCD
driver circuits, and a selectable frequency signal, ranging from fS/22 to fS/29, for the buzzer output selectable via
configuration options.
It is recommended to select a frequency as close as
possible to 4kHz for the LCD driver circuits to obtain the
best display clarity.
The WDT overflow under normal operation initiates a device reset which sets the status bit ²TO². In the Power
Down mode, the overflow initiates a warm reset, in which
only the Program Counter and Stack Pointer are reset to
zero. To clear the contents of the WDT, there are three
methods that can be adopted. These are, an external reset, which is a low level on the RES pin, a software instruction and a ²HALT² instruction. There are two types of
software instructions; a single ²CLR WDT² instruction or
S y s te m
The time base offers a periodic time-out period to generate a regular internal interrupt. Its time-out period
ranges from 212/fS to 215/fS selected by a configuration
option. If a time base time-out occurs, the related interrupt request flag, TBF; bit 5 of INTC1, will be set. If the
interrupt is enabled, and the stack is not full, a subroutine call to location 14H occurs.
C lo c k /4
R T C
O S C 3 2 7 6 8 H z
W D T
O S C
Time Base
R O M
C o d e
O p tio n
fS
D iv id e r
fS /2
8
W D T
P r e s c a le r
T
C K
R
M a s k O p tio n
1 2 k H z
W D T C le a r
T
C K
R
T im e 2 15/fS ~
2 14/fS ~
2 13/fS ~
2 12/fS ~
o u
2 1
2 1
2 1
2 1
t R e s e t
/fS
/fS
4 / f
S
3
/fS
6
5
Watchdog Timer
fs
D iv id e r
R O M
P r e s c a le r
R O M
C o d e
O p tio n
C o d e O p tio n
L C D D r iv e r ( fS /2 2 ~ fS /2 8 )
B u z z e r (fS /2 2~ fS /2 9)
T im e B a s e In te r r u p t
2 12/fS ~ 2 15/fS
Time Base
Rev. 1.00
14
December 19, 2006
HT46R652
Real Time Clock - RTC
executing the ²HALT² instruction. The TO flag is set if a
WDT time-out occurs, and causes a wake-up that only
resets the Program Counter and the Stack Pointer, but
leaves the others in their original state.
The real time clock, RTC, is operated in the same manner as the time base in that it is used to supply a regular
internal interrupt. Its time-out period ranges from fS/28 to
fS/215, the value being setup using software. Writing
data to the RT2, RT1 and RT0 bits in the RTCC register,
provides various time-out periods. If an RTC time-out
occurs, the related interrupt request flag, RTF; bit 6 of
INTC1, is set. But if the interrupt is enabled, and the
stack is not full, a subroutine call to location 18H occurs.
RT2
RT1
RT0
RTC Clock Divided Factor
0
0
0
2 8*
0
0
1
2 9*
0
1
0
210*
0
1
1
211*
1
0
0
212
1
0
1
213
1
1
0
214
1
1
1
215
The port A wake-up and interrupt methods can be considered as a continuation of normal execution. Each bit
in port A can be independently selected to wake up the
device by a configuration option. If awakened by an I/O
port stimulus, the program resumes execution at the
next instruction following the ²HALT² instruction. Awakening from an interrupt, two sequence may occur. If the
related interrupt is disabled or the interrupt is enabled
but the stack is full, the program resumes execution at
the next instruction. But if the interrupt is enabled, and
the stack is not full, a regular interrupt response takes
place.
When an interrupt request flag is set before entering the
Power Down mode, the system cannot be awakened using that interrupt.
If a wake-up events occur, it takes 1024 tSYS (system
clock periods) to resume normal operation. In other
words, a dummy period is inserted after the wake-up. If
the wake-up results from an interrupt acknowledgment,
the actual interrupt subroutine execution is delayed by
more than one cycle. However, if a wake-up results in
the next instruction execution, the execution will be performed immediately after the dummy period is finished.
Note: * not recommended to be used
Power Down Operation
The Power Down mode is entered by the execution of a
²HALT² instruction and results in the following.
· The system will cease to run but the WDT oscillator
will keep running if the WDT oscillator or the real time
clock is selected.
To minimise power consumption, all the I/O pins should
be carefully managed before entering the Power Down
mode.
· The contents of the Memory and registers remain un-
changed.
· The WDT will be cleared and starts recounting, if the
Reset
WDT clock source is sourced from the WDT oscillator
or the real time clock oscillator.
There are three ways in which a reset may occur.
· RES pin is pulled low during normal operation
· All I/O ports maintain their original status.
· RES pin is pulled low when in the Power Down mode
· The PDF flag is set but the TO flag is cleared.
· A WDT time-out during normal operation
· The LCD driver will maintain its function if the WDT
OSC or RTC OSC is selected.
A WDT time-out when the device is in the Power Down
mode differs from other device reset conditions, as it will
perform a ²warm reset² that resets only the program
counter and the SP but leaves the other circuits in their
original state. Some registers remain unaffected during
other reset conditions. Most registers are reset to their
initial condition once the reset conditions are met. By examining the PDF and TO flags, the program can distinguish between the different types of device resets.
The system will wake up from the Power Down mode via
an external reset, an interrupt, an external falling edge
signal on port A or a WDT overflow. An external reset will
generate a device initialisation, while a WDT overflow
performs a ²warm reset². After examining the TO and
PDF flags, the reason for the device reset can be determined. The PDF flag is cleared by a system power-up or
by executing the ²CLR WDT² instruction, and is set by
fS
D iv id e r
P r e s c a le r
R T 2
R T 1
R T 0
8 to 1
M u x .
2 8/fS ~ 2 15/fS
R T C In te rru p t
Real Time Clock
Rev. 1.00
15
December 19, 2006
HT46R652
TO
PDF
0
0
RES reset during power-up
u
u
RES reset during normal operation
0
1
RES Wake-up
V
RESET Conditions
1
u
WDT time-out during normal operation
1
1
WDT Wake-up
D D
0 .0 1 m F *
1 0 0 k W
R E S
1 0 k W
0 .1 m F *
Note: ²u² stands for unchanged
Reset Circuit
To guarantee that the system oscillator is started and
stabilised, the SST (System Start-up Timer) provides an
extra-delay of 1024 system clock pulses when the system awakes from the Power Down mode or during a
power up. When awakened from the Power Down mode
or during a system power-up, the SST delay will be
added.
Note:
An extra SST delay is added during the power-up period, and any wake-up from the Power Down mode may
enable only the SST delay.
V D D
R E S
tS
S T
+ tO
P D
S S T T im e - o u t
The following table shows how various components of
the microcontroller are affected after a power-on reset
occurs.
Program Counter
²*² Make the length of the wiring, which is connected to the RES pin as short as possible, to
avoid noise interference.
C h ip
R e s e t
Reset Timing Chart
000H
Interrupt
Disabled
Prescaler, Divider
Cleared
WDT, RTC, Time Base
Cleared. After master reset,
WDT starts counting
Timer/event Counter
Off
Input/output Ports
Input mode
Stack Pointer
Points to the top of the stack
H A L T
W D T
R e s e t
T im e - o u t
R e s e t
E x te rn a l
R E S
O S C 1
W a rm
W D T
C o ld
R e s e t
S S T
1 0 - b it R ip p le
C o u n te r
P o w e r - o n D e te c tio n
Reset Configuration
Rev. 1.00
16
December 19, 2006
HT46R652
The register states are summarised in the following table:
Register
Reset
(Power On)
WDT Time-out
RES Reset
(Normal Operation) (Normal Operation)
RES Reset
(HALT)
WDT Time-out
(HALT)*
TMR0H
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
TMR0L
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
TMR0C
00-0 1000
00-0 1000
00-0 1000
00-0 1000
uu-u uuuu
TMR1H
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
TMR1L
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
TMR1C
0000 1---
0000 1---
0000 1---
0000 1---
uuuu u---
Program
Counter
0000H
0000H
0000H
0000H
0000H
MP0
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
MP1
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
BP
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
ACC
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
TBLP
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
TBLH
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
STATUS
--00 xxxx
--1u uuuu
--uu uuuu
--01 uuuu
--11 uuuu
INTC0
-000 0000
-000 0000
-000 0000
-000 0000
-uuu uuuu
INTC1
-000 -000
-000 -000
-000 -000
-000 -000
-uuu -uuu
RTCC
--00 0111
--00 0111
--00 0111
--00 0111
--uu uuuu
PA
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PAC
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PB
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PBC
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PC
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PCC
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PD
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PDC
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PWM0~
PWM15
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
ADRL
xxxx ----
xxxx ----
xxxx ----
xxxx ----
uuuu ----
ADRH
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
ADCR
0100 0000
0100 0000
0100 0000
0100 0000
uuuu uuuu
ACSR
---- --00
---- --00
---- --00
---- --00
---- --uu
Note:
²*² stands for warm reset
²u² stands for unchanged
²x² stands for unknown
Rev. 1.00
17
December 19, 2006
HT46R652
Timer/Event Counter
registers. The Timer/Event Counter 0/1 preload register
is changed with each TMR0H/TMR1H write operations.
Reading TMR0H/TMR1H will latch the contents of
TMR0H/TMR1H and TMR0L/TMR1L counters to the
destination and the lower-order byte buffer, respectively.
Reading TMR0L/TMR1L will only read the contents of
the lower-order byte buffer. The TMR0C and TMR1C
registers are the Timer/Event Counter control registers,
which control the operating mode, the timer enable or
disable and the active edge type.
Two timer/event counters, Timer/Event Counter 0 and
Timer/Event Counter,1 are implemented within the
microcontroller. Timer/Event Counter 0 is a 16-bit programmable count-up counter whose clock may come
from an external or internal source. The internal clock
source will come from fSYS. Timer/Event Counter 1 is
also a 16-bit programmable count-up counter whose
clock may come from an external source or an internal
source. The internal clock source comes from fSYS/4 or
a 32768Hz source, selected by a configuration option.
The external clock input allows the user to count external events, measure time intervals or pulse widths, or to
generate an accurate time base.
The T0M0, T0M1 and T1M0, T1M1 bits define the timer
operational mode. The event count mode is used to
count external events, which requires that the clock
source comes from an external TMR0 or TMR1 pin. The
timer mode functions as a normal timer with the clock
source coming from the internally selected clock source.
The pulse width measurement mode can be used to
count the high or low level duration of an external signal
on pin TMR0 or TMR1, with the count value based on
the internally selected clock source.
There are three registers associated with Timer/Event
Counter 0; TMR0H, TMR0L and TMR0C, and another
three for Timer/Event Counter 1; TMR1H, TMR1L and
TMR1C. Writing to TMR0L and TMR1L will only put the
written data into an internal lower-order byte buffer
(8-bit) while writing to TMR0H and TMR1H will transfer
the specified data and the contents of the lower-order
byte buffer to the TMR0H/TMR1H and TMR0L/TMR1L
In the event count or timer mode, the timer/event counter starts counting from the current contents in the
D a ta B u s
fS
8 - s ta g e P r e s c a le r
Y S
f IN
8 -1 M U X
T 0 P S C 2 ~ T 0 P S C 0
L o w B y te
B u ffe r
T
T 0 M 1
T 0 M 0
T M R 0
1 6 - B it
P r e lo a d R e g is te r
T 0 E
T 0 M 1
T 0 M 0
T 0 O N
P u ls e W id th
M e a s u re m e n t
M o d e C o n tro l
H ig h B y te
R e lo a d
O v e r flo w
L o w B y te
1 6 - B it T im e r /E v e n t C o u n te r
to In te rru p t
P F D 0
Timer/Event Counter 0
D a ta B u s
fS
Y S
/4
3 2 7 6 8 H z
T 1 S
M
U
f IN
L o w B y te
B u ffe r
T
X
T 1 M 1
T 1 M 0
T M R 1
1 6 - B it
P r e lo a d R e g is te r
T 1 E
T 1 M 1
T 1 M 0
T 1 O N
P u ls e W id th
M e a s u re m e n t
M o d e C o n tro l
H ig h B y te
R e lo a d
O v e r flo w
L o w B y te
1 6 - B it T im e r /E v e n t C o u n te r
to In te rru p t
P F D 1
Timer/Event Counter 1
P F D 0
P F D 1
M
U
1 /2
X
P F D
P A 3 D a ta C T R L
P F D
S o u r c e O p tio n
PFD Source Option
Rev. 1.00
18
December 19, 2006
HT46R652
result remains in the timer/event counter even if the activated transient occurs again. In other words, only a single measurement can be made until the T0ON/T1ON is
again set. In this operation mode, the timer/event counter begins counting, not according to the logic level on
the pins, but according to the transient edges. In the
case of counter overflows, the counter is reloaded from
the timer/event counter register and issues an interrupt
request, as in the other two modes, i.e., event and timer
modes.
timer/event counter and ends at FFFFH. Once an overflow occurs, the counter is reloaded from the timer/event
counter preload register, and generates an interrupt request flag, T0F; bit 6 of INTC0 and T1F; bit 4 of INTC1.
In the pulse width measurement mode with the values of
the T0ON/T1ON and T0E/T1E bits equal to 1, after the
TMR0 or TMR1 pin has received a transient from low to
high, or high to low if the T0E/T1E bit is ²0², it will start
counting until the TMR0 or TMR1 pin returns to its original level and resets the T0ON/T1ON bit. The measured
Bit No.
0
1
2
Label
T0PSC0
T0PSC1
T0PSC2
3
T0E
4
T0ON
5
¾
6
7
T0M0
T0M1
Function
To define the prescaler stages.
T0PSC2, T0PSC1, T0PSC0=
000: fINT=fSYS
001: fINT=fSYS/2
010: fINT=fSYS/4
011: fINT=fSYS/8
100: fINT=fSYS/16
101: fINT=fSYS/32
110: fINT=fSYS/64
111: fINT=fSYS/128
Defines the TMR0 active edge of the timer/event counter:
In Event Counter Mode (T0M1,T0M0)=(0,1):
1: count on falling edge;
0: count on rising edge
In Pulse Width measurement mode (T0M1,T0M0)=(1,1):
1: start counting on the rising edge, stop on the falling edge;
0: start counting on the falling edge, stop on the rising edge
Enable/disable timer counting (0=disabled; 1=enabled)
Unused bit, read as ²0²
Defines the operating mode T0M1, T0M0=
01= Event count mode (External clock)
10= Timer mode (Internal clock)
11= Pulse Width measurement mode (External clock)
00= Unused
TMR0C (0EH) Register
Bit No.
Label
0~2
¾
3
T1E
4
T1ON
5
T1S
6
7
T1M0
T1M1
Function
Unused bit, read as ²0²
Defines the TMR1 active edge of the timer/event counter:
In Event Counter Mode (T1M1,T1M0)=(0,1):
1: count on falling edge;
0: count on rising edge
In Pulse Width measurement mode (T1M1,T1M0)=(1,1):
1: start counting on the rising edge, stop on the falling edge;
0: start counting on the falling edge, stop on the rising edge
Enable/disable timer counting (0= disabled; 1= enabled)
Defines the TMR1 internal clock source (0=fSYS/4; 1=32768Hz)
Defines the operating mode T1M1, T1M0=
01= Event count mode (External clock)
10= Timer mode (Internal clock)
11= Pulse Width measurement mode (External clock)
00= Unused
TMR1C (11H) Register
Rev. 1.00
19
December 19, 2006
HT46R652
mains unchanged until the output latch is rewritten.
To enable a counting operation, the Timer ON bit, T0ON
or T1ON should be set to 1. In the pulse width measurement mode, the T0ON/T1ON is automatically cleared
after the measurement cycle is completed. But in the
other two modes, the T0ON/T1ON can only be reset by
instructions. The overflow of the Timer/Event Counter
0/1 is one of the wake-up sources and can also be used
to drive the PFD (Programmable Frequency Divider)
output on pin PA3, a function which is selected by a
configuration option. If PA3 is setup as a PFD output,
there are two types of selections. One is to use PFD0 as
the PFD output, the other is to use PFD1 as the PFD
output. PFD0 and PFD1 are the timer overflow signals
of the Timer/Event Counter 0 and Timer/Event Counter
1 respectively. No matter what the operation mode is,
writing a 0 to ET0I or ET1I disables the related interrupt
service. When the PFD function is selected, executing a
²SET [PA].3² instruction will enable the PFD output and
executing a ²CLR [PA].3² instruction will disable the
PFD output.
Each port has has its own Port Control Register, known as
PAC, PBC, PCC and PDC to control the input/output configuration. With this control register, a CMOS output or
Schmitt Trigger input with or without pull-high resistor
structures can be reconfigured dynamically under software control. To function as an input, the corresponding bit
of the control register must contain a ²1². The input source
also depends on the control register. If the control register
bit is ²1², the input will read the pad state. If the control register bit is ²0², the contents of the latches will move to the
internal bus. The latter is possible in the ²read-mod ify-write² instruction.
After a device reset, as the Port Control Registers will be
set high, the input/output lines will be setup as inputs,
and will be at a high level or in a floating state, depending on the pull-high configuration options. Each bit of
these input/output latches can be set or cleared by the
²SET [m].i² and ²CLR [m].i² instructions.
Some instructions first input data and then follow the
output operations. For example, ²SET [m].i², ²CLR
[m].i², ²CPL [m]², ²CPLA [m]² read the entire port states
into the CPU, execute the defined operations (bit-operation), and then write the results back to the latches or the
accumulator.
In cases where the timer/event counter is turned off,
writing data to the timer/event counter preload register
will also reload the new data into the timer/event counter. But if the timer/event counter is turned on, data written to the timer/event counter will only be stored in the
timer/event counter preload register. The timer/event
counter will continue with its normal operation until an
overflow occurs.
Each line of port A has the capability of waking-up the
device. Each I/O port has pull-high options. Once the
pull-high option is selected, the I/O port has a pull-high
resistor. It should be noted that a non-pull-high I/O port
operating in an input mode will be in a floating condition.
When the timer/event counter is read, the clock is
blocked to avoid errors, which may result in a counting
error and should therefore be taken into account by the
programmer. It is strongly recommended to load a desired value into the timer registers first before turning on
the related timer/event counter, for proper operation
since the initial value of the timer registers is unknown.
Due to the timer/event counter scheme, the programmer should pay special attention with instructions to enable then disable the timer for the first time, whenever
there is a need to use the timer/event counter function,
to avoid unpredictable results. After this procedure, the
timer/event function can be operated normally.
Pin PA3 is pin-shared with the PFD signal. If the PFD
configuration option is selected, the output signal for
PA3, if it setup as an output, will be the PFD signal generated by the timer/event counter overflow signal. If
setup as an input the PA3 will always retain its input
function. Once the PFD configuration option is selected,
the PFD output signal can be controlled by the PA3 data
register. Writing a ²1² to the PA3 data register will enable
the PFD output function while writing a ²0² will force the
PA3 pin to remain in a low condition. The I/O functions of
the PA3 pin are shown in the table.
Bits 0~2 of TMR0C can be used to define the
pre-scaling stages of the internal clock sources of the
timer/event counter. The overflow signal of the
timer/event counter can be used to generate the PFD
signal. The timer prescaler is also used as the the PWM
counter.
I/O
I/P
Mode (Normal)
PA3
Note:
Input/Output Ports
I/P
(PFD)
O/P
(PFD)
Logical
Output
Logical
Input
PFD
(Timer on)
The PFD frequency is the timer/event counter
overflow frequency divided by 2.
Pins PA0, PA1, PA3, PA5, PA6, PA4 and PA7 are
pin-shared with the BZ, BZ, PFD, INT0, INT1, TMR0
and TMR1 pins respectively.
There are 32 bidirectional input/output lines in the
microcontroller, divided among several ports labeled as
PA, PB, PC and PD. All of these I/O ports can be used
for input and output operations. For input operation,
these ports are non-latching, that is, the inputs must be
ready at the T2 rising edge of instruction ²MOV A,[m]².
For output operations, all the data is latched and reRev. 1.00
Logical
Input
O/P
(Normal)
The PA0 and PA1 pins are pin-shared with the BZ and
BZ signal, respectively. If the BZ/BZ option is selected,
the output signal in the output mode of PA0/PA1 will be
the buzzer signal, which is generated by the multi-func20
December 19, 2006
HT46R652
V
C o n tr o l B it
W r ite C o n tr o l R e g is te r
P U
Q
D
D a ta B u s
C K
D D
P A 0
P A 1
P A 2
P A 3
P A 4
P A 5
P A 6
P A 7
P B 0
P C 0
P D 0
Q
S
C h ip R e s e t
R e a d C o n tr o l R e g is te r
D a ta B it
Q
D
Q
C K
W r ite D a ta R e g is te r
/B Z
/B Z
/P
/T
/IN
/IN
/T
/A
/P
/P
F D
M R 0
T 0
T 1
M R 1
N 0 ~ P B 7 /A N 7
W M 0 ~ P C 7 /P W M 7
W M 8 ~ P D 7 /P W M 1 5
S
M
P A 0 /P A 1 /P A 3 /P C 0 ~ P C 7 /P D 0 ~ P D 7
B Z /B Z /P F D /P W M 0 ~ P W M 7 /P W M 8 ~ P W M 1 5
M
R e a d D a ta R e g is te r
U
R 0
T 0
T 1
R 1
fo
fo
fo
fo
r P
r P
r P
r P
A 4
A 5
A 6
A 7
o n
o n
o n
o n
X
P F D E N
(P A 3 )
X
S y s te m W a k e -u p
( P A o n ly )
T M
IN
IN
T M
U
O P 0 ~ O P 7
ly
ly
ly
ly
Input/Output Ports
tion timer. If the pins are setup as inputs then they will always retain their input function. Once the BZ/BZ
configuration option is selected, the buzzer output signal is controlled by the PA0/PA1 data register.
I/O
Mode
PC0~PC7,
PD0~PD7
I/P
O/P
(Normal) (Normal)
Logical
Input
Logical
Output
I/P
(PWM)
O/P
(PWM)
Logical
Input
PWM0~
PWM15
The PA0/PA1 pins I/O functions are shown in the table.
PA0 I/O
I
I
O O O O O O O O
PA1 I/O
I
O
I
PA0 Mode
X X C B B C B B B B
PA1 Mode
X C X X X C C C B B
PA0 Data
X X D 0
PA1 Data
X D X X X D1 D D X X
PA0 Pad Status
I
I
D 0
B D0 0
0
B
PA1 Pad Status
I
D
I
I D1 D D 0
B
I
I
I
Any unused pins must be carefully managed to ensure
that there are no floating input lines which will result in increased power consumption. It is therefore recommended that any unused pins are setup as outputs or
connected to a pull-high resistor if setup as inputs.
O O O O O
1 D0 0
1
B
0
The definitions of the PFD control signals and the PFD
output frequencies are listed in the following table.
1
PA3
Timer
Data
Timer Preload
Value Register
PA3
Pad
State
PFD
Frequency
²I² input; ²O² output; ²D, D0, D1² Data
²B² buzzer option, BZ or BZ
²X² don¢t care; ²C² CMOS output
OFF
X
0
0
X
OFF
X
1
U
X
ON
N
0
0
X
The PB port is also used for the A/D converter inputs.
The PWM outputs are shared with pins PC0~PC7 and
PD0~PD7. If the PWM function is enabled, the
PWM0~PWM15 outputs will appear on pins PC0~PC7
and PD0~PD7, if PC0~PC7 and PD0~PD7 are setup as
outputs. Writing a ²1² to the PC0~PC7 and PD0~PD7
data registers will enable the PWM output function while
writing a ²0² will force PC0~PC7 and PD0~PD7 to remain at a ²0²level. The I/O functions of PC0~PC7 and
PD0~PD7 are shown in the table.
ON
N
1
PFD
fTMR/[2´(M-N)]
Note:
Rev. 1.00
Note:
21
²X² stands for unused
²U² stands for unknown
²M² is ²65536² for PFD0 or PFD1
²N² is the timer/event counter preload value
²fTMR² is the input clock frequency for the
timer/event counter
December 19, 2006
HT46R652
PWM
value of PWM.1~PWM.0.
The microcontroller provides a 16-channel PWM output
shared with pins PC0~PC7 and PD0~PD7. Its output
signals can be configured as (6+2) or (7+1) type dependent upon configuration options. Each PWM channel has its own 8-bit data register, denoted as
PWM0~PWM15. The PWM frequency source comes
from fSYS. Once the PC0~PC7 and PD0~PD7 pins are
selected as PWM outputs, if the pins are setup as outputs, writing a ²1² to the PC0~PC7 and PD0~PD7 data
registers will enable the corresponding PWM output
function, while writing a ²0² will force the PC0~PC7 and
PD0~PD7 pins to remain at ²0².
In the (6+2) mode, the duty cycle of each modulation cycle is shown in the table.
Parameter
Duty Cycle
i<AC
DC + 1
64
i³AC
DC
64
Modulation cycle i
(i=0~3)
The (7+1) mode PWM cycle is divided into two modulation cycles, modulation cycle0~modulation cycle 1.
Each modulation cycle has 128 PWM input clock periods. In the (7+1) mode, the contents of each PWM register is divided into two groups. Group 1 of the PWM
register is denoted by DC which is the value of
PWM.7~PWM.1. Group 2 is denoted by AC which is the
value of PWM.0.
In the (6+2) mode, the PWM cycle is divided into four
modulation cycles, modulation cycle 0~modulation cycle 3. Each modulation cycle has 64 PWM input clock
periods. In the (6+2) mode, the contents of each PWM
register is divided into two groups. Group 1 of the PWM
register is denoted by a DC which is the value of
PWM.7~PWM.2. Group 2 is denoted by AC which is the
fS
AC (0~3)
In the (7+1) mode, the duty cycle of each modulation cycle is shown in the table.
/2
Y S
[P W M ] = 1 0 0
P W M
2 5 /6 4
2 5 /6 4
2 5 /6 4
2 5 /6 4
2 5 /6 4
2 6 /6 4
2 5 /6 4
2 5 /6 4
2 5 /6 4
2 6 /6 4
2 6 /6 4
2 6 /6 4
2 5 /6 4
2 5 /6 4
2 6 /6 4
2 6 /6 4
2 6 /6 4
2 5 /6 4
2 6 /6 4
[P W M ] = 1 0 1
P W M
[P W M ] = 1 0 2
P W M
[P W M ] = 1 0 3
P W M
2 6 /6 4
P W M
m o d u la tio n p e r io d : 6 4 /fS
M o d u la tio n c y c le 0
Y S
M o d u la tio n c y c le 1
P W M
M o d u la tio n c y c le 2
c y c le : 2 5 6 /fS
M o d u la tio n c y c le 3
M o d u la tio n c y c le 0
Y S
(6+2) PWM Mode
fS
Y S
/2
[P W M ] = 1 0 0
P W M
5 0 /1 2 8
5 0 /1 2 8
5 0 /1 2 8
5 1 /1 2 8
5 0 /1 2 8
5 1 /1 2 8
5 1 /1 2 8
5 1 /1 2 8
5 1 /1 2 8
5 1 /1 2 8
5 2 /1 2 8
[P W M ] = 1 0 1
P W M
[P W M ] = 1 0 2
P W M
[P W M ] = 1 0 3
P W M
5 2 /1 2 8
P W M
m o d u la tio n p e r io d : 1 2 8 /fS
Y S
M o d u la tio n c y c le 0
M o d u la tio n c y c le 1
P W M
c y c le : 2 5 6 /fS
M o d u la tio n c y c le 0
Y S
(7+1) PWM Mode
Rev. 1.00
22
December 19, 2006
HT46R652
Parameter
AC (0~1)
Duty Cycle
i<AC
DC + 1
128
i³AC
DC
128
Modulation cycle i
(i=0~1)
analog input channel. There are a total of eight selectable
channels. Bits 5~3 of ADCR are used to set the PB configurations. PB can be setup to be either an analog input
or digital I/O line decided by these 3 bits. Once a PB line
is selected as an analog input, the I/O function and
pull-high resistor of the I/O line is disabled and the A/D
converter circuit is powered-on. The EOCB bit, bit6 of
ADCR, is the end of A/D conversion flag. This bit can be
monitored to know when the A/D conversion has finished. The START bit in the ADCR register is used to initiate an A/D conversion process. By providing the START
bit with a rising edge and then a falling edge, the A/D
conversion process will be initiated. In order to ensure
that the A/D conversion has completed, the START bit
should remain at ²0² until the EOCB has cleared to ²0²,
which indicates the end of A/D conversion.
The modulation frequency, cycle frequency and cycle
duty of the PWM output signal are summarised in the
following table.
PWM
Modulation Frequency
fSYS/64 for (6+2) bits mode
fSYS/128 for (7+1) bits mode
PWM Cycle PWM Cycle
Frequency
Duty
fSYS/256
[PWM]/256
A/D Converter
An 8-channel, 12-bit resolution A/D converter is implemented within the microcontroller. The reference voltage is VDD. The A/D converter contains 4 special
registers which are; ADRL, ADRH, ADCR and ACSR.
The ADRH and ADRL registers contain the A/D result
register higher-order byte and lower-order byte conversion values and are read-only. After the A/D conversion
is completed, the ADRH and ADRL should be read to
get the conversion result data. The ADCR is an A/D converter control register, which defines the A/D channel
number, analog channel select, start A/D conversion
control bit and the end of A/D conversion flag. This register is used to start an A/D conversion, define the PB
configuration, select the analog channel, and give the
START bit a rising and falling edge (0®1®0). At the end
of the A/D conversion, the EOCB bit will be automatically cleared to indicate that the conversion process has
finished. The ACSR is the A/D clock setting register,
which is used to select the A/D clock source.
Bit 7 of the ACSR register is used for test purposes only
and must not be used for other purposes by the application program. Bit1 and bit0 of the ACSR register are
used to select the A/D clock source.
When the A/D conversion has completed, the A/D interrupt request flag will be set. The EOCB bit will be set to
²1² when the START bit is set from ²0² to ²1².
Important Note for A/D initialisation:
Special care must be taken to initialise the A/D converter each time the Port B A/D channel selection bits
are modified, otherwise the EOCB flag may be in an undefined condition. An A/D initialisation is implemented
by setting the START bit high and then clearing it to zero
within 10 instruction cycles of the Port B channel selection bits being modified. Note that if the Port B channel
selection bits are all cleared to zero then an A/D initialisation is not required.
The A/D converter control register is used to control the
A/D converter. Bits 2~0 of ADCR are used to select the
Bit No.
Label
0
1
ADCS0
ADCS1
2~7
¾
Function
Selects the A/D converter clock source
00= system clock/2
01= system clock/8
10= system clock/32
11= undefined
Unused bit, read as ²0²
ACSR (27H) Register
Rev. 1.00
23
December 19, 2006
HT46R652
Bit No.
Label
Function
0
1
2
ACS0
ACS1
ACS2
Defines the analog channel select.
3
4
5
PCR0
PCR1
PCR2
Defines the port B configuration select. If PCR0, PCR1 and PCR2 are all zero, the ADC circuit is
powered off to reduce power consumption
6
EOCB
Indicates end of A/D conversion. (0 = end of A/D conversion)
Each time bits 3~5 change state the A/D should be initialised by issuing a START signal, otherwise the EOCB flag may have an undefined condition. See ²Important note for A/D initialisation².
7
START
Starts the A/D conversion. (0®1®0= start; 0®1= Resets the A/D converter and sets EOCB to
²1²)
ADCR (26H) Register
PCR2
PCR1
PCR0
7
6
5
4
3
2
1
0
0
0
0
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
0
0
1
PB7
PB6
PB5
PB4
PB3
PB2
PB1
AN0
0
1
0
PB7
PB6
PB5
PB4
PB3
PB2
AN1
AN0
0
1
1
PB7
PB6
PB5
PB4
PB3
AN2
AN1
AN0
1
0
0
PB7
PB6
PB5
PB4
AN3
AN2
AN1
AN0
1
0
1
PB7
PB6
PB5
AN4
AN3
AN2
AN1
AN0
1
1
0
PB7
PB6
AN5
AN4
AN3
AN2
AN1
AN0
1
1
1
AN7
AN6
AN5
AN4
AN3
AN2
AN1
AN0
Port B Configuration
ACS2
ACS1
ACS0
Analog Channel
0
0
0
AN0
0
0
1
AN1
0
1
0
AN2
0
1
1
AN3
1
0
0
AN4
1
0
1
AN5
1
1
0
AN6
1
1
1
AN7
Analog Input Channel Selection
Register
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
ADRL
D3
D2
D1
D0
¾
¾
¾
¾
ADRH
D11
D10
D9
D8
D7
D6
D5
D4
Note: D0~D11 is the A/D conversion result data bit LSB~MSB.
ADRL (24H), ADRH (25H) Register
Rev. 1.00
24
December 19, 2006
HT46R652
The following programming example illustrates how to setup and implement an A/D conversion. The method of polling the EOCB bit in the ADCR register is used to detect when the conversion cycle is complete.
Example: using EOCB Polling Method to detect end of conversion
clr
mov
mov
mov
mov
EADI
a,00000001B
ACSR,a
a,00100000B
ADCR,a
:
:
; disable ADC interrupt
; setup the ACSR register to select fSYS/8 as the A/D clock
; setup ADCR register to configure Port PB0~PB3 as A/D inputs
; and select AN0 to be connected to the A/D converter
; As the Port B channel bits have changed the following START
; signal (0-1-0) must be issued within 10 instruction cycles
:
Start_conversion:
clr
START
set
START
clr
START
Polling_EOC:
sz
EOCB
jmp
polling_EOC
mov
a,ADRH
mov
adrh_buffer,a
mov
a,ADRL
mov
adrl_buffer,a
:
:
jmp
start_conversion
M in im u m
; reset A/D
; start A/D
; poll the ADCR register EOCB bit to detect an end of A/D conversion
; continue polling
; read the conversion result high byte value from the ADRH register
; save result to the user defined memory
; read the conversion result low byte value from the ADRL register
; save the result to the user defined memory
; start the next A/D conversion
o n e in s tr u c tio n c y c le n e e d e d , M a x im u m
te n in s tr u c tio n c y c le s a llo w e d
S T A R T
E O C B
A /D s a m p lin g tim e
tA D C S
P C R 2 ~
P C R 0
0 0 0 B
A /D
tA
s a m p lin g tim e
A /D
tA
D C S
1 0 0 B
1 0 0 B
s a m p lin g tim e
D C S
1 0 1 B
0 0 0 B
1 . P B p o rt s e tu p a s I/O s
2 . A /D c o n v e r te r is p o w e r e d o ff
to r e d u c e p o w e r c o n s u m p tio n
A C S 2 ~
A C S 0
0 0 0 B
P o w e r-o n
R e s e t
0 1 0 B
0 0 0 B
0 0 1 B
S ta rt o f A /D
c o n v e r s io n
S ta rt o f A /D
c o n v e r s io n
S ta rt o f A /D
c o n v e r s io n
R e s e t A /D
c o n v e rte r
R e s e t A /D
c o n v e rte r
E n d o f A /D
c o n v e r s io n
1 : D e fin e P B c o n fig u r a tio n
2 : S e le c t a n a lo g c h a n n e l
A /D
N o te :
A /D
tA D
tA
C S
D C
c lo c k m u s t b e fS
= 3 2 tA D
= 8 0 tA D
Y S
/2 , fS
tA D C
c o n v e r s io n tim e
Y S
/8 o r fS
Y S
R e s e t A /D
c o n v e rte r
E n d o f A /D
c o n v e r s io n
A /D
tA D C
c o n v e r s io n tim e
d o n 't c a r e
E n d o f A /D
c o n v e r s io n
A /D
tA D C
c o n v e r s io n tim e
/3 2
A/D Conversion Timing
Rev. 1.00
25
December 19, 2006
HT46R652
LCD Display Memory
C O M
The device provides an area of embedded data memory
for the LCD display. This area is located from 40H to
68H of the Data Memory inside Bank 1. The Bank
Pointer, known as BP, is used to select the LCD display
memory. When the BP is set to ²1², any data written into
locations 40H~68H will affect only the LCD display.
When the BP is cleared to ²0² or set to ²2², any data written into locations 40H~68H will access the general purpose data memory. The LCD display memory can be
read and written to only by an indirect addressing mode
using MP1. When data is written into the display data
area, it is automatically read by the LCD driver which
then generates the corresponding LCD driving signals.
To turn the display on or off, a ²1² or a ²0² is written to the
corresponding bit of the display memory, respectively.
The figure illustrates the mapping between the display
memory and LCD pattern for the device.
4 0 H
4 1 H
4 2 H
4 3 H
6 6 H
6 7 H
6 8 H
0
B it
0
1
1
2
2
3
3
S E G M E N T
0
1
2
3
3 8
3 9
4 0
Display Memory
1/4 duty. The LCD driver can either have an ²R² type or
²C² bias type. If the ²R² bias type is selected, no external
capacitors are required. If the ²C² bias type is selected, a
capacitor is required to be connected between the C1
and C2 pins. The LCD driver bias voltage can be 1/2
bias or 1/3 bias, selected via a configuration option. If
the 1/2 bias is selected, a capacitor must be connected
between the V2 pin and ground. If the 1/3 bias is selected, two capacitors are needed for the V1 and V2
pins.
LCD Driver Output
The output number of the device LCD driver can be
41´2 or 41´3 or 40´4 by option, i.e., 1/2 duty, 1/3 duty or
V A
V B
V C
C O M 0
V S S
V A
V B
V C
C O M 1
V S S
V A
V B
V C
C O M 2
V S S
V A
V B
C O M 3
V C
V S S
V A
V B
V C
L C D s e g m e n ts O N
C O M 2 s id e lig h te d
V S S
N o te : 1 /4 d u ty , 1 /3 b ia s , C
ty p e : " V A " 3 /2 V L C D , " V B " V L C D , " V C " 1 /2 V L C D
1 /4 d u ty , 1 /3 b ia s , R
ty p e : "V A " V L C D , "V B " 2 /3 V L C D , "V C " 1 /3 V L C D
LCD Driver Output
Rev. 1.00
26
December 19, 2006
HT46R652
D u r in g a R e s e t P u ls e
C O M 0 ,C O M 1 ,C O M 2
A ll L C D
d r iv e r o u tp u ts
N o r m a l O p e r a tio n M o d e
*
*
*
C O M 0
C O M 1
C O M 2 *
L C D s e g m e n ts O N
C O M 0 ,1 , 2 s id e s a r e u n lig h te d
O n ly L C D s e g m e n ts O N
C O M 0 s id e a r e lig h te d
O n ly L C D s e g m e n ts O N
C O M 1 s id e a r e lig h te d
O n ly L C D s e g m e n ts O N
C O M 2 s id e a r e lig h te d
L C D s e g m e n ts O N
C O M 0 ,1 s id e s a r e lig h te d
L C D s e g m e n ts O N
C O M 0 , 2 s id e s a r e lig h te d
L C D s e g m e n ts O N
C O M 1 , 2 s id e s a r e lig h te d
L C D s e g m e n ts O N
C O M 0 ,1 , 2 s id e s a r e lig h te d
H A L T M o d e
V L
1 /2
V S
V L
1 /2
V S
C D
V L
1 /2
V S
V L
1 /2
V S
V L
1 /2
V S
V L
1 /2
V S
V L
1 /2
V S
V L
1 /2
V S
V L
1 /2
V S
V L
1 /2
V S
V L
1 /2
V S
V L
1 /2
V S
V L
1 /2
V S
C D
V L
1 /2
V S
V L
1 /2
V S
C O M 0 , C O M 1 , C O M 2
A ll lc d d r iv e r o u tp u ts
V L C D
S
C D
V L C D
S
V L C D
S
C D
V L C D
S
C D
V L C D
S
C D
V L C D
S
C D
V L C D
S
C D
V L C D
S
C D
V L C D
S
C D
V L C D
S
C D
V L C D
S
C D
V L C D
S
C D
V L C D
S
C D
V L C D
S
C D
S
V L C D
N o te : " * " O m it th e C O M 2 s ig n a l, if th e 1 /2 d u ty L C D is u s e d .
LCD Driver Output - 1/3 Duty, 1/2 Bias, R/C Type
LCD Segments as Logic Outputs
The SEG0~SEG23 pins can also can be setup as logic outputs via a configuration options. Once an LCD segment is configured as a logic output, the content of bit0 of the related segment address in the LCD RAM will appear on the segment.
Pins SEG0~SEG7 and SEG8~SEG15 are together byte optioned as logic outputs, SEG16~SEG23 are individually bit
optioned as logic outputs.
LCD Type
LCD Bias Type
VMAX
Rev. 1.00
R Type
1/2 bias
1/3 bias
C Type
1/2 bias
If VDD>VLCD, then VMAX connect to VDD,
else VMAX connect to VLCD
27
1/3 bias
3
If VDD> VLCD, then VMAX connect to VDD,
2
else VMAX connect to V1
December 19, 2006
HT46R652
Low Voltage Reset/Detector Functions
A low voltage detector, LVD, and low voltage reset, LVR, functions are implemented within the microcontroller. These
two functions can be enabled/disabled by options. Once the LVD option is enabled, the user can use the RTCC.3 to enable/disable (1/0) the LVD circuit and read the LVD detector status (0/1) from RTCC.5; otherwise, the LVD function is
disabled.
The RTCC register definitions are listed below.
Bit No.
Label
Function
0~2
RT0~RT2
3
LVDC
LVD enable/disable (1/0)
4
QOSC
32768Hz OSC quick start-up oscillator
0/1: quickly/slowly start
5
LVDO
LVD detection output (1/0)
1: low voltage detected, read only
6, 7
¾
8 to 1 multiplexer control inputs to select the real clock prescaler output
Unused bit, read as ²0²
RTCC (09H) Register
The relationship between VDD and VLVR is shown below.
The LVR has the same effect or function as the external
RES signal which performs a chip reset. During the
HALT state, both LVR and LVD are disabled.
V D D
5 .5 V
The microcontroller provides a low voltage reset circuit
in order to monitor the supply voltage of the device. If
the supply voltage of the device is within the range
0.9V~VLVR, such as when changing a battery, the LVR
will automatically reset the device internally.
V
O P R
5 .5 V
V
L V R
3 .0 V
2 .2 V
The LVR includes the following specifications:
· The low voltage (0.9V~VLVR) has to remain in its origi-
nal state for longer than 1ms. If the low voltage state
does not exceed 1ms, the LVR will ignore it and will
not perform a reset function.
0 .9 V
Note: VOPR is the voltage range for proper chip
operation with a 4MHz system clock.
· The LVR uses an ²OR² function with the external RES
signal to perform a chip reset.
V
D D
5 .5 V
V
L V R
L V R
D e te c t V o lta g e
0 .9 V
0 V
R e s e t S ig n a l
N o r m a l O p e r a tio n
R e s e t
*1
R e s e t
*2
Low Voltage Reset
Note:
*1: To make sure that the system oscillator has stabilized, the SST provides an extra delay of 1024 system
clock pulses before starting normal operation.
*2: Since a low voltage state has to be maintained its original state for over tLVR, therefore after tLVR delay,
the device enters the reset mode.
Rev. 1.00
28
December 19, 2006
HT46R652
Configuration Options
The following shows the configuration options in the device. All these options must be defined in order to ensure proper
functioning of the microcontroller.
Options
OSC type selection. This option is to decide if an RC or crystal or 32768Hz crystal oscillator is chosen as the system
clock.
WDT, RTC and time base clock source selection.
There are three types of selections: system clock/4 or RTC OSC or WDT OSC.
WDT enable/disable selection. WDT can be enabled or disabled by option.
WDT time-out period selection. There are four types of selection: WDT clock source divided by 212/fS~213/fS,
213/fS~214/fS, 214/fS~215/fS or 215/fS~216/fS.
CLR WDT times selection. This option defines the method to clear the WDT by instruction. ²One time² means that
the ²CLR WDT² instruction can clear the WDT. ²Two times² means only if both of the ²CLR WDT1² and ²CLR WDT2²
instructions have been executed, the WDT can be cleared.
Time Base time-out period selection. The Time Base time-out period ranges from 212/fS to 215/fS. ²fS² means the clock
source selected by options.
Buzzer output frequency selection. There are eight types of frequency signals for buzzer output: fS/22~fS/29. ²fS²
means the clock source selected by options.
Wake-up selection. This option defines the wake-up capability. External I/O pins (PA only) all have the capability to
wake-up the chip from a HALT by a falling edge (bit option).
Pull-high selection. This option is to decide whether the pull-high resistance is visible or not in the input mode of the
I/O ports. PA, PB, PC and PD can be independently selected (bit option).
I/O pins shared with other function selections.
PA0/BZ, PA1/BZ: PA0 and PA1 can be set as I/O pins or as buzzer outputs.
LCD common selection. There are three types of selections: 2 common (1/2 duty) or 3 common (1/3 duty) or 4 common (1/4 duty). If the 4 common is selected, the segment output pin ²SEG40² will be setup as a common output.
LCD bias power supply selection.
There are two types of selections: 1/2 bias or 1/3 bias
LCD bias type selection. This option is to determine what kind of bias is selected, R type or C type.
LCD driver clock frequency selection.
There are seven types of frequency signals for the LCD driver circuits: fS/22~fS/28. ²fS² stands for the clock source selection by options.
LCD ON/OFF at HALT selection.
LCD Segments as logical output selection, (byte, byte, bit, bit, bit, bit, bit, bit, bit, bit option)
[SEG0~SEG7], [SEG8~SEG15], SEG16, SEG17, SEG18, SEG19, SEG20, SEG21, SEG22, or SEG23
LVR selection. LVR enable\disable option
LVD selection. LVD enable\disable option
PFD selection. If PA3 is setup as a PFD output, there are two types of selections; One is PFD0 as the PFD output, the
other is PFD1 as the PFD output. PFD0, PFD1 are the timer overflow signals of the Timer/Event Counter 0 and
Timer/Event Counter 1, respectively.
PWM selection: (7+1) or (6+2) mode
PC0~PC7: General Purpose I/Os or PWM outputs (port option - no individual pin selection)
PD0~PD7: General Purpose I/O or PWM output (bit option - individual pin selection)
INT0 or INT1 triggering edge selection: disable; high to low; low to high; low to high or high to low.
LCD bias current selection: low/high driving current (for R type only).
Rev. 1.00
29
December 19, 2006
HT46R652
Application Circuits
V
D D
0 .0 1 m F *
C O M 0 ~ C O M 2
C O M 3 /S E G 4 0
S E G 0 ~ S E G 3 9
V D D
1 0 0 k W
0 .1 m F
R E S
L C D
P A N E L
V L C D
1 0 k W
L C D
P o w e r S u p p ly
V M A X
0 .1 m F *
V S S
C 1
0 .1 m F
V
C 2
O S C
C ir c u it
O S C 1
4 7 0 p F
V 1
O S C 2
0 .1 m F
S e e r ig h t s id e
3 2 7 6 8 H z
D D
R
V 2
1 0 p F
O S C 4
P
~
P C 0 /P W M 0
P C 7 /P W M 7
P A
P
P
P A
P D 0 /P W M 8
P D 7 /P W M 1 5
P A 0 /B
P A 1 /B
P A
A 3 /P F
4 /T M R
A 5 /IN T
A 6 /IN T
7 /T M R
O S C 1
fS
C 1
0 .1 m F
O S C 3
O S C
Z
2
R 1
D
/4
O S C 2
O S C 1
C 2
Z
Y S
R C S y s te m O s c illa to r
2 4 k W < R O S C < 1 M W
C ry s ta l S y s te m
F o r th e v a lu e s ,
s e e ta b le b e lo w
O s c illa to r
O S C 2
0
0
O S C 1
1
1
~
P B 0 /A N 0
P B 7 /A N 7
~
O S C 2
H T 4 6 R 6 5 2
O S C
3 2
O s
O S
u n
7 6 8 H z C ry s ta l S y s te m
c illa to r
C 1 a n d O S C 2 le ft
c o n n e c te d
C ir c u it
The following table shows the C1, C2 and R1 values corresponding to the different crystal values. (For reference only)
C1, C2
R1
4MHz Crystal
Crystal or Resonator
25pF
12kW
4MHz Resonator
10pF
18kW
3.58MHz Crystal
25pF
12kW
3.58MHz Resonator
10pF
15kW
2MHz Crystal & Resonator
25pF
12kW
1MHz Crystal
68pF
24kW
480kHz Resonator
100pF
12kW
455kHz Resonator
200pF
12kW
429kHz Resonator
200pF
12kW
400kHz Resonator
300pF
10kW
The function of the resistor R1 is to ensure that the oscillator will switch off should low voltage conditions occur. Such a low voltage, as mentioned here, is one which is less than the lowest value of the
MCU operating voltage. Note however that if the LVR is enabled then R1 can be removed.
Note:
The resistance and capacitance for reset circuit should be designed in such a way as to ensure that the VDD is
stable and remains within a valid operating voltage range before bringing RES to high.
²*² Make the length of the wiring, which is connected to the RES pin as short as possible, to avoid noise
interference.
²VMAX² connect to VDD or VLCD or V1 refer to the table.
LCD Type
LCD bias type
VMAX
Rev. 1.00
R Type
1/2 bias
1/3 bias
C Type
1/2 bias
If VDD>VLCD, then VMAX connect to VDD,
else VMAX connect to VLCD
30
1/3 bias
If VDD > 3/2VLCD, then VMAX connect to VDD,
else VMAX connect to V1
December 19, 2006
HT46R652
Instruction Set Summary
Description
Instruction
Cycle
Flag
Affected
Add data memory to ACC
Add ACC to data memory
Add immediate data to ACC
Add data memory to ACC with carry
Add ACC to data memory with carry
Subtract immediate data from ACC
Subtract data memory from ACC
Subtract data memory from ACC with result in data memory
Subtract data memory from ACC with carry
Subtract data memory from ACC with carry and result in data memory
Decimal adjust ACC for addition with result in data memory
1
1(1)
1
1
1(1)
1
1
1(1)
1
1(1)
1(1)
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
C
1
1
1
1(1)
1(1)
1(1)
1
1
1
1(1)
1
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Increment data memory with result in ACC
Increment data memory
Decrement data memory with result in ACC
Decrement data memory
1
1(1)
1
1(1)
Z
Z
Z
Z
Rotate data memory right with result in ACC
Rotate data memory right
Rotate data memory right through carry with result in ACC
Rotate data memory right through carry
Rotate data memory left with result in ACC
Rotate data memory left
Rotate data memory left through carry with result in ACC
Rotate data memory left through carry
1
1(1)
1
1(1)
1
1(1)
1
1(1)
None
None
C
C
None
None
C
C
Move data memory to ACC
Move ACC to data memory
Move immediate data to ACC
1
1(1)
1
None
None
None
Clear bit of data memory
Set bit of data memory
1(1)
1(1)
None
None
Mnemonic
Arithmetic
ADD A,[m]
ADDM A,[m]
ADD A,x
ADC A,[m]
ADCM A,[m]
SUB A,x
SUB A,[m]
SUBM A,[m]
SBC A,[m]
SBCM A,[m]
DAA [m]
Logic Operation
AND A,[m]
OR A,[m]
XOR A,[m]
ANDM A,[m]
ORM A,[m]
XORM A,[m]
AND A,x
OR A,x
XOR A,x
CPL [m]
CPLA [m]
AND data memory to ACC
OR data memory to ACC
Exclusive-OR data memory to ACC
AND ACC to data memory
OR ACC to data memory
Exclusive-OR ACC to data memory
AND immediate data to ACC
OR immediate data to ACC
Exclusive-OR immediate data to ACC
Complement data memory
Complement data memory with result in ACC
Increment & Decrement
INCA [m]
INC [m]
DECA [m]
DEC [m]
Rotate
RRA [m]
RR [m]
RRCA [m]
RRC [m]
RLA [m]
RL [m]
RLCA [m]
RLC [m]
Data Move
MOV A,[m]
MOV [m],A
MOV A,x
Bit Operation
CLR [m].i
SET [m].i
Rev. 1.00
31
December 19, 2006
HT46R652
Instruction
Cycle
Flag
Affected
Jump unconditionally
Skip if data memory is zero
Skip if data memory is zero with data movement to ACC
Skip if bit i of data memory is zero
Skip if bit i of data memory is not zero
Skip if increment data memory is zero
Skip if decrement data memory is zero
Skip if increment data memory is zero with result in ACC
Skip if decrement data memory is zero with result in ACC
Subroutine call
Return from subroutine
Return from subroutine and load immediate data to ACC
Return from interrupt
2
1(2)
1(2)
1(2)
1(2)
1(3)
1(3)
1(2)
1(2)
2
2
2
2
None
None
None
None
None
None
None
None
None
None
None
None
None
Read ROM code (current page) to data memory and TBLH
Read ROM code (last page) to data memory and TBLH
2(1)
2(1)
None
None
No operation
Clear data memory
Set data memory
Clear Watchdog Timer
Pre-clear Watchdog Timer
Pre-clear Watchdog Timer
Swap nibbles of data memory
Swap nibbles of data memory with result in ACC
Enter power down mode
1
1(1)
1(1)
1
1
1
1(1)
1
1
None
None
None
TO,PDF
TO(4),PDF(4)
TO(4),PDF(4)
None
None
TO,PDF
Mnemonic
Description
Branch
JMP addr
SZ [m]
SZA [m]
SZ [m].i
SNZ [m].i
SIZ [m]
SDZ [m]
SIZA [m]
SDZA [m]
CALL addr
RET
RET A,x
RETI
Table Read
TABRDC [m]
TABRDL [m]
Miscellaneous
NOP
CLR [m]
SET [m]
CLR WDT
CLR WDT1
CLR WDT2
SWAP [m]
SWAPA [m]
HALT
Note:
x: Immediate data
m: Data memory address
A: Accumulator
i: 0~7 number of bits
addr: Program memory address
Ö: Flag is affected
-: Flag is not affected
(1)
: If a loading to the PCL register occurs, the execution cycle of instructions will be delayed for one more cycle
(four system clocks).
(2)
: If a skipping to the next instruction occurs, the execution cycle of instructions will be delayed for one more
cycle (four system clocks). Otherwise the original instruction cycle is unchanged.
(3) (1)
:
(4)
Rev. 1.00
and (2)
: The flags may be affected by the execution status. If the Watchdog Timer is cleared by executing the
CLR WDT1 or CLR WDT2 instruction, the TO and PDF are cleared.
Otherwise the TO and PDF flags remain unchanged.
32
December 19, 2006
HT46R652
Instruction Definition
ADC A,[m]
Add data memory and carry to the accumulator
Description
The contents of the specified data memory, accumulator and the carry flag are added simultaneously, leaving the result in the accumulator.
Operation
ACC ¬ ACC+[m]+C
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
ADCM A,[m]
Add the accumulator and carry to data memory
Description
The contents of the specified data memory, accumulator and the carry flag are added simultaneously, leaving the result in the specified data memory.
Operation
[m] ¬ ACC+[m]+C
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
ADD A,[m]
Add data memory to the accumulator
Description
The contents of the specified data memory and the accumulator are added. The result is
stored in the accumulator.
Operation
ACC ¬ ACC+[m]
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
ADD A,x
Add immediate data to the accumulator
Description
The contents of the accumulator and the specified data are added, leaving the result in the
accumulator.
Operation
ACC ¬ ACC+x
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
ADDM A,[m]
Add the accumulator to the data memory
Description
The contents of the specified data memory and the accumulator are added. The result is
stored in the data memory.
Operation
[m] ¬ ACC+[m]
Affected flag(s)
Rev. 1.00
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
33
December 19, 2006
HT46R652
AND A,[m]
Logical AND accumulator with data memory
Description
Data in the accumulator and the specified data memory perform a bitwise logical_AND operation. The result is stored in the accumulator.
Operation
ACC ¬ ACC ²AND² [m]
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
AND A,x
Logical AND immediate data to the accumulator
Description
Data in the accumulator and the specified data perform a bitwise logical_AND operation.
The result is stored in the accumulator.
Operation
ACC ¬ ACC ²AND² x
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
ANDM A,[m]
Logical AND data memory with the accumulator
Description
Data in the specified data memory and the accumulator perform a bitwise logical_AND operation. The result is stored in the data memory.
Operation
[m] ¬ ACC ²AND² [m]
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
CALL addr
Subroutine call
Description
The instruction unconditionally calls a subroutine located at the indicated address. The
program counter increments once to obtain the address of the next instruction, and pushes
this onto the stack. The indicated address is then loaded. Program execution continues
with the instruction at this address.
Operation
Stack ¬ Program Counter+1
Program Counter ¬ addr
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
CLR [m]
Clear data memory
Description
The contents of the specified data memory are cleared to 0.
Operation
[m] ¬ 00H
Affected flag(s)
Rev. 1.00
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
34
December 19, 2006
HT46R652
CLR [m].i
Clear bit of data memory
Description
The bit i of the specified data memory is cleared to 0.
Operation
[m].i ¬ 0
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
CLR WDT
Clear Watchdog Timer
Description
The WDT is cleared (clears the WDT). The power down bit (PDF) and time-out bit (TO) are
cleared.
Operation
WDT ¬ 00H
PDF and TO ¬ 0
Affected flag(s)
TO
PDF
OV
Z
AC
C
0
0
¾
¾
¾
¾
CLR WDT1
Preclear Watchdog Timer
Description
Together with CLR WDT2, clears the WDT. PDF and TO are also cleared. Only execution
of this instruction without the other preclear instruction just sets the indicated flag which implies this instruction has been executed and the TO and PDF flags remain unchanged.
Operation
WDT ¬ 00H*
PDF and TO ¬ 0*
Affected flag(s)
TO
PDF
OV
Z
AC
C
0*
0*
¾
¾
¾
¾
CLR WDT2
Preclear Watchdog Timer
Description
Together with CLR WDT1, clears the WDT. PDF and TO are also cleared. Only execution
of this instruction without the other preclear instruction, sets the indicated flag which implies this instruction has been executed and the TO and PDF flags remain unchanged.
Operation
WDT ¬ 00H*
PDF and TO ¬ 0*
Affected flag(s)
TO
PDF
OV
Z
AC
C
0*
0*
¾
¾
¾
¾
CPL [m]
Complement data memory
Description
Each bit of the specified data memory is logically complemented (1¢s complement). Bits
which previously contained a 1 are changed to 0 and vice-versa.
Operation
[m] ¬ [m]
Affected flag(s)
Rev. 1.00
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
35
December 19, 2006
HT46R652
CPLA [m]
Complement data memory and place result in the accumulator
Description
Each bit of the specified data memory is logically complemented (1¢s complement). Bits
which previously contained a 1 are changed to 0 and vice-versa. The complemented result
is stored in the accumulator and the contents of the data memory remain unchanged.
Operation
ACC ¬ [m]
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
DAA [m]
Decimal-Adjust accumulator for addition
Description
The accumulator value is adjusted to the BCD (Binary Coded Decimal) code. The accumulator is divided into two nibbles. Each nibble is adjusted to the BCD code and an internal
carry (AC1) will be done if the low nibble of the accumulator is greater than 9. The BCD adjustment is done by adding 6 to the original value if the original value is greater than 9 or a
carry (AC or C) is set; otherwise the original value remains unchanged. The result is stored
in the data memory and only the carry flag (C) may be affected.
Operation
If ACC.3~ACC.0 >9 or AC=1
then [m].3~[m].0 ¬ (ACC.3~ACC.0)+6, AC1=AC
else [m].3~[m].0 ¬ (ACC.3~ACC.0), AC1=0
and
If ACC.7~ACC.4+AC1 >9 or C=1
then [m].7~[m].4 ¬ ACC.7~ACC.4+6+AC1,C=1
else [m].7~[m].4 ¬ ACC.7~ACC.4+AC1,C=C
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
DEC [m]
Decrement data memory
Description
Data in the specified data memory is decremented by 1.
Operation
[m] ¬ [m]-1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
DECA [m]
Decrement data memory and place result in the accumulator
Description
Data in the specified data memory is decremented by 1, leaving the result in the accumulator. The contents of the data memory remain unchanged.
Operation
ACC ¬ [m]-1
Affected flag(s)
Rev. 1.00
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
36
December 19, 2006
HT46R652
HALT
Enter power down mode
Description
This instruction stops program execution and turns off the system clock. The contents of
the RAM and registers are retained. The WDT and prescaler are cleared. The power down
bit (PDF) is set and the WDT time-out bit (TO) is cleared.
Operation
Program Counter ¬ Program Counter+1
PDF ¬ 1
TO ¬ 0
Affected flag(s)
TO
PDF
OV
Z
AC
C
0
1
¾
¾
¾
¾
INC [m]
Increment data memory
Description
Data in the specified data memory is incremented by 1
Operation
[m] ¬ [m]+1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
INCA [m]
Increment data memory and place result in the accumulator
Description
Data in the specified data memory is incremented by 1, leaving the result in the accumulator. The contents of the data memory remain unchanged.
Operation
ACC ¬ [m]+1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
JMP addr
Directly jump
Description
The program counter are replaced with the directly-specified address unconditionally, and
control is passed to this destination.
Operation
Program Counter ¬addr
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
MOV A,[m]
Move data memory to the accumulator
Description
The contents of the specified data memory are copied to the accumulator.
Operation
ACC ¬ [m]
Affected flag(s)
Rev. 1.00
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
37
December 19, 2006
HT46R652
MOV A,x
Move immediate data to the accumulator
Description
The 8-bit data specified by the code is loaded into the accumulator.
Operation
ACC ¬ x
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
MOV [m],A
Move the accumulator to data memory
Description
The contents of the accumulator are copied to the specified data memory (one of the data
memories).
Operation
[m] ¬ACC
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
NOP
No operation
Description
No operation is performed. Execution continues with the next instruction.
Operation
Program Counter ¬ Program Counter+1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
OR A,[m]
Logical OR accumulator with data memory
Description
Data in the accumulator and the specified data memory (one of the data memories) perform a bitwise logical_OR operation. The result is stored in the accumulator.
Operation
ACC ¬ ACC ²OR² [m]
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
OR A,x
Logical OR immediate data to the accumulator
Description
Data in the accumulator and the specified data perform a bitwise logical_OR operation.
The result is stored in the accumulator.
Operation
ACC ¬ ACC ²OR² x
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
ORM A,[m]
Logical OR data memory with the accumulator
Description
Data in the data memory (one of the data memories) and the accumulator perform a
bitwise logical_OR operation. The result is stored in the data memory.
Operation
[m] ¬ACC ²OR² [m]
Affected flag(s)
Rev. 1.00
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
38
December 19, 2006
HT46R652
RET
Return from subroutine
Description
The program counter is restored from the stack. This is a 2-cycle instruction.
Operation
Program Counter ¬ Stack
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
RET A,x
Return and place immediate data in the accumulator
Description
The program counter is restored from the stack and the accumulator loaded with the specified 8-bit immediate data.
Operation
Program Counter ¬ Stack
ACC ¬ x
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
RETI
Return from interrupt
Description
The program counter is restored from the stack, and interrupts are enabled by setting the
EMI bit. EMI is the enable master (global) interrupt bit.
Operation
Program Counter ¬ Stack
EMI ¬ 1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
RL [m]
Rotate data memory left
Description
The contents of the specified data memory are rotated 1 bit left with bit 7 rotated into bit 0.
Operation
[m].(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6)
[m].0 ¬ [m].7
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
RLA [m]
Rotate data memory left and place result in the accumulator
Description
Data in the specified data memory is rotated 1 bit left with bit 7 rotated into bit 0, leaving the
rotated result in the accumulator. The contents of the data memory remain unchanged.
Operation
ACC.(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6)
ACC.0 ¬ [m].7
Affected flag(s)
Rev. 1.00
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
39
December 19, 2006
HT46R652
RLC [m]
Rotate data memory left through carry
Description
The contents of the specified data memory and the carry flag are rotated 1 bit left. Bit 7 replaces the carry bit; the original carry flag is rotated into the bit 0 position.
Operation
[m].(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6)
[m].0 ¬ C
C ¬ [m].7
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
RLCA [m]
Rotate left through carry and place result in the accumulator
Description
Data in the specified data memory and the carry flag are rotated 1 bit left. Bit 7 replaces the
carry bit and the original carry flag is rotated into bit 0 position. The rotated result is stored
in the accumulator but the contents of the data memory remain unchanged.
Operation
ACC.(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6)
ACC.0 ¬ C
C ¬ [m].7
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
RR [m]
Rotate data memory right
Description
The contents of the specified data memory are rotated 1 bit right with bit 0 rotated to bit 7.
Operation
[m].i ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6)
[m].7 ¬ [m].0
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
RRA [m]
Rotate right and place result in the accumulator
Description
Data in the specified data memory is rotated 1 bit right with bit 0 rotated into bit 7, leaving
the rotated result in the accumulator. The contents of the data memory remain unchanged.
Operation
ACC.(i) ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6)
ACC.7 ¬ [m].0
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
RRC [m]
Rotate data memory right through carry
Description
The contents of the specified data memory and the carry flag are together rotated 1 bit
right. Bit 0 replaces the carry bit; the original carry flag is rotated into the bit 7 position.
Operation
[m].i ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6)
[m].7 ¬ C
C ¬ [m].0
Affected flag(s)
Rev. 1.00
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
40
December 19, 2006
HT46R652
RRCA [m]
Rotate right through carry and place result in the accumulator
Description
Data of the specified data memory and the carry flag are rotated 1 bit right. Bit 0 replaces
the carry bit and the original carry flag is rotated into the bit 7 position. The rotated result is
stored in the accumulator. The contents of the data memory remain unchanged.
Operation
ACC.i ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6)
ACC.7 ¬ C
C ¬ [m].0
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
SBC A,[m]
Subtract data memory and carry from the accumulator
Description
The contents of the specified data memory and the complement of the carry flag are subtracted from the accumulator, leaving the result in the accumulator.
Operation
ACC ¬ ACC+[m]+C
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
SBCM A,[m]
Subtract data memory and carry from the accumulator
Description
The contents of the specified data memory and the complement of the carry flag are subtracted from the accumulator, leaving the result in the data memory.
Operation
[m] ¬ ACC+[m]+C
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
SDZ [m]
Skip if decrement data memory is 0
Description
The contents of the specified data memory are decremented by 1. If the result is 0, the next
instruction is skipped. If the result is 0, the following instruction, fetched during the current
instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle).
Operation
Skip if ([m]-1)=0, [m] ¬ ([m]-1)
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SDZA [m]
Decrement data memory and place result in ACC, skip if 0
Description
The contents of the specified data memory are decremented by 1. If the result is 0, the next
instruction is skipped. The result is stored in the accumulator but the data memory remains
unchanged. If the result is 0, the following instruction, fetched during the current instruction
execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle).
Operation
Skip if ([m]-1)=0, ACC ¬ ([m]-1)
Affected flag(s)
Rev. 1.00
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
41
December 19, 2006
HT46R652
SET [m]
Set data memory
Description
Each bit of the specified data memory is set to 1.
Operation
[m] ¬ FFH
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SET [m]. i
Set bit of data memory
Description
Bit i of the specified data memory is set to 1.
Operation
[m].i ¬ 1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SIZ [m]
Skip if increment data memory is 0
Description
The contents of the specified data memory are incremented by 1. If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a
dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with
the next instruction (1 cycle).
Operation
Skip if ([m]+1)=0, [m] ¬ ([m]+1)
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SIZA [m]
Increment data memory and place result in ACC, skip if 0
Description
The contents of the specified data memory are incremented by 1. If the result is 0, the next
instruction is skipped and the result is stored in the accumulator. The data memory remains unchanged. If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper
instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle).
Operation
Skip if ([m]+1)=0, ACC ¬ ([m]+1)
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SNZ [m].i
Skip if bit i of the data memory is not 0
Description
If bit i of the specified data memory is not 0, the next instruction is skipped. If bit i of the data
memory is not 0, the following instruction, fetched during the current instruction execution,
is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle).
Operation
Skip if [m].i¹0
Affected flag(s)
Rev. 1.00
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
42
December 19, 2006
HT46R652
SUB A,[m]
Subtract data memory from the accumulator
Description
The specified data memory is subtracted from the contents of the accumulator, leaving the
result in the accumulator.
Operation
ACC ¬ ACC+[m]+1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
SUBM A,[m]
Subtract data memory from the accumulator
Description
The specified data memory is subtracted from the contents of the accumulator, leaving the
result in the data memory.
Operation
[m] ¬ ACC+[m]+1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
SUB A,x
Subtract immediate data from the accumulator
Description
The immediate data specified by the code is subtracted from the contents of the accumulator, leaving the result in the accumulator.
Operation
ACC ¬ ACC+x+1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
SWAP [m]
Swap nibbles within the data memory
Description
The low-order and high-order nibbles of the specified data memory (1 of the data memories) are interchanged.
Operation
[m].3~[m].0 « [m].7~[m].4
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SWAPA [m]
Swap data memory and place result in the accumulator
Description
The low-order and high-order nibbles of the specified data memory are interchanged, writing the result to the accumulator. The contents of the data memory remain unchanged.
Operation
ACC.3~ACC.0 ¬ [m].7~[m].4
ACC.7~ACC.4 ¬ [m].3~[m].0
Affected flag(s)
Rev. 1.00
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
43
December 19, 2006
HT46R652
SZ [m]
Skip if data memory is 0
Description
If the contents of the specified data memory are 0, the following instruction, fetched during
the current instruction execution, is discarded and a dummy cycle is replaced to get the
proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle).
Operation
Skip if [m]=0
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SZA [m]
Move data memory to ACC, skip if 0
Description
The contents of the specified data memory are copied to the accumulator. If the contents is
0, the following instruction, fetched during the current instruction execution, is discarded
and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed
with the next instruction (1 cycle).
Operation
Skip if [m]=0
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SZ [m].i
Skip if bit i of the data memory is 0
Description
If bit i of the specified data memory is 0, the following instruction, fetched during the current
instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle).
Operation
Skip if [m].i=0
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
TABRDC [m]
Move the ROM code (current page) to TBLH and data memory
Description
The low byte of ROM code (current page) addressed by the table pointer (TBLP) is moved
to the specified data memory and the high byte transferred to TBLH directly.
Operation
[m] ¬ ROM code (low byte)
TBLH ¬ ROM code (high byte)
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
TABRDL [m]
Move the ROM code (last page) to TBLH and data memory
Description
The low byte of ROM code (last page) addressed by the table pointer (TBLP) is moved to
the data memory and the high byte transferred to TBLH directly.
Operation
[m] ¬ ROM code (low byte)
TBLH ¬ ROM code (high byte)
Affected flag(s)
Rev. 1.00
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
44
December 19, 2006
HT46R652
XOR A,[m]
Logical XOR accumulator with data memory
Description
Data in the accumulator and the indicated data memory perform a bitwise logical Exclusive_OR operation and the result is stored in the accumulator.
Operation
ACC ¬ ACC ²XOR² [m]
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
XORM A,[m]
Logical XOR data memory with the accumulator
Description
Data in the indicated data memory and the accumulator perform a bitwise logical Exclusive_OR operation. The result is stored in the data memory. The 0 flag is affected.
Operation
[m] ¬ ACC ²XOR² [m]
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
XOR A,x
Logical XOR immediate data to the accumulator
Description
Data in the accumulator and the specified data perform a bitwise logical Exclusive_OR operation. The result is stored in the accumulator. The 0 flag is affected.
Operation
ACC ¬ ACC ²XOR² x
Affected flag(s)
Rev. 1.00
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
45
December 19, 2006
HT46R652
Package Information
100-pin QFP (14´20) Outline Dimensions
C
H
D
8 0
G
5 1
I
5 0
8 1
F
A
B
E
3 1
1 0 0
K
a
J
1
Symbol
Rev. 1.00
3 0
Dimensions in mm
Min.
Nom.
Max.
A
18.50
¾
19.20
B
13.90
¾
14.10
C
24.50
¾
25.20
D
19.90
¾
20.10
E
¾
0.65
¾
F
¾
0.30
¾
G
2.50
¾
3.10
H
¾
¾
3.40
I
¾
0.10
¾
J
1
¾
1.40
K
0.10
¾
0.20
a
0°
¾
7°
46
December 19, 2006
HT46R652
Holtek Semiconductor Inc. (Headquarters)
No.3, Creation Rd. II, Science Park, Hsinchu, Taiwan
Tel: 886-3-563-1999
Fax: 886-3-563-1189
http://www.holtek.com.tw
Holtek Semiconductor Inc. (Taipei Sales Office)
4F-2, No. 3-2, YuanQu St., Nankang Software Park, Taipei 115, Taiwan
Tel: 886-2-2655-7070
Fax: 886-2-2655-7373
Fax: 886-2-2655-7383 (International sales hotline)
Holtek Semiconductor Inc. (Shanghai Sales Office)
7th Floor, Building 2, No.889, Yi Shan Rd., Shanghai, China 200233
Tel: 86-21-6485-5560
Fax: 86-21-6485-0313
http://www.holtek.com.cn
Holtek Semiconductor Inc. (Shenzhen Sales Office)
5/F, Unit A, Productivity Building, Cross of Science M 3rd Road and Gaoxin M 2nd Road, Science Park, Nanshan District,
Shenzhen, China 518057
Tel: 86-755-8616-9908, 86-755-8616-9308
Fax: 86-755-8616-9533
Holtek Semiconductor Inc. (Beijing Sales Office)
Suite 1721, Jinyu Tower, A129 West Xuan Wu Men Street, Xicheng District, Beijing, China 100031
Tel: 86-10-6641-0030, 86-10-6641-7751, 86-10-6641-7752
Fax: 86-10-6641-0125
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709, Building 3, Champagne Plaza, No.97 Dongda Street, Chengdu, Sichuan, China 610016
Tel: 86-28-6653-6590
Fax: 86-28-6653-6591
Holmate Semiconductor, Inc. (North America Sales Office)
46729 Fremont Blvd., Fremont, CA 94538
Tel: 1-510-252-9880
Fax: 1-510-252-9885
http://www.holmate.com
Copyright Ó 2006 by HOLTEK SEMICONDUCTOR INC.
The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used
solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable
without further modification, nor recommends the use of its products for application that may present a risk to human life
due to malfunction or otherwise. Holtek¢s products are not authorized for use as critical components in life support devices
or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information,
please visit our web site at http://www.holtek.com.tw.
Rev. 1.00
47
December 19, 2006