HT46RU22 A/D Type 8-Bit MCU Technical Document · Tools Information · FAQs · Application Note - HA0004E HT48 & HT46 MCU UART Software Implementation Method - HA0005E Controlling the I2C bus with the HT48 & HT46 MCU Series - HA0013E HT48 & HT46 LCM Interface Design - HA0047E An PWM application example using the HT46 series of MCUs Features · Operating voltage: · Up to 0.5ms instruction cycle with 8MHz system clock fSYS=4MHz: 2.2V~5.5V fSYS=8MHz: 3.3V~5.5V at VDD=5V · 6-level subroutine nesting · 19 bidirectional I/O lines (max.) · 8 channels 9-bit resolution A/D converter · 1 interrupt input shared with an I/O line · 1-channel 8-bit PWM output shared with one I/O line · 8-bit programmable timer/event counter with · Universal Asynchronous Receiver Transmitter overflow interrupt and 7-stage prescaler (UART) · On-chip crystal and RC oscillator · Bit manipulation instruction · Watchdog Timer · 14-bit table read instruction · 2048´14 program memory · 63 powerful instructions · 64´8 data memory RAM · All instructions in one or two machine cycles · Supports PFD for sound generation · Low voltage reset function · HALT function and wake-up feature reduce power · I2C Bus (slave mode) consumption · 24-pin SKDIP/SOP/SSOP package General Description Width Modulation function, UART function, I2C interface, HALT and wake-up functions, enhance the versatility of these devices to suit a wide range of A/D application possibilities such as sensor signal processing, motor driving, industrial control, consumer products, subsystem controllers, etc. The HT46RU22 are 8-bit, high performance, RISC architecture microcontroller devices specifically designed for A/D applications that interface directly to analog signals, such as those from sensors. The advantages of low power consumption, I/O flexibility, programmable frequency divider, timer functions, oscillator options, multi-channel A/D Converter, Pulse I2C is a trademark of Philips Semiconductors Rev. 1.20 1 March 23, 2007 HT46RU22 Block Diagram P A 5 /IN T In te rru p t C ir c u it S T A C K P ro g ra m R O M P ro g ra m C o u n te r M T M R C T M R IN T C P A 3 /P F D U P r e s c a le r M M P U W D T P r e s c a le r D A T A M e m o ry X P A 4 U X P o rt D O S C P D 0 /P W M M U X In s tr u c tio n D e c o d e r 8 -C h a n n e l A /D C o n v e rte r S T A T U S A L U P B C S h ifte r T im in g G e n e ra to r P A 3 , P A 5 S S C 1 A C C P o rt B P B P A C O S R E V D V S W D T /4 R C P D O S C 2 Y S M P W M P D C Y S P A 4 /T M R X fS In s tr u c tio n R e g is te r fS P o rt A P A L V R I2 C B u s S la v e M o d e D P C P C C P o rt C P B 0 /A N 0 ~ P B 7 /A N 7 P A P A P A P A P A P A 0 ~ P 3 /P 4 /T 5 /IN 6 /S 7 /S A 2 F D M R T D A C L P C 0 /T X , P C 1 /R X Pin Assignment P B 5 /A N 5 1 2 4 P B 6 /A N 6 P B 4 /A N 4 2 2 3 P B 7 /A N 7 P A 3 /P F D 3 2 2 P A 4 /T M R P A 2 4 2 1 P A 5 /IN T P A 1 5 2 0 P A 6 /S D A P A 0 6 1 9 P A 7 /S C L P B 3 /A N 3 7 1 8 O S C 2 P B 2 /A N 2 8 1 7 O S C 1 P B 1 /A N 1 9 1 6 V D D P B 0 /A N 0 1 0 1 5 R E S V S S 1 1 1 4 P D 0 /P W M P C 0 /T X 1 2 1 3 P C 1 /R X H T 4 6 R U 2 2 2 4 S K D IP -A /S O P -A /S S O P -A Rev. 1.20 2 March 23, 2007 HT46RU22 Pad Description Pad Name I/O Options Description I/O Pull-high Wake-up PA3 or PFD I/O or Serial Bus Bidirectional 8-bit input/output port. Each bit can be configured as wake-up input by options. Software instructions determine the CMOS output or Schmitt trigger input with or without pull-high resistor (determined by pull-high options: bit option). The PFD, TMR and INT are pin-shared with PA3, PA4 and PA5, respectively. Once the I2C Bus function is used, the internal registers related to PA6 and PA7 can not be used. Pull-high Bidirectional 8-bit input/output port. Software instructions determine the CMOS output, Schmitt trigger input with or without pull-high resistor (determined by pull-high option: port option) or A/D input. Once a PB line is selected as an A/D input (by using software control), the I/O function and pull-high resistor are disabled automatically. I/O Pull-high Bidirectional 2-bit input/output port. Software instructions determine the CMOS output, Schmitt trigger input with or without pull-high resistor (determine by pull-high option: bit option). TX and RX are pin-shared with PC0 and PC1, once the UART Bus function is used, the internal registers related to PC0 and PC1 can not be used. Software instructions determine the UART function to be used. PD0/PWM I/O Pull-high I/O or PWM Bidirectional 1-bit input/output port. Software instructions determine the CMOS output, Schmitt trigger input with or without a pull-high resistor (determined by pull-high option: port option). The PWM output function is pin-shared with PD0 (dependent on PWM options). OSC1 OSC2 I O Crystal or RC OSC1, OSC2 are connected to an RC network or a Crystal (determined by options) for the internal system clock. In the case of RC operation, OSC2 is the output terminal for 1/4 system clock. RES I ¾ Schmitt trigger reset input. Active low. VSS ¾ ¾ Negative power supply, ground. VDD ¾ ¾ Positive power supply I ¾ TEST mode input pin It disconnects in normal operation PA0~PA2 PA3/PFD PA4/TMR PA5/INT PA6/SDA PA7/SCL PB0/AN0 PB1/AN1 PB2/AN2 PB3/AN3 PB4/AN4 PB5/AN5 PB6/AN6 PB7/AN7 PC0/TX PC1/RX TEST1 TEST2 TEST3 I/O Absolute Maximum Ratings Supply Voltage ...........................VSS-0.3V to VSS+6.0V Storage Temperature ............................-50°C to 125°C Input Voltage..............................VSS-0.3V to VDD+0.3V IOL Total ..............................................................150mA Total Power Dissipation .....................................500mW Operating Temperature...........................-40°C to 85°C IOH Total............................................................-100mA Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maximum Ratings² may cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability. Rev. 1.20 3 March 23, 2007 HT46RU22 D.C. Characteristics Symbol VDD IDD1 IDD2 IDD3 Parameter Ta=25°C Test Conditions Conditions VDD Min. Typ. Max. Unit ¾ fSYS=4MHz 2.2 ¾ 5.5 V ¾ fSYS=8MHz 3.3 ¾ 5.5 V Operating Current (Crystal OSC) 3V No load, fSYS=4MHz ADC Off, UART Off ¾ 0.6 1.5 mA ¾ 2 4 mA Operating Current (RC OSC) 3V ¾ 0.8 1.5 mA ¾ 2.5 4 mA Operating Current (Crystal OSC, RC OSC) 3V ¾ 1 2 mA ¾ 3 6 mA Operating Voltage 5V 5V 5V No load, fSYS=4MHz ADC Off, UART Off No load, fSYS=4MHz, ADC Off, UART On IDD4 Operating Current (Crystal OSC, RC OSC) 5V No load, fSYS=8MHz, ADC Off, UART Off ¾ 4 8 mA IDD5 Operating Current (Crystal OSC, RC OSC) 5V No load, fSYS=8MHz, ADC Off, UART On ¾ 5 10 mA ISTB1 Standby Current (WDT Enabled) 3V ¾ ¾ 5 mA ¾ ¾ 10 mA Standby Current (WDT Disabled) 3V ¾ ¾ 1 mA ¾ ¾ 2 mA VIL1 Input Low Voltage for I/O Ports, TMR and INT ¾ ¾ 0 ¾ 0.3VDD V VIH1 Input High Voltage for I/O Ports, TMR and INT ¾ ¾ 0.7VDD ¾ VDD V VIL2 Input Low Voltage (RES) ¾ ¾ 0 ¾ 0.4VDD V VIH2 Input High Voltage (RES) ¾ ¾ 0.9VDD ¾ VDD V VLVR Low Voltage Reset ¾ ¾ 2.7 3 3.3 V IOL I/O Port Sink Current ISTB2 IOH RPH No load, system HALT 5V No load, system HALT 5V 3V VOL=0.1VDD 4 8 ¾ mA 5V VOL=0.1VDD 10 20 ¾ mA 3V VOH=0.9VDD -2 -4 ¾ mA 5V VOH=0.9VDD -5 -10 ¾ mA 3V ¾ 20 60 100 kW 5V ¾ 10 30 50 kW I/O Port Source Current Pull-high Resistance VAD A/D Input Voltage ¾ ¾ 0 ¾ VDD V EAD A/D Conversion Error ¾ ¾ ¾ ±0.5 ±1 LSB IADC Additional Power Consumption if A/D Converter is Used 3V ¾ 0.5 1 mA ¾ 1.5 3 mA Rev. 1.20 ¾ 5V 4 March 23, 2007 HT46RU22 A.C. Characteristics Ta=25°C Test Conditions Symbol Parameter fSYS fTIMER tWDTOSC System Clock (Crystal OSC, RC OSC) Timer I/P Frequency (TMR) Min. Typ. Max. Unit Conditions VDD ¾ 2.2V~5.5V 400 ¾ 4000 kHz ¾ 3.3V~5.5V 400 ¾ 8000 kHz ¾ 2.2V~5.5V 0 ¾ 4000 kHz ¾ 3.3V~5.5V 0 ¾ 8000 kHz 3V ¾ 45 90 180 ms 5V ¾ 32 65 130 ms ¾ 1 ¾ ¾ ms ¾ 1024 ¾ *tSYS Watchdog Oscillator Period tRES External Reset Low Pulse Width ¾ tSST System Start-up Timer Period ¾ tLVR Low Voltage Width to Reset ¾ ¾ 0.25 1 2 ms tINT Interrupt Pulse Width ¾ ¾ 1 ¾ ¾ ms tAD A/D Clock Period ¾ ¾ 1 ¾ ¾ ms tADC A/D Conversion Time ¾ ¾ ¾ 76 ¾ tAD tADCS A/D Sampling Time ¾ ¾ ¾ 32 ¾ tAD tIIC I2C Bus Clock Period ¾ Connect to external pull-high resistor 2kW 64 ¾ ¾ *tSYS Wake-up from HALT Note: *tSYS=1/fSYS Rev. 1.20 5 March 23, 2007 HT46RU22 Functional Description Execution Flow cremented by 1. The program counter then points to the memory word containing the next instruction code. The system clock for the microcontroller is derived from either a crystal or an RC oscillator. The system clock is internally divided into four non-overlapping clocks. One instruction cycle consists of four system clock cycles. When executing a jump instruction, conditional skip execution, loading PCL register, subroutine call, initial reset, internal interrupt, external interrupt or return from subroutine, the PC manipulates the program transfer by loading the address corresponding to each instruction. Instruction fetching and execution are pipelined in such a way that a fetch takes an instruction cycle while decoding and execution takes the next instruction cycle. However, the pipelining scheme causes each instruction to effectively execute in a cycle. If an instruction changes the program counter, two cycles are required to complete the instruction. The conditional skip is activated by instructions. Once the condition is met, the next instruction, fetched during the current instruction execution, is discarded and a dummy cycle replaces it to get the proper instruction. Otherwise proceed with the next instruction. The lower byte of the program counter (PCL) is a readable and writeable register (06H). Moving data into the PCL performs a short jump. The destination will be within 256 locations. Program Counter - PC The program counter (PC) controls the sequence in which the instructions stored in program ROM are executed and its contents specify full range of program memory. When a control transfer takes place, an additional dummy cycle is required. After accessing a program memory word to fetch an instruction code, the contents of the program counter are in- S y s te m C lo c k T 1 T 2 T 3 T 4 T 1 T 2 T 3 T 4 T 1 T 2 T 3 T 4 O S C 2 ( R C o n ly ) P C P C P C + 1 F e tc h IN S T (P C ) E x e c u te IN S T (P C -1 ) P C + 2 F e tc h IN S T (P C + 1 ) E x e c u te IN S T (P C ) F e tc h IN S T (P C + 2 ) E x e c u te IN S T (P C + 1 ) Execution Flow Mode Program Counter *10 *9 *8 *7 *6 *5 *4 *3 *2 *1 *0 Initial Reset 0 0 0 0 0 0 0 0 0 0 0 External Interrupt 0 0 0 0 0 0 0 0 1 0 0 Timer/Event Counter Overflow 0 0 0 0 0 0 0 1 0 0 0 A/D Converter Interrupt 0 0 0 0 0 0 0 1 1 0 0 I2C Bus Interrupt 0 0 0 0 0 0 1 0 0 0 0 UART Interrupt 0 0 0 0 0 0 1 0 1 0 0 @3 @2 @1 @0 Skip Program Counter + 2 Loading PCL *10 *9 *8 @7 @6 @5 @4 Jump, Call Branch #10 #9 #8 #7 #6 #5 #4 #3 #2 #1 #0 Return from Subroutine S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 S0 Program Counter Note: *10~*0: Program counter bits #10~#0: Instruction code bits Rev. 1.20 S10~S0: Stack register bits @7~@0: PCL bits 6 March 23, 2007 HT46RU22 Program Memory - ROM current page, 1 page=256 words) and ²TABRDL [m]² (the last page) transfer the contents of the lower-order byte to the specified data memory, and the higher-order byte to TBLH (08H). Only the destination of the lower-order byte in the table is well-defined, the other bits of the table word are transferred to the lower portion of TBLH, and the remaining 2 bit is read as ²0². The Table Higher-order byte register (TBLH) is read only. The table pointer (TBLP) is a read/write register (07H), which indicates the table location. Before accessing the table, the location must be placed in TBLP. The TBLH is read only and cannot be restored. If the main routine and the ISR (Interrupt Service Routine) both employ the table read instruction, the contents of the TBLH in the main routine are likely to be changed by the table read instruction used in the ISR. Errors can occur. In other words, using the table read instruction in the main routine and the ISR simultaneously should be avoided. However, if the table read instruction has to be applied in both the main routine and the ISR, the interrupt is supposed to be disabled prior to the table read instruction. It will not be enabled until the TBLH has been backed up. All table related instructions require two cycles to complete the operation. These areas may function as normal program memory depending upon the requirements. The program memory is used to store the program instructions which are to be executed. It also contains data, table, and interrupt entries, and is organized into 2048´14 bits, addressed by the program counter and table pointer. Certain locations in the program memory are reserved for special usage: · Location 000H This area is reserved for program initialization. After chip reset, the program always begins execution at location 000H. · Location 004H This area is reserved for the external interrupt service program. If the INT input pin is activated, the interrupt is enabled and the stack is not full, the program begins execution at location 004H. · Location 008H This area is reserved for the timer/event counter interrupt service program. If a timer interrupt results from a timer/event counter overflow, and if the interrupt is enabled and the stack is not full, the program begins execution at location 008H. · Location 00CH 0 0 0 H This area is reserved for the A/D converter interrupt service program. If an A/D converter interrupt results from an end of A/D conversion, and if the interrupt is enabled and the stack is not full, the program begins execution at location 00CH. D e v ic e In itia liz a tio n P r o g r a m 0 0 4 H 0 0 8 H 0 0 C H E x te r n a l In te r r u p t S u b r o u tin e T im e r /E v e n t C o u n te r In te r r u p t S u b r o u tin e A /D 0 1 0 H · Location 010H This area is reserved for the I2C Bus interrupt service program. If the I2C Bus interrupt resulting from a slave address is match or completed 1 byte of data transfer, and if the interrupt is enable and the stack is not full, the program begins execution at location 010H. 0 1 4 H C o n v e r te r In te r r u p t S u b r o u tin e I C 2 B u s In te r r u p t S u b r o u tin e P ro g ra m M e m o ry U A R T B u s In te r r u p t S u b r o u tin e n 0 0 H L o o k - u p T a b le ( 2 5 6 w o r d s ) n F F H · Location 014H This area is reserved for the UART interrupt service program. If the UART interrupt resulting from transmission/reception is completed, and if the interrupt is enable and the stack is not full, the program begins execution at location 014H. 7 0 0 H L o o k - u p T a b le ( 2 5 6 w o r d s ) 7 F F H 1 4 b its N o te : n ra n g e s fro m 0 to 7 Program Memory · Table location Any location in the ROM space can be used as look-up tables. The instructions ²TABRDC [m]² (the Table Location Instruction *10 *9 *8 *7 *6 *5 *4 *3 *2 *1 *0 TABRDC [m] P10 P9 P8 @7 @6 @5 @4 @3 @2 @1 @0 TABRDL [m] 1 1 1 @7 @6 @5 @4 @3 @2 @1 @0 Table Location Note: *10~*0: Table location bits @7~@0: Table pointer bits Rev. 1.20 P10~P8: Current program counter bits 7 March 23, 2007 HT46RU22 Stack Register - STACK Accumulator This is a special part of the memory which is used to save the contents of the program counter (PC) only. The stack is organized into 6 levels and is neither part of the data nor part of the program space, and is neither readable nor writeable. The activated level is indexed by the stack pointer (SP) and is neither readable nor writeable. At a subroutine call or interrupt acknowledgment, the contents of the program counter are pushed onto the stack. At the end of a subroutine or an interrupt routine, signaled by a return instruction (RET or RETI), the program counter is restored to its previous value from the stack. After a chip reset, the SP will point to the top of the stack. The accumulator is closely related to ALU operations. It is also mapped to location 05H of the data memory and can carry out immediate data operations. The data movement between two data memory locations must pass through the accumulator. 0 0 H In d ir e c t A d d r e s s in g R e g is te r 0 1 H M P 0 2 H 0 3 H 0 4 H 0 5 H If the stack is full and a non-masked interrupt takes place, the interrupt request flag will be recorded but the acknowledgment will be inhibited. When the stack pointer is decremented (by RET or RETI), the interrupt will be serviced. This feature prevents stack overflow allowing the programmer to use the structure more easily. In a similar case, if the stack is full and a ²CALL² is subsequently executed, stack overflow occurs and the first entry will be lost (only the most recent 6 return addresses are stored). A C C 0 6 H P C L 0 7 H T B L P 0 8 H T B L H 0 9 H 0 A H S T A T U S 0 B H IN T C 0 0 C H 0 D H T M R 0 E H T M R C 0 F H 1 0 H 1 1 H 1 2 H P A 1 3 H P A C 1 4 H P B Data Memory - RAM 1 5 H P B C 1 6 H P C The data memory is designed with 92´8 bits. The data memory is divided into two functional groups: special function registers and general purpose data memory (64´8). Most are read/write, but some are read only. 1 7 H P C C The remaining space before the 40H is reserved for future expanded usage and reading these locations will get ²00H². The general purpose data memory, addressed from 40H to 7FH, is used for data and control information under instruction commands. All of the data memory areas can handle arithmetic, logic, increment, decrement and rotate operations directly. Except for some dedicated bits, each bit in the data memory can be set and reset by ²SET [m].i² and ²CLR [m].i². They are also indirectly accessible through memory pointer register (MP;01H). 1 C H 1 8 H P D 1 9 H P D C 1 A H P W M S p e c ia l P u r p o s e D a ta M e m o ry 1 B H 1 D H 1 E H IN T C 1 1 F H 2 0 H H A D R 2 1 H H C R 2 2 H H S R 2 3 H H D R 2 4 H A D R L 2 5 H A D R H 2 6 H A D C R 2 7 H A C S R 2 8 H Indirect Addressing Register 2 9 H Location 00H is an indirect addressing register that is not physically implemented. Any read/write operation of [00H] accesses data memory pointed to by MP (01H). Reading location 00H itself indirectly will return the result 00H. Writing indirectly results in no operation. The memory pointer register MP (01H) is a 7-bit register. The bit 7 of MP is undefined and reading will return the result ²1². Any writing operation to MP will only transfer the lower 7-bit data to MP. 2 A H U S R 2 B H U C R 1 2 C H U C R 2 2 D H T X R /R X R 2 E H 3 0 H B R G 3 F H 4 0 H 7 F H G e n e ra l P u rp o s e D a ta M e m o ry (6 4 B y te s ) : U n u s e d R e a d a s "0 0 " RAM Mapping Rev. 1.20 8 March 23, 2007 HT46RU22 Arithmetic and Logic Unit - ALU pushed onto the stack automatically. If the contents of the status are important and if the subroutine can corrupt the status register, precautions must be taken to save it properly. This circuit performs 8-bit arithmetic and logic operations. The ALU provides the following functions: · Arithmetic operations (ADD, ADC, SUB, SBC, DAA) · Logic operations (AND, OR, XOR, CPL) Interrupt · Rotation (RL, RR, RLC, RRC) The device provides an external interrupt, an internal timer/event counter interrupt, the A/D converter interrupt, the I2C Bus interrupts and an UART interrupt. The interrupt control register 0 (INTC0;0BH) and interrupt control register 1 (INTC1;1EH) contains the interrupt control bits to set the enable or disable and the interrupt request flags. · Increment and Decrement (INC, DEC) · Branch decision (SZ, SNZ, SIZ, SDZ ....) The ALU not only saves the results of a data operation but also changes the status register. Status Register - STATUS Once an interrupt subroutine is serviced, all the other interrupts will be blocked (by clearing the EMI bit). This scheme may prevent any further interrupt nesting. Other interrupt requests may happen during this interval but only the interrupt request flag is recorded. If a certain interrupt requires servicing within the service routine, the EMI bit and the corresponding bit of INTC0 and INTC1 may be set to allow interrupt nesting. If the stack is full, the interrupt request will not be acknowledged, even if the related interrupt is enabled, until the SP is decremented. If immediate service is desired, the stack must be prevented from becoming full. This 8-bit register (0AH) contains the 0 flag (Z), carry flag (C), auxiliary carry flag (AC), overflow flag (OV), power down flag (PDF), and watchdog time-out flag (TO). It also records the status information and controls the operation sequence. With the exception of the TO and PDF flags, bits in the status register can be altered by instructions like most other registers. Any data written into the status register will not change the TO or PDF flag. In addition operations related to the status register may give different results from those intended. The TO flag can be affected only by system power-up, a WDT time-out or executing the ²CLR WDT² or ²HALT² instruction. The PDF flag can be affected only by executing the ²HALT² or ²CLR WDT² instruction or a system power-up. All these kinds of interrupts have a wake-up capability. As an interrupt is serviced, a control transfer occurs by pushing the program counter onto the stack, followed by a branch to a subroutine at specified location in the program memory. Only the program counter is pushed onto the stack. If the contents of the register or status register (STATUS) are altered by the interrupt service program which corrupts the desired control sequence, the contents should be saved in advance. The Z, OV, AC and C flags generally reflect the status of the latest operations. In addition, on entering the interrupt sequence or executing the subroutine call, the status register will not be Bit No. Label Function 0 C C is set if the operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation; otherwise C is cleared. C is also affected by a rotate through carry instruction. 1 AC AC is set if the operation results in a carry out of the low nibbles in addition or no borrow from the high nibble into the low nibble in subtraction; otherwise AC is cleared. 2 Z 3 OV OV is set if the operation results in a carry into the highest-order bit but not a carry out of the highest-order bit, or vice versa; otherwise OV is cleared. 4 PDF PDF is cleared by system power-up or executing the ²CLR WDT² instruction. PDF is set by executing the ²HALT² instruction. 5 TO TO is cleared by system power-up or executing the ²CLR WDT² or ²HALT² instruction. TO is set by a WDT time-out. 6, 7 ¾ Unused bit, read as ²0² Z is set if the result of an arithmetic or logic operation is 0; otherwise Z is cleared. Status (0AH) Register Rev. 1.20 9 March 23, 2007 HT46RU22 The I2C Bus interrupt is initialized by setting the I2C Bus interrupt request flag (HIF; bit 4 of INTC1), caused by a slave address match (HAAS=²1²) or 1 byte of data transfer is completed. When the interrupt is enabled, the stack is not full and the HIF bit is set, a subroutine call to location 10H will occur. The related interrupt request flag (HIF) will be reset and the EMI bit cleared to disable further interrupts. External interrupts are triggered by a high to low transition of INT and the related interrupt request flag (EIF; bit 4 of INTC0) will be set. When the interrupt is enabled, the stack is not full and the external interrupt is active, a subroutine call to location 04H will occur. The interrupt request flag (EIF) and EMI bits will be cleared to disable other interrupts. The internal timer/event counter interrupt is initialized by setting the timer/event counter interrupt request flag (TF; bit 5 of INTC0), caused by a timer overflow. When the interrupt is enabled, the stack is not full and the TF bit is set, a subroutine call to location 08H will occur. The related interrupt request flag (TF) will be reset and the EMI bit cleared to disable further interrupts. The UART interrupt is initialized by setting the UART interrupt request flag (URF; bit 7 of INTC1), caused by UART transmission/reception completion or address detection. When the interrupt is enabled, the stack is not full and the URF bit is set, a subroutine call to location 014H will occur. The related interrupt request flag (URF) will be reset and the EMI bit cleared to disable further interrupts. The A/D converter interrupt is initialized by setting the A/D converter request flag (ADF; bit 6 of INTC0), caused by an end of A/D conversion. When the interrupt is enabled, the stack is not full and the ADF is set, a subroutine call to location 0CH will occur. The related interrupt request flag (ADF) will be reset and the EMI bit cleared to disable further interrupts. During the execution of an interrupt subroutine, other interrupt acknowledgments are held until the ²RETI² instruction is executed or the EMI bit and the related interrupt control bit are set to 1 (of course, if the stack is not full). To return from the interrupt subroutine, ²RET² or ²RETI² may be invoked. RETI will set the EMI bit to enable an interrupt service, but RET will not. Bit No. Label 0 EMI Controls the master (global) interrupt (1= enabled; 0= disabled) Function 1 EEI Controls the external interrupt (1= enabled; 0= disabled) 2 ETI Controls the timer/event counter interrupt (1= enabled; 0= disabled) 3 EADI 4 EIF External interrupt request flag (1= active; 0= inactive) 5 TF Internal timer/event counter request flag (1= active; 0= inactive) 6 ADF 7 ¾ Controls the A/D converter interrupt (1= enabled; 0= disabled) A/D converter request flag (1= active; 0= inactive) For test mode used only. Must be written as ²0²; otherwise may result in unpredictable operation. INTC0 (0BH) Register Bit No. Label Function 2 Controls the I C Bus interrupt (1=enabled; 0=disabled) 0 EHI 1 EURI 2~3, 6~7 ¾ 4 HIF I2C Bus interrupt request flag (1=active; 0=inactive) 5 URF UART request flag ( 1=active; 0:inactive ) Control the UART interrupt ( 1=enable ; 0=disable ) Unused bit, read as ²0² INTC1 (1EH) Register Rev. 1.20 10 March 23, 2007 HT46RU22 mode stops the system oscillator and ignores an external signal to conserve power. Interrupts, occurring in the interval between the rising edges of two consecutive T2 pulses, will be serviced on the latter of the two T2 pulses, if the corresponding interrupts are enabled. In the case of simultaneous requests the following table shows the priority that is applied. These can be masked by resetting the EMI bit. Priority Vector External Interrupt Interrupt Source 1 04H Timer/Event Counter Overflow 2 08H A/D Converter Interrupt 3 0CH I C Bus Interrupt 4 10H UART Interrupt 5 14H 2 If an RC oscillator is used, an external resistor between OSC1 and VSS is required and the resistance must range from 24kW to 1MW. The system clock, divided by 4, is available on OSC2 with pull-high resistor, which can be used to synchronize external logic. The RC oscillator provides the most cost effective solution. However, the frequency of oscillation may vary with VDD, temperatures and the chip itself due to process variations. It is, therefore, not suitable for timing sensitive operations where an accurate oscillator frequency is desired. If the Crystal oscillator is used, a crystal across OSC1 and OSC2 is needed to provide the feedback and phase shift required for the oscillator, and no other external components are required. Instead of a crystal, a resonator can also be connected between OSC1 and OSC2 to get a frequency reference, but two external capacitors in OSC1 and OSC2 are required (If the oscillating frequency is less than 1MHz). Once the interrupt request flags, composed of TF, EIF, ADF and HIF, are set, they will remain in the INTC0 and INTC1 register until the interrupts are serviced or cleared by a software instruction. It is recommended that a program does not use the ²CALL subroutine² within the interrupt subroutine. Interrupts often occur in an unpredictable manner or need to be serviced immediately in some applications. If only one stack is left and enabling the interrupt is not well controlled, the original control sequence will be damaged once the ²CALL² operates in the interrupt subroutine. The WDT oscillator is a free running on-chip RC oscillator, and no external components are required. Even if the system enters the power down mode, the system clock is stopped, but the WDT oscillator still works with a period of approximately 65ms at 5V. The WDT oscillator can be disabled by options to conserve power. Oscillator Configuration Watchdog Timer - WDT There are two oscillator circuits in the microcontroller. V O S C 1 D D 4 7 0 p F fS O S C 2 Y S The clock source of the WDT is implemented by an dedicated RC oscillator (WDT oscillator) or instruction clock (system clock divided by 4) decided by options. This timer is designed to prevent a software malfunction or sequence jumping to an unknown location with unpredictable results. The watchdog Timer can be disabled by an option. If the watchdog Timer is disabled, all the executions related to the WDT result in no operation. O S C 1 O S C 2 /4 C r y s ta l O s c illa to r R C O s c illa to r System Oscillator Once an internal WDT oscillator (RC oscillator with period 65ms at 5V normally) is selected, it is divided by 212~215 (by option to get the WDT time-out period). The minimum period of WDT time-out period is about 300ms~600ms. This time-out period may vary with tem- Both are designed for system clocks, namely the RC oscillator and the Crystal oscillator, which are determined by the options. No matter what oscillator type is selected, the signal provides the system clock. The HALT S y s te m C lo c k /4 O p tio n S e le c t W D T O S C fS D iv id e r fS /2 8 W D T P r e s c a le r M a s k O p tio n W D T C le a r C K R T C K R T T im e 2 1 5/fS 2 1 4/fS 2 1 3/fS 2 1 2/fS -o ~ ~ ~ ~ u t 2 1 2 1 2 1 2 1 R e s e t /fS 5 /fS 4 /fS 3 /fS 6 Watchdog Timer Rev. 1.20 11 March 23, 2007 HT46RU22 perature, VDD and process variations. By selection the WDT options, longer time-out periods can be realized. If the WDT time-out is selected 215, the maximum time-out period is divided by 215~216about 2.1s~4.3s. The system can leave the HALT mode by means of an external reset, an interrupt, an external falling edge signal on port A or a WDT overflow. An external reset causes a device initialization and the WDT overflow performs a ²warm reset². After the TO and PDF flags are examined, the reason for chip reset can be determined. If the WDT oscillator is disabled, the WDT clock may still come from the instruction clock and operate in the same manner except that in the halt state the WDT may stop counting and lose its protecting purpose. In this situation the logic can only be restarted by external logic. If the device operates in a noisy environment, using the on-chip RC oscillator (WDT OSC) is strongly recommended, since the HALT will stop the system clock. The PDF flag is cleared by system power-up or executing the ²CLR WDT² instruction and is set when executing the ²HALT² instruction. The TO flag is set if the WDT time-out occurs, and causes a wake-up that only resets the program counter and stack pointer; the others keep their original status. The WDT overflow under normal operation will initialize ²chip reset² and set the status bit TO. Whereas in the HALT mode, the overflow will initialize a ²warm reset² only the program counter and stack pointer are reset to 0. To clear the contents of WDT, three methods are adopted; external reset (a low level to RES), software instructions, or a HALT instruction. The software instructions include CLR WDT and the other set - CLR WDT1 and CLR WDT2. Of these two types of instruction, only one can be active depending on the options - ²CLR WDT times selection option². If the ²CLR WDT² is selected (i.e. CLRWDT times equal 1), any execution of the CLR WDT instruction will clear the WDT. In case ²CLR WDT1² and ²CLR WDT2² are chosen (i.e. CLRWDT times equal two), these two instructions must be executed to clear the WDT; otherwise, the WDT may reset the chip because of time-out. The port A wake-up and interrupt methods can be considered as a continuation of normal execution. Each bit in port A can be independently selected to wake up the device by the options. Awakening from an I/O port stimulus, the program will resume execution of the next instruction. If it is awakening from an interrupt, two sequences may happen. If the related interrupt is disabled or the interrupt is enabled but the stack is full, the program will resume execution at the next instruction. If the interrupt is enabled and the stack is not full, the regular interrupt response takes place. If an interrupt request flag is set to ²1² before entering the HALT mode, the wake-up function of the related interrupt will be disabled. Once a wake-up event occurs, it takes 1024 tSYS (system clock period) to resume normal operation. In other words, a dummy period will be inserted after wake-up. If the wake-up results from an interrupt acknowledgment, the actual interrupt subroutine execution will be delayed by one or more cycles. If the wake-up results in the next instruction execution, this will be executed immediately after the dummy period is finished. If the WDT time-out period is selected fs/212 (options), the WDT time-out period ranges from fs/212~fs/213, since the ²CLR WDT² or ²CLR WDT1² and ²CLR WDT2² instructions only clear the last two stages of the WDT. Power Down Operation - HALT To minimize power consumption, all the I/O pins should be carefully managed before entering the HALT status. The HALT mode is initialized by the ²HALT² instruction and results in the following... · The system oscillator will be turned off but the WDT oscillator keeps running (if the WDT oscillator is selected). · The contents of the on chip RAM and registers remain unchanged. · WDT will be cleared and recounted again (if the WDT clock is from the WDT oscillator). · All of the I/O ports maintain their original status. · The PDF flag is set and the TO flag is cleared. Rev. 1.20 12 March 23, 2007 HT46RU22 V Reset 0 .0 1 m F * There are three ways in which a reset can occur: · RES reset during normal operation 1 0 0 k W · RES reset during HALT R E S · WDT time-out reset during normal operation 1 0 k W The WDT time-out during HALT is different from other chip reset conditions, since it can perform a ²warm re set² that resets only the program counter and SP, leaving the other circuits in their original state. Some registers remain unchanged during other reset conditions. Most registers are reset to the ²initial condition² when the reset conditions are met. By examining the PDF and TO flags, the program can distinguish between different ²chip resets². TO PDF 0 0 RES reset during power-up u u RES reset during normal operation 0 .1 m F * Reset Circuit Note: RESET Conditions 0 1 RES wake-up HALT 1 u WDT time-out during normal operation 1 1 WDT wake-up HALT D D ²*² Make the length of the wiring, which is connected to the RES pin as short as possible, to avoid noise interference. V D D R E S tS S T S S T T im e - o u t C h ip R e s e t Reset Timing Chart Note: ²u² means unchanged To guarantee that the system oscillator is started and stabilized, the SST (System Start-up Timer) provides an extra-delay of 1024 system clock pulses when the system reset (power-up, WDT time-out or RES reset) or the system awakes from the HALT state. H A L T W a rm R e s e t W D T When a system reset occurs, the SST delay is added during the reset period. Any wake-up from HALT will enable the SST delay. R E S O S C 1 An extra option load time delay is added during system reset (power-up, WDT time-out at normal mode or RES reset). S S T 1 0 - b it R ip p le C o u n te r S y s te m C o ld R e s e t R e s e t The functional unit chip reset status are shown below. Reset Configuration Program Counter 000H Interrupt Disable WDT Clear after master reset, WDT begins counting Timer/Event Counter Off Input/Output ports Input mode Stack Pointer Points to the top of the stack Rev. 1.20 13 March 23, 2007 HT46RU22 The registers states are summarized in the following table. Register Reset (Power On) WDT Time-out RES Reset (Normal Operation) (Normal Operation) RES Reset (HALT) WDT Time-out (HALT)* TMR xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu TMRC 00-0 1000 00-0 1000 00-0 1000 00-0 1000 uu-u uuuu 000H 000H 000H 000H 000H MP -xxx xxxx -uuu uuuu -uuu uuuu -uuu uuuu -uuu uuuu ACC xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu TBLP xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu TBLH --xx xxxx --uu uuuu --uu uuuu --uu uuuu --uu uuuu STATUS --00 xxxx --1u uuuu --uu uuuu --01 uuuu --11 uuuu INTC0 -000 0000 -000 0000 -000 0000 -000 0000 -uuu uuuu INTC1 --xx --xx --xx --xx --xx --xx --xx --xx --uu --uu PA 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu PAC 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu PB 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu PBC 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu PC ---- --11 ---- --11 ---- --11 ---- --11 ---- --uu PCC ---- --11 ---- --11 ---- --11 ---- --11 ---- --uu PD ---- ---1 ---- ---1 ---- ---1 ---- ---1 ---- ---u PDC ---- ---1 ---- ---1 ---- ---1 ---- ---1 ---- ---u PWM xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu HADR xxxx xxx- xxxx xxx- xxxx xxx- xxxx xxx- uuuu uuu- Program Counter HCR 0--0 0--- 0--0 0--- 0--0 0--- 0--0 0--- u--u u--- HSR 100- -0-1 100- -0-1 100- -0-1 100- -0-1 uuu- -u-u HDR xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu ADRL x--- ---- x--- ---- x--- ---- x--- ---- u--- ---- ADRH xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu ADCR 0100 0000 0100 0000 0100 0000 0100 0000 uuuu uuuu ACSR 1--- --00 1--- --00 1--- --00 1--- --00 u--- --uu USR 0000 1011 0000 1011 0000 1011 0000 1011 uuuu uuuu UCR1 0000 00x0 0000 00x0 0000 00x0 0000 00x0 uuuu uuuu UCR2 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu TXR/RXR xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu BGR xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu Note: ²*² stands for warm reset ²u² stands for unchanged ²x² stands for unknown Rev. 1.20 14 March 23, 2007 HT46RU22 Timer/Event Counter In the event count or timer mode, once the timer/event counter starts counting, it will count from the current contents in the timer/event counter to FFH. Once overflow occurs, the counter is reloaded from the timer/event counter preload register and generates the interrupt request flag (TF; bit 5 of INTC0) at the same time. A timer/event counter (TMR) is implemented in the microcontroller. The timer/event counter contains an 8-bit programmable count-up counter and the clock may come from an external source or the system clock. Using the internal system clock, there is only one reference time-base. The internal clock source comes from fSYS. Using external clock input allows the user to count external events, measure time internals or pulse widths, or generate an accurate time base. While using the internal clock allows the user to generate an accurate time base. In the pulse width measurement mode with the TON and TE bits equal to 1, once the TMR has received a transient from low to high (or high to low if the TE bits is ²0²) it will start counting until the TMR returns to the original level and resets the TON. The measured result will remain in the timer/event counter even if the activated transient occurs again. In other words, only 1 cycle measurement can be done. Until setting the TON, the cycle measurement will function again as long as it receives further transient pulse. Note that, in this operating mode, the timer/event counter starts counting not according to the logic level but according to the transient edges. In the case of counter overflows, the counter is reloaded from the timer/event counter preload register and issues the interrupt request just like the other two modes. To enable the counting operation, the timer ON bit (TON; bit 4 of TMRC) should be set to 1. In the pulse width measurement mode, the TON will be cleared automatically after the measurement cycle is completed. But in the other two modes the TON can only be reset by instructions. The overflow of the timer/event counter is one of the wake-up sources. No matter what the operation mode is, writing a 0 to ETI can disable the interrupt service. There are two registers related to the timer/event counter; TMR ([0DH]), TMRC ([0EH]). Two physical registers are mapped to TMR location; writing TMR makes the starting value be placed in the timer/event counter preload register and reading TMR gets the contents of the timer/event counter. The TMRC is a timer/event counter control register, which defines some options. The TM0, TM1 bits define the operating mode. The event count mode is used to count external events, which means the clock source comes from an external (TMR) pin. The timer mode functions as a normal timer with the clock source coming from the fINT clock. The pulse width measurement mode can be used to count the high or low level duration of the external signal (TMR). The counting is based on the fINT. Bit No. 0 1 2 Label PSC0 PSC1 PSC2 3 TE 4 TON 5 ¾ 6 7 TM0 TM1 Function To define the prescaler stages, PSC2, PSC1, PSC0= 000: fINT=fSYS 001: fINT=fSYS/2 010: fINT=fSYS/4 011: fINT=fSYS/8 100: fINT=fSYS/16 101: fINT=fSYS/32 110: fINT=fSYS/64 111: fINT=fSYS/128 Defines the TMR active edge of the timer/event counter: In Event Counter Mode (TM1,TM0)=(0,1): 1:count on falling edge; 0:count on rising edge In Pulse Width measurement mode (TM1,TM0)=(1,1): 1: start counting on the rising edge, stop on the falling edge; 0: start counting on the falling edge, stop on the rising edge To enable or disable timer counting (0=disabled; 1=enabled) Unused bit, read as ²0² To define the operating mode 01=Event count mode (external clock) 10=Timer mode (internal clock) 11=Pulse width measurement mode 00=Unused TMRC (0EH) Register Rev. 1.20 15 March 23, 2007 HT46RU22 P W M (6 + 2 ) o r (7 + 1 ) C o m p a re fS Y S T o P D 0 C ir c u it 8 - s ta g e P r e s c a le r f IN 8 -1 M U X P S C 2 ~ P S C 0 D a ta B u s T T M 1 T M 0 T M R 8 - B it T im e r /E v e n t C o u n te r P r e lo a d R e g is te r R e lo a d T E T M 1 T M 0 T O N 8 - B it T im e r /E v e n t C o u n te r P u ls e W id th M e a s u re m e n t M o d e C o n tro l O v e r flo w 1 /2 to In te rru p t P F D Timer/Event Counter For output function, CMOS is the only configuration. These control registers are mapped to locations 13H, 15H, 17H and 19H. In the case of timer/event counter OFF condition, writing data to the timer/event counter preload register will also reload that data to the timer/event counter. But if the timer/event counter is turned on, data written to it will only be kept in the timer/event counter preload register. The timer/event counter will still operate until overflow occurs. When the timer/event counter (reading TMR) is read, the clock will be blocked to avoid errors. As clock blocking may results in a counting error, this must be taken into consideration by the programmer. After a chip reset, these input/output lines remain at high levels or floating state (dependent on pull-high options). Each bit of these input/output latches can be set or cleared by ²SET [m].i² and ²CLR [m].i² (m=12H, 14H, 16H or 18H) instructions. Some instructions first input data and then follow the output operations. For example, ²SET [m].i², ²CLR [m].i², ²CPL [m]², ²CPLA [m]² read the entire port states into the CPU, execute the defined operations (bit-operation), and then write the results back to the latches or the accumulator. The bit0~bit2 of the TMRC can be used to define the pre-scaling stages of the internal clock sources of timer/event counter. The definitions are as shown. The overflow signal of timer/event counter can be used to generate the PFD signal. Each line of port A has the capability of waking-up the device. The highest 6-bit of port C and 7-bit of port D are not physically implemented; on reading them a ²0² is returned whereas writing then results in a no-operation. See Application note. Input/Output Ports There are 19 bidirectional input/output lines in the microcontroller, labeled as PA, PB, PC and PD, which are mapped to the data memory of [12H], [14H], [16H] and [18H] respectively. All of these I/O ports can be used for input and output operations. For input operation, these ports are non-latching, that is, the inputs must be ready at the T2 rising edge of instruction ²MOV A,[m]² (m=12H, 14H, 16H or 18H). For output operation, all the data is latched and remains unchanged until the output latch is rewritten. Each I/O port has a pull-high option. Once the pull-high option is selected, the I/O port has a pull-high resistor, otherwise, there¢s none. Take note that a non-pull-high I/O port operating in input mode will cause a floating state. The PA3 is pin-shared with the PFD signal. If the PFD option is selected, the output signal in output mode of PA3 will be the PFD signal generated by timer/event counter overflow signal. The input mode always remaining its original functions. Once the PFD option is selected, the PFD output signal is controlled by PA3 data register only. Writing ²1² to PA3 data register will enable the PFD output function and writing ²0² will force the PA3 to remain at ²0². Each I/O line has its own control register (PAC, PBC, PCC, PDC) to control the input/output configuration. With this control register, CMOS output or Schmitt trigger input with or without pull-high resistor structures can be reconfigured dynamically (i.e. on-the-fly) under software control. To function as an input, the corresponding latch of the control register must write ²1². The input source also depends on the control register. If the control register bit is ²1², the input will read the pad state. If the control register bit is ²0², the contents of the latches will move to the internal bus. The latter is possible in the ²read-modify-write² instruction. Rev. 1.20 16 March 23, 2007 HT46RU22 V C o n tr o l B it D a ta B u s W r ite C o n tr o l R e g is te r Q D C K Q S C h ip R e s e t D D P u ll- h ig h O p tio n P A P A P A P A P A P A P B P D R e a d C o n tr o l R e g is te r D a ta B it Q D W r ite D a ta R e g is te r C K A 2 F D M R T D A C L N 0 ~ P B 7 /A N 7 W M Q S M (P D 0 o r P W M ) P A 3 P F D M R e a d D a ta R e g is te r S y s te m 0 ~ P 3 /P 4 /T 5 /IN 6 /S 7 /S 0 /A 0 /P U U X P F D E N (P A 3 ) X W a k e - u p ( P A o n ly ) O P 0 ~ O P 7 IN T fo r P A 5 O n ly T M R fo r P A 4 O n ly Input/Output Ports V D a ta B u s W r ite C o n tr o l R e g is te r Q D C K D D P u ll- h ig h O p tio n C o n tr o l B it Q S C h ip R e s e t P C 0 /T X R e a d C o n tr o l R e g is te r W r ite D a ta R e g is te r D a ta B it Q D C K Q S M F ro m U A R T T X M R e a d D a ta R e g is te r U U X U A R T E N X & T X E N PC0/TX Input/Output Ports V C o n tr o l B it D a ta B u s W r ite C o n tr o l R e g is te r Q D C K D D P u ll- h ig h O p tio n Q S C h ip R e s e t R e a d C o n tr o l R e g is te r W r ite D a ta R e g is te r P C 1 /R X D a ta B it Q D C K S Q M R e a d D a ta R e g is te r U X T o U A R T R X PC1/RX Input/Output Ports Rev. 1.20 17 March 23, 2007 HT46RU22 In a (6+2) bit PWM function, the contents of the PWM register is divided into two groups. Group 1 of the PWM register is denoted by DC which is the value of PWM.7~PWM.2. The group 2 is denoted by AC which is the value of PWM.1~PWM.0. The I/O functions of PA3 are shown below. I/O Mode Logical Input PA3 Note: I/P O/P (Normal) (Normal) Logical Output I/P (PFD) O/P (PFD) Logical PFD Input (Timer on) In a (6+2) bits mode PWM cycle, the duty cycle of each modulation cycle is shown in the table. The PFD frequency is the timer/event counter overflow frequency divided by 2. Parameter AC (0~3) Duty Cycle i<AC DC + 1 64 i³AC DC 64 The PA5 and PA4 are pin-shared with INT and TMR pins respectively. Modulation cycle i (i=0~3) The PB can also be used as A/D converter inputs. The A/D function will be described later. There is a PWM function shared with PD0. If the PWM function is enabled, the PWM signal will appear on PD0 (if PD0 is operating in output mode). Writing ²1² to PD0 data register will enable the PWM output function and writing ²0² will force the PD0 to remain at ²0². The I/O functions of PD0 is as shown. I/O I/P Mode (Normal) PD0 Logical Input O/P (Normal) I/P (PWM) O/P (PWM) Logical Output Logical Input PWM A (7+1) bits mode PWM cycle is divided into two modulation cycles (modulation cycle 0 ~ modulation cycle 1). Each modulation cycle has 128 PWM input clock period. In a (7+1) bits PWM function, the contents of the PWM register is divided into two groups. Group 1 of the PWM register is denoted by DC which is the value of PWM.7~PWM.1. The group 2 is denoted by AC which is the value of PWM.0. In a (7+1) bits mode PWM cycle, the duty cycle of each modulation cycle is shown in the table. It is recommended that unused or not bonded out I/O lines should be set as output pins by software instruction to avoid consuming power under input floating state. Parameter AC (0~1) Duty Cycle i<AC DC + 1 128 i³AC DC 128 Modulation cycle i (i=0~1) PWM The microcontroller provides 1 channels (6+2)/(7+1) (dependent on options) bits PWM output shared with PD0. The PWM channel has its data registers denoted as PWM(1AH). The frequency source of the PWM counter comes from fSYS. The PWM registers is a 8-bit register. The waveforms of PWM outputs are as shown. Once the PD0 is selected as the PWM outputs and the output function of PD0 is enabled (PDC.0=²0²), writing 1 to PD0 data register will enable the PWM output function and writing ²0² will force the PD0 to stay at ²0². The modulation frequency, cycle frequency and cycle duty of the PWM output signal are summarized in the following table. PWM Modulation Frequency fSYS/64 for (6+2) bits mode fSYS/128 for (7+1) bits mode PWM Cycle PWM Cycle Frequency Duty fSYS/256 [PWM]/256 A (6+2) bits mode PWM cycle is divided into four modulation cycles (modulation cycle 0~modulation cycle 3). Each modulation cycle has 64 PWM input clock period. Rev. 1.20 18 March 23, 2007 HT46RU22 fS /2 Y S [P W M ] = 1 0 0 P W M 2 5 /6 4 2 5 /6 4 2 5 /6 4 2 5 /6 4 2 5 /6 4 2 6 /6 4 2 5 /6 4 2 5 /6 4 2 5 /6 4 2 6 /6 4 2 6 /6 4 2 6 /6 4 2 5 /6 4 2 5 /6 4 2 6 /6 4 2 6 /6 4 2 6 /6 4 2 5 /6 4 2 6 /6 4 [P W M ] = 1 0 1 P W M [P W M ] = 1 0 2 P W M [P W M ] = 1 0 3 P W M 2 6 /6 4 P W M m o d u la tio n p e r io d : 6 4 /fS M o d u la tio n c y c le 0 Y S M o d u la tio n c y c le 1 P W M M o d u la tio n c y c le 2 c y c le : 2 5 6 /fS M o d u la tio n c y c le 3 M o d u la tio n c y c le 0 Y S (6+2) PWM Mode fS Y S /2 [P W M ] = 1 0 0 P W M 5 0 /1 2 8 5 0 /1 2 8 5 0 /1 2 8 5 1 /1 2 8 5 0 /1 2 8 5 1 /1 2 8 5 1 /1 2 8 5 1 /1 2 8 5 1 /1 2 8 5 1 /1 2 8 5 2 /1 2 8 [P W M ] = 1 0 1 P W M [P W M ] = 1 0 2 P W M [P W M ] = 1 0 3 P W M 5 2 /1 2 8 P W M m o d u la tio n p e r io d : 1 2 8 /fS Y S M o d u la tio n c y c le 0 M o d u la tio n c y c le 1 P W M c y c le : 2 5 6 /fS M o d u la tio n c y c le 0 Y S (7+1) PWM Mode A/D Converter The A/D converter control register is used to control the A/D converter. The bit2~bit0 of the ADCR are used to select an analog input channel. There are a total of eight channels to select. The bit5~bit3 of the ADCR are used to set PB configurations. PB can be an analog input or as digital I/O line decided by these 3 bits. Once a PB line is selected as an analog input, the I/O functions and pull-high resistor of this I/O line are disabled and the A/D converter circuit is power on. The EOCB bit (bit6 of the ADCR) is end of A/D conversion flag. Check this bit to know when A/D conversion is completed. The START bit of the ADCR is used to begin the conversion of the A/D converter. Giving START bit a rising edge and falling edge means that the A/D conversion has started. In order to ensure the A/D conversion is completed, the START should remain at ²0² until the EOCB is cleared to ²0² (end of A/D conversion). The 8 channels and 9-bit resolution A/D converter are implemented in this microcontroller. The reference voltage is VDD. The A/D converter contains 4 special registers which are; ADRL (24H), ADRH (25H), ADCR (26H) and ACSR (27H). The ADRH and ADRL are A/D result register higher-order byte and lower-order byte and are read-only. After the A/D conversion is completed, the ADRH and ADRL should be read to get the conversion result data. The ADCR is an A/D converter control register, which defines the A/D channel number, analog channel select, start A/D conversion control bit and the end of A/D conversion flag. If the users want to start an A/D conversion, define PB configuration, select the converted analog channel, and give START bit a raising edge and falling edge (0®1®0). At the end of A/D conversion, the EOCB bit is cleared and an A/D converter interrupt occurs (if the A/D converter interrupt is enabled). The ACSR is A/D clock setting register, which is used to select the A/D clock source. Rev. 1.20 19 March 23, 2007 HT46RU22 Bit No. Label Function Selects the A/D converter clock source 00= system clock/2 ADCS0 01= system clock/8 ADCS1 10= system clock/32 11= undefined 0 1 2~6 ¾ Unused bit, read as ²0² 7 TEST For test mode used only ACSR (27H) Register Bit No. Label Function 0 1 2 ACS0 ACS1 ACS2 Defines the analog channel select. 3 4 5 PCR0 PCR1 PCR2 Defines the port B configuration select. If PCR0, PCR1 and PCR2 are all 0, the ADC circuit is power off to reduce power consumption 6 EOCB Indicates end of A/D conversion. (0 = end of A/D conversion) Each time bits 3~5 change state the A/D should be initialized by issuing a START signal, otherwise the EOCB flag may have an undefined condition. See ²Important note for A/D initialization². 7 START Starts the A/D conversion. (0®1®0= start; 0®1= Reset A/D converter and set EOCB to ²1²) ADCR (26H) Register PCR2 PCR1 PCR0 7 6 5 4 3 2 1 0 0 0 0 PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 0 0 1 PB7 PB6 PB5 PB4 PB3 PB2 PB1 AN0 0 1 0 PB7 PB6 PB5 PB4 PB3 PB2 AN1 AN0 0 1 1 PB7 PB6 PB5 PB4 PB3 AN2 AN1 AN0 1 0 0 PB7 PB6 PB5 PB4 AN3 AN2 AN1 AN0 1 0 1 PB7 PB6 PB5 AN4 AN3 AN2 AN1 AN0 1 1 0 PB7 PB6 AN5 AN4 AN3 AN2 AN1 AN0 1 1 1 AN7 AN6 AN5 AN4 AN3 AN2 AN1 AN0 Port B Configuration ACS2 ACS1 ACS0 Analog Channel 0 0 0 AN0 0 0 1 AN1 0 1 0 AN2 0 1 1 AN3 1 0 0 AN4 1 0 1 AN5 1 1 0 AN6 1 1 1 AN7 Analog Input Channel Selection Rev. 1.20 20 March 23, 2007 HT46RU22 Bit 7 of the ACSR register is used for test purposes only and must not be used for other purposes by the application program. Bit1 and bit0 of the ACSR register are used to select the A/D clock source. When the A/D conversion has completed, the A/D interrupt request flag will be set. The EOCB bit is set to ²1² when the START bit is set from ²0² to ²1². Important Note for A/D initialization: Special care must be taken to initialize the A/D converter each time the Port B A/D channel selection bits are modified, otherwise the EOCB flag may be in an undefined condition. An A/D initialization is implemented by setting the START bit high and then clearing it to zero within 10 instruction cycles of the Port B channel selection bits being modified. Note that if the Port B channel selection bits are all cleared to zero then an A/D initialization is not required. Register Bit7 ADRL D0 ¾ ¾ ¾ ¾ ¾ ¾ ¾ ADRH D8 D7 D6 D5 D4 D3 D2 D1 Note: Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 D0~D8 is A/D conversion result data bit LSB~MSB. ADRL (24H), ADRH (25H) Register The following two programming examples illustrate how to setup and implement an A/D conversion. In the first example, the method of polling the EOCB bit in the ADCR register is used to detect when the conversion cycle is complete, whereas in the second example, the A/D interrupt is used to determine when the conversion is complete. Example: using EOCB Polling Method to detect end of conversion clr mov mov mov mov EADI a,00000001B ACSR,a a,00100000B ADCR,a : : : Start_conversion: clr START set START clr START Polling_EOC: sz EOCB jmp polling_EOC mov a,ADRH mov adrh_buffer,a mov a,ADRL mov adrl_buffer,a : : jmp start_conversion ; disable ADC interrupt ; setup the ACSR register to select fSYS/8 as the A/D clock ; setup ADCR register to configure Port PB0~PB3 as A/D inputs ; and select AN0 to be connected to the A/D converter ; As the Port B channel bits have changed the following START ; signal (0-1-0) must be issued within 10 instruction cycles ; reset A/D ; start A/D ; poll the ADCR register EOCB bit to detect end of A/D conversion ; continue polling ; read conversion result high byte value from the ADRH register ; save result to user defined memory ; read conversion result low byte value from the ADRL register ; save result to user defined memory ; start next A/D conversion Example: using interrupt method to detect end of conversion clr EADI ; disable ADC interrupt mov a,00000001B mov ACSR,a ; setup the ACSR register to select fSYS/8 as the A/D clock mov mov a,00100000B ADCR,a : ; setup ADCR register to configure Port PB0~PB3 as A/D inputs ; and select AN0 to be connected to the A/D converter ; As the Port B channel bits have changed the following START ; signal (0-1-0) must be issued within 10 instruction cycles Rev. 1.20 21 March 23, 2007 HT46RU22 : Start_conversion: clr START set START clr START clr ADF set EADI set EMI : : : ; ADC interrupt service routine ADC_ISR: mov acc_stack,a mov a,STATUS mov status_stack,a : : mov a,ADRH mov adrh_buffer,a mov a,ADRL mov adrl_buffer,a clr START set START clr START : : EXIT_INT_ISR: mov a,status_stack mov STATUS,a mov a,acc_stack reti M in im u m ; reset A/D ; start A/D ; clear ADC interrupt request flag ; enable ADC interrupt ; enable global interrupt ; save ACC to user defined memory ; save STATUS to user defined memory ; read conversion result high byte value from the ADRH register ; save result to user defined register ; read conversion result low byte value from the ADRL register ; save result to user defined register ; reset A/D ; start A/D ; restore STATUS from user defined memory ; restore ACC from user defined memory o n e in s tr u c tio n c y c le n e e d e d , M a x im u m te n in s tr u c tio n c y c le s a llo w e d S T A R T E O C B A /D s a m p lin g tim e tA D C S P C R 2 ~ P C R 0 0 0 0 B A /D tA s a m p lin g tim e A /D tA D C S 1 0 0 B 1 0 0 B s a m p lin g tim e D C S 1 0 1 B 0 0 0 B 1 . P B p o rt s e tu p a s I/O s 2 . A /D c o n v e r te r is p o w e r e d o ff to r e d u c e p o w e r c o n s u m p tio n A C S 2 ~ A C S 0 0 0 0 B P o w e r-o n R e s e t 0 1 0 B 0 0 0 B 0 0 1 B S ta rt o f A /D c o n v e r s io n S ta rt o f A /D c o n v e r s io n S ta rt o f A /D c o n v e r s io n R e s e t A /D c o n v e rte r R e s e t A /D c o n v e rte r E n d o f A /D c o n v e r s io n 1 : D e fin e P B c o n fig u r a tio n 2 : S e le c t a n a lo g c h a n n e l tA D C A /D c o n v e r s io n tim e N o te : A /D tA D tA C S D C c lo c k m u s t b e fS = 3 2 tA D = 7 6 tA D Y S /2 , fS Y S /8 o r fS Y S R e s e t A /D c o n v e rte r E n d o f A /D c o n v e r s io n A /D tA D C c o n v e r s io n tim e d o n 't c a r e E n d o f A /D c o n v e r s io n A /D tA D C c o n v e r s io n tim e /3 2 A/D Conversion Timing Rev. 1.20 22 March 23, 2007 HT46RU22 Low Voltage Reset - LVR I2C Bus Serial Interface The microcontroller provides low voltage reset circuit in order to monitor the supply voltage of the device. If the supply voltage of the device is within the range 0.9V~3.3V, such as changing a battery, the LVR will automatically reset the device internally. I2C Bus is implemented in the device. The I2C Bus is a bidirectional 2-wire lines. The data line and clock line are implement in SDA pin and SCL pin. The SDA and SCL are NMOS open drain output pin. They must connect a pull-high resistor respectively. The LVR includes the following specifications: Using the I2C Bus, the device has two ways to transfer data. One is in slave transmit mode, the other is in slave receive mode. There are four registers related to I2C Bus; HADR([20H]), HCR([21H]), HSR([22H]), HDR([23H]). The HADR register is the slave address setting of the device, if the master sends the calling address which match, it means that this device is selected. The HCR is I2C Bus control register which defines the device enable or disable the I2C Bus as a transmitter or as a receiver. The HSR is I2C Bus status register, it responds with the I2C Bus status. The HDR is input/output data register, data to transmit or receive must be via the HDR register. · The low voltage (0.9V~VLVR) has to remain in their original state to exceed 1ms. If the low voltage state does not exceed 1ms, the LVR will ignore it and do not perform a reset function. · The LVR uses the ²OR² function with the external RES signal to perform chip reset. The relationship between VDD and VLVR is shown below. V D D 5 .5 V V O P R 5 .5 V V The I2C Bus control register contains three bits. The HEN bit define the enable or disable the I2C Bus. If the data wants transfer via I2C Bus, this bit must be set. The HTX bit defines whether the I2C Bus is in transmit or receive mode. If the device is as a transmitter, this bit must be set to ²1². The TXAK defines the transmit acknowledge signal, when the device received 8-bit data, the device sends this bit to I2C Bus at the 9th clock. If the receiver wants to continue to receive the next data, this bit must be reset to ²0² before receiving data. L V R 3 .0 V 2 .2 V 0 .9 V Note: VOPR is the voltage range for proper chip operation at 4MHz system clock. V D D 5 .5 V V L V R L V R D e te c t V o lta g e 0 .9 V 0 V R e s e t S ig n a l N o r m a l O p e r a tio n R e s e t *1 R e s e t *2 Low Voltage Reset Note: *1: To make sure that the system oscillator has stabilized, the SST provides an extra delay of 1024 system clock pulses before entering the normal operation. *2: Since low voltage state has to be maintained in its original state for over 1ms, therefore after 1ms delay, the device enters the reset mode. Rev. 1.20 23 March 23, 2007 HT46RU22 The I2C Bus status register contains 5 bits. The HCF bit is reset to ²0² when one data byte is being transferred. If one data transfer is completed, this bit is set to ²1². The HASS bit is set ²1² when the address is match, and the I2C Bus interrupt request flag is set to ²1². If the interrupt is enabled and the stack is not full, a subroutine call to location 10H will occur. Writing data to the I2C Bus control register clears HAAS bit. If the address is not match, this bit is reset to ²0². The HBB bit is set to respond the I2C Bus is busy. It mean that a START signal is detected. This bit is reset to ²0² when the I2C Bus is not busy. It means that a STOP signal is detected and the I2C Bus is free. The SRW bit defines the read/write command bit, if the calling address is match. When HAAS is set to ²1², the device check SRW bit to determine whether the device is working in transmit or receive mode. When SRW bit is set ²1², it means that the master wants to read data from I2C Bus, the slave device must write data to I2C Bus, so the slave device is working in transmit mode. When SRW is reset to ²0², it means that the master wants to write data to I2C Bus, the slave device must read data from the bus, so the slave device is working in receive mode. The RXAK bit is reset ²0² indicates an acknowledges signal has been received. In the transmit mode, the transmitter checks RXAK bit to know the receiver which wants to receive the next data byte, so the transmitter continue to write data to the I2C Bus until the RXAK bit is set to ²1² and the transmitter releases the SDA line, so that the master can send the STOP signal to release the bus. ister. At the beginning of the transfer of the I2C Bus, the device must initial the bus, the following are the notes for initialing the I2C Bus. Note: 1: Write the I2C Bus address register (HADR) to define its own slave address. 2: Set HEN bit of I2C Bus control register (HCR) bit 0 to enable the I2C Bus. Bit0 Slave Address ¾ Label 7 HEN 6~5 ¾ 4 HTX 3 2~0 To enable or disable I2C Bus function (0= disable; 1= enable) Unused bit, read as ²0² To define the transmit or receive mode (0= receive mode; 1= transmit) To enable or disable transmit acknowlTXAK edge (0=acknowledge; 1=don¢t acknowledge) ¾ Unused bit, read as ²0² 3: Set EHI bit of the interrupt control register 1 (INTC1) bit 0 to enable the I2C Bus interrupt. Bit Label No. 7 5 HBB is set to ²1² when I2C Bus is busy HBB and HBB is cleared to ²0² means that the I2C Bus is not busy. 2 1 0 2 The HDR register is the I C Bus input/output data register. Before transmitting data, the HDR must write the data which we want to transmit. Before receiving data, the device must dummy read data from HDR. Transmit or Receive data from I2C Bus must be via the HDR reg- HCF is clear to ²0² when one data byte is being transferred, HCF is set to ²1² indicating 8-bit data communication has been finished. HAAS is set to ²1² when the calling adHAAS dress has matched, and I2C Bus interrupt will occur and HIF is set. 4~3 HADR (20H) Register HCF Function 6 ²¾² means undefined Rev. 1.20 Function HCR (21H) Register The HADR bit7~bit1 define the device slave address. At the beginning of transfer, the master must select a device by sending the address of the slave device. The bit 0 is unused and is not defined. If the I2C Bus receives a start signal, all slave device notice the continuity of the 8-bit data. The front of 7 bits is slave address and the first bit is MSB. If the address is match, the HAAS status bit is set and generate an I2C Bus interrupt. In the ISR, the slave device must check the HAAS bit to know the I2C Bus interrupt comes from the slave address that has match or completed one 8-bit data transfer. The last bit of the 8-bit data is read/write command bit, it responds in SRW bit. The slave will check the SRW bit to know if the master wants to transmit or receive data. The device check SRW bit to know it is as a transmitter or receiver. Bit7~Bit1 Bit No. ¾ Unused bit, read as ²0² SRW is set to ²1² when the master wants to read data from the I2C Bus, so the slave must transmit data to the masSRW ter. SRW is cleared to ²0² when the master wants to write data to the I2C Bus, so the slave must receive data from the master. ¾ Unused bit, read as ²0² RXAK is cleared to ²0² when the master receives an 8-bit data and acknowledgRXAK ment at the 9th clock, RXAK is set to ²1² means not acknowledged. HSR (22H) Register 24 March 23, 2007 HT46RU22 S ta rt W r ite S la v e A d d re s s to H A D R S E T H E N D is a b le I2C B u s In te rru p t= ? E n a b le C L R E H I P o ll H IF to d e c id e w h e n to g o to I2C B u s IS R S E T E H I W a it fo r In te r r u p t G o to M a in P r o g r a m G o to M a in P r o g r a m S ta rt N o N o R e a d fro m Y e s Y e s H T X = 1 ? H D R R E T I Y e s Y e s H A A S = 1 ? R X A K = 1 ? N o C L R H T X C L R T X A K W r ite to H D R D u m m y R e a d fro m H D R R E T I S R W = 1 ? N o S E T H T X C L R H T X C L R T X A K W r ite to H D R D u m m y R e a d F ro m H D R R E T I R E T I R E T I Rev. 1.20 25 March 23, 2007 HT46RU22 S C L S ta rt S R W S la v e A d d r e s s 0 1 S D A 1 1 0 1 0 1 D a ta S C L 1 0 0 1 A C K 0 A C K 0 1 0 S to p 0 S D A S = S A S R M = D = A = P = S ta rt (1 = S la v e = S R W S la v e d D a ta (8 A C K (R S to p (1 S S A b it) A d d r e s s ( 7 b its ) b it ( 1 b it) e v ic e s e n d a c k n o w le d g e b it ( 1 b it) b its ) X A K b it fo r tr a n s m itte r , T X A K b it fo r r e c e iv e r 1 b it) b it) S R M D A D A S S A S R M D A D A P I2C Communication Timing Diagram In interrupt subroutine, check HAAS bit to know whether the I2C Bus interrupt comes from a slave address that is matched or a data byte transfer is completed. When the slave address is matched, the device must be in transmit mode or receive mode and write data to HDR or dummy read from HDR to release the SCL line. Start Signal The START signal is generated only by the master device. The other device in the bus must detect the START signal to set the I2C Bus busy bit (HBB). The START signal is SDA line from high to low, when SCL is high. S C L SRW Bit The SRW bit means that the master device wants to read from or write to the I2C Bus. The slave device check this bit to understand itself if it is a transmitter or a receiver. The SRW bit is set to ²1² means that the master wants to read data from the I2C Bus, so the slave device must write data to a bus as a transmitter. The SRW is cleared to ²0² means that the master wants to write data to the I2C Bus, so the slave device must read data from the I2C Bus as a receiver. S D A Start Bit Slave Address The master must select a device for transferring the data by sending the slave device address after the START signal. All device in the I2C Bus will receive the I2C Bus slave address (7 bits) to compare with its own slave address (7 bits). If the slave address is matched, the slave device will generate an interrupt and save the following bit (8th bit) to SRW bit and sends an acknowledge bit (low level) to the 9th bit. The slave device also sets the status flag (HAAS), when the slave address is matched. Rev. 1.20 26 March 23, 2007 HT46RU22 master sends a STOP signal to release the I2C Bus. The data is stored in the HDR register. The transmitter must write data to the HDR before transmit data and the receiver must read data from the HDR after receiving data. Acknowledge Bit One of the slave device generates an acknowledge signal, when the slave address is matched. The master device can check this acknowledge bit to know if the slave device accepts the calling address. If no acknowledge bit, the master must send a STOP bit and end the communication. When the I2C Bus status register bit 6 HAAS is high, it means the address is matched, so the slave must check SRW as a transmitter (set HTX) to ²1² or as a receiver (clear HTX) to ²0². S C L S D A S ta r t b it S C L S to p b it D a ta s ta b le D a ta a llo w c h a n g e Data Timing Diagram S D A Receive Acknowledge Bit When the receiver wants to continue to receive the next data byte, it generates an acknowledge bit (TXAK) at the 9th clock. The transmitter checks the acknowledge bit (RXAK) to continue to write data to the I2C Bus or change to receive mode and dummy read the HDR register to release the SDA line and the master sends the STOP signal. Stop Bit Data Byte The data is 8 bits and is sent after the slave device has acknowledges the slave address. The first bit is MSB and the 8th bit is LSB. The receiver sends the acknowledge signal (²0²) and continues to receive the next 1 byte data. If the transmitter checks and there¢s no acknowledge signal, then it release the SDA line, and the Rev. 1.20 27 March 23, 2007 HT46RU22 which can also be used as a general purpose I/O pin, if the pin is not configured as a receiver, which occurs if the RXEN bit in the UCR2 register is equal to zero. Along with the UARTEN bit, the TXEN and RXEN bits, if set, will automatically setup these I/O pins to their respective TX output and RX input conditions and disable any pull-high resistor option which may exist on the RX pin. UART Bus Serial Interface The HT46RU22 devices contain an integrated full-duplex asynchronous serial communications UART interface that enables communication with external devices that contain a serial interface. The UART function has many features and can transmit and receive data serially by transferring a frame of data with eight or nine data bits per transmission as well as being able to detect errors when the data is overwritten or incorrectly framed. The UART function possesses its own internal interrupt which can be used to indicate when a reception occurs or when a transmission terminates. · UART data transfer scheme The block diagram shows the overall data transfer structure arrangement for the UART. The actual data to be transmitted from the MCU is first transferred to the TXR register by the application program. The data will then be transferred to the Transmit Shift Register from where it will be shifted out, LSB first, onto the TX pin at a rate controlled by the Baud Rate Generator. Only the TXR register is mapped onto the MCU Data Memory, the Transmit Shift Register is not mapped and is therefore inaccessible to the application program. Data to be received by the UART is accepted on the external RX pin, from where it is shifted in, LSB first, to the Receiver Shift Register at a rate controlled by the Baud Rate Generator. When the shift register is full, the data will then be transferred from the shift register to the internal RXR register, where it is buffered and can be manipulated by the application program. Only the RXR register is mapped onto the MCU Data Memory, the Receiver Shift Register is not mapped and is therefore inaccessible to the application program. It should be noted that the actual register for data transmission and reception, although referred to in the text, and in application programs, as separate TXR and RXR registers, only exists as a single shared register in the Data Memory. This shared register known as the TXR/RXR register is used for both data transmission and data reception. · UART features The integrated UART function contains the following features: ¨ Full-duplex, asynchronous communication ¨ 8 or 9 bits character length ¨ Even, odd or no parity options ¨ One or two stop bits ¨ Baud rate generator with 8-bit prescaler ¨ Parity, framing, noise and overrun error detection ¨ Support for interrupt on address detect (last character bit=1) ¨ Separately enabled transmitter and receiver ¨ 2-byte Deep Fifo Receive Data Buffer ¨ Transmit and receive interrupts ¨ Interrupts can be initialized by the following conditions: - Transmitter Empty - Transmitter Idle - Receiver Full - Receiver Overrun - Address Mode Detect · UART status and control registers There are five control registers associated with the UART function. The USR, UCR1 and UCR2 registers control the overall function of the UART, while the BRG register controls the Baud rate. The actual data to be transmitted and received on the serial interface is managed through the TXR/RXR data registers. · UART external pin interfacing To communicate with an external serial interface, the internal UART has two external pins known as TX and RX. The TX pin is the UART transmitter pin, which can be used as a general purpose I/O pin if the pin is not configured as a UART transmitter, which occurs when the TXEN bit in the UCR2 control register is equal to zero. Similarly, the RX pin is the UART receiver pin, T r a n s m itte r S h ift R e g is te r M S B R e c e iv e r S h ift R e g is te r L S B T X P in C L K T X R R e g is te r M S B R X P in L S B C L K B a u d R a te G e n e ra to r M C U R X R R e g is te r B u ffe r D a ta B u s UART Data Transfer Scheme Rev. 1.20 28 March 23, 2007 HT46RU22 · USR register RXIF flag is cleared when the USR register is read with RXIF set, followed by a read from the RXR register, and if the RXR register has no data available. The USR register is the status register for the UART, which can be read by the program to determine the present status of the UART. All flags within the USR register are read only. Further explanation on each of the flags is given below: ¨ ¨ ¨ TXIF The TXIF flag is the transmit data register empty flag. When this read only flag is ²0² it indicates that the character is not transferred to the transmit shift registers. When the flag is ²1² it indicates that the transmit shift register has received a character from the TXR data register. The TXIF flag is cleared by reading the UART status register (USR) with TXIF set and then writing to the TXR data register. Note that when the TXEN bit is set, the TXIF flag bit will also be set since the transmit buffer is not yet full. TIDLE The TIDLE flag is known as the transmission complete flag. When this read only flag is ²0² it indicates that a transmission is in progress. This flag will be set to ²1² when the TXIF flag is ²1² and when there is no transmit data, or break character being transmitted. When TIDLE is ²1² the TX pin becomes idle. The TIDLE flag is cleared by reading the USR register with TIDLE set and then writing to the TXR register. The flag is not generated when a data character, or a break is queued and ready to be sent. RXIF The RXIF flag is the receive register status flag. When this read only flag is ²0² it indicates that the RXR read data register is empty. When the flag is ²1² it indicates that the RXR read data register contains new data. When the contents of the shift register are transferred to the RXR register, an interrupt is generated if RIE=1 in the UCR2 register. If one or more errors are detected in the received word, the appropriate receive-related flags NF, FERR, and/or PERR are set within the same clock cycle. The b 7 P E R R ¨ RIDLE The RIDLE flag is the receiver status flag. When this read only flag is ²0² it indicates that the receiver is between the initial detection of the start bit and the completion of the stop bit. When the flag is ²1² it indicates that the receiver is idle. Between the completion of the stop bit and the detection of the next start bit, the RIDLE bit is ²1² indicating that the UART is idle. ¨ OERR The OERR flag is the overrun error flag, which indicates when the receiver buffer has overflowed. When this read only flag is ²0² there is no overrun error. When the flag is ²1² an overrun error occurs which will inhibit further transfers to the RXR receive data register. The flag is cleared by a software sequence, which is a read to the status register USR followed by an access to the RXR data register. ¨ FERR The FERR flag is the framing error flag. When this read only flag is ²0² it indicates no framing error. When the flag is ²1² it indicates that a framing error has been detected for the current character. The flag can also be cleared by a software sequence which will involve a read to the USR status register followed by an access to the RXR data register. ¨ NF The NF flag is the noise flag. When this read only flag is ²0² it indicates a no noise condition. When the flag is ²1² it indicates that the UART has detected noise on the receiver input. The NF flag is set during the same cycle as the RXIF flag but will not be set in the case of an overrun. The NF flag can be cleared by a software sequence which will involve a read to the USR status register, followed by an access to the RXR data register. b 0 N F F E R R O E R R R ID L E R X IF T ID L E T X IF U S R R e g is te r T r a n s m it d a ta r e g is te r e m p ty 1 : c h a r a c te r tr a n s fe r r e d to tr a n s m it s h ift r e g is te r 0 : c h a r a c te r n o t tr a n s fe r r e d to tr a n s m it s h ift r e g is te r T r a n s m is s io n id le 1 : n o tr a n s m is s io n in p r o g r e s s 0 : tr a n s m is s io n in p r o g r e s s R e c e iv e R X R r e g is te r s ta tu s 1 : R X R r e g is te r h a s a v a ila b le d a ta 0 : R X R r e g is te r is e m p ty R e c e iv e r s ta tu s 1 : r e c e iv e r is id le 0 : d a ta b e in g r e c e iv e d O v e rru n e rro r 1 : o v e rru n e rro r d e te c te d 0 : n o o v e rru n e rro r d e te c te d F r a m in g e r r o r fla g 1 : fr a m in g e r r o r d e te c te d 0 : n o fr a m in g e r r o r N o is e fla g 1 : n o is e d e te c te d 0 : n o n o is e d e te c te d P a r ity e r r o r fla g 1 : p a r ity e r r o r d e te c te d 0 : n o p a r ity e r r o r d e te c te d Rev. 1.20 29 March 23, 2007 HT46RU22 ¨ used, if the bit is equal to ²0² then only one stop bit is used. PERR The PERR flag is the parity error flag. When this read only flag is ²0² it indicates that a parity error has not been detected. When the flag is ²1² it indicates that the parity of the received word is incorrect. This error flag is applicable only if Parity mode (odd or even) is selected. The flag can also be cleared by a software sequence which involves a read to the USR status register, followed by an access to the RXR data register. · UCR1 register The UCR1 register together with the UCR2 register are the two UART control registers that are used to set the various options for the UART function, such as overall on/off control, parity control, data transfer bit length etc. Further explanation on each of the bits is given below: ¨ TX8 This bit is only used if 9-bit data transfers are used, in which case this bit location will store the 9th bit of the transmitted data, known as TX8. The BNO bit is used to determine whether data transfers are in 8-bit or 9-bit format. ¨ RX8 This bit is only used if 9-bit data transfers are used, in which case this bit location will store the 9th bit of the received data, known as RX8. The BNO bit is used to determine whether data transfers are in 8-bit or 9-bit format. ¨ TXBRK The TXBRK bit is the Transmit Break Character bit. When this bit is ²0² there are no break characters and the TX pin operates normally. When the bit is ²1² there are transmit break characters and the transmitter will send logic zeros. When equal to ²1² after the buffered data has been transmitted, the transmitter output is held low for a minimum of a 13-bit length and until the TXBRK bit is reset. ¨ STOPS This bit determines if one or two stop bits are to be used. When this bit is equal to ²1² two stop bits are b 7 U A R T E N ¨ PRT This is the parity type selection bit. When this bit is equal to ²1² odd parity will be selected, if the bit is equal to ²0² then even parity will be selected. ¨ PREN This is parity enable bit. When this bit is equal to ²1² the parity function will be enabled, if the bit is equal to ²0² then the parity function will be disabled. ¨ BNO This bit is used to select the data length format, which can have a choice of either 8-bits or 9-bits. If this bit is equal to ²1² then a 9-bit data length will be selected, if the bit is equal to ²0² then an 8-bit data length will be selected. If 9-bit data length is selected then bits RX8 and TX8 will be used to store the 9th bit of the received and transmitted data respectively. ¨ UARTEN The UARTEN bit is the UART enable bit. When the bit is ²0² the UART will be disabled and the RX and TX pins will function as General Purpose I/O pins. When the bit is ²1² the UART will be enabled and the TX and RX pins will function as defined by the TXEN and RXEN control bits. When the UART is disabled it will empty the buffer so any character remaining in the buffer will be discarded. In addition, the baud rate counter value will be reset. When the UART is disabled, all error and status flags will be reset. The TXEN, RXEN, TXBRK, RXIF, OERR, FERR, PERR, and NF bits will be cleared, while the TIDLE, TXIF and RIDLE bits will be set. Other control bits in UCR1, UCR2, and BRG registers will remain unaffected. If the UART is active and the UARTEN bit is cleared, all pending transmissions and receptions will be terminated and the module will be reset as defined above. When the UART is re-enabled it will restart in the same configuration. b 0 B N O P R E N P R T S T O P S T X B R K R X 8 T X 8 U C R 1 R e g is te r T r a n s m it d a ta b it 8 ( w r ite o n ly ) R e c e iv e d a ta b it 8 ( r e a d o n ly ) T r a n s m it b r e a k c h a r a c te r 1 : tr a n s m it b r e a k c h a r a c te r s 0 : n o b re a k c h a ra c te rs D e fin e s th e n u m b e r o f s to p b its 1 : tw o s to p b its 0 : o n e s to p b it P a r ity ty p e b it 1 : o d d p a r ity fo r p a r ity g e n e r a to r 0 : e v e n p a r ity fo r p a r ity g e n e r a to r P a r ity e n a b le b it 1 : p a r ity fu n c tio n e n a b le d 0 : p a r ity fu n c tio n d is a b le d N u m b e r o f d a ta tr a n s fe r b its 1 : 9 - b it d a ta tr a n s fe r 0 : 8 - b it d a ta tr a n s fe r U A R T e n a b le b it 1 : e n a b le U A R T , T X & R X p in s a s U A R T p in s 0 : d is a b le U A R T , T X & R X p in s a s I/O p o r t p in s Rev. 1.20 30 March 23, 2007 HT46RU22 · UCR2 register to ²0² and if the MCU is in the Power Down Mode, any edge transitions on the RX pin will not wake-up the device. The UCR2 register is the second of the two UART control registers and serves several purposes. One of its main functions is to control the basic enable/disable operation of the UART Transmitter and Receiver as well as enabling the various UART interrupt sources. The register also serves to control the baud rate speed, receiver wake-up enable and the address detect enable. Further explanation on each of the bits is given below: ¨ ADDEN The ADDEN bit is the address detect mode bit. When this bit is ²1² the address detect mode is enabled. When this occurs, if the 8th bit, which corresponds to RX7 if BNO=0, or the 9th bit, which corresponds to RX8 if BNO=1, has a value of ²1² then the received word will be identified as an address, rather than data. If the corresponding interrupt is enabled, an interrupt request will be generated each time the received word has the address bit set, which is the 8 or 9 bit depending on the value of BNO. If the address bit is ²0² an interrupt will not be generated, and the received data will be discarded. ¨ TEIE This bit enables or disables the transmitter empty interrupt. If this bit is equal to ²1² when the transmitter empty TXIF flag is set, due to a transmitter empty condition, the UART interrupt request flag will be set. If this bit is equal to ²0² the UART interrupt request flag will not be influenced by the condition of the TXIF flag. ¨ ¨ TIIE This bit enables or disables the transmitter idle interrupt. If this bit is equal to ²1² when the transmitter idle TIDLE flag is set, the UART interrupt request flag will be set. If this bit is equal to ²0² the UART interrupt request flag will not be influenced by the condition of the TIDLE flag. BRGH The BRGH bit selects the high or low speed mode of the Baud Rate Generator. This bit, together with the value placed in the BRG register, controls the Baud Rate of the UART. If this bit is equal to ²1² the high speed mode is selected. If the bit is equal to ²0² the low speed mode is selected. ¨ ¨ RIE This bit enables or disables the receiver interrupt. If this bit is equal to ²1² when the receiver overrun OERR flag or receive data available RXIF flag is set, the UART interrupt request flag will be set. If this bit is equal to ²0² the UART interrupt will not be influenced by the condition of the OERR or RXIF flags. ¨ WAKE This bit enables or disables the receiver wake-up function. If this bit is equal to ²1² and if the MCU is in the Power Down Mode, a low going edge on the RX input pin will wake-up the device. If this bit is equal RXEN The RXEN bit is the Receiver Enable Bit. When this bit is equal to ²0² the receiver will be disabled with any pending data receptions being aborted. In addition the buffer will be reset. In this situation the RX pin can be used as a general purpose I/O pin. If the RXEN bit is equal to ²1² the receiver will be enabled and if the UARTEN bit is equal to ²1² the RX pin will be controlled by the UART. Clearing the RXEN bit during a transmission will cause the data reception to be aborted and will reset the receiver. If this occurs, the RX pin can be used as a general purpose I/O pin. b 7 T X E N b 0 R X E N B R G H A D D E N W A K E R IE T IIE T E IE U C R 2 R e g is te r T r a n s m itte r e m p ty in te r r u p t e n a b le 1 : T X IF in te r r u p t r e q u e s t e n a b le 0 : T X IF in te r r u p t r e q u e s t d is a b le T r a n s m itte r id le in te r r u p t e n a b le 1 : T ID L E in te r r u p t r e q u e s t e n a b le 0 : T ID L E in te r r u p t r e q u e s t d is a b le R e c e iv e r in te r r u p t e n a b le 1 : R X IF in te r r u p t r e q u e s t e n a b le 0 : R X IF in te r r u p t r e q u e s t d is a b le D e fin e s th e R X w a k e u p e n a b le 1 : R X w a k e u p e n a b le ( fa llin g e d g e ) 0 : R X w a k e u p d is a b le A d d re s s d e te c t m o d e 1 : e n a b le 0 : d is a b le H ig h b a u d r a te s e le c t b it 1 : h ig h s p e e d 0 : lo w s p e e d R e c e iv e r e n a b le b it 1 : r e c e iv e r e n a b le 0 : r e c e iv e r d is a b le T r a n s m itte r e n a b le b it 1 : tr a n s m itte r e n a b le 0 : tr a n s m itte r d is a b le Rev. 1.20 31 March 23, 2007 HT46RU22 ¨ TXEN The TXEN bit is the Transmitter Enable Bit. When this bit is equal to ²0² the transmitter will be disabled with any pending transmissions being aborted. In addition the buffer will be reset. In this situation the TX pin can be used as a general purpose I/O pin. If the TXEN bit is equal to ²1² the transmitter will be enabled and if the UARTEN bit is equal to ²1² the TX pin will be controlled by the UART. Clearing the TXEN bit during a transmission will cause the transmission to be aborted and will reset the transmitter. If this occurs, the TX pin can be used as a general purpose I/O pin. By programming the BRGH bit which allows selection of the related formula and programming the required value in the BRG register, the required baud rate can be setup. Note that because the actual baud rate is determined using a discrete value, N, placed in the BRG register, there will be an error associated between the actual and requested value. The following example shows how the BRG register value N and the error value can be calculated. Calculating the register and error values For a clock frequency of 8MHz, and with BRGH set to ²0² determine the BRG register value N, the actual baud rate and the error value for a desired baud rate of 9600. From the above table the desired baud rate BR fSYS = [64 (N + 1)] fSYS Re-arranging this equation gives N = -1 (BRx64) 8000000 - 1 = 12.0208 Giving a value for N = (9600x 64) · Baud rate generator To setup the speed of the serial data communication, the UART function contains its own dedicated baud rate generator. The baud rate is controlled by its own internal free running 8-bit timer, the period of which is determined by two factors. The first of these is the value placed in the BRG register and the second is the value of the BRGH bit within the UCR2 control register. The BRGH bit decides, if the baud rate generator is to be used in a high speed mode or low speed mode, which in turn determines the formula that is used to calculate the baud rate. The value in the BRG register determines the division factor, N, which is used in the following baud rate calculation formula. Note that N is the decimal value placed in the BRG register and has a range of between 0 and 255. UCR2 BRGH Bit Baud Rate 0 1 fSYS [64 (N + 1)] fSYS [16 (N + 1)] To obtain the closest value, a decimal value of 12 should be placed into the BRG register. This gives an actual or calculated baud rate value of 8000000 BR = = 9615 [64(12 + 1)] Therefore the error is equal to = 0.16% The following tables show actual values of baud rate and error values for the two values of BRGH. Baud Rate K/BPS Baud Rates for BRGH=0 fSYS=8MHz fSYS=7.159MHz fSYS=4MHz fSYS=3.579545MHz BRG Kbaud Error BRG Kbaud Error BRG Kbaud Error BRG Kbaud Error 0.3 ¾ ¾ ¾ ¾ ¾ ¾ 207 0.300 0.00 185 0.300 0.00 1.2 103 1.202 0.16 92 1.203 0.23 51 1.202 0.16 46 1.19 -0.83 2.4 51 2.404 0.16 46 2.38 -0.83 25 2.404 0.16 22 2.432 1.32 4.8 25 4.807 0.16 22 4.863 1.32 12 4.808 0.16 11 4.661 -2.9 9.6 12 9.615 0.16 11 9.322 -2.9 6 8.929 -6.99 5 9.321 -2.9 19.2 6 17.857 -6.99 5 18.64 -2.9 2 20.83 8.51 2 18.643 -2.9 38.4 2 41.667 8.51 2 37.29 -2.9 1 ¾ ¾ 1 ¾ ¾ 57.6 1 62.5 8.51 1 55.93 -2.9 0 62.5 8.51 0 55.93 -2.9 115.2 0 125 8.51 0 111.86 -2.9 ¾ ¾ ¾ ¾ ¾ ¾ Baud Rates and Error Values for BRGH = 0 Rev. 1.20 32 March 23, 2007 HT46RU22 Baud Rate K/BPS Baud Rates for BRGH=1 fSYS=8MHz fSYS=7.159MHz fSYS=4MHz fSYS=3.579545MHz BRG Kbaud Error BRG Kbaud Error BRG Kbaud Error BRG Kbaud Error 0.3 ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ 1.2 ¾ ¾ ¾ ¾ ¾ ¾ 207 1.202 0.16 185 1.203 0.23 2.4 207 2.404 0.16 185 2.405 0.23 103 2.404 0.16 92 2.406 0.23 4.8 103 4.808 0.16 92 4.811 0.23 51 4.808 0.16 46 4.76 -0.83 9.6 51 9.615 0.16 46 9.520 -0.832 25 9.615 0.16 22 9.727 1.32 19.2 25 19.231 0.16 22 19.454 1.32 12 19.231 0.16 11 18.643 -2.9 38.4 12 38.462 0.16 11 37.287 -2.9 6 35.714 -6.99 5 37.286 -2.9 57.6 8 55.556 -3.55 7 55.93 -2.9 3 62.5 8.51 3 55.930 -2.9 115.2 3 125 8.51 3 111.86 -2.9 1 125 8.51 1 111.86 -2.9 250 1 250 0 ¾ ¾ ¾ 0 250 0 ¾ ¾ ¾ Baud Rates and Error Values for BRGH = 1 · Setting up and controlling the UART ¨ ¨ Clearing the UARTEN bit will disable the TX and RX pins and allow these two pins to be used as normal I/O pins. When the UART function is disabled the buffer will be reset to an empty condition, at the same time discarding any remaining residual data. Disabling the UART will also reset the error and status flags with bits TXEN, RXEN, TXBRK, RXIF, OERR, FERR, PERR and NF being cleared while bits TIDLE, TXIF and RIDLE will be set. The remaining control bits in the UCR1, UCR2 and BRG registers will remain unaffected. If the UARTEN bit in the UCR1 register is cleared while the UART is active, then all pending transmissions and receptions will be immediately suspended and the UART will be reset to a condition as defined above. If the UART is then subsequently re-enabled, it will restart again in the same configuration. Introduction For data transfer, the UART function utilizes a non-return-to-zero, more commonly known as NRZ, format. This is composed of one start bit, eight or nine data bits, and one or two stop bits. Parity is supported by the UART hardware, and can be setup to be even, odd or no parity. For the most common data format, 8 data bits along with no parity and one stop bit, denoted as 8, N, 1, is used as the default setting, which is the setting at power-on. The number of data bits and stop bits, along with the parity, are setup by programming the corresponding BNO, PRT, PREN, and STOPS bits in the UCR1 register. The baud rate used to transmit and receive data is setup using the internal 8-bit baud rate generator, while the data is transmitted and received LSB first. Although the UART¢s transmitter and receiver are functionally independent, they both use the same data format and baud rate. In all cases stop bits will be used for data transmission. ¨ Enabling/disabling the UART The basic on/off function of the internal UART function is controlled using the UARTEN bit in the UCR1 register. As the UART transmit and receive pins, TX and RX respectively, are pin-shared with normal I/O pins, one of the basic functions of the UARTEN control bit is to control the UART function of these two pins. If the UARTEN, TXEN and RXEN bits are set, then these two I/O pins will be setup as a TX output pin and an RX input pin respectively, in effect disabling the normal I/O pin function. If no data is being transmitted on the TX pin then it will default to a logic high value. Rev. 1.20 33 Data, parity and stop bit selection The format of the data to be transferred, is composed of various factors such as data bit length, parity on/off, parity type, address bits and the number of stop bits. These factors are determined by the setup of various bits within the UCR1 register. The BNO bit controls the number of data bits which can be set to either 8 or 9, the PRT bit controls the choice of odd or even parity, the PREN bit controls the parity on/off function and the STOPS bit decides whether one or two stop bits are to be used. The following table shows various formats for data transmission. The address bit identifies the frame as an address character. The number of stop bits, which can be either one or two, is independent of the data length. March 23, 2007 HT46RU22 Start Bit Data Bits Address Bits Parity Bits Stop Bit ¨ Example of 8-bit Data Formats 1 8 0 0 1 1 7 0 1 1 7 1 0 1 1 1 Example of 9-bit Data Formats 1 9 0 0 1 1 8 0 1 1 1 8 11 0 1 Transmitting data When the UART is transmitting data, the data is shifted on the TX pin from the shift register, with the least significant bit first. In the transmit mode, the TXR register forms a buffer between the internal bus and the transmitter shift register. It should be noted that if 9-bit data format has been selected, then the MSB will be taken from the TX8 bit in the UCR1 register. The steps to initiate a data transfer can be summarized as follows: - Make the correct selection of the BNO, PRT, PREN and STOPS bits to define the required word length, parity type and number of stop bits. - Setup the BRG register to select the desired baud rate. - Set the TXEN bit to ensure that the TX pin is used as a UART transmitter pin and not as an I/O pin. - Access the USR register and write the data that is to be transmitted into the TXR register. Note that this step will clear the TXIF bit. - This sequence of events can now be repeated to send additional data. Transmitter Receiver Data Format The following diagram shows the transmit and receive waveforms for both 8-bit and 9-bit data formats. · UART transmitter Data word lengths of either 8 or 9 bits, can be selected by programming the BNO bit in the UCR1 register. When BNO bit is set, the word length will be set to 9 bits. In this case the 9th bit, which is the MSB, needs to be stored in the TX8 bit in the UCR1 register. At the transmitter core lies the Transmitter Shift Register, more commonly known as the TSR, whose data is obtained from the transmit data register, which is known as the TXR register. The data to be transmitted is loaded into this TXR register by the application program. The TSR register is not written to with new data until the stop bit from the previous transmission has been sent out. As soon as this stop bit has been transmitted, the TSR can then be loaded with new data from the TXR register, if it is available. It should be noted that the TSR register, unlike many other registers, is not directly mapped into the Data Memory area and as such is not available to the application program for direct read/write operations. An actual transmission of data will normally be enabled when the TXEN bit is set, but the data will not be transmitted until the TXR register has been loaded with data and the baud rate generator has defined a shift clock source. However, the transmission can also be initiated by first loading data into the TXR register, after which the TXEN bit can be set. When a transmission of data begins, the TSR is normally empty, in which case a transfer to the TXR register will result in an immediate transfer to the TSR. If during a transmission the TXEN bit is cleared, the transmission will immediately cease and the transmitter will be reset. The TX output pin will then return to having a normal general purpose I/O pin function. It should be noted that when TXIF=0, data will be inhibited from being written to the TXR register. Clearing the TXIF flag is always achieved using the following software sequence: 1. A USR register access 2. A TXR register write execution The read-only TXIF flag is set by the UART hardware and if set indicates that the TXR register is empty and that other data can now be written into the TXR register without overwriting the previous data. If the TEIE bit is set then the TXIF flag will generate an interrupt. During a data transmission, a write instruction to the TXR register will place the data into the TXR register, which will be copied to the shift register at the end of the present transmission. When there is no data transmission in progress, a write instruction to the TXR register will place the data directly into the shift register, resulting in the commencement of data transmission, and the TXIF bit being immediately set. When a frame transmission is complete, which happens after stop bits are sent or after the break frame, the TIDLE bit will be set. To clear the TIDLE bit the following software sequence is used: 1. A USR register access 2. A TXR register write execution Note that both the TXIF and TIDLE bits are cleared by the same software sequence. P a r ity B it S ta r t B it B it 0 B it 1 B it 2 B it 3 B it 4 B it 5 B it 6 B it 7 S to p B it N e x t S ta rt B it 8 -B it D a ta F o r m a t P a r ity B it S ta r t B it B it 0 B it 1 B it 2 B it 3 B it 4 B it 5 B it 6 B it 7 B it 8 S to p B it N e x t S ta rt B it 9 -B it D a ta F o r m a t Rev. 1.20 34 March 23, 2007 HT46RU22 ¨ - Transmit break If the TXBRK bit is set then break characters will be sent on the next transmission. Break character transmission consists of a start bit, followed by 13´ N ¢0¢ bits and stop bits, where N=1, 2, etc. If a break character is to be transmitted then the TXBRK bit must be first set by the application program, then cleared to generate the stop bits. Transmitting a break character will not generate a transmit interrupt. Note that a break condition length is at least 13 bits long. If the TXBRK bit is continually kept at a logic high level then the transmitter circuitry will transmit continuous break characters. After the application program has cleared the TXBRK bit, the transmitter will finish transmitting the last break character and subsequently send out one or two stop bits. The automatic logic highs at the end of the last break character will ensure that the start bit of the next frame is recognized. At this point the receiver will be enabled which will begin to look for a start bit. When a character is received the following sequence of events will occur: Introduction The UART is capable of receiving word lengths of either 8 or 9 bits. If the BNO bit is set, the word length will be set to 9 bits with the MSB being stored in the RX8 bit of the UCR1 register. At the receiver core lies the Receive Serial Shift Register, commonly known as the RSR. The data which is received on the RX external input pin, is sent to the data recovery block. The data recovery block operating speed is 16 times that of the baud rate, while the main receive serial shifter operates at the baud rate. After the RX pin is sampled for the stop bit, the received data in RSR is transferred to the receive data register, if the register is empty. The data which is received on the external RX input pin is sampled three times by a majority detect circuit to determine the logic level that has been placed onto the RX pin. It should be noted that the RSR register, unlike many other registers, is not directly mapped into the Data Memory area and as such is not available to the application program for direct read/write operations. ¨ Receiving data When the UART receiver is receiving data, the data is serially shifted in on the external RX input pin, LSB first. In the read mode, the RXR register forms a buffer between the internal bus and the receiver shift register. The RXR register is a two byte deep FIFO data buffer, where two bytes can be held in the FIFO while a third byte can continue to be received. Note that the application program must ensure that the data is read from RXR before the third byte has been completely shifted in, otherwise this third byte will be discarded and an overrun error OERR will be subsequently indicated. The steps to initiate a data transfer can be summarized as follows: - Make the correct selection of BNO, PRT, PREN and STOPS bits to define the word length, parity type and number of stop bits. - Setup the BRG register to select the desired baud rate. Rev. 1.20 - The RXIF bit in the USR register will be set when RXR register has data available, at least one more character can be read. - When the contents of the shift register have been transferred to the RXR register, then if the RIE bit is set, an interrupt will be generated. - If during reception, a frame error, noise error, parity error, or an overrun error has been detected, then the error flags can be set. The RXIF bit can be cleared using the following software sequence: 1. A USR register access 2. An RXR register read execution · UART receiver ¨ Set the RXEN bit to ensure that the RX pin is used as a UART receiver pin and not as an I/O pin. ¨ ¨ 35 Receive break Any break character received by the UART will be managed as a framing error. The receiver will count and expect a certain number of bit times as specified by the values programmed into the BNO and STOPS bits. If the break is much longer than 13 bit times, the reception will be considered as complete after the number of bit times specified by BNO and STOPS. The RXIF bit is set, FERR is set, zeros are loaded into the receive data register, interrupts are generated if appropriate and the RIDLE bit is set. If a long break signal has been detected and the receiver has received a start bit, the data bits and the invalid stop bit, which sets the FERR flag, the receiver must wait for a valid stop bit before looking for the next start bit. The receiver will not make the assumption that the break condition on the line is the next start bit. A break is regarded as a character that contains only zeros with the FERR flag set. The break character will be loaded into the buffer and no further data will be received until stop bits are received. It should be noted that the RIDLE read only flag will go high when the stop bits have not yet been received. The reception of a break character on the UART registers will result in the following: - The framing error flag, FERR, will be set. - The receive data register, RXR, will be cleared. - The OERR, NF, PERR, RIDLE or RXIF flags will possibly be set. Idle status When the receiver is reading data, which means it will be in between the detection of a start bit and the reading of a stop bit, the receiver status flag in the USR register, otherwise known as the RIDLE flag, will have a zero value. In between the reception of a stop bit and the detection of the next start bit, the RIDLE flag will have a high value, which indicates the receiver is in an idle condition. March 23, 2007 HT46RU22 ¨ - Receiver interrupt The read only receive interrupt flag RXIF in the USR register is set by an edge generated by the receiver. An interrupt is generated if RIE=1, when a word is transferred from the Receive Shift Register, RSR, to the Receive Data Register, RXR. An overrun error can also generate an interrupt if RIE=1. No interrupt will be generated. However this bit rises at the same time as the RXIF bit which itself generates an interrupt. Note that the NF flag is reset by a USR register read operation followed by an RXR register read operation. ¨ Framing Error - FERR Flag The read only framing error flag, FERR, in the USR register, is set if a zero is detected instead of stop bits. If two stop bits are selected, both stop bits must be high, otherwise the FERR flag will be set. The FERR flag is buffered along with the received data and is cleared on any reset. ¨ Parity Error - PERR Flag The read only parity error flag, PERR, in the USR register, is set if the parity of the received word is incorrect. This error flag is only applicable if the parity is enabled, PREN = 1, and if the parity type, odd or even is selected. The read only PERR flag is buffered along with the received data bytes. It is cleared on any reset. It should be noted that the FERR and PERR flags are buffered along with the corresponding word and should be read before reading the data word. · Managing receiver errors Several types of reception errors can occur within the UART module, the following section describes the various types and how they are managed by the UART. ¨ Overrun Error - OERR flag The RXR register is composed of a two byte deep FIFO data buffer, where two bytes can be held in the FIFO register, while a third byte can continue to be received. Before this third byte has been entirely shifted in, the data should be read from the RXR register. If this is not done, the overrun error flag OERR will be consequently indicated. In the event of an overrun error occurring, the following will happen: - The OERR flag in the USR register will be set. - The RXR contents will not be lost. - The shift register will be overwritten. · UART interrupt scheme The UART internal function possesses its own internal interrupt and independent interrupt vector. Several individual UART conditions can generate an internal UART interrupt. These conditions are, a transmitter data register empty, transmitter idle, receiver data available, receiver overrun, address detect and an RX pin wake-up. When any of these conditions are created, if the UART interrupt is enabled and the stack is not full, the program will jump to the UART interrupt vector where it can be serviced before returning to the main program. Four of these conditions, have a corresponding USR register flag, which will generate a UART interrupt if its associated interrupt enable flag in - An interrupt will be generated if the RIE bit is set. The OERR flag can be cleared by an access to the USR register followed by a read to the RXR register. ¨ Noise Error - NF Flag Over-sampling is used for data recovery to identify valid incoming data and noise. If noise is detected within a frame the following will occur: - The read only noise flag, NF, in the USR register will be set on the rising edge of the RXIF bit. - Data will be transferred from the Shift register to the RXR register. U S R R e g is te r U C R 2 R e g is te r 0 T E IE T r a n s m itte r E m p ty F la g T X IF 1 IN T C 1 R e g is te r U A R T In te rru p t R e q u e s t F la g U R F 0 T IIE T r a n s m itte r Id le F la g T ID L E 1 R e c e iv e r O v e r r u n F la g O E R R R e c e iv e r D a ta A v a ila b le R X IF E M I 0 R IE O R E U R I IN T C 0 R e g is te r 1 0 A D D E N 1 0 1 R X P in W a k e -u p 0 W A K E R X 7 if B N O = 0 R X 8 if B N O = 1 1 U C R 2 R e g is te r UART Interrupt Scheme Rev. 1.20 36 March 23, 2007 HT46RU22 mode is enabled, then to ensure correct operation, the parity function should be disabled by resetting the parity enable bit to zero. the UCR2 register is set. The two transmitter interrupt conditions have their own corresponding enable bits, while the two receiver interrupt conditions have a shared enable bit. These enable bits can be used to mask out individual UART interrupt sources. The address detect condition, which is also a UART interrupt source, does not have an associated flag, but will generate a UART interrupt when an address detect condition occurs if its function is enabled by setting the ADDEN bit in the UCR2 register. An RX pin wake-up, which is also a UART interrupt source, does not have an associated flag, but will generate a UART interrupt if the microcontroller is woken up by a low going edge on the RX pin, if the WAKE and RIE bits in the UCR2 register are set. Note that in the event of an RX wake-up interrupt occurring, there will be a delay of 1024 system clock cycles before the system resumes normal operation. Note that the USR register flags are read only and cannot be cleared or set by the application program, neither will they be cleared when the program jumps to the corresponding interrupt servicing routine, as is the case for some of the other interrupts. The flags will be cleared automatically when certain actions are taken by the UART, the details of which are given in the UART register section. The overall UART interrupt can be disabled or enabled by the EURI bit in the INTC1 interrupt control register to prevent a UART interrupt from occurring. ADDEN 0 Ö 1 Ö 0 X 1 Ö 0 1 ADDEN Bit Function · UART operation in power down mode When the MCU is in the Power Down Mode the UART will cease to function. When the device enters the Power Down Mode, all clock sources to the module are shutdown. If the MCU enters the Power Down Mode while a transmission is still in progress, then the transmission will be terminated and the external TX transmit pin will be forced to a logic high level. In a similar way, if the MCU enters the Power Down Mode while receiving data, then the reception of data will likewise be terminated. When the MCU enters the Power Down Mode, note that the USR, UCR1, UCR2, transmit and receive registers, as well as the BRG register will not be affected. The UART function contains a receiver RX pin wake-up function, which is enabled or disabled by the WAKE bit in the UCR2 register. If this bit, along with the UART enable bit, UARTEN, the receiver enable bit, RXEN and the receiver interrupt bit, RIE, are all set before the MCU enters the Power Down Mode, then a falling edge on the RX pin will wake-up the MCU from the Power Down Mode. Note that as it takes 1024 system clock cycles after a wake-up, before normal microcontroller operation resumes, any data received during this time on the RX pin will be ignored. For a UART wake-up interrupt to occur, in addition to the bits for the wake-up being set, the global interrupt enable bit, EMI, and the UART interrupt enable bit, EURI must also be set. If these two bits are not set then only a wake up event will occur and no interrupt will be generated. Note also that as it takes 1024 system clock cycles after a wake-up before normal microcontroller resumes, the UART interrupt will not be generated until after this time has elapsed. · Address detect mode Setting the Address Detect Mode bit, ADDEN, in the UCR2 register, enables this special mode. If this bit is enabled then an additional qualifier will be placed on the generation of a Receiver Data Available interrupt, which is requested by the RXIF flag. If the ADDEN bit is enabled, then when data is available, an interrupt will only be generated, if the highest received bit has a high value. Note that the EURI and EMI interrupt enable bits must also be enabled for correct interrupt generation. This highest address bit is the 9th bit if BNO=1 or the 8th bit if BNO=0. If this bit is high, then the received word will be defined as an address rather than data. A Data Available interrupt will be generated every time the last bit of the received word is set. If the ADDEN bit is not enabled, then a Receiver Data Available interrupt will be generated each time the RXIF flag is set, irrespective of the data last bit status. The address detect mode and parity enable are mutually exclusive functions. Therefore if the address detect Rev. 1.20 Bit 9 if BNO=1, UART Interrupt Bit 8 if BNO=0 Generated 37 March 23, 2007 HT46RU22 Options The following shows ten kinds of options in the microcontroller. ALL the options must be defined to ensure proper system function. No. Options 1 OSC type selection. This option is to decide if an RC or crystal oscillator is chosen as system clock. 2 WDT source selection. There are three types of selection: On-chip RC oscillator, instruction clock or disable the WDT. 3 CLRWDT times selection. This option defines how to clear the WDT by instruction. ²One time² means that the CLR WDT instruction can clear the WDT. ²Two times² means only if both of the CLR WDT1 and CLR WDT2 instructions have been executed, then WDT can be cleared. 4 Wake-up selection. This option defines the wake-up function activity. External I/O pins (PA only) all have the capability to wake-up the chip from a HALT. 5 Pull-high selection. This option is to decide whether a pull-high resistance is visible or not in the input mode of the I/O ports. PA0~PA7, can be independently selected. 6 PFD selection. PA3: Level output or PFD output 7 PWM selection: (7+1) or (6+2) mode PD0: Level output or PWM output 8 WDT time-out period selection. 212/fS~213/fS, 213/fS~214/fS, 214/fS~215/fS, 215/fS~216/fS. 9 Low voltage reset selection: Enable or disable LVR function. 10 I2C Bus function: Enable or disable Rev. 1.20 38 March 23, 2007 HT46RU22 Application Circuits V D D 0 .0 1 m F * P A 0 ~ P A 2 V D D P A 3 /P F D 1 0 0 k W V P A 4 /T M R 0 .1 m F R E S 4 7 0 p F P A 5 /IN T 1 0 k W P A 6 /S D A 0 .1 m F * R P A 7 /S C L V S S O S C 1 O S C 2 C 1 P C 0 /T X P C 1 /R X C 2 O S C 1 fS H T 4 6 R U 2 2 Y S /4 R C S y s te m O s c illa to r 3 0 k W < R O S C < 7 5 0 k W O S C 2 O S C 1 R 1 P D 0 /P W M S e e R ig h t S id e O S C P B 0 /A N 0 P B 7 /A N 7 ~ O S C C ir c u it D D C ry s ta l S y s te m F o r th e v a lu e s , s e e ta b le b e lo w O s c illa to r O S C 2 O S C C ir c u it The following table shows the C1, C2 and R1 values corresponding to the different crystal values. (For reference only) Crystal or Resonator C1, C2 R1 4MHz Crystal 0pF 10kW 4MHz Resonator 10pF 12kW 3.58MHz Crystal 0pF 10kW 3.58MHz Resonator 25pF 10kW 2MHz Crystal & Resonator 25pF 10kW 1MHz Crystal 35pF 27kW 480kHz Resonator 300pF 9.1kW 455kHz Resonator 300pF 10kW 429kHz Resonator 300pF 10kW The function of the resistor R1 is to ensure that the oscillator will switch off should low voltage conditions occur. Such a low voltage, as mentioned here, is one which is less than the lowest value of the MCU operating voltage. Note however that if the LVR is enabled then R1 can be removed. Note: The resistance and capacitance for reset circuit should be designed in such a way as to ensure that the VDD is stable and remains within a valid operating voltage range before bringing RES to high. ²*² Make the length of the wiring, which is connected to the RES pin as short as possible, to avoid noise interference. Rev. 1.20 39 March 23, 2007 HT46RU22 Instruction Set Summary Description Instruction Cycle Flag Affected Add data memory to ACC Add ACC to data memory Add immediate data to ACC Add data memory to ACC with carry Add ACC to data memory with carry Subtract immediate data from ACC Subtract data memory from ACC Subtract data memory from ACC with result in data memory Subtract data memory from ACC with carry Subtract data memory from ACC with carry and result in data memory Decimal adjust ACC for addition with result in data memory 1 1(1) 1 1 1(1) 1 1 1(1) 1 1(1) 1(1) Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV C 1 1 1 1(1) 1(1) 1(1) 1 1 1 1(1) 1 Z Z Z Z Z Z Z Z Z Z Z Increment data memory with result in ACC Increment data memory Decrement data memory with result in ACC Decrement data memory 1 1(1) 1 1(1) Z Z Z Z Rotate data memory right with result in ACC Rotate data memory right Rotate data memory right through carry with result in ACC Rotate data memory right through carry Rotate data memory left with result in ACC Rotate data memory left Rotate data memory left through carry with result in ACC Rotate data memory left through carry 1 1(1) 1 1(1) 1 1(1) 1 1(1) None None C C None None C C Move data memory to ACC Move ACC to data memory Move immediate data to ACC 1 1(1) 1 None None None Clear bit of data memory Set bit of data memory 1(1) 1(1) None None Mnemonic Arithmetic ADD A,[m] ADDM A,[m] ADD A,x ADC A,[m] ADCM A,[m] SUB A,x SUB A,[m] SUBM A,[m] SBC A,[m] SBCM A,[m] DAA [m] Logic Operation AND A,[m] OR A,[m] XOR A,[m] ANDM A,[m] ORM A,[m] XORM A,[m] AND A,x OR A,x XOR A,x CPL [m] CPLA [m] AND data memory to ACC OR data memory to ACC Exclusive-OR data memory to ACC AND ACC to data memory OR ACC to data memory Exclusive-OR ACC to data memory AND immediate data to ACC OR immediate data to ACC Exclusive-OR immediate data to ACC Complement data memory Complement data memory with result in ACC Increment & Decrement INCA [m] INC [m] DECA [m] DEC [m] Rotate RRA [m] RR [m] RRCA [m] RRC [m] RLA [m] RL [m] RLCA [m] RLC [m] Data Move MOV A,[m] MOV [m],A MOV A,x Bit Operation CLR [m].i SET [m].i Rev. 1.20 40 March 23, 2007 HT46RU22 Instruction Cycle Flag Affected Jump unconditionally Skip if data memory is zero Skip if data memory is zero with data movement to ACC Skip if bit i of data memory is zero Skip if bit i of data memory is not zero Skip if increment data memory is zero Skip if decrement data memory is zero Skip if increment data memory is zero with result in ACC Skip if decrement data memory is zero with result in ACC Subroutine call Return from subroutine Return from subroutine and load immediate data to ACC Return from interrupt 2 1(2) 1(2) 1(2) 1(2) 1(3) 1(3) 1(2) 1(2) 2 2 2 2 None None None None None None None None None None None None None Read ROM code (current page) to data memory and TBLH Read ROM code (last page) to data memory and TBLH 2(1) 2(1) None None No operation Clear data memory Set data memory Clear Watchdog Timer Pre-clear Watchdog Timer Pre-clear Watchdog Timer Swap nibbles of data memory Swap nibbles of data memory with result in ACC Enter power down mode 1 1(1) 1(1) 1 1 1 1(1) 1 1 None None None TO,PDF TO(4),PDF(4) TO(4),PDF(4) None None TO,PDF Mnemonic Description Branch JMP addr SZ [m] SZA [m] SZ [m].i SNZ [m].i SIZ [m] SDZ [m] SIZA [m] SDZA [m] CALL addr RET RET A,x RETI Table Read TABRDC [m] TABRDL [m] Miscellaneous NOP CLR [m] SET [m] CLR WDT CLR WDT1 CLR WDT2 SWAP [m] SWAPA [m] HALT Note: x: Immediate data m: Data memory address A: Accumulator i: 0~7 number of bits addr: Program memory address Ö: Flag is affected -: Flag is not affected (1) : If a loading to the PCL register occurs, the execution cycle of instructions will be delayed for one more cycle (four system clocks). (2) : If a skipping to the next instruction occurs, the execution cycle of instructions will be delayed for one more cycle (four system clocks). Otherwise the original instruction cycle is unchanged. (3) (1) : (4) Rev. 1.20 and (2) : The flags may be affected by the execution status. If the Watchdog Timer is cleared by executing the CLR WDT1 or CLR WDT2 instruction, the TO and PDF are cleared. Otherwise the TO and PDF flags remain unchanged. 41 March 23, 2007 HT46RU22 Instruction Definition ADC A,[m] Add data memory and carry to the accumulator Description The contents of the specified data memory, accumulator and the carry flag are added simultaneously, leaving the result in the accumulator. Operation ACC ¬ ACC+[m]+C Affected flag(s) TO PDF OV Z AC C ¾ ¾ Ö Ö Ö Ö ADCM A,[m] Add the accumulator and carry to data memory Description The contents of the specified data memory, accumulator and the carry flag are added simultaneously, leaving the result in the specified data memory. Operation [m] ¬ ACC+[m]+C Affected flag(s) TO PDF OV Z AC C ¾ ¾ Ö Ö Ö Ö ADD A,[m] Add data memory to the accumulator Description The contents of the specified data memory and the accumulator are added. The result is stored in the accumulator. Operation ACC ¬ ACC+[m] Affected flag(s) TO PDF OV Z AC C ¾ ¾ Ö Ö Ö Ö ADD A,x Add immediate data to the accumulator Description The contents of the accumulator and the specified data are added, leaving the result in the accumulator. Operation ACC ¬ ACC+x Affected flag(s) TO PDF OV Z AC C ¾ ¾ Ö Ö Ö Ö ADDM A,[m] Add the accumulator to the data memory Description The contents of the specified data memory and the accumulator are added. The result is stored in the data memory. Operation [m] ¬ ACC+[m] Affected flag(s) Rev. 1.20 TO PDF OV Z AC C ¾ ¾ Ö Ö Ö Ö 42 March 23, 2007 HT46RU22 AND A,[m] Logical AND accumulator with data memory Description Data in the accumulator and the specified data memory perform a bitwise logical_AND operation. The result is stored in the accumulator. Operation ACC ¬ ACC ²AND² [m] Affected flag(s) TO PDF OV Z AC C ¾ ¾ ¾ Ö ¾ ¾ AND A,x Logical AND immediate data to the accumulator Description Data in the accumulator and the specified data perform a bitwise logical_AND operation. The result is stored in the accumulator. Operation ACC ¬ ACC ²AND² x Affected flag(s) TO PDF OV Z AC C ¾ ¾ ¾ Ö ¾ ¾ ANDM A,[m] Logical AND data memory with the accumulator Description Data in the specified data memory and the accumulator perform a bitwise logical_AND operation. The result is stored in the data memory. Operation [m] ¬ ACC ²AND² [m] Affected flag(s) TO PDF OV Z AC C ¾ ¾ ¾ Ö ¾ ¾ CALL addr Subroutine call Description The instruction unconditionally calls a subroutine located at the indicated address. The program counter increments once to obtain the address of the next instruction, and pushes this onto the stack. The indicated address is then loaded. Program execution continues with the instruction at this address. Operation Stack ¬ Program Counter+1 Program Counter ¬ addr Affected flag(s) TO PDF OV Z AC C ¾ ¾ ¾ ¾ ¾ ¾ CLR [m] Clear data memory Description The contents of the specified data memory are cleared to 0. Operation [m] ¬ 00H Affected flag(s) Rev. 1.20 TO PDF OV Z AC C ¾ ¾ ¾ ¾ ¾ ¾ 43 March 23, 2007 HT46RU22 CLR [m].i Clear bit of data memory Description The bit i of the specified data memory is cleared to 0. Operation [m].i ¬ 0 Affected flag(s) TO PDF OV Z AC C ¾ ¾ ¾ ¾ ¾ ¾ CLR WDT Clear Watchdog Timer Description The WDT is cleared (clears the WDT). The power down bit (PDF) and time-out bit (TO) are cleared. Operation WDT ¬ 00H PDF and TO ¬ 0 Affected flag(s) TO PDF OV Z AC C 0 0 ¾ ¾ ¾ ¾ CLR WDT1 Preclear Watchdog Timer Description Together with CLR WDT2, clears the WDT. PDF and TO are also cleared. Only execution of this instruction without the other preclear instruction just sets the indicated flag which implies this instruction has been executed and the TO and PDF flags remain unchanged. Operation WDT ¬ 00H* PDF and TO ¬ 0* Affected flag(s) TO PDF OV Z AC C 0* 0* ¾ ¾ ¾ ¾ CLR WDT2 Preclear Watchdog Timer Description Together with CLR WDT1, clears the WDT. PDF and TO are also cleared. Only execution of this instruction without the other preclear instruction, sets the indicated flag which implies this instruction has been executed and the TO and PDF flags remain unchanged. Operation WDT ¬ 00H* PDF and TO ¬ 0* Affected flag(s) TO PDF OV Z AC C 0* 0* ¾ ¾ ¾ ¾ CPL [m] Complement data memory Description Each bit of the specified data memory is logically complemented (1¢s complement). Bits which previously contained a 1 are changed to 0 and vice-versa. Operation [m] ¬ [m] Affected flag(s) Rev. 1.20 TO PDF OV Z AC C ¾ ¾ ¾ Ö ¾ ¾ 44 March 23, 2007 HT46RU22 CPLA [m] Complement data memory and place result in the accumulator Description Each bit of the specified data memory is logically complemented (1¢s complement). Bits which previously contained a 1 are changed to 0 and vice-versa. The complemented result is stored in the accumulator and the contents of the data memory remain unchanged. Operation ACC ¬ [m] Affected flag(s) TO PDF OV Z AC C ¾ ¾ ¾ Ö ¾ ¾ DAA [m] Decimal-Adjust accumulator for addition Description The accumulator value is adjusted to the BCD (Binary Coded Decimal) code. The accumulator is divided into two nibbles. Each nibble is adjusted to the BCD code and an internal carry (AC1) will be done if the low nibble of the accumulator is greater than 9. The BCD adjustment is done by adding 6 to the original value if the original value is greater than 9 or a carry (AC or C) is set; otherwise the original value remains unchanged. The result is stored in the data memory and only the carry flag (C) may be affected. Operation If ACC.3~ACC.0 >9 or AC=1 then [m].3~[m].0 ¬ (ACC.3~ACC.0)+6, AC1=AC else [m].3~[m].0 ¬ (ACC.3~ACC.0), AC1=0 and If ACC.7~ACC.4+AC1 >9 or C=1 then [m].7~[m].4 ¬ ACC.7~ACC.4+6+AC1,C=1 else [m].7~[m].4 ¬ ACC.7~ACC.4+AC1,C=C Affected flag(s) TO PDF OV Z AC C ¾ ¾ ¾ ¾ ¾ Ö DEC [m] Decrement data memory Description Data in the specified data memory is decremented by 1. Operation [m] ¬ [m]-1 Affected flag(s) TO PDF OV Z AC C ¾ ¾ ¾ Ö ¾ ¾ DECA [m] Decrement data memory and place result in the accumulator Description Data in the specified data memory is decremented by 1, leaving the result in the accumulator. The contents of the data memory remain unchanged. Operation ACC ¬ [m]-1 Affected flag(s) Rev. 1.20 TO PDF OV Z AC C ¾ ¾ ¾ Ö ¾ ¾ 45 March 23, 2007 HT46RU22 HALT Enter power down mode Description This instruction stops program execution and turns off the system clock. The contents of the RAM and registers are retained. The WDT and prescaler are cleared. The power down bit (PDF) is set and the WDT time-out bit (TO) is cleared. Operation Program Counter ¬ Program Counter+1 PDF ¬ 1 TO ¬ 0 Affected flag(s) TO PDF OV Z AC C 0 1 ¾ ¾ ¾ ¾ INC [m] Increment data memory Description Data in the specified data memory is incremented by 1 Operation [m] ¬ [m]+1 Affected flag(s) TO PDF OV Z AC C ¾ ¾ ¾ Ö ¾ ¾ INCA [m] Increment data memory and place result in the accumulator Description Data in the specified data memory is incremented by 1, leaving the result in the accumulator. The contents of the data memory remain unchanged. Operation ACC ¬ [m]+1 Affected flag(s) TO PDF OV Z AC C ¾ ¾ ¾ Ö ¾ ¾ JMP addr Directly jump Description The program counter are replaced with the directly-specified address unconditionally, and control is passed to this destination. Operation Program Counter ¬addr Affected flag(s) TO PDF OV Z AC C ¾ ¾ ¾ ¾ ¾ ¾ MOV A,[m] Move data memory to the accumulator Description The contents of the specified data memory are copied to the accumulator. Operation ACC ¬ [m] Affected flag(s) Rev. 1.20 TO PDF OV Z AC C ¾ ¾ ¾ ¾ ¾ ¾ 46 March 23, 2007 HT46RU22 MOV A,x Move immediate data to the accumulator Description The 8-bit data specified by the code is loaded into the accumulator. Operation ACC ¬ x Affected flag(s) TO PDF OV Z AC C ¾ ¾ ¾ ¾ ¾ ¾ MOV [m],A Move the accumulator to data memory Description The contents of the accumulator are copied to the specified data memory (one of the data memories). Operation [m] ¬ACC Affected flag(s) TO PDF OV Z AC C ¾ ¾ ¾ ¾ ¾ ¾ NOP No operation Description No operation is performed. Execution continues with the next instruction. Operation Program Counter ¬ Program Counter+1 Affected flag(s) TO PDF OV Z AC C ¾ ¾ ¾ ¾ ¾ ¾ OR A,[m] Logical OR accumulator with data memory Description Data in the accumulator and the specified data memory (one of the data memories) perform a bitwise logical_OR operation. The result is stored in the accumulator. Operation ACC ¬ ACC ²OR² [m] Affected flag(s) TO PDF OV Z AC C ¾ ¾ ¾ Ö ¾ ¾ OR A,x Logical OR immediate data to the accumulator Description Data in the accumulator and the specified data perform a bitwise logical_OR operation. The result is stored in the accumulator. Operation ACC ¬ ACC ²OR² x Affected flag(s) TO PDF OV Z AC C ¾ ¾ ¾ Ö ¾ ¾ ORM A,[m] Logical OR data memory with the accumulator Description Data in the data memory (one of the data memories) and the accumulator perform a bitwise logical_OR operation. The result is stored in the data memory. Operation [m] ¬ACC ²OR² [m] Affected flag(s) Rev. 1.20 TO PDF OV Z AC C ¾ ¾ ¾ Ö ¾ ¾ 47 March 23, 2007 HT46RU22 RET Return from subroutine Description The program counter is restored from the stack. This is a 2-cycle instruction. Operation Program Counter ¬ Stack Affected flag(s) TO PDF OV Z AC C ¾ ¾ ¾ ¾ ¾ ¾ RET A,x Return and place immediate data in the accumulator Description The program counter is restored from the stack and the accumulator loaded with the specified 8-bit immediate data. Operation Program Counter ¬ Stack ACC ¬ x Affected flag(s) TO PDF OV Z AC C ¾ ¾ ¾ ¾ ¾ ¾ RETI Return from interrupt Description The program counter is restored from the stack, and interrupts are enabled by setting the EMI bit. EMI is the enable master (global) interrupt bit. Operation Program Counter ¬ Stack EMI ¬ 1 Affected flag(s) TO PDF OV Z AC C ¾ ¾ ¾ ¾ ¾ ¾ RL [m] Rotate data memory left Description The contents of the specified data memory are rotated 1 bit left with bit 7 rotated into bit 0. Operation [m].(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6) [m].0 ¬ [m].7 Affected flag(s) TO PDF OV Z AC C ¾ ¾ ¾ ¾ ¾ ¾ RLA [m] Rotate data memory left and place result in the accumulator Description Data in the specified data memory is rotated 1 bit left with bit 7 rotated into bit 0, leaving the rotated result in the accumulator. The contents of the data memory remain unchanged. Operation ACC.(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6) ACC.0 ¬ [m].7 Affected flag(s) Rev. 1.20 TO PDF OV Z AC C ¾ ¾ ¾ ¾ ¾ ¾ 48 March 23, 2007 HT46RU22 RLC [m] Rotate data memory left through carry Description The contents of the specified data memory and the carry flag are rotated 1 bit left. Bit 7 replaces the carry bit; the original carry flag is rotated into the bit 0 position. Operation [m].(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6) [m].0 ¬ C C ¬ [m].7 Affected flag(s) TO PDF OV Z AC C ¾ ¾ ¾ ¾ ¾ Ö RLCA [m] Rotate left through carry and place result in the accumulator Description Data in the specified data memory and the carry flag are rotated 1 bit left. Bit 7 replaces the carry bit and the original carry flag is rotated into bit 0 position. The rotated result is stored in the accumulator but the contents of the data memory remain unchanged. Operation ACC.(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6) ACC.0 ¬ C C ¬ [m].7 Affected flag(s) TO PDF OV Z AC C ¾ ¾ ¾ ¾ ¾ Ö RR [m] Rotate data memory right Description The contents of the specified data memory are rotated 1 bit right with bit 0 rotated to bit 7. Operation [m].i ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6) [m].7 ¬ [m].0 Affected flag(s) TO PDF OV Z AC C ¾ ¾ ¾ ¾ ¾ ¾ RRA [m] Rotate right and place result in the accumulator Description Data in the specified data memory is rotated 1 bit right with bit 0 rotated into bit 7, leaving the rotated result in the accumulator. The contents of the data memory remain unchanged. Operation ACC.(i) ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6) ACC.7 ¬ [m].0 Affected flag(s) TO PDF OV Z AC C ¾ ¾ ¾ ¾ ¾ ¾ RRC [m] Rotate data memory right through carry Description The contents of the specified data memory and the carry flag are together rotated 1 bit right. Bit 0 replaces the carry bit; the original carry flag is rotated into the bit 7 position. Operation [m].i ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6) [m].7 ¬ C C ¬ [m].0 Affected flag(s) Rev. 1.20 TO PDF OV Z AC C ¾ ¾ ¾ ¾ ¾ Ö 49 March 23, 2007 HT46RU22 RRCA [m] Rotate right through carry and place result in the accumulator Description Data of the specified data memory and the carry flag are rotated 1 bit right. Bit 0 replaces the carry bit and the original carry flag is rotated into the bit 7 position. The rotated result is stored in the accumulator. The contents of the data memory remain unchanged. Operation ACC.i ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6) ACC.7 ¬ C C ¬ [m].0 Affected flag(s) TO PDF OV Z AC C ¾ ¾ ¾ ¾ ¾ Ö SBC A,[m] Subtract data memory and carry from the accumulator Description The contents of the specified data memory and the complement of the carry flag are subtracted from the accumulator, leaving the result in the accumulator. Operation ACC ¬ ACC+[m]+C Affected flag(s) TO PDF OV Z AC C ¾ ¾ Ö Ö Ö Ö SBCM A,[m] Subtract data memory and carry from the accumulator Description The contents of the specified data memory and the complement of the carry flag are subtracted from the accumulator, leaving the result in the data memory. Operation [m] ¬ ACC+[m]+C Affected flag(s) TO PDF OV Z AC C ¾ ¾ Ö Ö Ö Ö SDZ [m] Skip if decrement data memory is 0 Description The contents of the specified data memory are decremented by 1. If the result is 0, the next instruction is skipped. If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Operation Skip if ([m]-1)=0, [m] ¬ ([m]-1) Affected flag(s) TO PDF OV Z AC C ¾ ¾ ¾ ¾ ¾ ¾ SDZA [m] Decrement data memory and place result in ACC, skip if 0 Description The contents of the specified data memory are decremented by 1. If the result is 0, the next instruction is skipped. The result is stored in the accumulator but the data memory remains unchanged. If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Operation Skip if ([m]-1)=0, ACC ¬ ([m]-1) Affected flag(s) Rev. 1.20 TO PDF OV Z AC C ¾ ¾ ¾ ¾ ¾ ¾ 50 March 23, 2007 HT46RU22 SET [m] Set data memory Description Each bit of the specified data memory is set to 1. Operation [m] ¬ FFH Affected flag(s) TO PDF OV Z AC C ¾ ¾ ¾ ¾ ¾ ¾ SET [m]. i Set bit of data memory Description Bit i of the specified data memory is set to 1. Operation [m].i ¬ 1 Affected flag(s) TO PDF OV Z AC C ¾ ¾ ¾ ¾ ¾ ¾ SIZ [m] Skip if increment data memory is 0 Description The contents of the specified data memory are incremented by 1. If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Operation Skip if ([m]+1)=0, [m] ¬ ([m]+1) Affected flag(s) TO PDF OV Z AC C ¾ ¾ ¾ ¾ ¾ ¾ SIZA [m] Increment data memory and place result in ACC, skip if 0 Description The contents of the specified data memory are incremented by 1. If the result is 0, the next instruction is skipped and the result is stored in the accumulator. The data memory remains unchanged. If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Operation Skip if ([m]+1)=0, ACC ¬ ([m]+1) Affected flag(s) TO PDF OV Z AC C ¾ ¾ ¾ ¾ ¾ ¾ SNZ [m].i Skip if bit i of the data memory is not 0 Description If bit i of the specified data memory is not 0, the next instruction is skipped. If bit i of the data memory is not 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Operation Skip if [m].i¹0 Affected flag(s) Rev. 1.20 TO PDF OV Z AC C ¾ ¾ ¾ ¾ ¾ ¾ 51 March 23, 2007 HT46RU22 SUB A,[m] Subtract data memory from the accumulator Description The specified data memory is subtracted from the contents of the accumulator, leaving the result in the accumulator. Operation ACC ¬ ACC+[m]+1 Affected flag(s) TO PDF OV Z AC C ¾ ¾ Ö Ö Ö Ö SUBM A,[m] Subtract data memory from the accumulator Description The specified data memory is subtracted from the contents of the accumulator, leaving the result in the data memory. Operation [m] ¬ ACC+[m]+1 Affected flag(s) TO PDF OV Z AC C ¾ ¾ Ö Ö Ö Ö SUB A,x Subtract immediate data from the accumulator Description The immediate data specified by the code is subtracted from the contents of the accumulator, leaving the result in the accumulator. Operation ACC ¬ ACC+x+1 Affected flag(s) TO PDF OV Z AC C ¾ ¾ Ö Ö Ö Ö SWAP [m] Swap nibbles within the data memory Description The low-order and high-order nibbles of the specified data memory (1 of the data memories) are interchanged. Operation [m].3~[m].0 « [m].7~[m].4 Affected flag(s) TO PDF OV Z AC C ¾ ¾ ¾ ¾ ¾ ¾ SWAPA [m] Swap data memory and place result in the accumulator Description The low-order and high-order nibbles of the specified data memory are interchanged, writing the result to the accumulator. The contents of the data memory remain unchanged. Operation ACC.3~ACC.0 ¬ [m].7~[m].4 ACC.7~ACC.4 ¬ [m].3~[m].0 Affected flag(s) Rev. 1.20 TO PDF OV Z AC C ¾ ¾ ¾ ¾ ¾ ¾ 52 March 23, 2007 HT46RU22 SZ [m] Skip if data memory is 0 Description If the contents of the specified data memory are 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Operation Skip if [m]=0 Affected flag(s) TO PDF OV Z AC C ¾ ¾ ¾ ¾ ¾ ¾ SZA [m] Move data memory to ACC, skip if 0 Description The contents of the specified data memory are copied to the accumulator. If the contents is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Operation Skip if [m]=0 Affected flag(s) TO PDF OV Z AC C ¾ ¾ ¾ ¾ ¾ ¾ SZ [m].i Skip if bit i of the data memory is 0 Description If bit i of the specified data memory is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Operation Skip if [m].i=0 Affected flag(s) TO PDF OV Z AC C ¾ ¾ ¾ ¾ ¾ ¾ TABRDC [m] Move the ROM code (current page) to TBLH and data memory Description The low byte of ROM code (current page) addressed by the table pointer (TBLP) is moved to the specified data memory and the high byte transferred to TBLH directly. Operation [m] ¬ ROM code (low byte) TBLH ¬ ROM code (high byte) Affected flag(s) TO PDF OV Z AC C ¾ ¾ ¾ ¾ ¾ ¾ TABRDL [m] Move the ROM code (last page) to TBLH and data memory Description The low byte of ROM code (last page) addressed by the table pointer (TBLP) is moved to the data memory and the high byte transferred to TBLH directly. Operation [m] ¬ ROM code (low byte) TBLH ¬ ROM code (high byte) Affected flag(s) Rev. 1.20 TO PDF OV Z AC C ¾ ¾ ¾ ¾ ¾ ¾ 53 March 23, 2007 HT46RU22 XOR A,[m] Logical XOR accumulator with data memory Description Data in the accumulator and the indicated data memory perform a bitwise logical Exclusive_OR operation and the result is stored in the accumulator. Operation ACC ¬ ACC ²XOR² [m] Affected flag(s) TO PDF OV Z AC C ¾ ¾ ¾ Ö ¾ ¾ XORM A,[m] Logical XOR data memory with the accumulator Description Data in the indicated data memory and the accumulator perform a bitwise logical Exclusive_OR operation. The result is stored in the data memory. The 0 flag is affected. Operation [m] ¬ ACC ²XOR² [m] Affected flag(s) TO PDF OV Z AC C ¾ ¾ ¾ Ö ¾ ¾ XOR A,x Logical XOR immediate data to the accumulator Description Data in the accumulator and the specified data perform a bitwise logical Exclusive_OR operation. The result is stored in the accumulator. The 0 flag is affected. Operation ACC ¬ ACC ²XOR² x Affected flag(s) Rev. 1.20 TO PDF OV Z AC C ¾ ¾ ¾ Ö ¾ ¾ 54 March 23, 2007 HT46RU22 Package Information 24-pin SKDIP (300mil) Outline Dimensions A B 2 4 1 3 1 1 2 H C D E Symbol Rev. 1.20 F a G I Dimensions in mil Min. Nom. Max. A 1235 ¾ 1265 B 255 ¾ 265 C 125 ¾ 135 D 125 ¾ 145 E 16 ¾ 20 F 50 ¾ 70 G ¾ 100 ¾ H 295 ¾ 315 I 345 ¾ 360 a 0° ¾ 15° 55 March 23, 2007 HT46RU22 24-pin SOP (300mil) Outline Dimensions 1 3 2 4 A B 1 2 1 C C ' G H D E Symbol Rev. 1.20 a F Dimensions in mil Min. Nom. Max. A 394 ¾ 419 B 290 ¾ 300 C 14 ¾ 20 C¢ 590 ¾ 614 D 92 ¾ 104 E ¾ 50 ¾ F 4 ¾ ¾ G 32 ¾ 38 H 4 ¾ 12 a 0° ¾ 10° 56 March 23, 2007 HT46RU22 24-pin SSOP (150mil) Outline Dimensions 1 3 2 4 A B 1 2 1 C C ' G H D E Symbol Rev. 1.20 a F Dimensions in mil Min. Nom. Max. A 228 ¾ 244 B 150 ¾ 157 C 8 ¾ 12 C¢ 335 ¾ 346 D 54 ¾ 60 E ¾ 25 ¾ F 4 ¾ 10 G 22 ¾ 28 H 7 ¾ 10 a 0° ¾ 8° 57 March 23, 2007 HT46RU22 Product Tape and Reel Specifications Reel Dimensions D T 2 A C B T 1 SOP 24W Symbol Description Dimensions in mm A Reel Outer Diameter 330±1.0 B Reel Inner Diameter 62±1.5 C Spindle Hole Diameter 13.0+0.5 -0.2 D Key Slit Width 2.0±0.5 T1 Space Between Flange 24.8+0.3 -0.2 T2 Reel Thickness 30.2±0.2 SSOP 24S (150mil) Symbol Description Dimensions in mm A Reel Outer Diameter 330±1.0 B Reel Inner Diameter 62±1.5 C Spindle Hole Diameter 13.0+0.5 -0.2 D Key Slit Width 2.0±0.5 T1 Space Between Flange 16.8+0.3 -0.2 T2 Reel Thickness 22.2±0.2 Rev. 1.20 58 March 23, 2007 HT46RU22 Carrier Tape Dimensions P 0 D P 1 t E F W C D 1 B 0 P K 0 A 0 SOP 24W Symbol Description Dimensions in mm W Carrier Tape Width 24.0±0.3 P Cavity Pitch 12.0±0.1 E Perforation Position 1.75±0.1 F Cavity to Perforation (Width Direction) 11.5±0.1 D Perforation Diameter 1.55+0.1 D1 Cavity Hole Diameter 1.5+0.25 P0 Perforation Pitch 4.0±0.1 P1 Cavity to Perforation (Length Direction) 2.0±0.1 A0 Cavity Length 10.9±0.1 B0 Cavity Width 15.9±0.1 K0 Cavity Depth 3.1±0.1 t Carrier Tape Thickness C Cover Tape Width 0.35±0.05 21.3 SSOP 24S (150mil) Symbol Description Dimensions in mm W Carrier Tape Width 16.0+0.3 -0.1 P Cavity Pitch 8.0±0.1 E Perforation Position 1.75±0.1 F Cavity to Perforation (Width Direction) 7.5±0.1 D Perforation Diameter 1.5+0.1 D1 Cavity Hole Diameter 1.5+0.25 P0 Perforation Pitch 4.0±0.1 P1 Cavity to Perforation (Length Direction) 2.0±0.1 A0 Cavity Length 6.5±0.1 B0 Cavity Width 9.5±0.1 K0 Cavity Depth 2.1±0.1 t Carrier Tape Thickness 0.3±0.05 C Cover Tape Width Rev. 1.20 13.3 59 March 23, 2007 HT46RU22 Holtek Semiconductor Inc. (Headquarters) No.3, Creation Rd. II, Science Park, Hsinchu, Taiwan Tel: 886-3-563-1999 Fax: 886-3-563-1189 http://www.holtek.com.tw Holtek Semiconductor Inc. (Taipei Sales Office) 4F-2, No. 3-2, YuanQu St., Nankang Software Park, Taipei 115, Taiwan Tel: 886-2-2655-7070 Fax: 886-2-2655-7373 Fax: 886-2-2655-7383 (International sales hotline) Holtek Semiconductor Inc. (Shanghai Sales Office) 7th Floor, Building 2, No.889, Yi Shan Rd., Shanghai, China 200233 Tel: 021-6485-5560 Fax: 021-6485-0313 http://www.holtek.com.cn Holtek Semiconductor Inc. (Shenzhen Sales Office) 5/F, Unit A, Productivity Building, Cross of Science M 3rd Road and Gaoxin M 2nd Road, Science Park, Nanshan District, Shenzhen, China 518057 Tel: 0755-8616-9908, 8616-9308 Fax: 0755-8616-9722 Holtek Semiconductor Inc. (Beijing Sales Office) Suite 1721, Jinyu Tower, A129 West Xuan Wu Men Street, Xicheng District, Beijing, China 100031 Tel: 010-6641-0030, 6641-7751, 6641-7752 Fax: 010-6641-0125 Holtek Semiconductor Inc. (Chengdu Sales Office) 709, Building 3, Champagne Plaza, No.97 Dongda Street, Chengdu, Sichuan, China 610016 Tel: 028-6653-6590 Fax: 028-6653-6591 Holtek Semiconductor (USA), Inc. (North America Sales Office) 46729 Fremont Blvd., Fremont, CA 94538 Tel: 510-252-9880 Fax: 510-252-9885 http://www.holmate.com Copyright Ó 2007 by HOLTEK SEMICONDUCTOR INC. The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. Holtek¢s products are not authorized for use as critical components in life support devices or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw. Rev. 1.20 60 March 23, 2007