HOLTEK HT82V24

HT82V24
16-Bit, 15MSPS, 3-Channel CCD/CIS Analog Signal Processor
Features
· Operating voltage: 5V
· Input clamp circuitry
· Low power consumption at 380mW (Typ.)
· Internal voltage reference
· Power-down mode: Under 2mA (Typ.)
· Multiplexed byte/nibble-wide output (8´2/4´4 format)
· 16-bit 15 MSPS A/D converter
· Programmable 3-wire serial interface
· Supports ADI/WM mode data output formats selec-
· 3V/5V digital I/O compatibility
tion
· 3-channel operation up to 5 MSPS for each channel
· Guaranteed won¢t miss codes
· 2-channel (Even-Odd) operation up to 7.5 MSPS for
· 1~6x programmable gain
each channel
· Correlated Double Sampling
· 1-channel operation up to 15 MSPS
· ±300mV programmable offset
· 20/28-pin SOP/SSOP package (Pb-free on request)
Applications
Flatbed document scanners
Digital color copiers
Film scanners
Multifunction peripherals
General Description
The 16-bit digital output is multiplexed into an 8/4-bit
output word that is accessed using two/four read cycles.
The internal registers are programmed through a 3-wire
serial interface, which provides gain, offset and operating mode adjustments. HT82V24 supports ADI/WM
mode data output formats.
The HT82V24 is a complete analog signal processor for
CCD imaging applications. It features a 3-channel architecture designed to sample and condition the outputs of
tri-linear color CCD arrays. Each channel consists of an
input clamp, Correlated Double Sampler (CDS), offset
DAC and Programmable Gain Amplifier (PGA), and a
high performance 16-bit A/D converter.
The HT82V24 operates from a single 5V power supply,
typically consumes 380mW of power.
The CDS amplifiers may be disabled for use with sensors such as Contact Image Sensors (CIS) and CMOS
active pixel sensors, which do not require CDS.
Block Diagram
A V D D
V IN R
A V S S
R E F T
R E F B
+
A V D D
C D S
A V S S
D V D D
P G A
O E
9 - B it
D A C
V IN G
+
B A N D G A P
R e fe re n c e
C D S
C D S
O F F S E T
C D S C L K 1 /V S M P
Rev. 1.00
1 6
M U X
8 o r 4
D O U T
+
C o n fig u r a tio n
R e g is te r
M U X
R e g is te r
P G A
6
In p u t
C la m p
B ia s
1 6 - B it
A D C
3 .1
M U X
P G A
9 - B it
D A C
V IN B
D V S S
9 - B it
D A C
9
R E D
G R E E N
B L U E
R E D
G R E E N
B L U E
G a in
R e g is te r s
D ig ita l
C o n tro l
In te rfa c e
S C L K
S L O A D
S D A T A
O ffs e t
R e g is te r s
C D S C L K 2
A D C C L K
1
September 7, 2005
HT82V24
Pin Assignment
C D S C L K 1 /V S M P
1
2 8
A V D D
C D S C L K 2
2
2 7
A V S S
A D C C L K
3
2 6
V IN R
O E
4
2 5
O F F S E T
A V S S
1
2 0
V IN R
D V D D
5
2 4
V IN G
A V D D
2
1 9
O F F S E T
D V S S
6
2 3
C M L
V S M P
3
1 8
C M L
D 7 (M S B )
7
2 2
V IN B
A D C C L K
4
1 7
R E F T
D 6
8
2 1
R E F T
D V D D
5
1 6
R E F B
D 5
9
2 0
R E F B
D V S S
6
1 5
A V S S
D 4
1 0
1 9
A V S S
D 7
7
1 4
A V D D
D 3
1 1
1 8
A V D D
D 6
8
1 3
S L O A D
D 2
1 2
1 7
S L O A D
D 5
9
1 2
S C L K
D 1
1 3
1 6
S C L K
D 4
1 0
1 1
S D A T A
D 0 (L S B )
1 4
1 5
S D A T A
H T 8 2 V 2 4
2 0 S O P -A /S S O P -A
H T 8 2 V 2 4
2 8 S O P -A /S S O P -A
Pin Description
Pin Name
I/O
Description
CDSCLK1/VSMP
DI
CDS reference clock pulse input
ADI mode: CDSCLK1
WM mode: VSMP
CDSCLK2
DI
CDS data clock pulse input
ADCCLK
DI
A/D sample clock input for 3-channels mode
OE
DI
Output enable, active low
DVDD
P
Digital power
DVSS
P
Digital ground
D7~D0
DO
SDATA
Digital data output
DI/DO Serial data input/output
SCLK
DI
SLOAD
DI
Clock input for serial interface
Serial interface load pulse
AVSS
P
Analog ground
AVDD
P
Analog supply
REFB
AO
Reference decoupling
REFT
AO
Reference decoupling
VINB
AI
Analog input, blue
CML
AO
Internal reference output
VING
AI
Analog input, green
OFFSET
AO
Clamp bias level decoupling
VINR
AI
Analog input, red
Absolute Maximum Ratings
Supply Voltage ..........................VSS-0.3V to VSS+5.5V
Storage Temperature ...........................-50°C to 125°C
Input Voltage .............................VSS-0.3V to VDD+0.3V
Operating Temperature ..........................-25°C to 75°C
Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maximum Ratings² may
cause substantial damage to the device. Functional operation of this device at other conditions beyond those
listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability.
Rev. 1.00
2
September 7, 2005
HT82V24
D.C. Characteristics
Symbol
Parameter
Test Conditions
VDD
Conditions
Min.
Typ.
Max.
Unit
¾
¾
V
Logic Inputs
VIH
High Level Input Voltage
¾
¾
0.8´DVDD
VIL
Low Level Input Voltage
¾
¾
¾
¾
0.2´DVDD
V
IIH
High Level Input Current
¾
¾
¾
10
¾
mA
IIL
Low Level Input Current
¾
¾
¾
10
¾
mA
CIN
Input Capacitance
¾
¾
¾
10
¾
pF
¾
¾
DVDD-0.5
¾
¾
V
Logic Outputs
VOH
High Level Output Voltage
VOL
Low Level Output Voltage
¾
¾
¾
¾
0.5
V
IOH
High Level Output Current
5V
¾
¾
0.7
¾
mA
IOL
Low Level Output Current
5V
¾
¾
1.1
¾
mA
Min.
Typ.
Max.
Unit
A.C. Characteristics
Symbol
Parameter
Test Conditions
VDD
Conditions
Power Supplies
AVDD
Analog Power
¾
¾
4.75
5
5.25
V
DVDD
Digital I/O Power
¾
¾
3
5
5.25
V
Maximum Conversion Rate
fMAX3
3-channel Mode with CDS
¾
¾
15
¾
¾
MSPS
fMAX2
2-channel Mode with CDS
¾
¾
15
¾
¾
MSPS
fMAX1
1-channel Mode with CDS
¾
¾
15
¾
¾
MSPS
ADC Resolution
¾
¾
¾
16
¾
Bits
Integral Nonlinear (INL)
¾
¾
¾
±32
¾
LSB
Differential Nonlinear (DNL)
¾
¾
-1
¾
1
LSB
Offset Error
¾
¾
-150
¾
150
mV
Gain Error
¾
¾
¾
5
¾
%FSR
2.0/3.0*
¾
Vp-p
Accuracy (Entire Signal Path)
Analog Inputs
RFS
Full-scale Input Range
¾
¾
¾
Vi
Input Limits
¾
¾
AVSS-0.3
¾
AVDD+0.3
V
Ci
Input Capacitance
¾
¾
¾
10
¾
pF
Ii
Input Current
¾
¾
¾
10
¾
nA
Amplifiers
Rev. 1.00
PGA Gain at Minimum
¾
¾
¾
1
¾
V/V
PGA Gain at Maximum
¾
¾
¾
6
¾
V/V
PGA Gain Resolution
¾
¾
¾
6
¾
Bits
Programmable Offset at Minimum
¾
¾
¾
-300
¾
mV
Programmable Offset at Maximum
¾
¾
¾
300
¾
mV
Offset Resolution
¾
¾
¾
9
¾
Bits
3
September 7, 2005
HT82V24
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
¾
0
¾
70
°C
VDD
Conditions
¾
Temperature Range
tA
Operating
Power Consumption
Ptot3
Total Power Consumption (3CH)
¾
¾
¾
380
¾
mW
Ptot2
Total Power Consumption (2CH)
¾
¾
¾
340
¾
mW
Ptot1
Total Power Consumption (1CH)
¾
¾
¾
300
¾
mW
Note: ²*² means the full-scale input range select by configuration register
Timing Specification
Symbol
Parameter
Min.
Typ.
Max.
Unit
Clock Parameters
tPRA
3-channel pixel rate
200
¾
¾
ns
tPRB
2-channel (Even-Odd) pixel rate
133
¾
¾
ns
tPRC
1-channel pixel rate
66
¾
¾
ns
tADCLK
ADCCLK Pulse Width
33
¾
¾
ns
tC1
CDSCLK1 Pulse Width
15
30
¾
ns
tC2
CDSCLK2 Pulse Width
15
30
¾
ns
tC1C2
CDSCLK1 Falling to CDSCLK2 Rising
0
¾
¾
ns
tADC2
ADCCLK Rising to CDSCLK2 Falling
0
¾
¾
ns
tC2ADR
CDSCLK2 Rising to ADCCLK Rising
5
¾
¾
ns
tC2ADF
CDSCLK2 Falling to ADCCLK Falling
30
¾
¾
ns
tC2C1
CDSCLK2 Falling to CDSCLK1 Rising
30
¾
¾
ns
tAD
Analog Sampling Delay
¾
5
¾
ns
Serial Interface
fSCLK
Maximum SCLK Frequency
10
¾
¾
MHz
tLS
SLOAD to SCLK Setup Time
10
¾
¾
ns
tLH
SCLK to SLOAD Hold Time
10
¾
¾
ns
tDS
SDATA to SCLK Rising Setup Time
10
¾
¾
ns
tDH
SCLK Rising to SDATA Hold Time
10
¾
¾
ns
tRDV
Falling to SDATA Valid
10
¾
¾
ns
Output Delay
¾
12
¾
ns
Data Output
tOD
Rev. 1.00
4
September 7, 2005
HT82V24
Functional Description
The offset error is the deviation of the actual first code
transition level from the ideal level.
Integral Nonlinear (INL)
Integral nonlinear error refers to the deviation of each individual code from a line drawn from zero scale through
a positive full scale. The point used as zero scale occurs
1/2 LSB before the first code transition. A positive full
scale is defined as a level 1/2 LSB beyond the last code
transition. The deviation is measured from the middle of
each particular code to the true straight line.
Gain Error
The last code transition should occur for an analog
value of 1/2 LSB below the nominal full-scale voltage.
Gain error is the deviation of the actual difference between the first and the last code transitions and the ideal
difference between the first and the last code transitions.
Differential Nonlinear (DNL)
An ideal ADC exhibits code transitions that are exactly 1
LSB apart. DNL is the deviation from this ideal value.
Thus every code must have a finite width. No missing
codes guaranteed for the 16-bit resolution indicates that
all the 65536 codes respectively, are present in the
over-all operating range.
Sampling Delay
The sampling delay is the time delay that occurs when a
sampling edge is applied to the HT82V24 until the actual
sample of the input signal is held. Both CDSCLK1 and
CDSCLK2 sample the input signal during the transition
from high to low, so the sampling delay is measured
from each clock¢s falling edge to the instant the actual
internal sample is taken.
Offset Error
The first ADC code transition should occur at a level 1/2
LSB above the nominal zero scale voltage.
Internal Register Descriptions
Address
Data Bits
Register
Name
A2
A1
A0
D8
Configuration
0
0
0
0
MUX
0
0
1
0
RGB/
BGR
Red
Green
Red PGA
0
1
0
0
0
0
MSB
LSB
Green PGA
0
1
1
0
0
0
MSB
LSB
Blue PGA
1
0
0
0
0
0
MSB
LSB
Red Offset
1
0
1
MSB
LSB
Green Offset
1
1
0
MSB
LSB
Blue Offset
1
1
1
MSB
LSB
D7
D6
Don¢t care
D5
D4
3-CH CDS on
D3
Clamp
Voltage
Blue
0
D2
D1
D0
Enable
Input 1 byte
Power
Range
out
Down
0
0
0
Internal Register Map (ADI Mode)
Register
Name
Address
A2
A1
Data Bits
A0
D8
D7
D6
D5
D4
Clamp Timing
3-CH CDS on
Control
D3
Clamp
Voltage
D2
D1
D0
Enable
Input Output
Power
Range Format
Down
Configuration
0
0
0
1
MUX
0
0
1
DEL
RGB/
BGR
Red
Green
Red PGA
0
1
0
0
0
0
MSB
LSB
LSB
Blue POSNNEG
VDEL
Green PGA
0
1
1
0
0
0
MSB
Blue PGA
1
0
0
0
0
0
MSB
Red Offset
1
0
1
MSB
LSB
Green Offset
1
1
0
MSB
LSB
Blue Offset
1
1
1
MSB
LSB
LSB
Internal Register Map (Wolfson Mode)
Rev. 1.00
5
September 7, 2005
HT82V24
Configuration Register
clamp bias, unless a CCD with a reset feed through
transient exceeding 2V is used. Setting the bit D3 low,
the clamp voltage is 3V. Bit D2 controls the power-down
mode. Setting bit D2 high will place the HT82V24 into a
very low power ²sleep² mode. All register contents are
retained while the HT82V24 is in the power-down state.
Setting bit D1 high will select the 3V input range, otherwise the 2V input range is selected.
The configuration register controls the HT82V24¢s operating mode and bias levels. Bits D7 and D6 set the
clamp timing in WM mode and there are don't care in
ADI Mode. Bit D5 will configure the HT82V24 for the
3-channel (high) mode of operation. Setting the bit D4
high will enable the CDS mode of operation, and setting
this bit low will enable the SHA mode of operation.
Bit D3 sets the dc bias level of the HT82V24¢s input
clamp. This bit should always be set high for the 4V
D8
D7
D6
D5
D4
D3
D2
D1
D0
Power-down
Input
Range
1 byte out
(High-byte
only)
1=4V*
1=On
1=3V
1=On
0=3V
0=Off
(Normal)*
0=2V*
0=Off*
3 channels CDS operation Clamp bias
Set to 0
Don¢t care
1=On*
0=Off
1=CDS mode*
0=SHA mode
Configuration Register Settings (ADI Mode)
D8
D7
D6
D5
D4
D3
Clamp Timing Control 3 channels CDS operation Clamp bias
Set to 1 CDSREF1 CDSREF0
0*
0*
D2
D1
D0
Power-down
Input
Range
Output
Format
1=On*
1=CDS mode*
1=4V*
1=On
1=3V
1=Byte
output
0=Off
0=SHA mode
0=3V
0=Off
(Normal)*
0=2V*
0=Nibble
output*,**
Configuration Register Settings (Wolfson Mode)
Note: * Power-on default value
** It needs D5=0, D0=0 to enable Nibble output (1CH WM mode)
Bits D7 and D6 control the reset sample and clamp timing
A D C C L K
V S M P
R S /C L
C D S R E F = 0 0
R S /C L
C D S R E F = 0 1
R S /C L
C D S R E F = 1 0
R S /C L
C D S R E F = 1 1
Reset Sample and Clamp Timing (RS/CL)
Note: CDSREF=(CDSREF1,CDSREF0)
Rev. 1.00
6
September 7, 2005
HT82V24
Bit D0 control the ADC output cycle of the HT82V24.
Bit D8 selects the ADC data output format selection. Setting D8 high enables the WM mode data output format while
setting bit D8 low enables the ADI mode output data format. The one nibble data will output data to pins D7~D4 and 4´4
(WM) mode output the data format selected. The output format as the following table:
D8
D0
ADC Output Format
0
0
D5=1: 3-CH 8´2 (ADI)
D5=0: 1 or 2-CH 8´2 (ADI)
0
1
D5=1: 3-CH 8´1 (ADI)
D5=0: 1 or 2-CH 8´1 (ADI)
1
0
D5=0: 1-CH 4´4 (WM)
1
1
D5=1: 3-CH 8´2 (WM)
D5=0: 1-CH 8´2 (WM)
A D C C L K
A D C C L K
O u tp u t D a ta
D 7 ~ D 4
A
B
C
O u tp u t D a ta
D 7 ~ D 0
D
H ig h
N ib b le
L o w
N ib b le
A 1
B 1
H ig h
B y te
L o w
B y te
A 2
B 2
8 x 2 (A D I) O u tp u t D a ta F o r m a t
4 x 4 (W M ) O u tp u t D a ta F o rm a t
A D C C L K
A D C C L K
O u tp u t D a ta
D 7 ~ D 0
O u tp u t D a ta
D 7 ~ D 0
A
B
H ig h B y te
L o w B y te
8 x 2 (W M ) O u tp u t D a ta F o rm a t
A 1
A 2
H ig h B y te
H ig h B y te
8 x 1 (A D I) O u tp u t D a ta F o r m a t
MUX Register
MUX to sample the blue channel first. Bits D6, D5 and
D4 are used when operating in 1 or 2-channel mode. Bit
D6 is set high to sample the red channel. Bit D5 is set
high to sample the green channel. Bit D4 is set high to
sample the blue channel. The MUX will remain stationary during 1-channel mode. The two channel mode is
selected by setting two of the channel select bits
(D4~D6) high. The MUX samples the channels in the order selected by bit D7. In WM mode, Bits D0~D2 are
used to control the sampling point delay option. Bit D3 is
used to select the rising or falling edge on the CDSCLK1
input pin and generates an internal VSMP pulse. Bits
D0~D3 set to 0 in ADI Mode.
The MUX register controls the sampling channel order
and the 2-channel mode configuration in the HT82V24.
Bit D8 is used to set the output latency in ADC clock period and is only valid when WM mode data output format
is selected. Bit D7 is used when operating in the
3-channel mode or the 2-channel mode. Setting bit D7
high will sequence the MUX to sample the red channel
first, then the green channel, and then the blue channel.
When in the 3-channel mode, the CDSCLK2 rising edge
always resets the MUX to sample the red channel first
(see timing diagrams). When bit D7 is set low, the channel order is reversed to blue first, green second, and red
third. The CDSCLK2 rising edge will always reset the
D8
D7
D6
MUX Order
Set to 0
D5
D4
D3
D2
D1
D0
Channel Select
1=R-G-B*
1=RED*
1=GREEN
1=BLUE
0=B-G-R
0=Off
0=Off*
0=Off*
Set to 0
MUX Register Settings (ADI Mode)
Rev. 1.00
7
September 7, 2005
HT82V24
D8
D7
D6
DEL
MUX Order
D5
D4
D3
Channel Select
0=Off
0=Off*
D1
D0
CDS Edge Detection Select Delay Period Select
1: Delay by two ADC
1=R-G-B* 1=RED* 1=GREEN 1=BLUE
clock
0: Minimum latency* 0=B-G-R
D2
VDEL VDEL VDEL
2
1
0
POSNNEG
0=Off*
0*
0*
0*
0*
MUX Register Settings (Wolfson Mode)
Note: * Power-on default value
D0~D3 and D8 are valid only at WM mode.
A D C C L K
V S M P
P O S N N E G = 1
(V D E L = 0 0 0 ) IN T V S M P
V
V
S
(V D E L = 0 0 1 ) IN T V S M P
V
V
S
(V D E L = 0 1 0 ) IN T V S M P
V
V
V
V
V
V
V
S
V
S
V
S
S
S
S
S
(V D E L = 1 1 1 ) IN T V S M P
V
V
V
S
S
S
S
(V D E L = 1 1 0 ) IN T V S M P
V
V
V
S
S
S
S
(V D E L = 1 0 1 ) IN T V S M P
V
V
V
S
S
S
(V D E L = 0 1 1 ) IN T V S M P
(V D E L = 1 0 0 ) IN T V S M P
V
S
S
V
S
S
P O S N N E G = 0
V
(V D E L = 0 0 0 ) IN T V S M P
V
S
V
(V D E L = 0 0 1 ) IN T V S M P
V
S
V
(V D E L = 0 1 0 ) IN T V S M P
V
(V D E L = 1 0 0 ) IN T V S M P
V
(V D E L = 1 0 1 ) IN T V S M P
V
(V D E L = 1 1 0 ) IN T V S M P
(V D E L = 1 1 1 ) IN T V S M P
V
S
V
S
V
S
V
S
S
V
S
V
S
S
V
S
V
S
S
V
S
V
S
S
V
S
V
S
S
V
S
V
S
V
(V D E L = 0 1 1 ) IN T V S M P
V
S
S
S
Note: VDEL=(VDEL2, VDEL1, VDEL0)
Rev. 1.00
8
September 7, 2005
HT82V24
PGA Gain Registers
Where G is the decimal value of the gain register contents, and varies from 0 to 63.
1 6
6
1 2
5 .0
D7
D6
D5
D4
Set to 0
Set to 0
Set to 0
MSB
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
4 .0
6
3 .0
3
2 .0
0
1 .0
G A IN -d B (
The HT82V24 uses one Programmable Gain Amplifier
(PGA) for each channel. Each PGA has a gain range
from 1x (0dB) to 6x (15.6dB), adjustable in 64 steps.
The Figure shows the PGA gain as a function of the PGA
register code. Although the gain curve is approximately
linear in dB, the gain in V/V varies in nonlinear proportion with the register code, according to the following the
6
equation: Gain=
63 - G
1+ 4.85x(
)
63
D8
9
G A IN -V /V (
)
)
There are three PGA registers for use in individually programming the gain in the red, green and blue channels.
Bits D8, D7 and D6 in each register must be set low, and
bits D5 through D0 control the gain range in 64 increments. See figure for a graph of the PGA gain versus
PGA register code. The coding for the PGA registers is a
straight binary, with an all zero words corresponding to
the minimum gain setting (1x) and an all one word corresponding to the maximum gain setting (6x).
PGA Gain Transfer Function
D3
D2
D1
D0
Gain
(V/V)
Gain (dB)
1.0
1.039
.
.
.
5.57
6
0.0
0.33
.
.
.
14.9
15.6
LSB
0
0
.
.
.
1
1
0
0
0
0
0*
1
1
1
1
1
0
1
PGA Gain Register Settings
Note: * Power-on default value
Offset Registers
There are three offset registers for use in individually programming the offset in the red, green, and blue channels. Bits
D8 through D0 control the offset range from -300mV to 300mV in 512 increments.
The coding for the offset registers is sign magnitude, with D8 as the sign bit. The following table shows the offset range
as a function of the bits D8 through D0.
D8
D7
D6
D5
D4
D3
D2
D1
MSB
D0
Offset
(mV)
LSB
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
1
0
0
1
0
0
1
0
0
1
1
1
1
1
0
0
.
.
.
1
0
0
.
.
.
1
0
0
0
0
0*
1
1
0
0
1
0
0
1
0
1
1
1
1
0
1.17
.
.
.
300
0
-1.17
.
.
.
-300
Note: * Power-on default value
Rev. 1.00
9
September 7, 2005
HT82V24
Timing Diagrams
S D A T A
A 2
R /W b
tD
A 1
A 0
H
tD
D 7
D 8
D 6
D 5
D 4
D 3
D 2
D 1
D 0
S
S C L K
tL
tL
S
H
S L O A D
Serial Write Operation Timing
S D A T A
A 2
R /W b
A 1
D 8
A 0
tR
D 7
D 6
D 5
D 4
D 3
D 2
D 1
D 0
D V
S C L K
tL
tL
S
H
S L O A D
Serial Read Operation Timing
Part (A): 8´2 (ADI) Output Format
A n a lo g In p u t
(R , G , B )
P ix e l ( N + 2 )
tA
P ix e l ( N + 3 )
P ix e l ( N + 4 )
D
tC
tA
1
D
tC
tP
2 C 1
R A
C D S C L K 1
tC
1 C 2
C D S C L K 2
tA
tC
2
tC
2 A D F
tC
2 A D R
D C L K
tA
D C 2
A D C C L K
tA
O u tp u t D a ta
D 7 ~ D 0
R (N -2 )
G
(N -2 ) G
H ig h
B y te
tO
D C L K
(N -2 )
L o w
B y te
B (N -2 )
B (N -2 )
R (N -1 )
H ig h
B y te
L o w
B y te
H ig h
B y te
R (N -1 ) G
L o w
B y te
tO
D
(N -1 )
H ig h
B y te
G
(N -1 ) B (N -1 )
L o w
B y te
D
B (N -1 )
R (N )
R (N )
G
L o w
B y te
H ig h
B y te
L o w
B y te
H ig h
B y te
H ig h
B y te
(N )
G
(N )
L o w
B y te
3-Channel CDS Mode Timing
A n a lo g In p u t
(R , G , B )
P ix e l ( N + 3 )
tA
P ix e l ( N + 4 )
P ix e l ( N + 5 )
D
tC
tC
1
tP
2 C 1
R A
C D S C L K 1
tC
tC
1 C 2
2
C D S C L K 2
tA
tC
2 A D R
tC
D C 2
2 A D F
A D C C L K
tA
O u tp u t D a ta
D 7 ~ D 0
G
(N -2 )
H ig h
B y te
D C L K
G
(N -2 )
L o w
B y te
tA
D C L K
B (N -2 )
B (N -2 )
H ig h
B y te
L o w
B y te
G
(N -1 )
H ig h
B y te
G
(N -1 )
L o w
B y te
B (N -1 )
B (N -1 )
H ig h
B y te
L o w
B y te
G
(N )
H ig h
B y te
G
(N )
L o w
B y te
2-Channel CDS Mode Timing
Rev. 1.00
10
September 7, 2005
HT82V24
P ix e l ( N )
A n a lo g In p u t
tA
P ix e l ( N + 1 )
P ix e l ( N + 2 )
D
tC
tA
1
D
tC
tP
2 C 1
R A
C D S C L K 1
tC
tC
1 C 2
2
C D S C L K 2
tC
tC
2 A D R
tA
A D C C L K
tA
O u tp u t D a ta
D 7 ~ D 0
2 A D F
D C L K
tO
D C L K
D
P ix e l ( N - 9 )
P ix e l ( N - 9 )
P ix e l ( N - 8 )
P ix e l ( N - 8 )
P ix e l ( N - 7 )
H ig h B y te
L o w B y te
H ig h B y te
L o w B y te
H ig h B y te
P ix e l ( N - 7 )
L o w
B y te
1-Channel CDS Mode Timing
P ix e l ( N + 2 )
A n a lo g In p u t
(R , G , B )
tA
tC
C D S C L K 2
tA
tA
D C L K
P ix e l ( N + 3 )
D
tP
2
tC
tC
D C 2
R A
2 A D
2 A D R
A D C C L K
tA
O u tp u t D a ta
D 7 ~ D 0
R (N -2 )
G
(N -2 ) G
H ig h
B y te
tO
D C L K
(N -2 )
L o w
B y te
B (N -2 )
B (N -2 )
R (N -1 )
H ig h
B y te
L o w
B y te
H ig h
B y te
R (N -1 ) G
L o w
B y te
D
(N -1 )
H ig h
B y te
G
(N -1 ) B (N -1 )
L o w
B y te
H ig h
B y te
B (N -1 )
R (N )
R (N )
G
L o w
B y te
H ig h
B y te
L o w
B y te
H ig h
B y te
(N )
G
(N )
L o w
B y te
3-Channel SHA Mode Timing
P ix e l ( N + 3 )
A n a lo g In p u t
(R , G , B )
tA
tC
P ix e l ( N + 4 )
D
2
C D S C L K 2
tA
tC
2 A D R
tC
D C 2
2 A D F
A D C C L K
tA
O u tp u t D a ta
D 7 ~ D 0
G
(N -2 )
H ig h
B y te
D C L K
G
(N -2 )
L o w
B y te
tA
D C L K
B (N -2 )
B (N -2 )
H ig h
B y te
L o w
B y te
G
(N -1 )
H ig h
B y te
G
(N -1 )
L o w
B y te
B (N -1 )
B (N -1 )
H ig h
B y te
L o w
B y te
G
(N )
H ig h
B y te
G
(N )
L o w
B y te
2-Channel SHA Mode Timing
Rev. 1.00
11
September 7, 2005
HT82V24
P ix e l ( N )
tA
A n a lo g In p u t
P ix e l ( N + 1 )
D
tC
tP
2
R B
C D S C L K 2
tC
tC
2 A D R
tA
A D C C L K
tA
O u tp u t D a ta
D 7 ~ D 0
2 A D F
D C L K
tO
D C L K
P ix e l ( N - 9 )
P ix e l ( N - 9 )
H ig h B y te
L o w
B y te
D
P ix e l ( N - 8 )
P ix e l ( N - 8 )
P ix e l ( N - 7 )
H ig h B y te
L o w
H ig h B y te
B y te
P ix e l ( N - 7 )
L o w
B y te
1-Channel SHA Mode Timing
Part (B): WM Mode Output Format at VDEL=(0,0,0), POSNEG=1 (Those Diagrams are identical for both CDS
and SHA Operation)
· 3-CH 8´2 (WM)
1 6 .5 A D C C L K P e r io d s
A D C C L K
V S M P
A n a lo g In p u t
(R , G , B )
O u tp u t D a ta D 7 ~
8 x 2 (W
D E L
O u tp u t D a ta D 7 ~
8 x 2 (W
D E L
D 0
M )
= 0
D 0
M )
= 1
R
B
R
A
B
A
G
B
R
B
G
A
R
A
B
B
B
A
G
B
G
A
R
B
B
R
B
A
B
A
G
B
R
B
G
A
R
A
B
B
G
B
B
A
G
A
R
B
B
R
A
B
A
B
B
G
R
B
G
A
R
A
B
B
G
B
B
A
G
A
R
B
B
B
R
A
B
A
G
B
R
B
G
A
R
A
B
B
G
B
B
A
G
A
R
B
B
B
R
A
B
A
G
B
R
B
G
A
R
A
B
B
G
B
B
A
B
G
A
B
3-Channel Mode Timing (Select R-G-B Mode)
· 1-CH 8´2 (WM)
1 6 .5 A D C C L K P e r io d s
A D C C L K
V S M P
A n a lo g In p u t
(R , G , B )
O u tp u t D a ta D 7 ~
8 x 2 (W
D E L
O u tp u t D a ta D 7 ~
8 x 2 (W
D E L
D 0
M )
= 0
D 0
M )
= 1
R
R
A
x
x
B
x
R
x
R
A
x
B
x
x
R
x
R
A
x
x
B
x
R
x
R
A
x
x
x
B
R
x
R
A
x
x
B
x
R
x
R
A
x
x
x
B
R
x
R
A
x
x
B
x
R
x
R
A
x
x
B
x
R
x
R
A
x
B
x
1-Channel Mode Timing (Select R Mode)
· 1-CH 4´4 (WM)
1 6 .5 A D C C L K P e r io d s
A D C C L K
V S M P
A n a lo g In p u t ( R )
O u tp u t D a ta D 7 ~
4 x 4 (W
D E L
O u tp u t D a ta D 7 ~
4 x 4 (W
D E L
D 4
M ) A
= 0
D 4
M )
= 1
B
D
C
A
A
D
B
C
D
B
C
A
A
D
B
C
D
B
C
A
A
D
B
C
D
B
C
A
A
D
B
C
B
C
D
D
1-Channel Mode Timing (Select R Mode)
Rev. 1.00
12
September 7, 2005
HT82V24
Application Circuits
The recommended circuit configuration for the 3-channel CDS mode operation is shown in the figure below (ADI mode
data output format). The recommended input coupling capacitor value is 0.1mF.
A single ground plane is recommended for the HT82V24. A separate power supply may be used for DRVDD, the digital
driver supply, but this supply pin should still be decoupled to the same ground plane as with the rest of the HT82V24.
The loading of the digital outputs should be minimized, either by using short traces to the digital ASIC, or by using external digital buffers. To minimize the effect of digital transients during major output code transitions, the falling edge of the
CDSCLK2 should occur in coincidence with or before the rising edge of ADCCLK. All 0.1mF decoupling capacitors
should be located as close as possible to the HT82V24 pins. When operating in a single channel mode, the unused analog inputs should be grounded.
V
C lo c k
In p u ts
V
1
2
D D
0 .1 m F
3
R e d In p u t
0 .1 m F
1
2
C lo c k
In p u ts
3
A V S S
V IN R
A V D D
O F F S E T
V S M P
5 V /3 V
4
5
0 .1 m F
6
R E F T
D V D D
R E F B
D V S S
7
8
9
1 0
D a ta
O u tp u ts
C M L
A D C C L K
A V S S
D 7
A V D D
D 6
S L O A D
D 5
S C L K
D 4
S D A T A
5 V /3 V
4
1 8
1 3
1 2
1 1
H T 8 2 V 2 4 (C D S M o d e )
0 .1 m F
6
8
0 .1 m F
1 6
1 4
5
7
1 7
1 5
1 .0 m F
0 .1 m F 0 .1 m F
0 .1 m F 1 0 m F
9
0 .1 m F
1 0
1 1
0 .1 m F
1 2
5 V
1 3
S e r ia l
In p u ts
D a ta
O u tp u ts
A V D D
C D S C L K 2
A V S S
A D C C L K
V IN R
O E
2 0
1 9
C D S C L K 1 /V S M P
1 4
O F F S E T
D V D D
V IN G
D V S S
C M L
D 7 (M S B )
V IN B
D 6
R E F T
D 5
R E F B
D 4
A V S S
D 3
A V D D
D 2
S L O A D
D 1
D 0 (L S B )
S C L K
S D A T A
2 8
0 .1 m F
2 7
2 6
0 .1 m F
2 4
0 .1 m F
2 3
2 2
2
0 .1 m F
1
2
C lo c k
In p u ts
3
5 V /3 V
4
5
0 .1 m F
6
7
8
9
1 0
D a ta
O u tp u ts
Note:
1
A V S S
V IN R
A V D D
O F F S E T
V S M P
C M L
A D C C L K
R E F T
D V D D
R E F B
D V S S
A V S S
D 7
A V D D
D 6
S L O A D
D 5
S C L K
D 4
S D A T A
H T 8 2 V 2 4 (S H A M o d e )
R e d In p u t
D C L e v e l
2 0
1 9
1 8
1 3
1 2
1 1
4
6
8
9
0 .1 m F
1 0
1 1
0 .1 m F
1 2
5 V
S e r ia l
In p u ts
1 3
D a ta
O u tp u ts
A V S S
A D C C L K
V IN R
D V D D
0 .1 m F
0 .1 m F 1 0 m F
A V D D
O E
5
7
1 6
1 4
5 V /3 V
0 .1 m F
1 7
1 5
3
C D S C L K 1 /V S M P
C D S C L K 2
1 4
O F F S E T
V IN G
D V S S
C M L
D 7 (M S B )
V IN B
D 6
R E F T
D 5
R E F B
D 4
A V S S
D 3
A V D D
D 2
S L O A D
D 1
D 0 (L S B )
S C L K
S D A T A
H T 8 2 V 2 4 (S H A M o d e )
1 .0 m F
0 .1 m F
2 1
0 .1 m F
2 0
0 .1 m F 1 0 m F
1 9
1 8
0 .1 m F
0 .1 m F
1 7
5 V
1 6
1 5
2 8
S e r ia l
In p u ts
D D
0 .1 m F
R e d In p u t
G re e n In p u t
B lu e In p u t
2 7
2 6
2 5
2 4
2 3
R e d In p u t
G re e n In p u t
B lu e In p u t
0 .1 m F
V
D D
0 .1 m F
2 5
H T 8 2 V 2 4 (C D S M o d e )
C lo c k
In p u ts
V
D D
D C
L e v e l
0 .1 m F
2 2
2 1
0 .1 m F
2 0
1 9
1 8
1 7
1 6
1 5
0 .1 m F 1 0 m F
0 .1 m F
0 .1 m F
5 V
S e r ia l
In p u ts
For the 3-channel SHA mode, all of the above considerations also apply for this configuration, except that the
analog input signals are directly connected to the HT82V24 without the use of coupling capacitors. The OFFSET pin should be grounded if the inputs to the HT82V24 are to be referenced to ground, or a DC offset voltage
should be applied to the OFFSET pin in the case where a coarse offset needs to be removed from the inputs.
The analog input signals must already be dc-biased between 0V and 2V, if OFFSET is connected to ground.
Rev. 1.00
13
September 7, 2005
HT82V24
Package Information
20-pin SOP (300mil) Outline Dimensions
1 1
2 0
A
B
1
1 0
C
C '
G
H
D
E
Symbol
Rev. 1.00
a
F
Dimensions in mil
Min.
Nom.
Max.
A
394
¾
419
B
290
¾
300
C
14
¾
20
C¢
490
¾
510
D
92
¾
104
E
¾
50
¾
F
4
¾
¾
G
32
¾
38
H
4
¾
12
a
0°
¾
10°
14
September 7, 2005
HT82V24
20-pin SSOP (209mil) Outline Dimensions
1 1
2 0
A
B
1
1 0
C
C '
G
H
D
E
Symbol
Rev. 1.00
a
F
Dimensions in mil
Min.
Nom.
Max.
A
291
¾
323
B
196
¾
220
C
9
¾
15
C¢
271
¾
295
D
65
¾
73
E
¾
25.59
¾
F
4
¾
10
G
26
¾
34
H
4
¾
8
a
0°
¾
8°
15
September 7, 2005
HT82V24
28-pin SOP (300mil) Outline Dimensions
2 8
1 5
A
B
1
1 4
C
C '
G
H
D
E
Symbol
Rev. 1.00
a
F
Dimensions in mil
Min.
Nom.
Max.
A
394
¾
419
B
290
¾
300
C
14
¾
20
C¢
697
¾
713
D
92
¾
104
E
¾
50
¾
F
4
¾
¾
G
32
¾
38
H
4
¾
12
a
0°
¾
10°
16
September 7, 2005
HT82V24
28-pin SSOP (209mil) Outline Dimensions
1 5
2 8
A
B
1 4
1
C
C '
G
H
D
E
Symbol
Rev. 1.00
a
F
Dimensions in mil
Min.
Nom.
Max.
A
291
¾
323
B
196
¾
220
C
9
¾
15
C¢
396
¾
407
D
65
¾
73
E
¾
25.59
¾
F
4
¾
10
G
26
¾
34
H
4
¾
8
a
0°
¾
8°
17
September 7, 2005
HT82V24
Product Tape and Reel Specifications
Reel Dimensions
D
T 2
A
C
B
T 1
SOP 20W
Symbol
Description
Dimensions in mm
A
Reel Outer Diameter
330±1
B
Reel Inner Diameter
62±1.5
C
Spindle Hole Diameter
13+0.5
-0.2
D
Key Slit Width
2±0.5
T1
Space Between Flange
24.8+0.3
-0.2
T2
Reel Thickness
30.2±0.2
SSOP 20N (209mil)
Symbol
Description
Dimensions in mm
A
Reel Outer Diameter
330±1
B
Reel Inner Diameter
62±1.5
C
Spindle Hole Diameter
13+0.5
-0.2
D
Key Slit Width
2±0.5
T1
Space Between Flange
16.8+0.3
-0.2
T2
Reel Thickness
22.2±0.2
Rev. 1.00
18
September 7, 2005
HT82V24
SOP 28W (300mil)
Symbol
Description
Dimensions in mm
A
Reel Outer Diameter
B
Reel Inner Diameter
62±1.5
C
Spindle Hole Diameter
13+0.5
-0.2
D
Key Slit Width
330±1
2±0.5
T1
Space Between Flange
24.8+0.3
-0.2
T2
Reel Thickness
30.2±0.2
Carrier Tape Dimensions
P 0
D
P 1
t
E
F
W
C
D 1
B 0
P
K 0
A 0
SOP 20W
Symbol
Description
Dimensions in mm
W
Carrier Tape Width
24+0.3
-0.1
P
Cavity Pitch
12±0.1
E
Perforation Position
1.75±0.1
F
Cavity to Perforation (Width Direction)
11.5±0.1
D
Perforation Diameter
1.5+0.1
D1
Cavity Hole Diameter
1.5+0.25
P0
Perforation Pitch
4±0.1
P1
Cavity to Perforation (Length Direction)
2±0.1
A0
Cavity Length
10.8±0.1
B0
Cavity Width
13.3±0.1
K0
Cavity Depth
3.2±0.1
t
Carrier Tape Thickness
0.3±0.05
C
Cover Tape Width
Rev. 1.00
21.3
19
September 7, 2005
HT82V24
SSOP 20N (209mil)
Symbol
Description
Dimensions in mm
W
Carrier Tape Width
16+0.3
-0.1
P
Cavity Pitch
12±0.1
E
Perforation Position
1.75±0.1
F
Cavity to Perforation (Width Direction)
7.5±0.1
D
Perforation Diameter
1.5+0.1
D1
Cavity Hole Diameter
1.5+0.25
P0
Perforation Pitch
4±0.1
P1
Cavity to Perforation (Length Direction)
2±0.1
A0
Cavity Length
7.1±0.1
B0
Cavity Width
7.2±0.1
K0
Cavity Depth
2±0.1
t
Carrier Tape Thickness
C
Cover Tape Width
0.3±0.05
13.3
SOP 28W (300mil)
Symbol
Description
Dimensions in mm
W
Carrier Tape Width
24±0.3
P
Cavity Pitch
12±0.1
E
Perforation Position
1.75±0.1
F
Cavity to Perforation (Width Direction)
11.5±0.1
D
Perforation Diameter
1.5+0.1
D1
Cavity Hole Diameter
1.5+0.25
P0
Perforation Pitch
4±0.1
P1
Cavity to Perforation (Length Direction)
2±0.1
A0
Cavity Length
10.85±0.1
B0
Cavity Width
18.34±0.1
K0
Cavity Depth
2.97±0.1
t
Carrier Tape Thickness
0.35±0.01
C
Cover Tape Width
Rev. 1.00
21.3
20
September 7, 2005
HT82V24
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Copyright Ó 2005 by HOLTEK SEMICONDUCTOR INC.
The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used
solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable
without further modification, nor recommends the use of its products for application that may present a risk to human life
due to malfunction or otherwise. Holtek¢s products are not authorized for use as critical components in life support devices
or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information,
please visit our web site at http://www.holtek.com.tw.
Rev. 1.00
21
September 7, 2005