HT9172 DTMF Receiver Technical Document · Tools Information · FAQs · Application Note Features · Operating voltage: 2.5V~5.5V · Tristate data output for MCU interface · Minimal external component requirements · 3.58MHz crystal or ceramic resonator oscillator · No external filter required · 1633Hz can be inhibited by the INH pin · Low standby current in power down mode) · 18-pin DIP/SOP packaging · Excellent performance General Description output. Highly accurate switched capacitor filters are utilised to divide the DTMF dual tone frequencies into low and high group signals. An integrated dial tone rejection circuit is provided to eliminate the need for pre-filtering. The HT9172 is a Dual Tone Multi Frequency (DTMF) receiver device which includes an integrated digital decoder and band split filter functions as well as power-down and inhibit mode operations. The device uses digital counting techniques to detect and decode the full range of 16 DTMF tone pairs into a 4-bit code Block Diagram P W D N V R E F B ia s C ir c u it V re f G e n e ra to r R T /G T E S T D V D V B X 2 X 1 V P V N G S 3 .5 8 M H z C ry s ta l O s c illa to r S te e r in g C o n tr o l C ir c u it L o w G ro u p F ilte r O P A F re q u e n c y P r e - F ilte r D e te c to r H ig h G r o u p F ilte r C o d e D e te c to r D 0 D 1 D 2 D 3 IN H Rev. 1.00 L a tc h & O u tp u t B u ffe r 1 O E March 30, 2006 HT9172 Pin Assignment V P 1 1 8 V D D V N 2 1 7 R T /G T G S 3 1 6 E S T V R E F 4 1 5 D V IN H 5 1 4 D 3 P W D N 6 1 3 D 2 X 1 7 1 2 D 1 X 2 8 1 1 D 0 V S S 9 1 0 O E H T 9 1 7 2 1 8 D IP -A /S O P -A Pin Description I/O Internal Connection VP I Operational Amplifier VN I Operational amplifier inverting input GS O Operational amplifier output terminal VREEF O X1 I Pin Name VREF Description Operational amplifier non-inverting input Reference voltage output, normally VDD/2 oscillator The system oscillator consists of an inverter, a bias resistor and the required on-chip load capacitor. A standard 3.579545MHz crystal connected to the X1 and X2 terminals implements the oscillator function. X2 O PWDN I CMOS IN Pull-low Active high. This enables the device to go into its power down mode and inhibits the oscillator. This pin input is pulled low internally. INH I CMOS IN Pull-low Active high. This inhibits the detection of tones representing characters A, B, C and D. This pin input is pulled low internally. VSS ¾ ¾ OE I CMOS IN Pull-high D0~D3 O CMOS OUT Tristate Received data output terminals OE=²H²: Output enable OE=²L²: High impedance DV O CMOS OUT Data valid output. When the device has received a valid DTMF tone, this line will go high; otherwise it remains low. EST O CMOS OUT Early steering output - see Functional Description RT/GT I/O CMOS IN/OUT VDD ¾ ¾ Rev. 1.00 Negative power supply, ground D0~D3 output enable, active high Tone acquisition time and release time can be set through connection with external resistor and capacitor. Positive power supply, 2.5V~5.5V for normal operation 2 March 30, 2006 HT9172 Approximate Internal Connection Circuits O P E R A T IO N A L A M P L IF IE R V R E F X 1 V O P A V + V N V P C M O S IN P u ll- h ig h O S C IL L A T O R C M O S O U T T r is ta te X 2 E N O P A G S 1 0 M 2 0 p F C M O S IN P u ll- lo w C M O S IN /O U T C M O S O U T 1 0 p F Absolute Maximum Ratings Supply Voltage ..............................VSS-0.3V to VSS+6V Storage Temperature ............................-50°C to 125°C Input Voltage..............................VSS-0.3V to VDD+0.3V Operating Temperature...........................-40°C to 85°C Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maximum Ratings² may cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability. D.C. Characteristics Symbol Parameter Ta=25°C Test Conditions VDD Conditions Min. Typ. Max. Unit VDD Operating Voltage ¾ ¾ 2.5 5 5.5 V IDD Operating Current 5V ¾ ¾ 3 7 mA ISTB Standby Current 5V VPWDN=VDD, (Not include PWDN pull-low current) ¾ 1 5 mA VIL Input Low Voltage 5V ¾ ¾ ¾ 1.0 V VIH Input High Voltage 5V ¾ 4.0 ¾ ¾ V IIL Input Low Current 5V VVP=VVN=0V ¾ ¾ 0.1 mA IIH Input High Current 5V VVP=VVN=5V ¾ ¾ 0.1 mA ROE Pull-high Resistance (OE) 5V VOE=0V 70 110 160 kW VINH=5.0V, VPWDN=5.0V 150 250 375 kW ¾ 10 ¾ MW -0.4 -0.8 ¾ mA RPL Pull-low Resistance (INH, PWDN) 5V RIN Input Impedance (VN, VP) 5V ¾ IOH Source Current (D0~D3, EST, DV) 5V VOUT =4.5V IOL Sink Current (D0~D3, EST, DV) 5V VOUT =0.5V fOSC System Frequency 5V Crystal=3.5795MHz Rev. 1.00 3 1.0 2.5 ¾ mA 3.5759 3.5795 3.5831 MHz March 30, 2006 HT9172 A.C. Characteristics Symbol Parameter fOSC=3.5795MHz, Ta=25°C Test Conditions Min. Typ. Max. 3V -36 ¾ -6 5V -29 ¾ 1 Twist Accept Limit (Positive) 5V ¾ 10 ¾ dB Twist Accept Limit (Negative) 5V ¾ 10 ¾ dB Dial Tone Tolerance 5V ¾ 18 ¾ dB Noise Tolerance 5V ¾ -12 ¾ dB Third Tone Tolerance 5V ¾ -16 ¾ dB Frequency Deviation Acceptance 5V ¾ ¾ ±1.5 % Frequency Deviation Rejection 5V ±3.5 ¾ ¾ % Power Up Time (See Figure 4.) 5V ¾ 30 ¾ ms ¾ 10 ¾ MW ¾ 0.1 ¾ mA ¾ ±25 ¾ mV ¾ 60 ¾ dB ¾ 60 ¾ dB ¾ 65 ¾ dB ¾ 1.5 ¾ MHz ¾ 4.5 ¾ VPP Conditions VDD Unit DTMF Signal Input Signal Level tPU dBm Gain Setting Amplifier RIN Input Resistance 5V IIN Input Leakage Current 5V VOS Offset Voltage 5V PSRR Power Supply Rejection 5V ¾ VSS<(VVP,VVN)<VDD ¾ 100 Hz -3V<VIN<3V CMRR Common Mode Rejection 5V AVO Open Loop Gain 5V fT Gain Band Width 5V VOUT Output Voltage Swing 5V RL Load Resistance (GS) 5V ¾ ¾ 50 ¾ kW CL Load Capacitance (GS) 5V ¾ ¾ 100 ¾ pF VCM Common Mode Range 5V ¾ 3.0 ¾ VPP ¾ RL>100kW No load Steering Control tDP Tone Present Detection Time 5V 5 11 14 ms tDA Tone Absent Detection Time 5V ¾ 4 8.5 ms tACC Acceptable Tone Duration 5V ¾ ¾ 42 ms tREJ Rejected Tone Duration 5V 20 ¾ ¾ ms tIA Acceptable Inter-digit Pause 5V ¾ ¾ 42 ms tIR Rejected Inter-digit Pause 5V 20 ¾ ¾ ms tPDO Propagation Delay (RT/GT to DO) 5V ¾ 8 11 ms tPDV Propagation Delay (RT/GT to DV) 5V ¾ 12 ¾ ms tDOV Output Data Set Up (DO to DV) 5V ¾ 4.5 ¾ ms tDDO Disable Delay (OE to DO) 5V ¾ 300 ¾ ns tEDO Enable Delay (OE to DO) 5V ¾ 50 60 ns Note: DO=D0~D3 Rev. 1.00 4 March 30, 2006 HT9172 V 1 1 0 0 k W T o n e 0 .1 m F 2 3 4 1 0 0 k W 5 6 3 .5 7 9 5 4 5 M H z 7 8 2 0 p F 2 0 p F 9 V P V D D V N R T /G T G S E S T V R E F D V IN H D 3 P W D N D 2 X 1 D 1 X 2 D 0 V S S O E D D 0 .1 m F 1 8 0 .1 m F 1 7 1 6 1 5 3 0 0 k W 1 4 1 3 1 2 1 1 1 0 H T 9 1 7 2 Figure 1. Test Circuit Functional Description When the input signal is recognized as an effective DTMF tone, the DV line will go high, and the corresponding DTMF tone code will be generated. Overview The HT9172 tone decoder consists of three band pass filters and two digital decode circuits to convert a DTMF tone into a digital code output. Steering Control Circuit The device contains an operational amplifier to adjust the input signal level as shown in Figure 2. The steering control circuit is used to measure the effective signal duration and for protecting against valid signal drop out. This is achieved using an analog delay which is implemented using an external RC time-constant, controlled by the output line EST. (a ) S ta n d a r d In p u t C ir c u it C V V P R 1 i V N The timing diagram is shown in Figure 3. The EST pin is normally low and will pull the RT/GT pin low via the external RC network. When a valid tone input is detected, the EST pin will go high, which will in turn pull the RT/GT pin high through the RC network. H T 9 1 7 2 R F G S V R E F (b ) D iffe r e n tia l In p u t C ir c u it V i1 V i2 C 1 R 1 C 2 R 2 When the voltage on RT/GT rises from 0 to VTRT, which is 2.35V for a 5V power supply, the input signal is effective, and the corresponding code will be generated by the code detector. After D0~D3 have been latched, DV will go high. When the voltage on RT/GT falls from VDD to VTRT, i.e. when there is no input tone, the DV output will go low, and D0~D3 will maintain their present data until a next valid tone input is produced. V P V N R 3 R 4 R 5 H T 9 1 7 2 G S V R E F Figure 2. Amplifier Input Application Circuits By selecting suitable external RC values, the minimum acceptable input tone duration, tACC, and the minimum acceptable inter-tone rejection, tIR, can be set. The values of the external RC components, can be chosen using the following formula. Also refer to Figure 5 for details. The pre-filter is a band rejection filter which will reject frequencies between 350Hz to 400Hz. The low group filter, filters the low group frequency signal output whereas the high group filter, filters the high group frequency signal output. tACC=tDP+tGTP; tIR=tDA+tGTA; where tACC: Tone duration acceptable time Each filter output is followed by a zero-crossing detector with incorporates hysteresis. When the signal amplitude at the output exceeds a specified level, it is transferred to a full swing logic signal. Rev. 1.00 tDP: EST output delay time (²L²®²H²) tGTP: Tone present time tIR: Inter-digit pause rejection time 5 March 30, 2006 HT9172 Timing Diagrams tR t IA E J t IR T o n e n T o n e tD P tD T o n e n + 1 tD P tD A P E S T tA R T /G T V C C T R T tP D 0 ~ D 3 tG D O T o n e C o d e n 1 T A T o n e C o d e n + 1 T o n e C o d e n tD tP tG T P tP O V D V D V D V tD D O tE D O O E Figure 3. Steering Timing T o n e T o n e P W D N E S T tP U Figure 4. Power-up Timing Rev. 1.00 6 March 30, 2006 HT9172 (a) Fundamental circuit: tGTP = R ´ C ´ Ln (VDD / (VDD - VTRT)) tGTA = R ´ C ´ Ln (VDD / VTRT) (c) tGTP > tGTA : tGTP = R1 ´ C ´ Ln (VDD / (VDD - VTRT)) tGTA = (R1 // R2) ´ C ´ Ln (VDD / VTRT) V V D D D D V D D V D D H T 9 1 7 2 H T 9 1 7 2 C R T /G T R E S T C R T /G T R 1 E S T D 1 R 2 (b) tGTP < tGTA : tGTP = (R1 // R2) ´ C ´ Ln (VDD - VTRT)) tGTA = R1 ´ C ´ Ln (VDD / VTRT) V D D V D D H T 9 1 7 2 C R T /G T R 1 E S T D 1 R 2 Figure 5. Steering Time Adjustment Circuits DTMF Dialing Matrix C O L 1 C O L 2 C O L 3 C O L 4 R O W 1 1 2 3 A R O W 2 4 5 6 B R O W 3 7 8 9 C 0 # D R O W 4 * DTMF Data Output Table Low Group (Hz) High Group (Hz) Digit OE D3 D2 D1 D0 697 1209 1 H L L L H 697 1336 2 H L L H L 697 1477 3 H L L H H 770 1209 4 H L H L L 770 1336 5 H L H L H 770 1477 6 H L H H L 852 1209 7 H L H H H 852 1336 8 H H L L L 852 1477 9 H H L L H 941 1336 0 H H L H L 941 1209 * H H L H H 941 1477 # H H H L L 697 1633 A H H H L H 770 1633 B H H H H L 852 1633 C H H H H H 941 1633 D H L L L L ¾ ¾ ANY L Z Z Z Z Note: ²Z² High impedance; Rev. 1.00 ²ANY² Any digit 7 March 30, 2006 HT9172 Data Output The data outputs, D0~D3, are tristate outputs. When the OE input is low, the D0~D3 data outputs, will be in a high impedance condition. Application Circuits Application Circuit 1 V 1 1 0 0 k W D T M F 2 3 0 .1 m F 4 1 0 0 k W 5 T o o th e r d e v ic e 6 7 8 X 't a l 9 C 2 V S S C 1 Note: V P V D D V N R T /G T G S E S T V R E F D V IN H D 3 P W D N D 2 X 1 D 1 X 2 D 0 V S S O E D D 0 .1 m F 1 8 1 7 1 6 0 .1 m F 3 0 0 k W 1 5 1 4 1 3 T o o th e r d e v ic e 1 2 1 1 1 0 H T 9 1 7 2 X¢tal = 3.579545MHz crystal C1 = C2 @ 20pF X¢tal = 3.58MHz ceramic resonator C1 = C2 @ 39pF Application Circuit 2 V 0 .1 m F R 1 0 .1 m F A v = R 5 = 2 3 0 k 0 0 0 k 5 0 0 0 W k W k W C 1 C 2 D V IN H 6 P W D N D 3 D 2 7 X 't a l k W V N V R E F 5 W V D D R T /G T G S 4 T o o th e r d e v ic e = 3 = 6 = 1 = 6 = 1 = 3 V P E S T R 5 R 4 R 2 R 2 R 4 R 3 = R 2 + R 4 Note: R 2 R 3 R 3 + R 5 R 1 + R 3 E x a m p le : A v R 1 R 2 R 3 R 4 R 5 1 1 8 0 p F D T M F 8 9 V S S X 1 D 1 X 2 D 0 V S S O E D D 0 .1 m F 1 8 1 7 0 .1 m F 1 6 3 0 0 k W 1 5 1 4 1 3 1 2 1 1 T o o th e r d e v ic e 1 0 H T 9 1 7 2 X¢tal = 3.579545MHz crystal C1 = C2 @ 20pF X¢tal = 3.58MHz ceramic resonator C1 = C2 @ 39pF Rev. 1.00 8 March 30, 2006 HT9172 Package Information 18-pin DIP (300mil) Outline Dimensions A B 1 8 1 0 1 9 H C D E a G I F Symbol Rev. 1.00 Dimensions in mil Min. Nom. Max. A 895 ¾ 915 B 240 ¾ 260 C 125 ¾ 135 D 125 ¾ 145 E 16 ¾ 20 F 50 ¾ 70 G ¾ 100 ¾ H 295 ¾ 315 I 335 ¾ 375 a 0° ¾ 15° 9 March 30, 2006 HT9172 18-pin SOP (300mil) Outline Dimensions 1 0 1 8 B A 9 1 C C ' G H D E Symbol Rev. 1.00 a F Dimensions in mil Min. Nom. Max. A 394 ¾ 419 B 290 ¾ 300 C 14 ¾ 20 C¢ 447 ¾ 460 D 92 ¾ 104 E ¾ 50 ¾ F 4 ¾ ¾ G 32 ¾ 38 H 4 ¾ 12 a 0° ¾ 10° 10 March 30, 2006 HT9172 Product Tape and Reel Specifications Reel Dimensions D T 2 A C B T 1 SOP 18W Symbol Description Dimensions in mm A Reel Outer Diameter 330±1.0 B Reel Inner Diameter 62±1.5 C Spindle Hole Diameter D Key Slit Width 2.0±0.5 T1 Space Between Flange 24.8+0.3 -0.2 T2 Reel Thickness 30.2±0.2 Rev. 1.00 13.0+0.5 -0.2 11 March 30, 2006 HT9172 Carrier Tape Dimensions P 0 D P 1 t E F W C D 1 B 0 P K 0 A 0 SOP 18W Symbol Description Dimensions in mm W Carrier Tape Width 24.0+0.3 -0.1 P Cavity Pitch 16.0±0.1 E Perforation Position 1.75±0.1 F Cavity to Perforation (Width Direction) 11.5±0.1 D Perforation Diameter 1.5±0.1 D1 Cavity Hole Diameter 1.5+0.25 P0 Perforation Pitch 4.0±0.1 P1 Cavity to Perforation (Length Direction) 2.0±0.1 A0 Cavity Length 10.9±0.1 B0 Cavity Width 12.0±0.1 K0 Cavity Depth 2.8±0.1 t Carrier Tape Thickness 0.3±0.05 C Cover Tape Width Rev. 1.00 21.3 12 March 30, 2006 HT9172 Holtek Semiconductor Inc. (Headquarters) No.3, Creation Rd. II, Science Park, Hsinchu, Taiwan Tel: 886-3-563-1999 Fax: 886-3-563-1189 http://www.holtek.com.tw Holtek Semiconductor Inc. (Taipei Sales Office) 4F-2, No. 3-2, YuanQu St., Nankang Software Park, Taipei 115, Taiwan Tel: 886-2-2655-7070 Fax: 886-2-2655-7373 Fax: 886-2-2655-7383 (International sales hotline) Holtek Semiconductor Inc. (Shanghai Sales Office) 7th Floor, Building 2, No.889, Yi Shan Rd., Shanghai, China 200233 Tel: 021-6485-5560 Fax: 021-6485-0313 http://www.holtek.com.cn Holtek Semiconductor Inc. (Shenzhen Sales Office) 43F, SEG Plaza, Shen Nan Zhong Road, Shenzhen, China 518031 Tel: 0755-8346-5589 Fax: 0755-8346-5590 ISDN: 0755-8346-5591 Holtek Semiconductor Inc. (Beijing Sales Office) Suite 1721, Jinyu Tower, A129 West Xuan Wu Men Street, Xicheng District, Beijing, China 100031 Tel: 010-6641-0030, 6641-7751, 6641-7752 Fax: 010-6641-0125 Holmate Semiconductor, Inc. (North America Sales Office) 46712 Fremont Blvd., Fremont, CA 94538 Tel: 510-252-9880 Fax: 510-252-9885 http://www.holmate.com Copyright Ó 2006 by HOLTEK SEMICONDUCTOR INC. The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. Holtek¢s products are not authorized for use as critical components in life support devices or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw. Rev. 1.00 13 March 30, 2006