HYNIX HY62U8100BLLST

HY62U8100B Series
128Kx8bit CMOS SRAM
Document Title
128K x8 bit 3.0V Low Power CMOS slow SRAM
Revision History
Revision No
History
Draft Date
Remark
10
Initial Revision History Insert
Revised
- Insert 70ns Part
Jul.25.2000
Final
11
Change the Notch Location of sTSOP
- Left-Top => Left-Center
Sep.04.2000
Final
12
Marking Information Add
Revised
- AC Test Condition Add : 5pF Test Load
Dec.04.2000
Final
13
Changed Logo
- HYUNDAI -> hynix
- Marking Information Change
Apr.30.2001
Final
This document is a general product description and is subject to change without notice. Hynix Electronics does not assume any
responsibility for use of circuits described. No patent licenses are implied.
Rev 13 / Apr. 2001
Hynix Semiconductor
HY62U8100B Series
DESCRIPTION
FEATURES
The HY62U8100B is a high speed, low power and
1M bit CMOS SRAM organized as 131,072 words
by 8bit. The HY62U8100B uses high performance
CMOS process technology and designed for high
speed low power circuit technology. It is
particulary well suited for used in high density low
power system application. This device has a data
retention mode that guarantees data to remain
valid at a minimum power supply voltage of 2.0V.
• Fully static operation and Tri-state output
• TTL compatible inputs and outputs
• Battery backup(LL-part)
-. 2.0V(min) data retention
• Standard pin configuration
-. 32 - SOP - 525mil
-. 32 - TSOP-I - 8X20(Standard and Reversed)
-. 32 - sTSOP-I - 8X13.4
(Standard and Reversed)
Product
No.
HY62U8100B
HY62U8100B-E
HY62U8100B-I
Voltage
(V)
2.7~3.3
2.7~3.3
2.7~3.3
Speed
(ns)
70*/85/100
70*/85/100
70*/85/100
Operation
Current/Icc(mA)
5
5
5
Standby Current(uA)
LL
10
15
15
Temperature
(°C)
0~70
-25~85(E)
-40~85(I)
Note 1. Blank : Commercial, E : Extended, I : Industrial
2. Current value is max.
* 70ns is available with 30pF test load
PIN CONNECTION
NC
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O1
I/O2
I/O3
Vss
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Vcc
A15
CS2
/WE
A13
A8
A9
A11
/OE
A10
/CS1
I/O8
I/O7
I/O6
I/O5
I/O4
SOP
A11
A9
A8
A13
/WE
CS2
A15
Vcc
NC
A16
A14
A12
A7
A6
A5
A4
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
/OE
A10
/CS1
DQ8
DQ7
DQ6
DQ5
DQ4
Vss
DQ3
DQ2
DQ1
A0
A1
A2
A3
A11
A9
A8
A13
/WE
CS2
A15
Vcc
NC
A16
A14
A12
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
TSOP-I
( Standard )
sTSOP-I
(Standard)
PIN DESCRIPTION
A0
ROW
DECODER
WRITE DRIVER
MEMORY ARRAY
128K x 8
I/O1
DATA I/O
BUFFER
SENSE AMP
A16
COLUMN
DECODER
Pin Function
Chip Select 1
Chip Select 2
Write Enable
Output Enable
Address Inputs
Data Inputs / Outputs
Power(2.7V~3.3V)
Ground
BLOCK DIAGRAM
ADD INPUT
BUFFER
Pin Name
/CS1
CS2
/WE
/OE
A0 ~ A16
I/O1 ~ I/O8
Vcc
Vss
/OE
A10
/CS1
DQ8
DQ7
DQ6
DQ5
DQ4
Vss
DQ3
DQ2
DQ1
A0
A1
A2
A3
I/O8
/CS1
/OE
COLUMN
DECODER
CS2
/WE
Rev 13 / Apr. 2001
2
HY62U8100B Series
ORDERING INFORMATION
Part No.
HY62U8100BLLG
HY62U8100BLLT1
HY62U8100BLLR1
HY62U8100BLLST
HY62U8100BLLSR
HY62U8100BLLG-E
HY62U8100BLLT1-E
HY62U8100BLLR1-E
HY62U8100BLLST-E
HY62U8100BLLSR-E
HY62U8100BLLG-I
HY62U8100BLLT1-I
HY62U8100BLLR1-I
HY62U8100BLLST-I
HY62U8100BLLSR-I
Speed
70*/85/100
70*/85/100
70*/85/100
70*/85/100
70*/85/100
70*/85/100
70*/85/100
70*/85/100
70*/85/100
70*/85/100
70*/85/100
70*/85/100
70*/85/100
70*/85/100
70*/85/100
Power
LL-part
LL-part
LL-part
LL-part
LL-part
LL-part
LL-part
LL-part
LL-part
LL-part
LL-part
LL-part
LL-part
LL-part
LL-part
Temp.
E
E
E
E
E
I
I
I
I
I
Package
SOP
TSOP-I(Standard)
TSOP-I(Reversed)
smaller TSOP-I(Standard)
smaller TSOP-I(Reversed)
SOP
TSOP-I(Standard)
TSOP-I(Reversed)
Smaller TSOP-I(Standard)
Smaller TSOP-I(Reversed)
SOP
TSOP-I(Standard)
TSOP-I(Reversed)
Smaller TSOP-I(Standard)
Smaller TSOP-I(Reversed)
Note 1. Blank : Commercial, E : Extended, I : Industrial
* 70ns is available with 30pF test load
ABSOLUTE MAXIMUM RATING (1)
Symbol
Vcc, VIN, VOUT
TA
Parameter
Power Supply, Input/Output Voltage
Operating Temperature
TSTG
PD
IOUT
TSOLDER
Storage Temperature
Power Dissipation
Data Output Current
Lead Soldering Temperature & Time
Rating
-0.3 to 4.6
0 to 70
-25 to 85
-40 to 85
-65 to 125
10
50
260 • 10
Unit
V
°C
°C
°C
°C
W
mA
°C•sec
Remark
HY62U8100B
HY62U8100B-E
HY62U8100B-I
Note
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent
damage to the device. This is stress rating only and the functional operation of the device under these or
any other conditions above those indicated in the operation of this specification is not implied.
Exposure to the absolute maximum rating conditions for extended period may affect reliability.
TRUTH TABLE
/CS1
H
X
L
L
L
CS2
X
L
H
H
H
/WE
X
X
H
H
L
/OE
X
X
H
L
X
Mode
Deselected
Deselected
Output Disabled
Read
Write
I/O
High-Z
High-Z
High-Z
Data Out
Data In
Power
Standby
Standby
Active
Active
Active
Note :
1. H=VIH, L=VIL, X=don't care( VIH or VIL )
Rev 13 / Apr. 2001
2
HY62U8100B Series
RECOMMENDED DC OPERATING CONDITION
Symbol
Vcc
Vss
VIH
VIL
Parameter
Supply Voltage
Ground
Input High Voltage
Input Low Voltage
Min.
2.7
0
2.2
-0.3(1)
Typ.
3.0
0
-
Max.
3.3
0
Vcc+0.3
0.6
Unit
V
V
V
V
Note :
1. VIL = -1.5V for pulse width less than 30ns and not 100% tested
DC ELECTRICAL CHARACTERISTICS
Vcc = 2.7V~3.3V, TA = 0°C to 70°C / -25°C to 85°C (E) / -40°C to 85°C (I), unless otherwise specified
Symbol
Parameter
Test Condition
Min. Typ. Max.
ILI
Input Leakage Current
Vss < VIN < Vcc
-1
1
ILO
Output Leakage Current
Vss <VOUT < Vcc,
-1
1
/CS1 = VIH or CS2 = VIL or
/OE = VIH or /WE = VIL
Icc
Operating Power Supply
/CS1 = VIL, CS2 = VIH,
5
Current
VIN = VIH or VIL, II/O = 0mA
ICC1
Average Operating
/CS1 = VIL, CS2 = VIH,
30
Current
VIN = VIH or VIL
Cycle Time = Min, 100% duty,
IIO = 0mA
ISB
TTL Standby Current
/CS1 = VIH or CS2 = VIL ,
0.5
(TTL Input)
VIN = VIH or VIL
ISB1
Standby
HY62U8100B
/CS1 > Vcc - 0.2V or CS2 < 0.2V,
0.5
10
Current
HY62U8100B-E VIN > Vcc - 0.2V or
0.5
15
(CMOS Input)
HY62U8100B-I
VIN < Vss + 0.2V
0.5
15
VOL
Output Low Voltage
IOL = 2.1mA
0.4
VOH
Output High Voltage
IOH = -1.0mA
2.2
-
Unit
uA
uA
mA
mA
mA
uA
uA
uA
V
V
Note : Typical values are at Vcc = 3.0V, TA = 25°C
CAPACITANCE
(Temp = 25°C, f= 10MHz)
Symbol
Parameter
CIN
Input Capacitance
COUT
Output Capacitance
Condition
VIN = 0V
VI/O = 0V
Max.
6
8
Unit
pF
pF
Note : These parameters are sampled and not 100% tested
Rev 13 / Apr. 2001
3
HY62U8100B Series
AC CHARACTERISTICS
Vcc = 2.7V~3.3V, TA = 0°C to 70°C / -25°C to 85°C (E) / -40°C to 85°C (I), unless otherwise specified
-70*
-85
-10
# Symbol
Parameter
Min.
Max. Min.
Max. Min
Max.
READ CYCLE
1
tRC
Read Cycle Time
70
85
100
2
tAA
Address Access Time
70
85
100
3
tACS
Chip Select Access Time
70
85
100
4
tOE
Output Enable to Output Valid
40
45
50
5
tCLZ
Chip Select to Output in Low Z
10
10
10
6
tOLZ
Output Enable to Output in Low Z
5
5
5
7
tCHZ
Chip Deselection to Output in High Z
0
30
0
30
0
30
8
tOHZ
Out Disable to Output in High Z
0
30
0
30
0
30
9
tOH
Output Hold from Address Change
10
10
15
WRITE CYCLE
10 tWC
Write Cycle Time
70
85
100
11 tCW
Chip Selection to End of Write
60
70
80
12 tAW
Address Valid to End of Write
60
70
80
13 tAS
Address Set-up Time
0
0
0
14 tWP
Write Pulse Width
50
55
75
15 tWR
Write Recovery Time
0
0
0
16 tWHZ
Write to Output in High Z
0
25
0
30
0
35
17 tDW
Data to Write Time Overlap
30
40
45
18 tDH
Data Hold from Write Time
0
0
0
19 tOW
Output Active from End of Write
5
5
10
Note * 70ns is available with 30pF test load
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
AC TEST CONDITIONS
TA = 0°C to 70°C / -25°C to 85°C (E) / -40°C to 85°C (I), unless otherwise specified
Parameter
Value
Input Pulse Level
0.4V to 2.2V
Input Rise and Fall Time
5ns
Input and Output Timing Reference Level
1.5V
Output Load
tCLZ,tOLZ,tCHZ,tOHZ,tWHZ,tOW
CL = 5pF + 1TTL Load
Others
CL = 100pF + 1TTL Load
CL = 30pF + 1TTL Load
AC TEST LOADS
TTL
CL(1)
Note : 1 Including jig and scope capacitance
Rev 13 / Apr. 2001
4
HY62U8100B Series
TIMING DIAGRAM
READ CYCLE 1(Note 1,4)
tRC
ADDR
tAA
tOH
tACS
/CS1
CS2
tCHZ(3)
tOE
/OE
tOLZ(3)
Data
Out
tOHZ(3)
tCLZ(3)
High-Z
Data Valid
READ CYCLE 2(Note 1,2,4)
tRC
ADDR
tAA
tOH
tOH
Data
Out
Previous Data
Data Valid
READ CYCLE 3(Note 1,2,4)
/CS1
CS2
tACS
tCLZ(3)
Data
Out
tCHZ(3)
Data Valid
Notes:
1. A read occurs during the overlap of a low /OE, a high /WE, a low /CS1 and a high CS2.
2. /OE = VIL
3. Transition is measured + 200mV from steady state voltage.
This parameter is sampled and not 100% tested.
4. /CS1 in high for the standby, low for active
CS2 in low for the standby, high for active
Rev 13 / Apr. 2001
5
HY62U8100B Series
WRITE CYCLE 1(1,4,5,8) (/WE Controlled)
tW C
ADDR
tW R (2)
tCW
/C S 1
CS2
tAW
tW P
/W E
tAS
Data In
tDW
High-Z
tDH
Data Valid
tW H Z (3,7)
tOW
(5 )
(6 )
Data
Out
WRITE CYCLE 2 (Note 1,4,5,8) (/CS1, CS2 Controlled)
tW C
ADDR
tCW
tAS
tW R (2)
/CS1
tAW
CS2
tW P
/W E
tDW
Data In
Data
Out
High-Z
tDH
Data Valid
High-Z
Notes:
1. A write occurs during the overlap of a low /WE, a low /CS1 and a high CS2.
2. tWR is measured from the earlier of /CS1 or /WE going high or CS2 going low to the end of
write cycle.
3. During this period, I/O pins are in the output state so that the input signals of opposite phase to the
output must not be applied.
4. If the the /CS1 low transition and CS2 high transition occur simultaneously with the /WE low transition
or after the /WE transition, outputs remain in a high impedance state.
6. Q(data out) is the same phase with the write data of this write cycle.
7. Q(data out) is the read data of the next address.
8. Transition is measured +200mV from steady state.
This parameter is sampled and not 100% tested.
9. /CS1 in high for the standby, low for active
CS2 in low for the standby, high for active
Rev 13 / Apr. 2001
6
HY62U8100B Series
DATA RETENTION ELECTRIC CHARACTERISTIC
TA=0°C to 70°C / -25°C to 85°C (E) /-40°C to 85°C (I)
Sym
Parameter
Test Condition
VDR
Vcc for Data Retention
/CS1>Vcc-0.2V or CS2<0.2V,
VIN > Vcc - 0.2V or VIN<Vss + 0.2V
ICCDR Data
HY62U8100B
Vcc=3.0V,
Retention HY62U8100B-E /CS1>Vcc - 0.2V or CS2<0.2V,
Current
HY62U8100B-I
VIN > Vcc - 0.2V or VIN < Vss + 0.2V
tCDR
Chip Deselect to Data
See Data Retention Timing
Retention Time
Diagram
tR
Operating Recovery Time
Notes:
1. Typical values are under the condition of TA = 25°C.
2. tRC is read cycle time.
Min
2.0
Typ
-
Max
-
Unit
V
0
0.5
0.5
0.5
-
10
15
15
-
uA
uA
uA
ns
tRC(2)
-
-
ns
DATA RETENTION TIMING DIAGRAM 1
DATA RETENTION MODE
VCC
2.7V
tCDR
tR
2.2V
VDR
CS1>VCC-0.2V
CS1
VSS
DATA RETENTION TIMING DIAGRAM 2
DATA RETENTION MODE
VCC
2.7V
tCDR
tR
CS2
VDR
0.4V
VSS
Rev 13 / Apr. 2001
CS2<0.2V
7
HY62U8100B Series
PACKAGE INFORMATION
32pin 525mil Small Outline Package(G)
UNIT : INCH(mm)
0.810(20.574)
0.804(20.422)
0.444(11.278)
0.438(11.125)
0.564(14.326)
0.546(13.868)
0.109(2.769)
0.099(2.515)
0.011(0.279)
0.004(0.102)
0.050(1.27)BSC
0.0125(0.318)
0.0061(0.155)
0.020(0.508)
0 deg
0.0425(1.080)
0.014(0.356)
8 deg
0.0235(0.597)
32pin 8x20mm Thin Small Outline Package Standard(T1)
Rev 13 / Apr. 2001
8
HY62U8100B Series
#1
#32
UNIT : INCH(mm)
0.319(8.103)
0.311(7.900)
#17
#16
0.728(18.491)
0.720(18.288)
0.792(20.117)
0.784(19.914)
0.041(1.05)
0.037(0.95)
0.006(0.15)
0.002(0.05)
0.008(0.21)
0.004(0.10)
0.025(0.64)
0.021(0.54)
0.020(0.50)
BSC
0.011(0.27)
0.007(0.17)
32pin 8x20mm Thin Small Outline Package Reversed(R1)
#16
#17
UNIT : INCH(mm)
0.319(8.103)
0.311(7.900)
#32
#1
0.728(18.491)
0.720(18.288)
0.792(20.117)
0.784(19.914)
0.041(1.05)
0.037(0.95)
0.006(0.15)
0.002(0.05)
0.025(0.64)
0.021(0.54)
Rev 13 / Apr. 2001
0.008(0.21)
0.004(0.1)
0.020(0.50)
BSC
0.011(0.27)
0.007(0.17)
9
HY62U8100B Series
32pin 8x13.4mm Smaller Thin Small Outline Package Standard(ST)
#1
#32
UNIT : INCH(mm)
0.319(8.1)
0.311(7.9)
#17
#16
0.468(11.9)
0.460(11.7)
0.536(13.6)
0.520(13.2)
0.041(1.05)
0.037(0.95)
0.008(0.20)
0.002(0.05)
0.008(0.2)
0.004(0.1)
0.024(0.6)
0.016(0.4)
0.020(0.50)
0.011(0.27)
0.007(0.17)
32pin 8x13.4mm Thin Small Outline Package Reversed(SR)
#16
#17
UNIT : INCH(mm)
0.319(8.1)
0.311(7.9)
#32
#1
0.468(11.9)
0.460(11.7)
0.536(13.6)
0.520(13.2)
0.041(1.05)
0.037(0.95)
0.008(0.20)
0.002(0.05)
0.024(0.6)
0.016(0.4)
Rev 13 / Apr. 2001
0.008(0.2)
0.004(0.1)
0.020(0.50)
0.011(0.27)
0.007(0.17)
10
HY62U8100B Series
MARKING INFORMAION
Package
SOP
TSOP-I
sTSOP
Marking Example
h
y
n
i
x
H
Y
6
2
U
y
y
w
w
p
h
y
n
i
x
H
Y
6
2
U
y
y
w
w
p
H
Y
6
2
U
8
c
c
S
T
-
s
y
y
w
w
p
8
8
1
1
0
0
B
c
c
0
0
B
c
c
T
1
0
0
B
s
t
O
R
K
K
O
R
E
A
G
-
s
s
t
K
O
R
E
A
1
-
s
s
t
Index
• hynix
• KOREA / KOR
• HY62U8100B
• yy
• ww
•p
• cc
• G / T1 / ST
• ss
•t
Note
- Capital Letter
- Small Letter
Rev 13 / Apr. 2001
: hynix Logo
: Origin Country
: Part Name
: Year ( ex : 00 = year 2000, 01 = year 2001 )
: Work Week ( ex : 12 = ww12 )
: Process Code
: Power Consumption
-L
: Low Power
- LL
: Low Low Power
: Package Type
-G
: SOP
- T1
: TSOP-I
- ST
: sTSOP
: Speed
- 85
: 85ns
- 10
: 100ns
: Temperature
- Blank
: Commercial ( 0 ~ 70 °C )
-E
: Extended ( -25 ~ 85 °C )
-I
: Industrial ( -40 ~ 85 °C )
: Fixed Item
: Non-fixed Item (Except hynix)
11