HY64UD16162B Series Document Title 1M x 16 bit Low Low Power 1T/1C Pseudo SRAM Revision history Revision No. History Draft Date Remark 1.0 Dec. 3. ’02 Preliminary Initial This document is a general product description and is subject to change without notice. Hynix Semiconductor Inc. does not assume any responsibility for use of circuits described. No patent licenses are implied. Revision 1.0 / December. 2002 1 HY64UD16162B Series 1M x 16 bit Low Low Power 1T/1C SRAM DESCRIPTION FEATURES The HY64UD16162B is a 16Mbit 1T/1C SRAM featured by high-speed operation and super low power consumption. The HY64UD16162B adopts one transistor memory cell and is organized as 1,048,576 words by 16bits. The HY64UD16162B operates in the extended range of temperature and supports a wide operating voltage range. The HY64UD16162B also supports the deep power down mode for a super low standby current. The HY64UD16162B delivers the high-density low power SRAM capability to the high-speed low power system. • CMOS Process Technology • 1M x 16 bit Organization • TTL compatible and Tri-state outputs • Deep Power Down : Memory cell data hold invalid • Standard pin configuration : 48-FBGA(6mmX8mm) • Data mask function by /LB, /UB • Separated I/O Power Supply : Vddq PRODUCT FAMILY Product No. Power Dissipation Voltage [V] Vdd/Vddq Mode 3.0/3.0 3.0/3.0 3.0/3.0 3.0/3.0 1CS with /UB,/LB:tCS1 1CS with /UB,/LB:tCS1 1CS with /UB,/LB:tCS1 1CS with /UB,/LB:tCS1 HY64UD16162B-DF60E HY64UD16162B-DF60I HY64UD16162B-DF70E HY64UD16162B-DF70I (ISB1,Max) (IDPD,Max) (ICC2,Max) TBD 2µA 25mA TBD 2µA 25mA 85µA 2µA 25mA 85µA 2µA 25mA Speed tRC[ns] Temp. [°C] TBD TBD 70 70 -25~85 -40~85 -25~85 -40~85 Note 1. tCS - /UB,/LB=High : Chip Deselect. PIN CONNECTION (Top View) IO9 /OE A0 A1 A2 A5 A6 IO2 IO3 Vss A17 A7 IO4 Vdd Vddq IO13 DNU A16 IO5 Vss IO15 IO14 A14 A15 IO6 IO7 IO16 A19 A12 A13 /WE IO8 A18 A8 A9 A10 A11 NC A19 /CS1 CS2 /WE /OE /LB /UB MEMORY ARRAY 1,024K x 16 IO1 IO8 DATA I/O BUFFER IO10 IO11 WRITE DRIVER IO1 BLOCK DECODER /CS1 COLUMN DECODER A4 PRE DECODER A3 A0 ADD INPUT BUFFER /UB IO12 ROW DECODER CS2 SENSE AMP /LB BLOCK DIAGRAM IO9 IO16 CONTROL LOGIC PIN DESCRIPTION Pin Name /CS1 CS2 /WE /LB /UB DNU NC Pin Function Chip Select Deep Power Down Write Enable Lower Byte(I/O1~I/O8) Upper Byte(I/O9~I/O16) Do Not Use No Connection Pin Name /OE IO1~IO8 IO9~IO16 A0~A19 Vdd Vddq Vss Pin Function Output Enable Lower Data Inputs/Outputs Upper Data Inputs/Outputs Address Inputs Power Supply for Internal Circuit Power Supply for I/O Ground This document is a general product description and is subject to change without notice. Hynix Semiconductor Inc. does not assume any responsibility for use of circuits described. No patent licenses are implied. Revision 1.0 / December. 2002 2 HY64UD16162B Series ORDERING INFORMATION Part Number HY64UD16162B-E HY64UD16162B-I Speed 60 / 70 60 / 70 Power LL-Part LL-Part Temperature E1 I2* Package FBGA FBGA Note 1. E : Extended Temp. (-25°C ~ 85°C) 2. I : Industrial Temp. (-40°C ~ 85°C) ABSOLUTE MAXIMUM RATINGS 1 Symbol VIN VOUT Vdd Vddq Parameter Input Voltage Output Voltage Core Power Supply I/O Power Supply TA Rating -0.3 to Vdd+0.3 -0.3 to Vddq+0.3 Ambient Temperature TSTG PD Storage Temperature Power Dissipation Ball Soldering Temperature & Time TSOLDER -0.3 to 3.6 -0.3 to 3.6 -25 to 85 -40 to 85 -55 to 150 1.0 260•10 Unit V V V V °C °C °C W °C•sec Remark HY64PD16162A-E HY64PD16162A-I Note 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is stress rating only and the functional operation of the device under these or any other conditions above those indicated in the operation of this specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect reliability. TRUTH TABLE /CS1 CS2 H X X L L L L L L L L L H L H H H H H H H H H H /WE /OE /LB /UB Mode X X X L H H L H H L H H X X X X L H X L H X L H X X H L L L H H H L L L X X H H H H L L L L L L Deselected Deselected Deselected Write Read Output Disabled Write Read Output Disabled Write Read Output Disabled I/O Pin Power I/O1~I/O8 I/O9~I/O16 High-Z High-Z Standby High-Z High-Z Deep Power Down High-Z High-Z Standby DIN High-Z Active DOUT High-Z Active High-Z High-Z Active High-Z DIN Active High-Z DOUT Active High-Z High-Z Active DIN DIN Active DOUT DOUT Active High-Z High-Z Active Note 1. H=VIH, L=VIL, X=don’t care(VIL or VIH) 2. /UB, /LB(Upper, Lower Byte enable) These active LOW inputs allow individual bytes to be written or read. When /LB is LOW, data is written or read to the lower byte, I/O1 - I/O8. When /UB is LOW, data is written or read to the upper byte, I/O9 - I/O16. Revision 1.0 / December. 2002 3 HY64UD16162B Series RECOMMENDED DC OPERATING CONDITION Symbol Vdd Vddq VSS VIH VIL Parameter Core Supply Voltage I/O Supply Voltage Ground Input High Voltage Input Low Voltage Min. 2.7 2.7 0 2.2 -0.31 Typ. 3.0 3.0 - Max. 3.3 3.3 0 Vdd+0.3 0.6 Unit V V V V V Vdd=2.7V~3.3V, Vddq=2.7V~3.3V, TA= -25°C to 85°C(E) / -40°C to 85°C(I) Sym. Parameter Test Condition ILI Input Leakage Current VSS≤VIN≤Vdd Min. -1 Max. 1 Unit µA -1 1 µA Note 1. VIL=-1.5V for pulse width less than 10ns Undershoot is sampled, not 100% tested. DC ELECTRICAL CHARACTERISTICS ILO Output Leakage Current VSS≤VOUT≤Vddq, /CS1=VIH, CS2=VIH, /OE=VIH or /WE=VIL ICC Operating Power Supply Current /CS1=VIL, CS2=VIH, VIN=VIH or VIL, II/O=0mA - 3 mA - 5 mA Average Operating Current /CS1≤ 0.2V, CS2 ≥Vdd-0.2V, VIN ≤0.2V or VIN≥Vdd-0.2V, Cycle Time=1µs. 100% Duty, II/O=0mA 25 mA - 25 0.5 mA mA 60ns - TBD µA 70ns - 85 µA - 2 2.4 0.4 µA V V ICC1 /CS1=VIL, CS2=VIH, VIN=VIH or VIL, Cycle Time=Min. 100% Duty, II/O=0mA ICC2 ISB ISB1 IDPD VOH VOL 60ns 70ns TTL Standby Current /CS1,CS2=VIH or /UB,/LB= VIH Standby Current(CMOS Input) /CS1,CS2≥Vdd-0.2V, /UB,/LB ≤0.2V or /UB,/LB ≥Vdd-0.2V, otherwise CS2,/UB,/LB≥Vdd-0.2V, /CS1≤0.2V or /CS1≥Vdd-0.2V Deep Power Down Output High Voltage Output Low Voltage CS2≤VSS+0.2V IOH=-1.0mA IOL=2.1mA - - CAPACITANCE (Temp = 25°C, f=1.0MHz) Symbol Parameter CIN Input Capacitance(ADD, /CS1, CS2, /WE, /OE, /UB, /LB) COUT Output Capacitance(I/O) Condition VIN=0V VI/O=0V Max. Unit 8 pF 10 pF Note : These parameters are sampled and not 100% tested Revision 1.0 / December. 2002 4 HY64UD16162B Series AC CHARACTERISTICS Vdd=2.7V~3.3V, Vddq=2.7V~3.3V, TA = -25°C to 85°C(E) / -40°C to 85°C(I), unless otherwise specified -60 -70 # Symbol Parameter Unit Min. Max. Min. Max. Read Cycle Read Cycle Time 1 tRC 60 70 ns Address Access Time 2 tAA 60 70 ns Chip Select Access Time 3 tACS 60 70 ns Output Enable to Output Valid 4 tOE 20 20 ns /LB, /UB Access Time 5 tBA 60 70 ns Chip Select to Output in Low Z 6 tCLZ 10 10 ns Output Enable to Output in Low Z 7 tOLZ 5 5 ns /LB, /UB Enable to Output in Low Z 8 tBLZ 10 10 ns Chip Disable to Output in High Z 9 tCHZ 0 10 0 10 ns Out Disable to Output in High Z 10 tOHZ 0 10 0 10 ns /LB, /UB Disable to Output in High Z 11 tBHZ 0 10 0 10 ns Output Hold from Address Change 12 tOH 5 5 ns Write Cycle Write Cycle Time 13 tWC 60 70 ns Chip Selection to End of Write 14 tCW 55 60 ns Address Valid to End of Write 15 tAW 55 60 ns /LB, /UB Valid to End of Write 16 tBW 55 60 ns Address Set-up Time 17 tAS 0 0 ns Write Pulse Width 18 tWP 50 50 ns Write Recovery Time 19 tWR 0 0 ns Write to Output in High Z 20 tWHZ 0 15 0 20 ns Data to Write Time Overlap 21 tDW 25 30 ns Data Hold from Write Time 22 tDH 0 0 ns Output Active from End of Write 23 tOW 5 5 ns AC TEST CONDITIONS TA = -25°C to 85°C(E) / -40°C to 85°C(I), unless otherwise specified Parameter Value Input Pulse Level 0.4V to 2.2V Input Rising and Fall Time 5ns Input Timing Reference Level 1.5V Output Timing Reference Level 0.5*Vddq Output Load See Below AC TEST LOADS RL=50 Ohm DOUT VL=0.5*Vddq Z0=50 Ohm CL1 =50 pF Note 1. Including jig and scope capacitance. Revision 1.0 / December. 2002 5 HY64UD16162B Series Power-Up Sequence 1. Supply power with CS2 high. 2. Maintain stable power for longer than 200µs. Deep Power Down Entry Sequence 1. Keep CS2 low state. Deep power down mode is maintained while CS2 is low state. Deep Power Down Exit Sequence 1. Keep CS2 high state. 2. Maintain stable power for longer than 200µs. STATE DIAGRAM / CS1=VIL, CS2=VIH, /UB&/LB≠VIH Standby Standby Mode Mode / CS2=VIH Wait µs 200 Wait 200µ 200µs Active Active CS2=VIL CS2=VIH, /CS1=VIH or /UB,/LB=VIH Deep Deep Power Power Deep Power Down Exit Sequence Power-Up Sequence Power Power On On Down Down Mode Mode CS2=VIL Deep Power Down Entry Sequence STANDBY MODE CHARACTERISTICS Mode Memory Cell Data Standby Valid Deep Power Down Invalid Revision 1.0 / December. 2002 Standby Current[µA] TBD / 60ns 85 / 70ns 2 Wait Time[µs] 0 200 6 HY64UD16162B Series TIMING DIAGRAM READ CYCLE 1 ( Note 1, 4 ) tRC ADD tOH tAA tACS /CS1 tCHZ(3) CS2 Vih tBA /UB, /LB tBHZ(3) tOE /OE tOHZ(3) tOLZ(3) tBLZ(3) tCLZ(3) Data Out High-Z Data Valid READ CYCLE 2 ( Note 1, 2, 4 )( CS2=Vih ) tRC ADD tAA tOH tOH Previous Data Data Out Data Valid READ CYCLE 3 ( Note 1, 2, 4 )( CS2=Vih ) /CS1 /UB, /LB tACS tCHZ(3) tCLZ(3) Data Out High-Z Data Valid Notes : 1. Read Cycle occurs whenever a high on the /WE and /OE is low, while /UB and/or /LB and /CS1 and CS2 are in active status. 2. /OE = VIL 3. tCHZ, tBHZ and tOHZ are defined as the time at which the outputs achieve the high impedance state and tOLZ,tBLZ and tCLZ are defined as the time at which the outputs achieve the low impedance state. These are not referenced to output voltage levels. 4. /CS1 in high for the standby, low for active. /UB and /LB in high for the standby, low for active. Revision 1.0 / December. 2002 7 HY64UD16162B Series WRITE CYCLE 1 ( Note 1, 4, 5, 9, 10 ) ( /WE Controlled ) tWC ADD tWR(2) tCW /CS1 CS2 Vih tAW tBW /UB, /LB tWP tAS /WE tDW Data In High-Z tDH Data Valid tWHZ(3,8) tOW (6) (7) Data Out WRITE CYCLE 2 ( Note 1, 4, 5, 9, 10 ) ( /CS1 Controlled ) tWC ADD tAS tWR(2) tCW /CS1 CS2 Vih tAW tBW /UB, /LB tWP /WE tDW Data In Data Out High-Z tDH Data Valid High-Z Notes : 1. A write occurs during the overlap of low /CS1, low /WE and low /UB and/or /LB. 2. tWR is measured from the earlier of /CS1, /LB, /UB, or /WE going high to the end of write cycle. 3. During this period, I/O pins are in the output state so that the input signals of opposite phase to the output must not be applied. 4. If the /CS1, /LB and /UB low transition occur simultaneously with the /WE low transition or after the /WE transition, outputs remain in a high impedance state. 5. /OE is continuously low (/OE=VIL) 6. Q(data out) is the invalid data. 7. Q(data out) is the read data of the next address. 8. tWHZ is defined as the time at which the outputs achieve the high impedance state. It is not referenced to output voltage levels. 9. /CS1 in high for the standby, low for active. /UB and /LB in high for the standby, low for active. 10. Do not input data to the I/O pins while they are in the output state. Revision 1.0 / December. 2002 8 HY64UD16162B Series AVOID TIMING Hynix 1T/1C SRAM has a timing which is not supported at read operation. If your system has multiple invalid address signal shorter than tRC during over 10us at read operation which showed in abnormal timing, Hynix 1T/1C SRAM needs a normal read timing at least during 10us which showed in avoidable timing(1) or toggle the /CS1 to high(≥tRC) one time at least which showed in avoidable timing(2) ABNORMAL TIMING /CS1 ≥ 10us /WE < tRC ADD AVOIDABLE TIMING(1) /CS1 ≥ 10us /WE ≥ tRC ADD AVOIDABLE TIMING(2) ≥ tRC /CS1 ≥ 10us /WE < tRC ADD Revision 1.0 / December. 2002 9 HY64UD16162B Series PACKAGE DIMENSION 48ball Fine Pitch Ball Grid Array Package(F) BOTTOM BOTTOM VIEW VIEW TOP TOP VIEW VIEW A1 CORNER INDEX AREA A1 INDEX MARK B1 B A A A B C C D C1 E F C/2 G H 6 SIDE SIDE VIEW VIEW 5 4 3 2 1 B/2 5 E1 E C E2 SEATING PLANE A 3 D(DIAMETER) R unit : mm Symbol Min. Typ. Typ. Max. A B 5.90 0.75 6.00 6.10 B1 C 7.90 3.75 8.00 8.10 C1 - 5.25 - D 0.3 0.30 0.3 0.35 0.4 0.40 E - 1.00 1.10 E1 - 0.75 - E2 0.20 0.25 0.30 R - - 0.08 Revision 1.0 / December. 2002 4 NOTE. 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994. 2. ALL DIMENSIONS ARE MILLIMETERS. 3. DIMENSION “D” IS MEASURED AT THE MAXIMUM SOLDER BALL DIAMETER IN A PLANE PARALLEL TO DATUM C. 4. PRIMARY DATUM C(SEATING PLANE) IS DEFINED BY THE CROWN OF THE SOLDER BALLS. 5. THIS IS A CONTROLLING DIMENSION. 10 HY64UD16162B Series MARKING INFORMATION Package FBGA Marking Example H Y U D c s s t x x x x 1 x 6 1 6 2 B y y w w p K O R Index • HYUD16162B HY U D 16 16 2 B : Part Name : HYNIX : Power Supply : Tech. + Classification : Bit Organization : Density : Mode : Version • c • ss : Power Consumption : Speed : Vdd=2.7V~3.3V/Vddq=2.7V~3.3V : 1T+1C : x16 : 16M : 1CS with /UB,/LB;tCS : 3rd Generation • yy • ww • p : D – Low Low Power : 60 – 60ns 70 – 70ns : Temperature : E – Extended(-25 ~ 85°C) I – Industrial(-40 ~ 85°C) : Year (ex : 02 = year 2002, 03= year 2003) : Work Week ( ex : 12 = work week 12 ) : Process Code • xxxxx : Lot No. • KOR : Origin Country Note - Capital Letter - Small Letter : Fixed Item : Non-fixed Item • t Revision 1.0 / December. 2002 11