ICmic TM This X25097 device has been acquired by IC MICROSYSTEMS from Xicor, Inc. IC MICROSYSTEMS X25097 8K 1024 x 8 Bit 5MHz Low Power SPI Serial E2PROM with IDLockTM Memory FEATURES DESCRIPTION •5MHz Clock Rate •IDLock™ Memory —IDLock First or Last Page, any 1/4 or Lower 1/2 of E2PROM Array The X25097 is a CMOS 8K-bit serial E PROM, internally organized as 1024 x 8. The X25097 features a Serial Peripheral Interface (SPI) and software protocol allowing operation on a simple four-wire bus. The bus •Low Power CMOS —<1µA Standby Current —<3mA Active Current during Write —<400µA Active Current during Read •1.8V to 3.6V, 2.7V-5.5V or 4.5V to 5.5V Operation •Built-in Inadvertent Write Protection —Power-Up/Power-Down Protection Circuitry —Write Enable Latch —Write Protect Pin •SPI Modes (0,0 & 1,1) •1024 x 8 Bits —16 Byte Page Mode •Self-Timed Write Cycle —5ms Write Cycle Time (Typical) •High Reliability —Endurance: 100,000 Cycles/Byte —Data Retention: 100 Years —ESD: 2000V on all pins •8-Lead TSSOP Package •8-Lead SOIC Package •8-Lead PDIP Package signals are a clock input (SCK) plus separate data in (SI) and data out (SO) lines. Access to the device is 2 controlled through a chip select (CS) input, allowing any number of devices to share the same bus. IDLock is a programmble locking mechanism which allows the user to lock system ID and parametric data in 2 different portions of the E PROM memory space, ranging from as little as one page to as much as 1/2 of the total array. The X25097 also features a WP pin that can be used for hardwire protection of the part, disabling all write attempts, as well as a Write Enable Latch that must be set before a write operation can be initiated. TM The X25097 utilizes Xicor’s proprietary Direct Write cell, providing a minimum endurance of 100,000 cycles per byte and a minimum data retention of 100 years. FUNCTIONAL DIAGRAM DATA REGISTER SI Y DECODE LOGIC SO 16 SCK COMMAND DECODE AND CONTROL X DECODE LOGIC LOGIC 8 64 2 8K E PROM ARRAY (1024 x 8) CS WP HIGH VOLTAGE CONTROL WRITE CONTROL LOGIC 7038 FRM F01 ©Xicor, Inc. 1994, 1995, 1996 Patents Pending 7034-1.1 5/8/97 T1/C0/D0 SH 1 Characteristics subject to change without notice X25097 PIN DESCRIPTIONS PIN CONFIGURATION Serial Output (SO) SO is a push/pull serial data output pin. During a read cycle, data is shifted out on this pin. Data is clocked out by the falling edge of the serial clock. Not to scale 8 Lead SOIC/PDIP Serial Input (SI) SI is a serial data input pin. All opcodes, byte addresses, and data to be written to the memory are input on this pin. Data is latched by the rising edge of the serial clock. *0.197" 0.122" SI Serial Input SCK Serial Clock Input WP Write Protect Input VSS Ground VCC Supply Voltage NC No Connect 6 SCK 5 SI WP 3 V SS 4 NC 1 8 SCK VCC CS 2 7 SI 6 V SS SO 4 5 WP 3 X25097 7038 FRM F02.2 *SOIC Mesaurement PRINCIPLES OF OPERATION The X25097 is a 1024 x 8 E2PROM designed to interface directly with the synchronous Serial Peripheral Interface (SPI) of many popular microcontroller families. The X25097 contains an 8-bit instruction register. It is accessed via the SI input, with data being clocked in on the rising edge of SCK. CS must be LOW and the WP input must be HIGH during the entire operation. Table 1 contains a list of the instructions and their opcodes. All instructions, addresses and data are transferred MSB first. Data input is sampled on the first rising edge of SCK after CS goes LOW. SCK is static, allowing the user to stop the clock and then start it again to resume operations where left off. Description Serial Output NC X25097 0.252" PIN NAMES SO V CC 7 8 Lead TSSOP Write Protect (WP) When WP is LOW, nonvolatile writes to the X25097 are disabled, but the part otherwise functions normally. When WP is held HIGH, all functions, including nonvolatile writes operate normally. WP going LOW while CS is still LOW will interrupt a write to the X25097. If the internal write cycle has already been initiated, WP going low will have no affect on this write. Chip Select Input 8 2 *0.244" Chip Select (CS) When CS is HIGH, the X25097 is deselected and the SO output pin is at high impedance and unless an internal write operation is underway, the X25097 will be in the standby power mode. CS LOW enables the X25097, placing it in the active power mode. It should be noted that after power-up, a HIGH to LOW transition on CS is required prior to the start of any operation. CS 1 SO 7038 FRM F02 Serial Clock (SCK) The Serial Clock controls the serial bus timing for data input and output. Opcodes, addresses, or data present on the SI pin are latched on the rising edge of the clock input, while data on the SO pin change after the falling edge of the clock input. Symbol CS Write Enable Latch The X25097 contains a “Write Enable” latch. This latch must be SET before a write operation is initiated. The WREN instruction will set the latch and the WRDI instruction will reset the latch (Figure 4). This latch is automatically reset upon a power-up condition and after the completion of a byte or page write cycle. 7038 FRM T01 2 X25097 (Figure 1). The ID Lock bits define the ID Lock condition (Figure 1/Table1). The other bits are reserved and will return ’0’ when read. See Figure 3. IDLock Memory Xicor’s IDLock Memory provides a flexible mechanism to store and lock system ID and parametric information. There are seven distinct IDLock Memory areas within the array which vary in size from one page to as much as half of the entire array. These areas and associated address ranges are IDLocked by writing the appropriate two byte IDLock instruction to the device as described in Table 1 and Figure 7. Once an IDLock instruction has been completed, that IDLock setup is held in a nonvolatile Status Register (Figure 1) until the next IDLock instruction is issued. The sections of the memory array that are IDLocked can be read but not written until IDLock Protection is removed or changed. If a nonvolatile write is in progress, the Read Status Instruction returns a HIGH on SO. When the nonvolatile write cycle is completed, the status register data is read out. Clocking SCK is valid during a nonvolatile write in progress, but is not necessary. If the SCK line is clocked, the pointer to the status register is also clocked, even though the SO pin shows the status of the nonvolatile write operation (See Figure 3). Write Sequence Prior to any attempt to write data into the X25097, the “Write Enable” latch must first be set by issuing the WREN instruction (See Table 1 and Figure 4). CS is first taken LOW. Then the WREN instruction is clocked into the X25097. After all eight bits of the instruction are transmitted, CS must then be taken HIGH. If the user continues the write operation without taking CS HIGH after issuing the WREN instruction, the write operation will be ignored. Figure 1. Status Register/IDLock Byte 7 6 0 0 5 4 3 0 0 0 2 1 0 IDL2 IDL1 IDL0 Note: Bits [7:3] specified to be “0’s” 7038 FRM T02.1 Clock and Data Timing Data input on the SI line is latched on the rising edge of SCK. Data is output on the SO line by the falling edge of SCK. To write data to the E2PROM memory array, the user then issues the WRITE instruction, followed by the 16 bit address and the data to be written. Only the last 10 bits of the address are used and bits [15:10] are specified to be zeroes. This is minimally a thirty-two clock operation. CS must go LOW and remain LOW for the duration of the operation. The host may continue to write up to 16 bytes of data to the X25097. The only restriction is the 16 bytes must reside on the same page. If the address counter reaches the end of the page and the clock continues, the counter will “roll over” to the first address of the page and overwrite any data that may have been previously written. Read Sequence When reading from the E2PROM memory array, CS is first pulled LOW to select the device. The 8-bit READ instruction is transmitted to the X25097, followed by the 16-bit address, of which the last 10 bits are used (bits [15:10] specified to be zeroes). After the READ opcode and address are sent, the data stored in the memory at the selected address is shifted out on the SO line. The data stored in memory at the next address can be read sequentially by continuing to provide clock pulses. The address is automatically incremented to the next higher address after each byte of data is shifted out. When the highest address is reached (03FFh), the address counter rolls over to address 0000h, allowing the read cycle to be continued indefinitely. The read operation is terminated by taking CS HIGH. Refer to the Read Operation Sequence illustrated in Figure 2. For a byte or page write operation to be completed, CS can only be brought HIGH after bit 0 of the last data byte to be written is clocked in. If it is brought HIGH at any other time, the write operation will not be completed. Refer to Figures 5 and 6 for detailed illustration of the write sequences and time frames in which CS going HIGH are valid. Read Status Operation If there is not a nonvolatile write in progress, the Read Status instruction returns the ID Lock byte from the Status Register which contains the ID Lock bits IDL2-IDL0 3 X25097 Operational Notes The X25097 powers up in the following state: IDLock Operation Prior to any attempt to perform an IDLock Operation, the WREN instruction must first be issued. This instruction sets the “Write Enable” latch and allows the part to respond to an IDLock sequence (Figure 7). The IDLock instruction follows and consists of one command byte followed by one IDLock byte (See Figure 1). This byte contains the IDLock bits IDL2-IDL0. The rest of the bits [7:3] are unused and must be written as zeroes. Bringing CS HIGH after the two byte IDLock instruction initiates a nonvolatile write to the Status Register. Writing more than one byte to the Status Register will overwrite the previously written IDLock byte. See Table 1. • The device is in the low power, standby state. • A HIGH to LOW transition on CS is required to enter an active state and receive an instruction. • SO pin is at high impedance. • The “Write Enable” latch is reset. Data Protection The following circuitry has been included to prevent inadvertant writes: • The “Write Enable” latch is reset upon power-up. • A WREN instruction must be issued to set the “Write Enable” latch. • CS must come HIGH at the proper clock count in order to start a write cycle. Table 1. Instruction Set and Block Lock Protection Byte Definition Instruction Format* Instruction Name and Operation 0000 0110 WREN: Set the Write Enable Latch (Write Enable Operation) 0000 0100 WRDI: Reset the Write Enable Latch (Write Disable Operation) 0000 0001 IDLock Instruction—followed by: IDLock Byte: (See Figure 1) 0000 0000 --->NO IDLock: 00h-00h - - - - - - - - - - - >None of the Array 0000 0001 --->IDLock Q1: 0000h-00FFh - - - - - - - >Lower Quadrant (Q1) 0000 0010 --->IDLock Q2: 0100h-01FFh - - - - - - - >Q2 0000 0011 --->IDLock Q3: 0200h-02FFh - - - - - - - >Q3 0000 0100 --->IDLock Q4: 0300h-03FFh - - - - - - - >Upper Quadrant (Q4) 0000 0101 --->IDLock H1: 0000h-01FFh - - - - - - - >Lower Half of the Array (H1) 0000 0110 --->IDLock P0: 0000h-000Fh - - - - - - - >Lower Page (P0) 0000 0111 --->IDLock Pn: 03F0h-03FFh - - - - - - - >Upper Page (Pn) 0000 0101 READ STATUS: Reads IDLock & write in progress status on SO Pin 0000 0010 WRITE: Write operation followed by address and data 0000 0011 READ: Read operation followed by address 7038 FRM T03 *Instructions are shown with MSB in leftmost position. Instructions are transferred MSB first. 4 X25097 Figure 2. Read Operation Sequence CS 0 1 2 3 4 5 6 7 8 20 21 22 23 24 25 26 27 28 29 30 9 SCK READ INSTRUCTION (1 BYTE) BYTE ADDRESS (2 BYTE) 15 14 SI 3 2 HIGH IMPEDANCE 1 DATA OUT 0 7 SO 6 5 4 3 2 1 0 7038 FRM F03.1 Figure 3. Read Status Operation Sequence CS 0 1 2 3 4 5 6 7 ... SCK READ STATUS INSTRUCTION ... SI NONVOLATILE WRITE IN PROGRESS I D L 2 SO SO HIGH DURING NONVOLATILE WRITE CYCLE 5 SO = STATUS REG BIT WHEN NO NONVOLATILE WRITE CYCLE I D L 1 I D L 0 ... 7038 FRM F04.2 X25097 Figure 4. WREN/WRDI Sequence CS 0 1 2 3 4 5 6 7 SCK INSTRUCTION (1 BYTE) SI HIGH IMPEDANCE SO 7038 FRM F05.1 Figure 5. Byte Write Operation Sequence CS 0 1 2 3 4 5 6 7 8 20 21 22 23 24 25 26 27 28 29 30 31 9 SCK WRITE INSTRUCTION (1 BYTE) BYTE ADDRESS (2 BYTE) 15 14 SI 3 2 1 DATA BYTE 0 7 6 5 4 3 2 1 0 HIGH IMPEDANCE SO 7038 FRM F06 6 X25097 Figure 6. Page Write Operation Sequence CS 0 1 2 3 4 5 6 7 8 9 20 21 22 23 24 25 26 27 28 29 30 31 10 SCK PROGRAM INSTRUCTION BYTE ADDRESS (2 BYTE) 15 14 13 SI 3 2 DATA BYTE 1 1 0 7 6 5 4 3 2 1 0 150 151 149 148 147 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 146 145 CS 1 0 SCK DATA BYTE 2 SI 7 6 5 4 3 DATA BYTE 3 2 1 0 7 6 5 4 3 DATA BYTE 16 2 1 0 6 5 4 3 2 7038 FRM F07.3 Figure 7. IDLock Operation Sequence CS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SCK IDLock INSTRUCTION IDLock BYTE 0 SI 0 0 0 0 I D L 2 I D L 1 I D L 0 HIGH IMPEDANCE SO 7038 FRM F08.2 7 X25097 ABSOLUTE MAXIMUM RATINGS* Temperature under Bias ................... –65°C to +135°C Storage Temperature ....................... –65°C to +150°C Voltage on any Pin with Respect to VSS ................................... –1V to +7V D.C. Output Current.............................................. 5mA Lead Temperature (Soldering, 10 seconds).............................. 300°C *COMMENT Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and the functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS Temperature Min. Supply Voltage Max. Commercial 0°C +70°C Industrial –40°C +85°C Limits X25097 4.5V to 5.5V X25097-2.7 2.7V to 5.5V X25097-1.8 1.8V to 3.6V 7038 FRM T04 7038 FRM T05 D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions, unless otherwise specified.) Limits Symbol Parameter Min. Max. Units Test Conditions ICC1 VCC Supply Current (Write) 3 mA SCK = VCC x 0.1/VCC x 0.9 @ 5MHz, SO = Open, CS = VSS ICC2 VCC Supply Current (Read) 400 µA SCK = VCC x 0.1/VCC x 0.9 @ 5MHz, SO = Open, CS = VSS ISB VCC Supply Current (Standby) 1 µA CS = VCC, VIN = VSS or VCC ILI Input Leakage Current 10 µA VIN = VSS to VCC Output Leakage Current 10 µA VOUT = VSS to VCC ILO (1) Input LOW Voltage –0.5 VCC x 0.3 V (1) VCC x 0.7 VIL VIH Input HIGH Voltage VCC + 0.5 V VOL1 Output LOW Voltage 0.4 V VCC > 3.3V, IOL = 2.1mA VOL2 Output LOW Voltage 0.4 V 2V < VCC ≤ 3.3V, IOL = 1mA VOL3 Output LOW Voltage 0.4 V VCC ≤ 2V, IOL = 0.5mA VOH1 Output HIGH Voltage VCC – 0.8 V VCC > 3.3V, IOH = -1.0mA VOH2 Output HIGH Voltage VCC – 0.4 V 2V < VCC ≤ 3.3V, IOH = -0.4mA VOH3 Output HIGH Voltage VCC – 0.2 V VCC ≤ 2V, IOH = -0.25mA 7038 FRM T06 POWER-UP TIMING Symbol Parameter Min. Max. Units (2) Power-up to Read Operation 1 ms (2) Power-up to Write Operation 5 ms tPUR tPUW 7038 FRM T07 Notes: (1) VIL Min. and VIH Max. are for reference only and are not 100% tested. (2) tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated. These parameters are periodically sampled and not 100% tested. 8 X25097 CAPACITANCE TA = +25°C, f = 1MHz, VCC = 5.0V. Symbol Parameter (3) COUT (3) CIN Max. Units Conditions Output Capacitance (SO) 8 pF VOUT = 0V Input Capacitance (SCK, SI, CS, WP) 6 pF VIN = 0V 7038 FRM T08 Notes: (3) This parameter is periodically sampled and not 100% tested. EQUIVALENT A.C. LOAD CIRCUIT 5V A.C. TEST CONDITIONS 3.3V 2V 2061Ω 2696Ω 2800Ω OUTPUT 3025Ω OUTPUT 5288Ω OUTPUT 5600Ω 30pF 30pF 30pF Input Pulse Levels VCC x 0.1 to VCC x 0.9 Input Rise and Fall Times 10ns Input and Output Timing Level VCC X 0.5 7038 FRM T09 7005 FRM F09.1 A.C. CHARACTERISTICS (Over the recommended operating conditions, unless otherwise specified.) Data Input Timing Symbol Parameter Voltage Min. Max. Units 5 3.3 MHz fSCK Clock Frequency 2.7V–5.5V 1.8V–3.6V 0 tCYC Cycle Time 2.7V–5.5V 1.8V–3.6V 200 300 ns tLEAD CS Lead Time 2.7V–5.5V 1.8V–3.6V 100 150 ns tLAG CS Lag Time 2.7V–5.5V 1.8V–3.6V 100 150 ns tWH Clock HIGH Time 2.7V–5.5V 1.8V–3.6V 80 130 ns tWL Clock LOW Time 2.7V–5.5V 1.8V–3.6V 80 130 ns tSU Data Setup Time 20 ns tH Data Hold Time 20 ns (3) Data In Rise Time 2 µs (3) Data In Fall Time 2 µs tRI tFI CS Deselect Time tCS (4) tWC 100 Write Cycle Time ns 10 ms 7038 FRM T10 Notes: (3) This parameter is periodically sampled and not 100% tested. (4) tWC is the time from the rising edge of CS after a valid write sequence has been sent to the end of the self-timed internal nonvolatile write cycle. 9 X25097 Data Output Timing Symbol Parameter Voltage Min. Max. Units 0 5 3.3 MHz fSCK Clock Frequency 2.7V–5.5V 1.8V–3.6V tDIS Output Disable Time 2.7V–5.5V 1.8V–3.6V 100 150 ns tV Output Valid from Clock LOW 2.7V–5.5V 1.8V–3.6V 80 130 ns tHO Output Hold Time (5) 0 ns tRO Output Rise Time 50 ns tFO(5) Output Fall Time 50 ns 7038 FRM T11 Notes: (5) tWC is the time from the rising edge of CS after a valid write sequence has been sent to the end of the self-timed internal nonvolatile write cycle. Figure 8. Serial Output Timing CS t CYC tWH t LAG SCK t HO tV SO SI MSB OUT MSB–1 OUT t WL t DIS LSB OUT ADDR LSB IN 7038 FRM F10 SYMBOL TABLE WAVEFORM INPUTS OUTPUTS Must be steady Will be steady May change from LOW to HIGH Will change from LOW to HIGH May change from HIGH to LOW Will change from HIGH to LOW Don’t Care: Changes Allowed N/A Changing: State Not Known Center Line is High Impedance 10 X25097 Figure 9. Serial Input Timing tCS CS t LEAD t LAG SCK tH tSU SI tRI MSB IN t FI LSB IN HIGH IMPEDANCE SO 7005 FRM F11 11 X25097 PACKAGING INFORMATION 8-LEAD PLASTIC, TSSOP, PACKAGE TYPE V .025 (.65) BSC .169 (4.3) .252 (6.4) BSC .177 (4.5) .114 (2.9) .122 (3.1) .047 (1.20) .0075 (.19) .0118 (.30) .002 (.05) .006 (.15) .010 (.25) Gage Plane 0° – 8° Seating Plane .019 (.50) .029 (.75) Detail A (20X) .031 (.80) .041 (1.05) See Detail “A” NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 12 X25097 PACKAGING INFORMATION 8-LEAD PLASTIC SMALL OUTLINE GULL WING PACKAGE TYPE S 0.150 (3.80) 0.158 (4.00) 0.228 (5.80) 0.244 (6.20) PIN 1 INDEX PIN 1 0.014 (0.35) 0.019 (0.49) 0.188 (4.78) 0.197 (5.00) (4X) 7° 0.053 (1.35) 0.069 (1.75) 0.004 (0.19) 0.010 (0.25) 0.050 (1.27) 0.010 (0.25) 0.020 (0.50) X 45° 0.050" TYPICAL 0.050" TYPICAL 0° – 8° 0.0075 (0.19) 0.010 (0.25) 0.250" 0.016 (0.410) 0.037 (0.937) 0.030" TYPICAL 8 PLACES FOOTPRINT NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 3926 FRM F22.1 13 X25097 PACKAGING INFORMATION 8-LEAD PLASTIC DUAL IN-LINE PACKAGE TYPE P 0.430 (10.92) 0.360 (9.14) 0.260 (6.60) 0.240 (6.10) PIN 1 INDEX PIN 1 0.300 (7.62) REF. HALF SHOULDER WIDTH ON ALL END PINS OPTIONAL 0.060 (1.52) 0.020 (0.51) 0.145 (3.68) 0.128 (3.25) SEATING PLANE 0.025 (0.64) 0.015 (0.38) 0.065 (1.65) 0.045 (1.14) 0.150 (3.81) 0.125 (3.18) 0.020 (0.51) 0.016 (0.41) 0.110 (2.79) 0.090 (2.29) 0.325 (8.25) 0.300 (7.62) 0.015 (0.38) MAX. 0° 15° TYP .0.010 (0.25) NOTE: 1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 2. PACKAGE DIMENSIONS EXCLUDE MOLDING FLASH 14 X25097 ORDERING INFORMATION X25097 P T G –V VCC Limits Blank = 4.5V to 5.5V 2.7 = 2.7V to 5.5V 1.8 = 1.8V to 3.6V Device G = RoHS Compliant Lead-Free package Blank = Standard package. Non lead-free. Temperature Range Blank = Commercial = 0°C to +70°C I = Industrial = –40°C to +85°C Package V = 8-Lead TSSOP S = 8-Lead SOIC P = 8-Lead PDIP Part Mark Convention 8-Lead TSSOP EYWW 5097XXG 8-Lead SOIC/PDIP Blank = 8-Lead SOIC P = 8-Lead PDIP G = RoHS compliant lead free AG = 1.8 to 3.6V, 0 to +70°C AH = 1.8 to 3.6V, -40 to +85°C F = 2.7 to 5.5V, 0 to +70°C G = 2.7 to 5.5V, -40 to +85°C Blank = 4.5 to 5.5V, 0 to +70°C I = 4.5 to 5.5V, -40 to +85°C X25097 XG XX G = RoHS compliant lead free AG = 1.8 to 3.6V, 0 to +70°C AH = 1.8 to 3.6V, -40 to +85°C F = 2.7 to 5.5V, 0 to +70°C G = 2.7 to 5.5V, -40 to +85°C Blank = 4.5 to 5.5V, 0 to +70°C I = 4.5 to 5.5V, -40 to +85°C LIMITED WARRANTY Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and prices at any time and without notice. Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, licenses are implied. U.S. PATENTS Xicor products are covered by one or more of the following U.S. Patents: 4,263,664; 4,274,012; 4,300,212; 4,314,265; 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829, 482; 4,874, 967; 4,883, 976. Foreign patents and additional patents pending. LIFE RELATED POLICY In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detection and correction, redundancy and back-up features to prevent such an occurence. Xicor's products are not authorized for use in critical components in life support devices or systems. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 15