Preliminary Specification aMC8500 TWO PHASE VARIABLE SPEED FAN MOTOR CONTROLLER PRODUCT SPECIFICATION The aMC8500 is a full featured monolithic brushless DC motor controller containing all the required functions to implement fan speed control. This device features a selectable slope pulse width modulator (PWM) for efficient speed control with analog and digital control signal compatibility, programmable minimum speed setting, Hall amplifier with propriety noise immunity circuitry for proper drive sequencing, fixed non-overlapping commutation delay for reduced supply current spiking, dual on-chip 0.5 Ω power MOSFETs with thermal protection for direct motor drive, programmable cycle-by-cycle current limiting, internal fault timer with auto start retry, motor kick start timer to insure start up, combined frequency generator / rotor lock output, uncommitted op amp with reference for thermal sensor voltage scaling, and a selectable automatic low current power down mode for power sensitive applications. Pin Configuration Phase 2 Output 1 16 Phase 1 Output Current Limit Set 2 15 Freq Gen. Rotor Lock Hall + 3 14 Slope Select Hall - 4 13 Power Ground Reference Output 5 12 VDD Minimum Speed Set 6 11 Signal Ground Non-Inverting Input 7 10 Speed Control Input Inverting Input 8 9 Features • • • • • • • • • • • • • • • • • Analog and digital speed control signal compatibility Programmable minimum speed setting Selectable PWM speed control slope Latching PWM for enhanced noise immunity Integrated fault timer with auto start retry Motor kick start timer Combined frequency generator / rotor lock output Differential unbuffered and digital Hall compatibility Hall amplifier with propriety noise immunity circuitry Pinned out reference Uncommitted op amp for thermal sensor voltage scaling Fixed non-overlapping commutation delay Dual on-chip 0.5 Ω MOSFET motor drives Programmable cycle-by-cycle current limit protection Thermal shutdown protection Under voltage lockout protection Selectable automatic low current power down mode Op Amp Output Application Diagram 12V VDD Ref. H+ Ø1 H- Ø2 FG / RL Output Reference Non-Inv. Inv. Op Amp Output Commutation Logic Motor Drive Fault Timer Applications • • • • • • • aMC8500 Personal computer fans Workstation and mainframe fans LAN server blowers Industrial control system fans Telcom system fans Instrumentation test and measurement fans Card rack fans Minimum Speed Speed Control PWM Logic Slope Select Current Limit Signal Gnd Current Limit Set Power Gnd Ordering Information Part Number Package aMC8500DE16 SOIC 16 Lead Exposed Pad aMC8500QS16 QSOP 16 Lead Operating Junction Temperature Range Marking -40°C to 125°C aMC8500 Ayww Ayww – Assembly site year workweek © Andigilog, Inc. 2006 -1www.andigilog.com August 2006 - 70A04018 Preliminary Specification – Subject to change without notice Preliminary Specification – Subject to change without notice Product Description Preliminary Specification aMC8500 Absolute Maximum Ratings (Note 1) Parameter Power Supply Voltage (Pin 12) Hall Input Voltage Range (Pin 3, 4) Speed Control Input Voltage Range (Pin 10) Rating Unit VDD -0.3 to 18 V VIR(Hall) -0.3 to VDD V -0.3 to VDD V -0.3 to VDD V Reference Output Load Current (Pin 5) IO(Ref) Internally Limited mA Op Amp Input Voltage Range (Pin 7, 8) VIR(OA) -0.3 to VDD V Op Amp Output (Pin 9, Note 4) Voltage Range Source or Sink Current VOR(OA) IO(OA) -0.3 to VDD 30 V mA Slope Select Input Voltage Range (Pin 14) VIR(LS) -0.3 to VREF V Current Limit Set Input Voltage Range (Pin 2) VIR(ILim) -0.3 to VREF V VOR(FG/RL) ISink(FG/RL) -0.3 to 18 20 V mA VD(Ø1/Ø2) ISink(Ø1/Ø2) -0.3V to 36 1.5 -1.5 V A A Frequency Generator / Rotor Lock Output (Pin 15) Voltage Range Sink Current Drive Outputs (Pin 1, 16, Note 4) Voltage Range Sink Current Source Current Thermal Characteristics SOP-16 Exposed Pad Package Thermal Resistance, Junction to Air Thermal Resistance, Junction to Pad QSOP-16 Package Thermal Resistance, Junction to Air ISource(Ø1/Ø2) °C/W RØJA RØJC 92 15 RØJA 136 TJ(max) -40°C to 125 °C Storage Temperature Range Tstg -60°C to 150 °C IR Reflow Peak Temperature Treflow 260 °C Lead Soldering Temperature (10 sec) Tlead 300 °C Electrostatic Discharge (Note 2) Human Body Model Machine Model ESD Operating Junction Temperature Range Preliminary Specification – Subject to change without notice VIR(S) VIR(MSS) Minimum Speed Set Input Voltage Range (Pin 6) Preliminary Specification – Subject to change without notice Symbol V 2000 250 Notes: 1. Absolute maximum ratings are limits beyond which operation may cause permanent damage to the device. These are stress ratings only. Functional operation at or above these limits is not implied. 2. Human Body Model: 100 pF capacitor discharged through a 1.5 kΩ resistor into each pin. Machine Model: 200 pF capacitor discharged directly into each pin. 3. These specifications are guaranteed only for the test conditions listed. 4. Maximum package power dissipation limits must be observed. © Andigilog, Inc. 2006 -2www.andigilog.com August 2006 - 70A04018 Preliminary Specification aMC8500 Electrical Characteristics (V D D = 1 2 V, T A = 25°C, unless otherwise noted. Specifications subject to change without notice [Note 3].) Parameter Symbol Min Typ Max Units Input Threshold Voltage Pin 14 = Gnd 0% Drive Conduction 100% Drive Conduction Pin 14 = Open 0% Drive Conduction 100% Drive Conduction V Speed Control Input Threshold Voltage for Power Down (IO(ref) ≤1.0 mA) Input Voltage Below 0% Drive Conduction, Vth(0%), Pin 14 = Gnd Input Voltage Above 0% Drive Conduction, Vth(0%), Pin 14 = Open Vth(0%) Vth (100%) 0.95 2.85 1.0 3.0 1.05 3.15 Vth(0%) Vth(100%) 2.85 0.95 3.0 1.0 3.15 1.05 Vth(PD) mV - 20 20 - Speed Control Input PWM Signal Transition Time Maximum allowable rise or fall time for digital control tr/tf - - 50 µs Input Bias Current, (Vin = 3.5 V) IIB - 1.0 - µA fPWM - 30 - kHz Modulation Frequency SLOPE SELECT (Pin 14) Input Threshold Voltage Low State Increasing voltage at Pin 6, 10 causes increase in drive conduction High State Increasing voltage at Pin 6, 10 causes decrease in drive conduction V VIL(S) - - 1.0 VIH(S) 2.8 - - II(S) - 10 - µA Input Differential Voltage Sensitivity Required signal level to enable drive commutation VID(Hall) - 20 40 mVpp Input Hysteresis Voltage (Vin = 3.5 V) VIH(Hall) - 10 - mV Input Resistance RIN(Hall) - - MΩ Input Common Mode Voltage Range VICM(Hall) 0 to VDD 3.0 -0.3 to VDD +0.3 - V Input Offset Voltage (Vin = 3.5V) VIO - 2.0 - mV Input Bias Current (Vin = Gnd) IIB - - nA VICM(OA) - 50 0 to 4.2 - V Open Loop Voltage Gain AVOL 80 100 - dB Gain Bandwidth Product (f = 10 kHz) GBW - 70 - kHz Output Voltage Swing High State (Isource = 5.0 mA to Gnd) Low State (Isink = 5.0 mA to VDD) VOH(OA) VOL(OA) - VDD -1.5 0.5 - Low State Input Pull-Up Current (VIL(S) = 0 V) HALL AMPLIFIER (Pin 3, 4) OP AMP (Pin 7, 8, 9) Input Common Mode Voltage Range © Andigilog, Inc. 2006 -3www.andigilog.com V August 2006 - 70A04018 Preliminary Specification – Subject to change without notice Preliminary Specification – Subject to change without notice SPEED CONTROL (Pin 10) and MINIMUM SPEED SET (Pin 6) Preliminary Specification aMC8500 REFERENCE (Pin 5) Output Voltage (IO = 5.0 mA) Vref 3.325 3.5 3.675 V Line Regulation (VDD = 6.0 V to 15 V, IO = 5.0 mA) Refline - 2.0 30 mV Load Regulation (VDD = 6.0 V, IO = 1.0 mA to 10 mA) Refload - 11 30 mV ISC - 50 - mA Reference Output Load Current For Automatic Power Down Feature (Pin 10 = 500 mV, Pin 14 = Gnd, t > 2.0s) (Pin 10 = 3.5 V, Pin 14 = Open, t > 2.0s) Enabled Disabled IO(PD) mA 2.0 1.4 1.6 1.0 - FAULT TIMER Drive Enabled Time During A Fault Condition ton(Flt) - 0.25 - s Drive Disabled Time Before Restart toff(Flt) - 2.0 - s ton(KS) - 1.0 - s KICK START TIMER Motor Kick Start Time (100% duty cycle applied) FREQUENCY GENERATOR / ROTOR LOCK (Pin 15) Low State Output Sink Voltage (Isink = 1.0 mA) VOL(FG/RL) - 0.13 0.25 V Off-State Leakage Current (Voff = 12 V) Ioff(Tach) - 0.1 1.0 µA Minimum Hall Frequency For Rotor Lock Output High State fRL(min) - 4.0 - Hz Low State Output Voltage (Isink = 500 mA) VOL(Drv) - 250 300 mV Off-State Leakage Current (Voff = 30 V) Ioff(Drv) - - 5.0 µA MOTOR DRIVES (Pin 1, 16) Current Limit Threshold (Pin 2 open, Note 4) Non-Overlapping Commutation Delay ILim 900 1100 1300 mA tdly(Com) - 40 - µs Vth(on) VH - 4.7 500 - V mV IS IS(PwrDn) - 1.6 130 2.0 200 mA µA TOTAL DEVICE (Pin 12) Power Supply Threshold Voltage Start-Up (VDD increasing) Hysteresis (VDD decreasing after turn-on) Power Supply Current Operating Power Down (Pin 10 = 0.5 V, IO(ref) ≤1.0 mA, t > 2.0s, Pin 14 = Gnd) © Andigilog, Inc. 2006 -4www.andigilog.com August 2006 - 70A04018 Preliminary Specification – Subject to change without notice Preliminary Specification – Subject to change without notice Short Circuit Current (Note 4) 100 Kick Start 1.0 sec. VDD = 12 V Pin 14 = Gnd TA = 25°C 80 Motor remains at min speed setting. Auto power down disabled. IO(Ref) ≥2.0 mA 60 Minimum speed set shown for 1.5 V, 1.7 V, and 1.9 V. 40 Motor turns on/off at min speed setting. Auto power down enabled after 1 sec. IO(Ref) ≤1.0 mA 20 0 0 1.0 2.0 3.0 4.0 Vin(SC), Speed Control Input Voltage (V) 5.0 %ton, Motor Drives Percent On-Time (%) %ton, Motor Drives Percent On-Time (%) Figure 1- Motor Drives Percent On-Time versus Speed Control Input Voltage 100 VO, Output Voltage (V) 1.95 60 40 20 0 0 VO(OA), Output Voltage (V) Motor turns on/off at min speed setting. Auto power down enabled after 1.0 sec. IO(Ref) ≤1.0 mA Minimum speed set shown for 2.1 V, 2.3 V, and 2.5 V. 1.0 2.0 3.0 4.0 Vin(SC), Speed Control Input Voltage (V) 2.0 1.5 Figure 5- Op Amp Source and Sink Output Voltage versus Current Figure 6- Frequency Generator / Rotor Lock Low State Output Voltage versus Sink Current VDD -1.0 VDD = 12 V TA = 25°C -2.0 2.0 Low state output Load to VDD 1.0 Gnd 4.0 8.0 12 IO, Output Load Current (mA) © Andigilog, Inc. 2006 5.0 VDD = 12 V AV = +1.0 RL = 10 M CL = 10 pF TA = 25°C 2.5 4.0 μs/Division High state output Load to ground 0 Motor remains at min speed setting. Auto power down disabled. IO(Ref) ≥2.0 mA VDD = 12 V Pin 14 = Open TA = 25°C 1.0 μs/Division 16 VOL(FG/RL), Low State Output Voltage (V) VO, Output Voltage (V) 2.0 0 Kick Start 1.0 sec. Figure 4- Op Amp Large Signal Transient Response VDD = 12 V AV = +1.0 RL = 10 M CL = 10 pF TA = 25°C 0 Figure 2- Motor Drives Percent On-Time versus Speed Control Input Voltage 80 Figure 3- Op Amp Small Signal Transient Response 2.05 aMC8500 1.0 VDD = 12 V TA = 25°C 0.8 0.6 0.4 0.2 0 0 -5www.andigilog.com 1.5 3.0 4.5 Isink, Sink Current (mA) 6.0 August 2006 - 70A04018 Preliminary Specification – Subject to change without notice Preliminary Specification – Subject to change without notice Preliminary Specification VDD = 12 V TA = 25°C -8.0 -16 -24 -32 0 0.6 VOL(Drv), Low State Voltage (V) Vref, Reference Output Voltage (V) 0 4.0 8.0 12 16 IO, Reference Output Source Current (mA) 20 VDD = 12 V TA = 25°C 0.5 0.4 0.3 0.2 0.1 0 0 0.2 0.4 0.6 0.8 Isink, Sink Current (A) 1.0 1.2 VDD = 12 V CPin 2 = 10 nF TA = 25°C 0.8 0.6 0.4 0.2 0 0 0.2 0.4 0.6 0.8 Vpgm, Programming Voltage, Pin 2 (V) © Andigilog, Inc. 2006 1.0 Figure 8- Reference Output Voltage versus Power Supply Voltage TA = 25°C 3.0 2.0 1.0 0 0 1.0 4.0 8.0 12 VDD, Power Supply Voltage (V) 16 Figure 10- Phase 1 / Phase 2 Drive Output On Resistance versus Power Supply Voltage ISink = 500 mA TA = 25°C 0.9 0.8 0.7 0.6 0.5 0.4 4.0 1.2 Ilim, Current Limit Threshold (A) Ilim, Current Limit Threshold (A) Figure 11- Phase 1 / Phase 2 Current Limit Threshold versus Programming Voltage 1.2 1.0 4.0 Figure 9- Phase 1 / Phase 2 Drive Output Low State Voltage versus Sink Current Ron, Drive Output On Resistance (Ω) ΔVref, Reference Output Voltage Change (mV) Figure 7- Reference Output Voltage Change versus Output Source Current aMC8500 1.0 6.0 8.0 10 12 14 VDD, Power Supply Voltage (V) 16 18 Figure 12- Programming Resistance versus Current Limit Threshold VDD = 12 V CPin 2 = 10 nF TA = 25°C 0.8 0.6 0.4 0.2 0 10 k -6www.andigilog.com 100 k 1.0 M Rpgm, Programming Resistance (Ω) 10 M August 2006 - 70A04018 Preliminary Specification – Subject to change without notice Preliminary Specification – Subject to change without notice Preliminary Specification Preliminary Specification aMC8500 Figure 13- Representative Block Diagram 12 V H S VDD Non-Inverting Input Inverting Input Reference 5 Hall Input 4 Phase 1 Output 16 Under Voltage Lockout Phase 2 Output Motor Drives Hall Amplifier Non-Overlap Commutation Op Amp 1 Frequency Generator / Rotor Lock Output 7 Fault Timer Power Down Kick Start 8 Output Thermal Shutdown 15 9 Minimum Speed Set Input 6 Oscillator PWM Comparator R Speed Control Input Q 2 S Current Limit Comparator Digital Detector Signal Ground Power Ground R PWM Logic 10 13 Current Limit Latch Min Speed Comparator Current Limit Set 10 μA 11 14 Slope Select INTRODUCTION The aMC8500 is a full featured two phase half wave variable speed brushless motor controller containing all the required functions for implementing a fan control system. Motor control features consists of a selectable slope pulse width modulator (PWM) with double pulse suppression for efficient speed control that is compatible with an analog voltage or a varying duty cycle digital pulse train, a programmable minimum speed set input, and an uncommitted op amp with a pinned out reference for speed control signal scaling, Hall sensor amplifier with propriety noise immunity circuitry for proper drive sequencing, non-overlapping commutation drive for reduced supply current spiking, on-chip 0.5 Ω power MOSFETs for direct coil drive. Protective and diagnostic features include an internal fault timer with auto start retry, motor kick start timer to insure proper start up, programmable cycle-by-cycle current limiting, power supply under voltage lockout, and over temperature thermal shutdown, and a combined frequency generator / rotor lock output for status reporting. Also included is a selectable automatic low current power down mode aimed at power sensitive applications. The aMC8500 is designed for use in thermal open or closed loop systems. It can be controlled by simple NTC or PTC thermistors, Simistor™ silicon temperature sensors, or by complex digital or microcontroller based temperature monitors. FUNCTIONAL DESCRIPTION A representative block diagram is shown in Figure 13 and a detailed discussion on each of the functional blocks and features are given in the following sections. A complete list of the pin functions with a brief description is shown in Figure 33. © Andigilog, Inc. 2006 -7www.andigilog.com August 2006 - 70A04018 Preliminary Specification – Subject to change without notice Preliminary Specification – Subject to change without notice Reference Output Hall + Input 3 12 N MS N aMC8500 Speed Control Motor speed is efficiently controlled with the use of pulse width modulation, PWM. The voltage applied to the Speed Control Input, Pin 10, provides control of motor speed by varying the drive percent on-time or conduction time of the Phase 1 and Phase 2 outputs during the commutation cycle. The control signal can be in the form of an analog voltage ranging from 1.0 V to 3.0 V, or a variable duty cycle digital pulse train having a low state maximum of 0.98 V, a high state minimum of 3.02 V, with maximum transition times 50 µs. The control signal to PWM transfer slope or Speed Control Input voltage to drive percent on-time, is controlled by the Slope Select input, Pin 14. When connected to ground, an increase in control voltage or a digital high state results in an increase in drive output on-time. When unconnected, an increase in control voltage or a digital high state results in a decrease in drive output on-time. A Minimum Speed Set Input is made available at Pin 6 and it has a control transfer and slope that is identical to that of Pin 10. It is designed to be programmed form an analog voltage that ranges from 1.0 V to 3.0 V, which can be derived from the Reference. The minimum speed programmed at this input will take control of the motor speed if it is greater than the speed being requested at the Speed Control input. When directly controlling motor speed from a variable duty cycle digital pulse train, the minimum speed set feature is not available and the comparator input must be disabled. A method for preserving this feature is shown in Figure 40. Figure 1 shows the Motor Drives percent on-time versus the Speed Control input voltage with Pin 14 connected to ground for positive slope control. Notice that there are two defined outcomes when the Speed Control input voltage falls below that of the Minimum Speed Set. The first is that the motor continuously runs at the programmed minimum speed setting and this is selected by loading the Reference with 2.0 mA or more to disable auto Power Down. The second outcome is that the motor turns off after 1.0 second and this is selected by loading the Reference with 1.0 mA or less to enable auto Power Down. This gives the fan designer a choice between letting the motor run at a minimum speed or to stop running when Speed Control falls below the programmed minimum speed setting. Figure 2 shows the Motor Drives percent on-time versus the Speed Control input voltage with Pin 14 unconnected for negative slope control. The minimum speed operating characteristics are selected in the same manner as above but with the defined outcomes now occurring when the Speed Control input voltage rises above that of the Minimum Speed Set. The speed control and minimum speed operations are shown in table form in Figure 14. Compatibility with both analog and digital control signals combined with the ability to select both the transfer slope and automatic power down, allows this device to interface into a vast array applications. Figure 14- Speed Control and Minimum Speed Set Operation Speed Control Input Pin 10 Signal (V) 0 to 1.0 >1.0 to <3.0 3.0 to 5.0 Voltage Positive Pulse Negative Pulse Controlling Input Gnd (Disabled) Speed Control Minimum Speed Set 0 to <1.7 >1.7 to 3.0 1.7 >3.0 to 5.0 Pulse <0.98 to >3.02 Gnd (Disabled) Speed Control Tied to Pin 14 (Disabled) Speed Control 5.0 to 3.0 <3.0 to >1.0 1.0 to 0 Voltage Minimum Speed Set Input Pin 6 (V) <2.3 to 1.0 2.3 <1.0 to 0 Pulse >3.02 to <0.98 Tied to Pin 14 (Disabled) Speed Control Speed Control Motor Drive (% Low) 0 0 to 100 Gnd Speed Control Minimum Speed Set 3.0 to >2.3 Slope Select Pin 14 Zero speed, power down mode if IO(ref) ≤1.0 mA, t > 1.0s. %ton = (VSC - 1.0) / 0.02 100 Maximum speed. 35 Speed control voltage is less than minimum speed set. 35 to 100 100 Duty Cycle 0 0 to 100 100 Open Comments 35 35 to 100 100 Duty Cycle Speed control voltage is greater than minimum speed set. Maximum speed. Positive pulse width duty cycle controlled from Pin 10. Zero speed, power down mode if IO(ref) ≤1.0 mA, t > 1.0s. %ton = 100 - (VSC - 1.0 / 0.02) Maximum speed. Speed control voltage is greater than minimum speed set. Speed control voltage is less than minimum speed set. Maximum speed. Negative pulse width duty cycle controlled from Pin 10. Note that if the end application does not require a programmed minimum speed or is to be controlled by a variable duty cycle digital pulse train, the Minimum Speed Set comparator must be disabled as shown in Figure 28. For applications that do not require speed control, the device can be configured to provide commutation only, yielding maximum motor speed without requiring any additional components. This is accomplished by directly grounding Pins 6 and 10, while leaving Pin 14 open. © Andigilog, Inc. 2006 -8www.andigilog.com August 2006 - 70A04018 Preliminary Specification – Subject to change without notice Preliminary Specification – Subject to change without notice Preliminary Specification Preliminary Specification aMC8500 Commutation The aMC8500 features a non-overlapping commutation delay circuit that prevents simultaneous drive conduction for reduced power supply current spikes and radio frequency interference (RFI). The non-overlap delay time (tdly) is internally set to 40 µs. The commutation waveforms and truth table are shown below in Figures 15 and 16. Figure 15- Two Phase, Two Step, Half Wave Commutation Waveforms 0 Hall Inputs 180 360 Rotor Electrical Position (Degrees) 540 720 0 180 360 540 720 H+ HVClamp Phase 1 Drain Voltage VMotor 0 Phase 1 Drain Current 0 tdly(Com) tdly(Com) VClamp Phase 2 Drain Voltage VMotor 0 Phase 2 Drain Current FGRL Output Voltage 0 0 Full Speed (100% PWM) Reduced Speed (≈ 50% PWM) Figure 16- Commutation Truth Table Hall Inputs + (Pin 3) (Pin 4) Low High X = Don’t care © Andigilog, Inc. 2006 System Fault None Drive Outputs Phase 1 Phase 2 (Pin 16) (Pin 1) Off Low FGRL Output (Pin 15) Low High Low None Low Off High X X Yes Off Off High -9www.andigilog.com August 2006 - 70A04018 Preliminary Specification – Subject to change without notice Preliminary Specification – Subject to change without notice Hall Inputs Rotor position is detected by a single Hall sensor to enable proper motor drive commutation. The H+ and H- Amplifier inputs are designed to interface with a wide variety of economical 4 pin unbuffered 'naked' or 3 pin buffered 'digital' Hall sensor types. The unbuffered sensors provide a low level differential output signal that is directly proportional to the rotors applied magnetic field. The sensor outputs connect directly to the H+ and H- inputs. The Amplifier has a differential input sensitivity of 20 mV with a common mode voltage range that extends from VDD to ground. By extending the input range to include ground, the need for offsetting the Hall output voltage with a series ground resistor is eliminated. Figures 20 through 22 show three methods of biasing unbuffered Hall sensors. The aMC8500 Hall Amplifier features enhanced noise rejection by combining a small level of input hysteresis with a propriety zero crossing detector and a timed lockout. The buffered Hall sensors provide a high level digital output signal that changes state in direct response the rotor magnetic pole transitions. This output signal is single ended and can be applied to either the H+ or H- input while biasing the unused input to a level that is within the output voltage swing of the sensors. Economical buffered Hall sensors typically contain an NPN open collector sink only output which requires a pull-up resistor. Figures 23 and 24 show two methods for biasing buffered Hall sensors. Preliminary Specification aMC8500 Op Amp A fully compensated Op Amp with access to both inputs and output is provided to facilitate thermal sensor voltage scaling. The amplifier features a wide input common mode voltage range that extends from ground to 4.2 V, a DC voltage gain of 100 dB, and a 70 kHz gain bandwidth product. The amplifier output exhibits an voltage swing that extends from ground to VDD - 1.7 V, is capable of sinking and sourcing up to 10 mA, and is unity gain stability when driving capacitive loads. In applications where a single amplifier input can exceed the upper level of the common mode voltage range, the output will always maintain the proper state. If both inputs exceed the upper level of the common mode voltage range, a low state output phase reversal can occur and although non destructive, it may result in unexpected system behavior. If the intended application does not require use of the Op Amp, the inputs must be connected to a fixed low impedance source in a manner that will force the output into a defined state. This will prevent the possibility of amplifying unwanted noise which can result in erratic circuit behavior. Figure 27 shows three suggested connection methods. Frequency Generator / Rotor Lock Motor speed and fault signals are provided by the Frequency Generator and Rotor Lock output at Pin 15. These signals can provide diagnostic information to a thermal system controller. During normal operation, the output provides a digital square wave that switches at the Hall sensor commutation frequency. Internally, this signal is used to continuously reset the Fault Timer. If the motor encounters an obstruction, the decrease in rotational speed will result in a corresponding increase in time between reset pulses. If this time exceeds 0.25 s (ton(Flt)) a fault will be detected, which in turn will terminate motor drive and place Pin 15 into a high state, thus indicating a rotor lock condition. After an off time cool down period of 2.0 s (toff(Flt)) has elapsed, the Fault Timer circuit will apply maximum drive in attempt to restart the motor for another 0.25 s. This on/off cycling will repeat indefinitely until the motor restarts, or is commanded to stop by the Speed Control and Minimum Speed Set inputs. Upon a successful restart, Pin 15 will resume switching at the Hall commutation rate after completion of the Kick Start interval. The Frequency Generator and Rotor Lock output consists of an N-channel open drain device and therefore requires an external pull-up resistor. An internal high gain buffer with hysteresis is used to insure that the output waveform is always rectangular even when the peak to peak Hall output signals are at a low level. The operating waveforms are shown in Figure 17. Figure 17- Frequency Generator / Rotor Lock Waveforms Differential Hall Inputs Possible Low Or High State Rotor Locked Fault Detected 0.25 s Fault Timer Motor Drives Rotor Free ton(Flt) 0.25 s toff(Flt) 2.0 s On Off On Off On Running Cool Down Retry Cool Down Running Frequency Generator / Rotor Lock Output Defaults To High State After Fault Detected Constant Speed © Andigilog, Inc. 2006 Rotor Locked or Rotating Below Minimum Hall Frequency - 10 www.andigilog.com Kick Start 1.0 s Accelerating Constant Speed August 2006 - 70A04018 Preliminary Specification – Subject to change without notice Preliminary Specification – Subject to change without notice Reference A pinned out 3.5 V Reference with a tolerance ±5.0% is made available to ease the implementation of motor control and allow additional system features. The Reference can be used to program the minimum speed set input, provide Hall sensor power, or thermal sensor voltage scaling when used in conjunction with the uncommitted Op Amp. The Reference output also provides a means to selectively enable or disable the device's automatic low current power down feature. Automatic power down is enabled if the output load current is 1.0 mA or less, and disabled if it is 2.0 mA or greater. The Reference is a source only output and therefore is not designed to sink current from a higher voltage source. It is capable of sourcing in excess of 10 mA over temperature and has short circuit protection. In applications that require additional current capability, the output can be buffered with the addition of an external PNP transistor as shown in Figure 25. This simple circuit has the advantage of moving any additional regulator power dissipation off chip but it does not maintain output short circuit protection. Preliminary Specification aMC8500 %Smax, Percent Maximum Motor Speed (%) Figure 18- Typical DC Motor Startup and Run Characteristics Kick Start 100% Voltage 1.0 Second 100 80 Kick Start Extended Speed Range 60 40 Minimum Startup Speed 35% On-Time 20 0 Typical Useful Speed Range Minimum Run Speed 10% On-Time 0 20 40 60 80 %ton, Motor Drives Percent On-Time (%) 100 The Kick Start time, ton(KS), is internally set to 1.0 second and is automatically activated whenever the motor is at rest and commanded to run, or when it is under a command to run and one of the following events takes place: 1) Device comes out of power down mode 2) Rotor was locked and the obstruction has cleared 3) Device recovered from a thermal shutdown 4) Device comes out of an under voltage lockout condition Current Limit Abnormally high drive current conditions can occur if the motor is mechanically overloaded and may result in device and the drive coil overheating. During motor overload, any reduction in rotational speed reduces the generated back electromotive force, EMF, resulting in an corresponding increase in drive current. The most severe condition occurs when the rotor is locked and there is no back EMF generated. Under this condition, the drive current is limited only by the resistance total of the MOSFET switch and the driven coil. In order to protect the device and motor from abnormally high currents, a programmable Current Limit Comparator is incorporated. The comparator indirectly senses the drive current and when a maximum level is exceeded, the motor drive on-time is immediately terminated on a cycle-by-cycle basis of either the internal oscillator or the digital control signal applied to the Speed Control Input. The current limit threshold defaults to a peak current of 1.1 A with Pin 2 open. This level can be reduced by either applying a bias voltage to Pin 2 or by connecting a single resistor from this pin to ground. Figures 11 and 12 show the current limit behavior while Figure 32 illustrates two biasing methods. The Current Limit Set input is high impedance and in most applications will require a 10 nF bypass capacitor to prevent false triggering due to noise pick up. © Andigilog, Inc. 2006 - 11 www.andigilog.com August 2006 - 70A04018 Preliminary Specification – Subject to change without notice Preliminary Specification – Subject to change without notice Kick Start Most DC motors exhibit a large difference between the voltage required to insure startup and minimum speed operation. Figure 18 shows this difference as a hysteretic characteristic and is dependent upon bearing friction, lubrication, temperature, and rotor inertia. With the majority of motor controllers presently available, the applied voltage for minimum speed operation must be set equal to or greater than that required for startup. This limits the motors useful speed range from about 35 to 100 percent even though most motors will operate down to 10 percent. In order to guarantee near minimum run speed operation, the mechanical startup hysteresis must be overcome. This is accomplished in the aMC8500 by kick starting the motor in a controlled manner where full power is initially applied for a for a prescribed time, and control then reverts back to the level that is dictated by either the Speed Control or Minimum Speed Set input. This is graphically shown in Figures 1 and 2. With reliable starting guaranteed, the useful speed range is increased by approximately 25%, yielding lower speed operation for reduced acoustic noise and extended motor life. aMC8500 Motor Drives The aMC8500 contains two 0.5 Ω N-channel power MOSFETs that are designed to directly drive the motor coils from the Phase 1 and Phase 2 outputs. The drive characteristics are shown in Figures 9 and 10. Each output contains a 36 V zener with a series diode that connects from the drain to the gate. This configuration provides active clamp protection for the MOSFETs when switching off the inductive motor load. In applications that demand driving higher current or higher voltage motors, external MOSFET power transistors can be used. Two examples are shown in Figures 29 and 30. Although this device is designed to drive two phase half wave motors, a method for driving single phase full wave motors is shown in Figure 31. Due to the inherent winding coupling that is present in two phase motors, the drain voltage of the off phase will be driven negative and current will be sourced from that output. This current will cause additional device heating and may affect operation of high current motors at elevated ambient temperatures. A simple solution is to place the cathode of a low forward drop Schottky diode from each drive output to ground. Likewise if the motor windings are highly inductive, the internal active clamp will be required to dissipate this energy which will also result in additional heating. This too can be eliminated with the addition of an external zener diode connected from each drain to ground. The zener breakdown voltage should be in the range of 30 V to 34 V. Under Voltage Lockout and Auto Power Down An Under Voltage Lockout circuit has been incorporated to prevent erratic device operation under low power supply conditions. This circuit enables the Motor Drives when VDD rises above 4.7 V to guarantee full IC functionality, and disables the drives when VDD falls below 4.2 V. The UVLO circuit has 500 mV of hysteresis to prevent oscillations as the thresholds are crossed during power-up and power-down. The IC is designed to directly drive 9.0 V and 12 V motors. As previously discussed, the device features a selectable auto Power Down mode. This mode is automatically entered when the voltage applied to the Speed Control Input commands zero or less than zero percent on-time. When entered, the power supply current is reduced from 1.6 mA to 130 μA. Refer to Figures 1, 2, and 14. Thermal Shutdown Internal Thermal Shutdown circuitry is provided to protect the device in the event that the maximum junction temperature is exceeded. When activated, typically at 140°C, the Motor Drive outputs are disabled to reduce device power dissipation. This feature is intended to prevent catastrophic device failures in the event of accidental overheating. Although it is possible to operate the device above the specified maximum junction temperature of 125°C, this protection feature is not intended to be used as a substitute for proper thermal system design. When the junction temperature falls below 120°C, normal device operation resumes. Refer to Figure 19. Figure 19- Thermal Shutdown Operation Thermal Shut Down Deactivated Thermal Shut Down Activated Motor Drives Enabled Motor Drives Disabled TJ(max) 80 100 120 140 TJ, Junction Temperature (°C) 160 SYSTEM APPLICATIONS The following section shows numerous device circuit configurations and several complete fan control solutions with a brief description. For clarity, many of the circuits show only the internal functional blocks that are of interest with the associated pin numbers. © Andigilog, Inc. 2006 - 12 www.andigilog.com August 2006 - 70A04018 Preliminary Specification – Subject to change without notice Preliminary Specification – Subject to change without notice Preliminary Specification Preliminary Specification Figure 20- Motor Supply Powered Unbuffered Hall aMC8500 Figure 21- Reference Powered Unbuffered Hall VM VM Asahi Kasei HW-101A R1 H H VDD 12 3 12 VDD 4 Under Voltage Lockout 5 3 4 Under Voltage Lockout Reference Hall Amplifier Non-Overlap Commutation Hall Amplifier Non-Overlap Commutation When powering an unbuffered Hall sensor from motor voltage VM, resistor R1 is required. This resistor sets the Hall operating current and places the output within the input common mode voltage range of the Hall Amplifier. Unbuffered Hall sensors that require less than 10 mA can be powered directly from the Reference output thus eliminating the need for bias resistor R1. This bias method will disable the automatic power down feature if the sensors require more than 2.0 mA. Figure 22- Op Amp Powered Unbuffered Hall Figure 23- Motor Supply Biased Buffered Hall VM VM H 12 VDD 5 Reference 3 4 R2 Toshiba TSH124 VDD Hall Amplifier Non-Overlap Commutation Op Amp H R3 Under Voltage Lockout 7 R1 12 3 4 Ana Chip ATS177 Under Voltage Lockout Hall Amplifier Non-Overlap Commutation 8 9 The Op Amp output can be used as alternative method for powering unbuffered Hall sensors that require less than 10 mA. This method eliminates the need for bias resistor R1 while also preserving the automatic power down feature. With this bias method the reference output is essentially unloaded. Pull-up resistor R1 is required when using buffered Hall sensors that have an open collector output. Resistors R2 and R3 bias the unused amplifier input to a level that is within its input common mode range. Figure 24- Reference Biased Buffered Hall Figure 25- Reference Buffer VM VM R1 H VDD 12 3 4 KEC KTA1270 Ana Chip ATS177 0.1 5 Reference Under Voltage Lockout 5 Hall Amplifier Non-Overlap Commutation VDD Reference 12 Under Voltage Lockout Load Resistor R1 is required for buffered Hall sensors with an open collector output. Resistors R2 and R3 can be eliminated by biasing the unused amplifier input from the reference. © Andigilog, Inc. 2006 100 With the addition of an economical PNP transistor, the Reference output current can be boosted above 100 mA. This simple buffer circuit will not have the benefit of maintaining short circuit protection. - 13 www.andigilog.com August 2006 - 70A04018 Preliminary Specification – Subject to change without notice Preliminary Specification – Subject to change without notice Toshiba TSH124 Preliminary Specification aMC8500 Figure 26- Higher Voltage Reference 5 3.5 V Reference 7 8 R1 R2 R2 VO = VRef Op Amp R1 +1 VO Max = VDD - 1.7 V 9 The Op Amp can be used to gain up the Reference voltage in applications that require an additional regulated voltage source. This circuit can supply up to 10 mA for powering additional circuitry or to provide a higher reference voltage. To insure that the Op Amp output maintains regulation, the maximum programmed output voltage must be less than VDD - 1.7 V. Preliminary Specification – Subject to change without notice Preliminary Specification – Subject to change without notice VO Figure 27- Connections If Op Amp Is Not Required 5 5 Reference 7 7 Op Amp 5 Reference 7 Op Amp 8 8 8 9 9 9 Unity gain amplifier configuration with the output forced low. Reference Comparator configuration with the output forced high. Op Amp Comparator configuration with the output forced low. Figure 28- Connections To Disable Minimum Speed Set Or Digital Signal Speed Control Operation Slope Select Grounded 5 7 Slope Select Open Reference 5 Op Amp 7 8 Op Amp 8 9 6 Reference 9 Oscillator R Min Speed Comp PWM Comp 6 R PWM Logic 1 Min Speed Comp PWM Comp PWM Logic 1 Digital Detector 10 μA 11 Oscillator 14 Digital Detector 10 μA 11 14 If the end application does not require a programmed minimum speed or is to be controlled by a variable duty cycle digital pulse train, the Minimum Speed Set comparator must be disabled by connecting Pin 6 directly to Pin 14. © Andigilog, Inc. 2006 - 14 www.andigilog.com August 2006 - 70A04018 Preliminary Specification aMC8500 Figure 29- Driving Higher Current Motors 12 V H S 12 3 4 N M S 16 Under Voltage Lockout 1 Motor Drives Hall Amplifier Non-Overlap Commutation The Current Limit Comparator protects the Motor Drives by limiting the output sink current to 1100 mA. In applications that require driving higher current motors, the drive current can be significantly increased with the addition of two external P-channel MOSFET. Current limit protection is not maintained since the load is no longer in series with the internal MOSFETs. Figure 30- Driving Higher Voltage Motors 48 V 12 V H 12 3 4 S N M N S 16 Under Voltage Lockout Hall Amplifier Non-Overlap Commutation 1 Motor Drives The Motor Drives are limited to a maximum of 36 V. These outputs can be cascoded with two external N-channel MOSFETs for driving higher voltage motors. The cascode configuration maintains current limit protection since the load is in series with the internal MOSFETs. © Andigilog, Inc. 2006 - 15 www.andigilog.com August 2006 - 70A04018 Preliminary Specification – Subject to change without notice Preliminary Specification – Subject to change without notice N Preliminary Specification aMC8500 Figure 31- Driving Single Phase Full Wave Motors 12 V H 10 k 0.1 S N M N S 10 k 12 3 10 k 4 16 Under Voltage Lockout 1 Motor Drives Hall Amplifier Non-Overlap Commutation Single phase full wave motors can be driven with the addition of two external P-channel MOSFETs. With the gates cross coupled as shown above, the internal and external MOSFETs can perform as a full bridge driver. Commutation shoot through current is minimized by the internal non-overlapping delay circuit. The resistor capacitor time constant must be just long enough to prevent pulse width modulation of the two external PFETs. Current limit protection is maintained since the load is in series with the internal MOSFETs. The motor drive outputs are limited to a maximum of 36 V. Figure 32- Current Limit Threshold Programming, Noise Pick Up and Motor Soft Acceleration Current Limit Latch 13 R Q 10 μA S Current Limit Comparator Current Limit Set 2 Noise Pick Up Elimination Current Limit Threshold Reduction To Vref Soft Motor Acceleration To VM Optional 10 nF Caccl 110 k Bypass Capacitor Single Resistor Current Source Biased Dual Resistor Reference Biased The Current Limit Set input is susceptible to noise pick up and in most applications will require a 10 nF bypass capacitor. The Current Limit Comparator threshold can be reduced by connecting a single resistor from Pin 2 to ground. This is the most economical programming method but it is somewhat less accurate than using the dual resistor method shown. This is due to the fact that the Reference Output is more accurate than the absolute values of the internal current source pull-up and terminating resistor. Motor soft acceleration during power-up can be accomplished by connecting a capacitor from Pin 2 to ground. During initial device power-up, the internal current source will charge capacitor Caccl thus gradually increasing the current limit threshold. The diode shown is optional and may not be required if there is sufficient time for the internal components to discharge the capacitor from when the power source is removed and then reapplied. © Andigilog, Inc. 2006 - 16 www.andigilog.com August 2006 - 70A04018 Preliminary Specification – Subject to change without notice Preliminary Specification – Subject to change without notice 10 k 0.1 Preliminary Specification aMC8500 Figure 33- Pin Function Description Function 1 Phase 2 Output 2 Current Limit Set 3 4 Hall + Hall - 5 Reference Output 6 Minimum Speed Set 7 Non-Inverting Input 8 Inverting Input 9 Op Amp Output 10 Speed Control Input 11 Signal Gnd 12 13 VDD Power Ground 14 Slope Select 15 Freq. Generator / Rotor Lock 16 Phase 1 Output Description This output directly drives phase 2 of a unipolar motor. It is active low when the voltage applied to the Hall input exceeds that of Hall +. This input is left unconnected for a maximum motor drive current sink current of 1100 mA. The sink current can be programmed to a lower level by connecting a resistor from this input to ground. Most applications will require a 10 nF bypass capacitor on this pin to prevent noise pick up. This input connects to the output of an unbuffered differential type Hall sensor. This input connects to the output of an unbuffered differential type Hall sensor. This is the reference output and is capable of sourcing in excess of 10 mA. It is also used to selectively enable or disable the automatic power down feature. Automatic power down is enabled if the reference load current is 1.0 mA or less, and disabled if it is 2.0 mA or more. This input is used in conjunction with the Reference Output to program the minimum motor speed or the threshold for automatic power down. If continuous minimum speed operation is desired, the automatic power down feature must be disabled. The minimum speed set feature is not available when controlling motor speed from a variable duty cycle digital pulse train and this input must be disabled by connected it to Pin 14. This is the non-inverting input of the Op Amp. It has an operating voltage range that extends from ground to 4.2 V. This is the inverting input of the Op Amp. It has an operating voltage range that extends from ground to 4.2 V. This is the Op Amp output and it is capable of sinking or sourcing up to of 10 mA. The Op Amp can be used in conjunction with the Reference for scaling a speed control signal derived from a temperature sensor. A voltage level that ranges from 1.0 V to 3.0 V or a variable duty cycle pulse is applied to this input for controlling the motor speed. A positive or negative speed control slope can be selected via Pin 14. This pin is the ground return for the control circuitry. It connects directly to the power source ground terminal. Internally this pin connects to the device substrate and the exposed thermal pad. This pin is the control circuit positive supply. It connects to the power source positive terminal. This pin is the ground return for the motor drive MOSFETs. It connects to the power source ground terminal. This input selects between a positive or a negative speed control slope. When connected to ground, an increasing voltage at Pin 6 or 10 increases motor speed. When not connected, an increasing voltage at Pin 6 or 10 decreases motor speed. This input has an internal 10 μA current source pull-up. This output provides a digital square wave signal that switches at the Hall sensor frequency and is active low when the voltage applied to the Hall - input exceeds that of the Hall +. If the motor turns too slow or is stalled, the output will assume a high state. This is an active low open drain output and it requires a pull-up resistor. This output directly drives phase 1 of a unipolar motor. It is active low when the voltage applied to the Hall + input exceeds that of Hall -. Layout Considerations High frequency printed circuit layout techniques are required to prevent pulse jitter and the possibility of erratic operation. This can be caused by excessive noise pick-up imposed upon the Hall or Error Amplifier inputs. The printed circuit layout should contain as much copper ground as possible with separate low current signal and high current motor drive grounds that return back to the power supply input filter capacitor. Ceramic 0.1 µF bypass capacitors connected close to the integrated circuit VDD and Vref pins may also be required depending upon circuit board layout and the source voltage impedance. The use of bypass capacitors will provide a low impedance path to ground for filtering out high frequency noise. The signal and power ground pins along with the exposed thermal pad must be connected together at the package. All high current loops should be kept as short as possible with wide traces to minimize the generation of radiated electro magnetic interference, EMI. Wide copper trace connections with copious amounts of foil placed under the device will greatly enhance the devices ability to dissipate power. © Andigilog, Inc. 2006 - 17 www.andigilog.com August 2006 - 70A04018 Preliminary Specification – Subject to change without notice Preliminary Specification – Subject to change without notice Pin Preliminary Specification aMC8500 Figure 34- Thermistor Sensing Variable Speed Temperature Regulator 12 V H S N M N R1 Op Amp 7 T R3 10 k R5 @ 25°C β = 3694 R4 1 Motor Drives Fault Timer Power Down Kick Start 8 S 16 Hall Amplifier Non-Overlap Commutation R6 H 4 Under Voltage Lockout Reference 5 R2 3 15 Thermal Shutdown 9 R8 6 R7 Current Limit Latch Min Speed Comp Oscillator R PWM Comp R 13 H Q PWM Logic 10 2 S Current Limit Comp Digital Detector 10 nF 10 μA 11 Application Requirements 14 Closest Standard 1.0% Resistor Values Tmin Speed PWM Tmax Speed PWM Minimum Speed Setting °C %on °C %on %on Ω Ω Ω Ω Ω Ω Ω Ω 30 35 40 100 35 10000 6650 11500 32400 1130 1150 2550 1330 30 67 38 100 35 10000 6980 11500 16200 1870 1330 2550 1330 35 30 50 100 0 10000 4990 15400 29100 1370 1300 - - 37 30 40 100 30 10000 5900 10200 133000 1000 1000 2910 1330 40 30 50 100 30 10000 4640 14700 49900 1000 1000 2910 1330 Thermistor Linearization R1 R2 Gain R3 Offset R4 R5 Min Speed R6 R7 R8 The Op Amp used in conjunction with the Reference is extremely useful in providing voltage gain and offset to condition the thermistor signal so that it can drive the Speed Control Input. The table shows five different application requirements with the calculated closest standard 1.0% resistor values. In each example, the required motor speed or PWM %on is defined for two sensor temperatures along with a minimum speed setting. In the third application, the minimum speed set input is not required and the comparator must be disabled by connecting Pin 6 to Pin 14. Note that the total Reference load current must exceed 2.0 mA in order to disable the automatic power down feature. © Andigilog, Inc. 2006 - 18 www.andigilog.com August 2006 - 70A04018 Preliminary Specification – Subject to change without notice Preliminary Specification – Subject to change without notice 12 Preliminary Specification aMC8500 Figure 35- Simistor™ Sensing Variable Speed Temperature Regulator 12 V H S N M N Reference 5 R4 H 3 S 16 1 Under Voltage Lockout Motor Drives Hall Amplifier Non-Overlap Commutation Op Amp aSM121 4 7 R1 R3 R2 Fault Timer Power Down Kick Start 8 15 Thermal Shutdown 9 R6 R5 Current Limit Latch Min Speed Comp 6 Oscillator R H 13 R PWM Comp Q PWM Logic 10 2 S Current Limit Comp Digital Detector 10 nF 10 μA 14 11 Application Requirements Closest Standard 1.0% Resistor Values Tmax Speed PWM Minimum Speed Setting %on °C %on %on Ω Ω Ω Ω Ω Ω 35 40 100 35 13700 16500 1400 5360 1070 1130 30 67 38 100 35 10500 76800 1370 6810 1070 1130 35 30 50 100 0 1070 8870 232 845 - - 37 30 40 100 30 1070 48700 1330 4120 1070 1270 40 30 50 100 30 13000 169000 2320 7320 953 1130 Tmin Speed PWM °C 30 Gain R1 Offset R2 R3 Min Speed R4 R5 R6 This application circuit uses a Simistotr™ solid state silicon temperature sensor that provides a precision signal of 10 mV/°C with an offset of 500 mV at 0°C. The Op Amp in conjunction with the Reference is used to gain-up and offset the signal before applying it to the speed control input. The above table shows five application requirements that are similar to those in Figure 33 with the calculated resistor values. The Simistor™ sensor allows a reduced component count when compared to the equivalent thermistor circuit. In each example, the required PWM %on or motor speed is defined for a minimum and maximum sensor temperature, and for a minimum speed setting. In the third application, the minimum speed set input is not required and the comparator must be disabled by connecting Pin 6 to Pin 14. Note that the total Reference load current must exceed 2.0 mA in order to disable the automatic power down feature. © Andigilog, Inc. 2006 - 19 www.andigilog.com August 2006 - 70A04018 Preliminary Specification – Subject to change without notice Preliminary Specification – Subject to change without notice 12 Preliminary Specification aMC8500 Figure 36- Thermistor Sensing Thermostatic Temperature Regulator 12 V H S N M N 5 R4 4 7 R3 H R1 T R5 10 k @ 25°C β = 3694 R7 1 Motor Drives Hall Amplifier Non-Overlap Commutation Op Amp S 16 Under Voltage Lockout Reference R2 3 Fault Timer Power Down Kick Start 8 9 Current Limit Latch Min Speed Comp 6 R6 15 Thermal Shutdown Oscillator R PWM Comp R H Q PWM Logic 10 2 S Current Limit Comp Digital Detector 10 nF 10 μA 14 11 Application Requirements Speed Transition Temperature °C 13 Closest Standard 1.0% Resistor Values Minimum Speed Setting Thermistor Linearization R1 R2 Threshold R3 R4 Hysteresis R5 Min Speed R6 R7 Min to Max Max to Min %on Ω Ω Ω Ω Ω Ω Ω 30 28 35 10000 8060 1020 1000 158000 1070 1130 35 30 35 10000 7500 1020 1100 66500 1070 1130 38 35 0 10000 6340 1020 1070 113000 - - 40 38 30 10000 5760 1050 1100 180000 1070 1270 45 40 30 10000 4990 1050 1130 73200 1070 1270 Thermostatic control can be accomplished by configuring the Op Amp as a non-inverting voltage comparator. The above table shows five different application examples with the calculated resistor values. In applications 1, 2, 4, and 5, the motor will switch from the programmed minimum setting to maximum speed as the sensor temperature rises above the required transition temperature. A controlled amount of positive feedback shifts the transition temperatures to provide thermal hysteresis as the sensor cools. In the third application requirement, the motor speed switches between zero and full speed. In this case the minimum speed set input is not required and the comparator must be disabled by connecting Pin 6 to Pin 14. Note that the total Reference load current must exceed 2.0 mA in order to disable the automatic power down feature. © Andigilog, Inc. 2006 - 20 www.andigilog.com August 2006 - 70A04018 Preliminary Specification – Subject to change without notice Preliminary Specification – Subject to change without notice 12 Preliminary Specification aMC8500 Figure 37 Simistor™ Sensing Thermostatic Temperature Regulator 12 V H S N M N 4 1 Motor Drives Hall Amplifier Non-Overlap Commutation Op Amp S 16 Under Voltage Lockout Reference 5 R2 3 R1 aSM121 H Fault Timer Power Down Kick Start 8 R3 15 Thermal Shutdown 9 R5 6 R4 Current Limit Latch Min Speed Comp Oscillator R PWM Comp R H Q PWM Logic 10 S 2 Current Limit Comp Digital Detector 10 nF 10 μA 11 14 Application Requirements Speed Transition Temperature °C 13 Closest Standard 1.0% Resistor Values Minimum Speed Setting Threshold Hysteresis Min Speed R1 R2 R3 R4 Min to Max Max to Min %on Ω Ω Ω Ω R5 Ω 30 28 35 499 1740 221000 2320 1210 35 30 35 215 715 40200 3240 1690 38 35 0 200 619 60400 - - 40 38 30 187 562 68000 2490 1150 45 40 30 196 562 35700 2490 1150 Thermostatic control is achieved by configuring the Op Amp as a voltage comparator. The inverting input monitors the Simistor™ solid state thermal sensor while the non-inverting input is biased to a reference level. The above table shows five different application examples with the calculated resistor values. In applications 1, 2, 4, and 5, the motor speed switches from the programmed minimum setting to maximum as the sensor temperature rises above the required transition temperature. A controlled amount of positive feedback shifts the transition temperatures to provide thermal hysteresis as the sensor cools. In the third application requirement, the motor switches between zero and full speed. In this case the minimum speed set input is not required and the comparator must be disabled by connecting Pin 6 to Pin 14. Note that the total Reference load current must exceed 2.0 mA in order to disable the automatic power down feature. © Andigilog, Inc. 2006 - 21 www.andigilog.com August 2006 - 70A04018 Preliminary Specification – Subject to change without notice Preliminary Specification – Subject to change without notice 12 Preliminary Specification aMC8500 Figure 38- Balanced Technology Extended (BTX) Closed Loop Speed Control 12 V H S N M Duty Cycle to Voltage Converter 10 k H Temperature Controlled Clamp Ref Op Amp 22 μF FB 8 330 nF Error 47 k 2.8 k 6.8 k VDD 10 k FGRL Out Fault Timer Power Down Kick Start 15 Thermal Shutdown 9 SC 1M 6 13 Current Limit Latch Min Speed Comp Oscillator H 1 Motor Drives Hall Amplifier Non-Overlap Commutation R PWM Comp 20 k T S 16 Under Voltage Lockout Reference 7 6.8 k 74AC86PC 4 100 nF 5 330 nF 10 k 3 Q PWM Logic 10 S 2 Current Limit Comp Digital Detector 10 nF 10 μA Thermistor (°C) (Ω) 24 10464 25 10061 26 9712 28 9027 30 8394 32 7828 34 7291 36 6799 β = 3300 11 Frequency to Voltage Converter 100 k 10 nF 14 10 k 150 k Figure 39- Fan Speed versus Control Signal Duty Cycle for Various Inlet Air Temperatures 4800 36 Inlet Air Temperature °C 32 3200 30 2400 Min Speed Set Intercept Points 1600 28 26 24 20% 800 70% Duty Cycle 2200 Fan Speed (RPM) Fan Speed (RPM) Control Signal = 0 to 5.0 V, 10 kHz Inlet Air Temperature = 30°C 34 4000 0 2600 Figure 40- Fan Speed versus Motor Voltage for Various Control Signal Duty Cycles 1800 50% Duty Cycle 1400 30% Duty Cycle 1000 10% 0 60 40 20 80 Control Signal Duty Cycle (%) 100 600 10.8 11.2 11.6 12.0 12.4 12.8 Motor Voltage (V) 13.2 13.6 The above circuit controls fan speed in a closed loop manner that is proportional to the control signal duty cycle and inlet air temperature. A voltage indicating the required fan speed or Reference is applied to Pin 7 and is derived from the Duty Cycle to Voltage Converter and Temperature Controlled Clamp circuits. The Duty Cycle to Voltage Converter consists of an XOR gate buffer that drives a 10 k, 22 μF low pass filter, with the high state level limited by the Temperature Controlled Clamp. A voltage indicating the actual fan speed or Feedback is applied to Pin 8 and is derived from the Frequency to Voltage Converter that consists of two XOR gates. The first XOR buffers the FGRL tachometer signal and connects to the second which is configured as an edge transition one-shot that drives a 100 k, 330 nF low pass filter. The Op Amp compares the difference between the Reference and Feedback voltages and generates an Error signal that drives Pin 6 in a corrective fashion causing the fan to run either faster or slower so that the Feedback voltage level becomes the same as the Reference. Performance data is shown in the above graphs. Note that the Error signal is applied to Pin 6 instead of Pin 10 and that Pin 10 must be biased between 1.0 V to 3.0 V for proper operation. © Andigilog, Inc. 2006 - 22 www.andigilog.com August 2006 - 70A04018 Preliminary Specification – Subject to change without notice Preliminary Specification – Subject to change without notice Control Signal Input N 12 Preliminary Specification aMC8500 Figure 41- Digital Pulse Speed Control with Programmable Minimum Speed Set 12 V H S N M N 12 Reference 4 1 Under Voltage Lockout Motor Drives Hall Amplifier Non-Overlap Commutation Op Amp 7 Fault Timer Power Down Kick Start 8 S 16 15 Thermal Shutdown 9 453 909 6 Oscillator R 6.2 k 36 k 2.7 k Pulse Input 10 k C1 0.1 Current Limit Latch Min Speed Comp R PWM Comp Q PWM Logic 10 Q1 13 2 S Current Limit Comp Digital Detector 10 nF 10 μA 14 11 The programmable minimum speed set feature can be preserved when controlling motor speed from a varying duty cycle pulse. The above circuit uses transistor Q1, capacitor C1 and the Reference to convert the digital control signal to an analog voltage. With the resistor values shown, the voltage at Pin 10 varies between 3.0 V with Q1 off and 1.0 V with Q1 on, which represents a PWM on-time of 0% and 100% respectively. The value of capacitor C1 is dependent upon the pulse frequency and should be sized be so that the ripple at Pin 10 is less than 10 mV. The Op Amp is not required in this application and is connected as a unity gain follower with the noninverting grounded. The Minimum Speed Set input is programmed for a PWM on-time of approximately 33%. Since the Reference is always required, the programming resistors also provide a load that exceeds 2.0 mA for disabling the automatic power down feature. Figure 42- Speed Control Alarm 5 R2 Op Amp 7 Vth Speed Alarm Output R1 VOH VOL Vth 0V Reference 3.0 V R2 9 Oscillator Min Speed Comp PWM Comp 9 3.0 V Speed Control Input 10 7 8 VOL Vth 0V Reference Op Amp R1 VOH 6 5 Vth Speed Alarm Output 8 R Speed Control Input Pin 11 = Gnd Vth = 1 + 0.02(%ton) Pin 11 = Open Vth = 3 - 0.02(%ton) R2/R1 = (Vref / Vth) - 1 6 Oscillator R Min Speed Comp PWM Comp 10 The Op Amp and Reference can be used to generate a speed control alarm signal. Resistors R1 and R2 divide down the Reference output voltage to set trip threshold Vth. The Op Amp compares the speed control input voltage to the trip threshold and the output changes state when it is crossed. In the circuit on the left, the speed alarm output transitions from a low to high state as the Speed Control Input voltage increases. With the circuit on the right, the speed alarm output transitions from a high to low state as the speed control input voltage increases. Threshold hysteresis can be added to the circuit on the right by placing a resistor from Pin 9 to Pin 7. © Andigilog, Inc. 2006 - 23 www.andigilog.com August 2006 - 70A04018 Preliminary Specification – Subject to change without notice Preliminary Specification – Subject to change without notice 5 3 Preliminary Specification aMC8500 Figure 43- Dual Fan Redundancy 12 V H M 12 R2 590 C1 1.0 Ref 5 16 UVLO 1 Drives Hall Amp Commutation Op Amp 7 4 Timers Power Down 8 15 TSD 9 Min Spd 6 Osc R3 787 Latch PWM 13 R Q PWM Logic 10 2 S 10 nF Current Limit Digital Detector 10 μA 11 14 12 V H M 1 16 4 3 12 Hall Amp Commutation 15 Ref UVLO Drives Op Amp Timers Power Down TSD 5 R2 590 R1 1.0 M C1 1.0 7 8 9 Min Spd Latch 13 R Q 10 nF PWM Logic S 2 6 Osc PWM 10 R3 787 Current Limit Digital Detector 10 μA 14 11 In applications that require increased system reliability, multiple cooling fans can be employed for redundancy. In this example two aMC8500s are cross coupled so that each device drives a fan while monitoring operation of the other. Resistors R2 and R3 program the Speed Control inputs to operate each fan at a 50% speed. During normal operation, the Frequency Generator / Rotor Lock outputs, Pin 15, continuously discharges their respective C1 capacitors. In the event that one fan should fail, Pin 15 will allow R1 to charge C1 above 2.0 V. This causes the Op Amp output to drive the Minimum Speed Set input above 3.0 V for maximum speed on the remaining fan. The values for resistors R2 and R3 are chosen so that each Reference Output is loaded in excess of 2.0 mA in order to disable the automatic power down feature. © Andigilog, Inc. 2006 - 24 www.andigilog.com August 2006 - 70A04018 Preliminary Specification – Subject to change without notice Preliminary Specification – Subject to change without notice R1 1.0 M 3 Preliminary Specification aMC8500 Top View Bottom View Side View End View Detail A © Andigilog, Inc. 2006 - 25 www.andigilog.com August 2006 - 70A04018 Preliminary Specification – Subject to change without notice Preliminary Specification – Subject to change without notice Figure 44- QSOP16 Package Outline Drawing Preliminary Specification aMC8500 Preliminary Specification – Subject to change without notice Preliminary Specification – Subject to change without notice Figure 45- SOIC16 Exposed Pad Package Outline Drawing © Andigilog, Inc. 2006 - 26 www.andigilog.com August 2006 - 70A04018 Preliminary Specification aMC8500 Data Sheet Classifications Preliminary Specification This classification is shown on the heading of each page of a specification for products that are either under development (design and qualification), or in the formative planning stages. Andigilog reserves the right to change or discontinue these products without notice. This classification is shown on the heading of the first page only of a specification for products that are either under the later stages of development (characterization and qualification), or in the early weeks of release to production. Andigilog reserves the right to change the specification and information for these products without notice. Fully Released Specification Fully released datasheets do not contain any classification in the first page header. These documents contain specification on products that are in full production. Andigilog will not change any guaranteed limits without written notice to the customers. Obsolete datasheets that were written prior to January 1, 2001 without any header classification information should be considered as obsolete and non-active specifications, or in the best case as Preliminary Specifications. LIFE SUPPORT POLICY ANDIGILOG'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF ANDIGILOG, INC. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. Andigilog, Inc. 8380 S. Kyrene Rd., Suite 101 Tempe, Arizona 85284 Tel: (480) 940-6200 Fax: (480) 940-4255 © Andigilog, Inc. 2006 - 27 www.andigilog.com August 2006 - 70A04018 Preliminary Specification – Subject to change without notice Preliminary Specification – Subject to change without notice New Release Specification