ETC AX6108

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AX6108 Dot Matrix Liquid Crystal Graphic
Display Column Driver
Description
AX6108 is a column (segment) driver for dot matrix liquid crystal graphic display systems. It stores
the display data transferred from a 8-bit micro controller in the internal display RAM and generates dot
matrix liquid crystal driving signals.
Each bit data of display RAM corresponds to the on/off state of a dot of a liquid crystal display to
provide more flexible than character display.
As it is internally equipped with 64 output drivers for display, it is available for liquid crystal graphic
display with many dots.
The AX6108, which is produced in the CMOS process, can complete portable battery drive equipment
in combination with a CMOS microcontroller, utilizing the liquid crystal display's low power
dissipation.
Moreover it can facilitate dot matrix liquid crystal graphic display system configuration in combination
with the row (common) driver AX6107
Features
¡ ´
¡ ´
¡ ´
¡ ´
¡ ´
¡ ´
¡ ´
¡ ´
¡ ´
¡ ´
¡ ´
¡ ´
¡ ´
¡ ´
¡ ´
Dot matrix liquid crystal graphic display column driver incorporating display RAM
RAM data direct display by internal display RAM
RAM bit data 1:On
RAM bit data 1:Off
Internal display RAM address counter preset, increment
Display RAM capacity : 512 bytes (4096 bits)
8-bit parallel interface
Internal liquid crystal display driver circuit : 64
Display duty cycle : Drives liquid crystal panels with 1/32 - 1/64 duty cycle multiplexing
Wide range of instruction function : Display Data Read/Write, Display On/Off, Set Address, Set
Display Start Line, Read Status
Lower power dissipation : during display 2 mW max
Power supply : Vcc: 5V¡ Ó
10%
Liquid crystal display driving voltage : 8V to 17.0V
CMOS process
100-pin flat plastic package (FP-100)
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-----------------------------------------------------------------------------------------------------------------------AX6018 Dot Matrix Liquid Crystal Graphic Display Column Driver
-----------------------------------------------------------------------------------------------------------------------Absolute Maximum Ratings
Item
Symbol
Value
Unit
Note
Vcc
-0.3 to +7.0
V
2
Supply voltage
VEE1
VEE2
Vcc -19.0 to Vcc + 0.3
V
3
Terminal voltage (1)
VT1
VEE - 0.3 to Vcc + 0.3
V
4
Terminla voltage (2)
VT2
-0.3 to Vcc + 0.3
V
2, 5
Operating temperature
Topr
-20 to + 75
¢ J
Storage temperature
Tstg
-55 to + 125
¢ J
Notes : 1. LSls may be destroyed if they are used beyond the absolute maximum ratings.
In ordinary operation, it is desirable to use them within the recommended
operation conditions.
Using them beyond these conditons may cause malfunction and poor reliability.
2. All voltage values are referenced to GND = 0V.
3. Apply the same supply voltage to VEE1 and VEE2.
4. Applies to V1L, V2L, V3L, V4L, V1R, V2R, V3R, and V4R.
Maintain
Vcc¡ Ù
V1L=V1R¡ Ù
V3L¡ Ù
=V3R¡ Ù
V4L=V4R¡ Ù
V2L=V2R¡ Ù
VEE
5. Applies to M, FRM, CL, RST, ADC, £ p1, £ p2, CS1, CS2, CS3, E, R/W, D/i,
and DB0 - DB7.
------------------------------------------------------------------------------------------------------------------------
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AX6018 Dot Matrix Liquid Crystal Graphic Display Column Driver
-----------------------------------------------------------------------------------------------------------------------Pin Arrangement
DB2
91 90 89 88 87 86 85 84 83
DB3
DB4
DB5
DB6
DB7
NC
NC
NC
CS3
CS2
CS1
RST
R/W
D/I
CL
£p1
£p2
E
FRM
100 99 98 97 96 95 94 93 92
82 81
1
80
DB1
M
2
79
DB0
Vcc
3
78
GND
V4R
4
77
V4L
V3R
5
76
V3L
ADC
V2R
6
75
V2L
V1R
7
74
V1L
VEE 2
8
73
VEE 1
Y64
9
72
Y1
Y63
10
71
Y2
Y62
11
70
Y3
Y61
12
69
Y4
Y60
13
68
Y5
Y59
14
67
Y6
Y58
15
66 Y7
Y57
16
65
Y8
Y56
17
64
Y9
Y55
18
63 Y10
Y54
19
62 Y11
Y53
20
61
Y12
Y52
21
60
Y13
Y51
22
59 Y14
Y50
23
58 Y15
Y49
24
57 Y16
Y48
25
56 Y17
Y47
26
55 Y18
Y46
27
54
Y19
Y45
28
53
Y20
Y44
29
52 Y21
Y43
30
51
31
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49
Y22
50
Y23
Y24
Y25
Y26
Y27
Y28
Y29
Y30
Y31
Y33
Y32
Y35
Y34
Y36
Y38
Y37
Y39
Y41
Y40
Y42
------------------------------------------------------------------------------------------------------------------------
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AX6018 Dot Matrix Liquid Crystal Graphic Display Column Driver
-----------------------------------------------------------------------------------------------------------------------Electrical Characterisstics
(GND = 0 V, Vcc = 4.5 to 5.5V, Vcc - VEE = 8 to 17.0 V, Ta = -20 to +75¢ J)
Limit
Item
Symbol
Min
Typ
Max
Unit
VIHC
0.7xVcc
--
Vcc
V
1
VIHT
2
--
Vcc
V
2
VILC
0
--
0.3xVcc
V
1
VILT
0
--
0.8
V
2
Output high voltage
VOH
2.4
--
--
V
IOH= -205£ gA
3
Output low voltage
VOL
--
--
0.4
V
IOL= -1.6mA
3
Input leakage current
IIL
-1
--
1
£ gA Vin= GND - Vcc
4
Three-state (off) input current
ITSL
-5
--
5
£ gA Vin= GND - Vcc
5
Liquid crystal supply leakage
current
ILSL
-2
--
2
£ gA Vin= VEE - Vcc
6
Driver on resistance
RON
--
--
7.5
k£ [ Vcc - VEE= 15V
¡ Ó
ILOAD = 0.1 mA
8
Dissipation current
ICC (1)
--
--
100
£ gA During display
7
ICC (2)
--
--
500
£ gA During access
access cycle =
1MHz
7
Input high voltage
Input low voltage
Test Condition
Note
Notes : 1. Applies to M, FRM, CL, RST, £ p1 and £ p2.
2. Applies to CS1, CS2, CS3, E, R/W, D/I, and DB0 - DB7.
3. Applies to DB0 - DB7.
4. Applies to terminals except for DB0 - DB7.
5. Applies to DB0 - DB7 at high impedance.
6. Applies to V1L - V4L and V1R - V4R.
7. Specified when liquid crystal display is in 1/64 duty cycle mode.
Operation frequency fCLK = 250 kHz (£ p1 and £ p2 frequency)
Frame frequency fM = 70 Hz (FRM frequency)
Specified in the state of
Output terminal : not loaded
Input level : VIH = Vcc (V)
VIL = GND (V)
Measured at Vcc terminal
8. Resistance between terminal Y and terminal V (one of V1L, V1R, V2L, V2R, V3L, V3R,
V4L and V4R) when load current flows through one of the treminals Y1 to Y64. This value
is specified under the following condition :
-----------------------------------------------------------------------------------------------------------------------AX6018 Dot Matrix Liquid Crystal Graphic Display Column Driver
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-----------------------------------------------------------------------------------------------------------------------Vcc - VEE = 15.5V
V1L = V1R, V3L = V3R = Vcc - 2/7 (Vcc - VEE)
V2L = V2R, V4L = V4R = Vcc + 2/8 (Vcc - VEE)
RON
V1L, V1R
V3L, V3R
¡´
¡´
V4L, V4R
¡´
Terminal Y
(Y1 - Y64)
V2L, V2R
The following is a description of the range of power supply voltage for liquid crystal display drive.
Apply positive voltage to V1L = V1R and V3L = V3R and negative voltage to V2L = V2R and V4L
= V4R within the ¡ µ
V range. This range allows stable impedance on driver output (RON). Notice
that ¡ V
µdepends on power supply voltage Vcc - VEE.
Vcc
V1 (V1L =V1R)
Range of Power Supply
Voltage for Liquid Crystal
Display Drive
¡µV
V3 (V3L = V3R)
¡µ
V(V)
5.0
3
V4 (V4L = V4R)
¡µV
V2 (V2L = V2R)
VEE
8
Correlation between Driver
Output Waveform and Power
Supply Voltages for Liquid
Crystal Display Drive
17.0
- VEE (V)
betweenVcc
Power
Correlation
Supply Voltage Vcc - VEE and ¡ µ
V
-----------------------------------------------------------------------------------------------------------------------AX6018 Dot Matrix Liquid Crystal Graphic Display Column Driver
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-----------------------------------------------------------------------------------------------------------------------Terminal Configuration
Input Terminal
Vcc
Applicable terminals :
¡´
M, FRM, CL, RST, £p 1, £p 2, CS1,
CS2, CS3, E, R/W, D/I, ADC
PMOS
¡´
¡´
NMOS
¡´
Input/Output Terminal
Vcc
¡´
Applicable terminals : DB0 - DB7
(Input circuit)
PMOS
¡´
¡´
Vcc
¡´
¡´
NMOS
Enable
PMOS
¡´
¡´
¡´
¡´
Data
NMOS
¡´
(Output circuit)
(three state)
Output Terminal
Applicable Terminals :
Y1 - Y64
PMOS
V1L, V1R
Vcc
PMOS
V3L, V3R
Vcc
NMOS
V4L, V4R
VEE
NMOS
V2L, V2R
VEE
-----------------------------------------------------------------------------------------------------------------------AX6018 Dot Matrix Liquid Crystal Graphic Display Column Driver
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-----------------------------------------------------------------------------------------------------------------------Interface AC Characteristics
MPU Interface
(GND = 0 V, Vcc = 4.5 to 5.5 V, Ta = -20 to +75¢ J
Item
Symbol
Min
Typ
Max
Unit
Note
E cycle time
tCYC
1,000
--
--
ns
1, 2
E high level width
PWEH
450
--
--
ns
1, 2
E low level width
PWEL
450
--
--
ns
1, 2
E rise time
tr
--
--
25
ns
1, 2
E fall time
tf
--
--
25
ns
1, 2
Address setup time
tAS
140
--
--
ns
1, 2
Address hold time
tAH
10
--
--
ns
1, 2
Data setup time
tDSW
200
--
--
ns
1
Data delay time
tDDR
--
--
320
ns
2, 3
Data hold time (Write)
tDHW
10
--
--
ns
1
Data hold time (Read)
tDHR
20
--
--
ns
2
Notes : 1.
t cyc
E
2.0V
0.8V
P WEL
P WEL
tr
R/W
2.0V
0.8V
tf
t AH
t AS
t AH
t AS
CS1 - CS3
D/I
2.0V
0.8V
t DSW
DB0 - DB7
t DHW
2.0V
0.8V
Figure 1 CPU Write Timing
-----------------------------------------------------------------------------------------------------------------------AX6018 Dot Matrix Liquid Crystal Graphic Display Column Driver
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-----------------------------------------------------------------------------------------------------------------------Notes : 2.
t cyc
E
P WEH
P WEL
tr
2.0V
0.8V
R/W
t AS
t AH
t AH
t AS
CS1 - CS3
D/I
tf
2.0V
0.8V
t DDR
t DHR
2.4V
0.4V
DB0 - DB7
Figure 2 CPU Read Timing
3. DB0 - DB7 : load circuit
RL
D1
Test
point
¡´
C
R
RL = 2.4k£[
R = 11k £[
C = 130pF (including jig capacitance)
Diodes D1 - D4 are all 1S2074 H
D2
D3
D4
-----------------------------------------------------------------------------------------------------------------------AX6018 Dot Matrix Liquid Crystal Graphic Display Column Driver
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-----------------------------------------------------------------------------------------------------------------------Clock Timing
(GND = 0 V, Vcc = 4.5 to 5.5 V, Ta = -20 to + 75¢ J)
Limit
Item
Symbol
Min
Typ
Max
Unit
Test Condition
tCYC
2.5
--
20
ns
Fig. 3
£ p1, £ p2 cycle time
£ p1 low level width
tWL£
p1
625
--
--
ns
Fig. 3
£ p2 low level width
tWL£
p2
625
--
--
ns
Fig. 3
£ p1 high level width
tWH£
p1
1,875
--
--
ns
Fig. 3
£ p2 high level width
tWH£
p2
1,875
--
--
ns
Fig. 3
£ p1 - £ p2 phase
difference
tD12
625
--
--
ns
Fig. 3
£ p2 - £ p1 phase
difference
tD21
625
--
--
ns
Fig. 3
£ p1 - £ p2 rise time
tr
--
--
150
ns
Fig. 3
£ p1 - £ p2 fall time
tf
--
--
150
ns
Fig. 3
tcyc
tf
£p 1
0.7 Vcc
0.3 Vcc
t WL£p 1
£p 2
t WH£p 1
tr
t D21
t D12
0.7 Vcc
0.3 Vcc
tf
t WH£p 2
t WL£p 2
tr
tcyc
Figure 3 External Clock Waveform
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-----------------------------------------------------------------------------------------------------------------------AX6018 Dot Matrix Liquid Crystal Graphic Display Column Driver
-----------------------------------------------------------------------------------------------------------------------Display Control Timing
(GND = 0V, Vcc = 4.5 to 5.5 V, Ta = -20 to +75¢ J)
Limit
Item
Symbol
Min
Typ
Max
Unit
Test Condition
tDFRM
-2
--
2
£ gs
Fig. 4
tDM
-2
--
2
£ gs
Fig. 4
CL low level width
tWLCL
35
--
--
£ gs
Fig. 4
CL high level width
tWHCL
35
--
--
£ gs
Fig. 4
FRM delay time
M delay time
t
CL
0.7Vcc
0.3Vcc
t WHCL
t DFRM
FRM
WLCL
t DFRM
0.7Vcc
0.3Vcc
t DM
0.7Vcc
M
0.3Vcc
Figure 4 Display Control Signal Waveform
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-----------------------------------------------------------------------------------------------------------------------AX6018 Dot Matrix Liquid Crystal Graphic Display Column Driver
------------------------------------------------------------------------------------------------------------------------
Y64
64
64
V1R
V2R
V3R
V4R
Y63
63
64
2
1
64
63
Y62
Display date latch
M
62
2
3
driver circuit
3
1
Liquid crystal display
62
Y3
Y2
Y1
V1L
V2L
V3L
V4L
Block Diagram
CL
Vcc
6
¡´
6
8
VEE1
8
9
GND
¡´
Display
on/off
4096 bit
FRM
Display start
line register
6
Display data RAM
9
ADC
Z address counter
XY address counter
¡´
VEE2
¡´
¡´
Input
register
Output
register
Busy
flag
I/O buffer
DB0 - DB7
E
D/I
R/W
8
3
¡´
CS1, CS2, CS3
Interface control
Instruction
register
RST
£p 1
£p 2
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-----------------------------------------------------------------------------------------------------------------------AX6018 Dot Matrix Liquid Crystal Graphic Display Column Driver
-----------------------------------------------------------------------------------------------------------------------Terminal Functions
Terminal
Name
Vcc
GND
VEE1
VEE2
V1L, V1R
V2L, V2R
V3L, V3R
V4L, V4R
CS1
CS2
CS3
E
R/W
D/I
Number of
Terminals
I/O Connected to
2
2
3
1
1
1
Power
supply
Power supply for internal logic.
Recommended voltage is :
GND = 0 V
Vcc = 5 V ¡ Ó
10%
Power
supply
Power supply for liquid crystal display drive circuit.
Recommended power supply voltage is Vcc - Vee = 8 to 17.0
V. Connect the same power supply to VEE1 and VEE2. VEE1 and
VEE2 are not connected each other in the LSI.
Power
supply
8
I
I
I
I
Functions
Power supply for liquid crystal display drive.
Apply the voltage specified depending on liquid crystals within
the limit of VEE through Vcc.
V1L (V1R), V2L (V2R) : Selection level
V3L (V3R), V4L (V4R) : Non-selection level
Power supplies connected with V1L and V1R (V2L & V2R,
V3L & V3R, V4L & V4R) should have the same voltages.
MPU
Chip selection.
Data can be input or output when the terminals are in the
following conditions :
Terminal Name
CS1
CS2
CS3
Condition
L
L
H
MPU
Enable.
At write (R/W = Low) : Data of DB0 to DB7 is latched at the
fall of E.
At read (R/W = High) : Data appears at DB0 to DB7 while E
is at high level.
MPU
Read/write.
R/W = High : Data appears at DB0 to DB7 and can be
read by the CPU.
When E = high, CS1, CS2 = low and CS3
= high.
R/W = Low : DB0 to db7 can accept at fall of E when
CS1, CS2 = low and CS3 = high.
MPU
Data/instruction.
D/I = High : Indicates that the data of DB0 to DB7 is
display data.
D/I = Low : Indicates that the data of DB0 to DB7 is
display control data.
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-----------------------------------------------------------------------------------------------------------------------AX6018 Dot Matrix Liquid Crystal Graphic Display Column Driver
-----------------------------------------------------------------------------------------------------------------------Terminal
Name
Number of
Terminals
I/O
Connected
to
Functions
ADC
1I
Vcc/GND
Address control signal to determine the relation between Y
address of display RAM and terminals from which the data is
output.
ADC = High : Y1 : $0, Y64 : $63
ADC = Low : Y64 : $0, Y1 : $63
DB1 - DB7
8 I/O
MPU
Data bus, three-state I/O common terminal.
M
1I
AX6107
Switch signal to convert liquid crystal drive wavefojrm into AC.
FRM
1I
AX6107
Display synchronous signal (frame signal).
Presets the 6-bit display line counter and synchronizes the
common signal with the frame timing when the FRM signal
becomes high.
CL
1I
AX6107
Synchronous signal to latch display data. The rising CL signal
increments the disiplay output address counter and latches the
display data.
£ p1, £ p2
2I
AX6107
2-phase clock signal for internal operation.
The £ p1 and £ p2 clocks are used to preform operations (I/O
of display data and execution of instructions) other than display.
64 O
Liquid
crystal
display
Liquid crystal display column (segmnet) drive output.
These pins outputs light on level when 1 is in the display RAM,
and light off level when 0 is it.
Relation among output level, M, and display data (D) is as
follows:
Y1 - Y64
M
D
Output
level
0
1
0
1
0
1
V1
V3
V2 V4
RST
1I
CPU or
The following registers can be initialized by setting the RST
external CR signal to low level.
1. On/off register 0 set (display off)
2. Display start line register line 0 set (displays from line 0)
After releasing reset, this condition can be changed only by
instruction.
NC
3
Open
Unused terminals. Don't connect any lines to these terminals.
Note : 1 corresponds to high level in positive logic.
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AX6108 Dot Matrix Liquid Crystal Graphic Display Column Driver
-----------------------------------------------------------------------------------------------------------------------Function of Each Block
Interface Control
1. I/O buffer
Data is transferred through 8 data bus lines (DB0 - DB7) .
DB7 : MSB (Most significant bit)
DB0 : LSB (lleast significant bit)
Data can neither be input nor output unless CS1 to CS3 are in the active mode. Therefore, when CS1
to CS3 are not in active mode it is useless to switch the signals of input terminals except RST and
ADC: that is namely, the internal state is maintained and no instruction excutes. Besides, pay attention
to RST and ADC which operate irrespectively of CS1 to CS3.
2. Register
Both input register and output register are provided to interface to an MPU whose speed is different
from that of internal operation. The selection of these registers depend on the combination of R/W and
D/I signals (table 1).
a. Input register
The input register is used to store data temporarily before writing it into display data RAM.
The data from MPU is written into the input register, then into display data RAM automatically by
internal operation. When CS1 to CS3 are in the active mode and D/I and R/W select the input register
as shown in table 1, data is latched at the fall of the E signal.
b. Output register
The output register is used to store data temporarily that is read from display data RAM. To read out
the data from output register, CS1 to CS3 should be in the active mode and both D/I and R/W should
be 1. With the read display data instruction, data stored in the output register is output while E is high
level. Then, at the fall of E, the display data at the indicated address is latched into the output register
and the address is increased by 1.
The contents in the output register are rewritten by the read display data instructiion. but ree held by
address set instruction, etc.
Therefore, the data of the specified address cannot be output with the read display data instruction
right after the address is set, but can be output at the second read of data. That is to say, one dummy
read is necessary. Figure 5 shows the CPU read timing.
_________________________________________________________________________________
Table 1 Register Selection
D/I
R/W
Operation
1
1
Reads data out of output register as internal operation (display data RAM ¡ ÷
output register)
1
0
Writes data into input register as internal operation (input register ¡ ÷
display data RAM)
0
1
Busy check. Read of status data.
0
0
Instruction
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Page 15
Busy
check
Read
data at
address
N
Busy
check
DB0 - DB7
register
Output
Address
E
R/W
D/I
Busy
check
Write
address
N
Busy
check
N
Read
data
(dummy)
N+1
N+2
Data at address N Data at address N + 1
Data read
address
N+1
AX6108 Dot Matrix Liquid Crystal Graphic Display Column Driver
------------------------------------------------------------------------------------------------------------------------
Figure 5 CPU Read Timing
-----------------------------------------------------------------------------------------------------------------------AX6108 Dot Matrix Liquid Crystal Graphic Display Column Driver
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-----------------------------------------------------------------------------------------------------------------------Busy Flay
Busy flag = 1 indicates that AX6108 is operating and no instructions except status read instruction can
be accepted. The value of the busy flag is read out on DB7 by the status read instruction. Make sure
that the busy flag is reset (0) before issuing insstructions.
E
Busy
flag
T Busy
1/f CLK
¡ØT Busy ¡Ø3/f
CLK
f CLK is £p 1, £p 2 frequency
Figure 6 Busy Flag
Display On/Off Flip/Flop
The display on/off flip/flop selects one of two states, on state and off state of segments Y1 to Y64. In
on state, the display data corresponding to that in RAM is output to the segments. On the other hand,
the display data at all segments. On the other hand, thedisplay data at all segments disappear in off
state independent of the data in RAM. It is controlled by display on/off instruction. RST signal = 0 sets
the segments in off state. The status of the flip/flop is output to DB5 by status read instruction. Display
on/off instruction does not influence data in RAM. To control display data latch by this flip/flop, CL
signal (display synchronous signal) should be input correctly.
Display Start Line Register
The display start line register specifies the line in RAM which corresponds to the top line of LCD
panel, when displaying contents in display data RAM on the LCD panel. It is used for scrolling of the
screen.
6-bit display start line information is written into this register by the display start line set instruction.
When high level of the FRM signal starts the display, the information in this register is transferred to
the Z address counter, which controls the display address, presetting the Z address counter.
X, Y Adddress Counter
A 9-bit counter which designates addresses of the internal display data RAM. X address counter
(upper 3 bits) and Y address counter (lower 6 bits) should be set to each address by the respective
instructions.
-----------------------------------------------------------------------------------------------------------------------AX6108 Dot Matrix Liquid Crystal Graphic Display Column Driver
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Page 17
-----------------------------------------------------------------------------------------------------------------------1. X address counter
Ordinary register with no count functions. An address is set by instruction.
2. Y address counter
An address is set by instruction and is increased by 1 automatically by R/W operations of display data
The Y address counter loops the values of 0 to 63 to count.
Display Data RAM
Stores dot data for display. 1-bit data of this RAM corresponds to light on (data = 1) and light off
(data = 0) of 1 dot in the display panel. The correspondence between Y addresses of RAM and
segment pins can be reversed by ADC signal.
As the ADC signal controls the Y address counter, reversing of the signal during the operation causes
malfunction and destruction of the contents of register and data of RAM. Therefore, never fail to
connnect ADC pin to Vcc or GND when using.
Figure 7 shows the relations between Y address of RAM and segment pins in the cases of ADC = 1
and ADC = 0 (display start line = 0, 1/64 duty cycle).
-----------------------------------------------------------------------------------------------------------------------AX6108 Dot Matrix Liquid Crystal Graphic Display Column Driver
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Page 18
COM1 (AX61203 X1)
COM2 (AX61203 X2)
COM3 (AX61203 X3)
COM4 (AX61203 X4)
LCD
display pattern
COM5 (AX61203 X5)
COM6 (AX61203 X6)
COM7 (AX61203 X7)
COM8 (AX61203 X8)
COM9 (AX61203 X9)
COM62 (AX61203 X62)
COM63 (AX61203 X63)
COM64 (AX61203 X64)
Y1
Y2
Y3
Y4
Y
62
Y5
Y
63
Y64
0
0
1
0
0
0
1
0
1
0
0
1
1
0
0
1
0
1
1
1
0
0
0
1
1
0
0
1
0
0
0
0
1
0
0
0
1
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
1
1
1
1
0
0
0
0
1
0
0
0
0
0
1
0
0
0
0
1
1
0
0
0
1
1
1
1
0
1
Line 0
0
1
1
Line 1
1
0
Line 2
1
AX61202 Pin Name
DB0(LSB)
¡´
DB1
¡´
DB2
¡´
DB3
¡´
X=0
Display
RAM data
DB4
¡´
DB5
¡´
DB6
¡´
¡´
DB7(MSB)
X=1
X=7
Line 62
-----------------------------------------------------------------------------------------------------------------------0
0
0
0
0
0
0
0
0
Line 63
AX6108 Dot Matrix Liquid Crystal Graphic Display Column Driver
1
RAM Y Address
0
2
3
4
5
61 62 63
-----------------------------------------------------------------------------------------------------------------------ADC = 1 (Connected to Vcc)
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Page 19
COM1 (AX61203 X1)
COM2 (AX61203 X2)
COM3 (AX61203 X3)
COM4 (AX61203 X4)
LCD
display pattern
COM5 (AX61203 X5)
COM6 (AX61203 X6)
COM7 (AX61203 X7)
COM8 (AX61203 X8)
COM9 (AX61203 X9)
COM62 (AX61203 X62)
COM63 (AX61203 X63)
COM64 (AX61203 X64)
Y
63
Y
64
Y
62
Y
59
Y
61
Y3
Y2 Y1
Line 0
0
1
1
1
0
0
0
0
0
1
Line 1
1
0
0
0
1
0
0
0
0
1
Line 2
1
0
0
0
1
0
1
0
0
1
1
0
0
0
1
0
0
1
0
1
1
1
1
1
1
0
0
0
1
1
1
0
0
0
1
0
0
0
0
1
1
0
0
0
1
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
1
1
1
1
0
0
0
0
AX61202 Pin Name
DB0(LSB)
¡´
DB1
¡´
DB2
¡´
DB3
¡´
X=0
Display
RAM data
DB4
¡´
DB5
¡´
DB6
¡´
¡´
DB7(MSB)
X=1
X=7
Line 62
0
0
0
0
0
0
0
0
0
Line 63
-----------------------------------------------------------------------------------------------------------------------AX6108 Dot Matrix Liquid Crystal Graphic Display Column Driver
1
RAM Y Address
0
2
3
4
5
61 62 63
-----------------------------------------------------------------------------------------------------------------------ADC = 0 (Connected to GND)
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Page 20
Z Address Counter
The Z address counter generates addresses for outputting the display data synchronized with the
common signal. This counter consists of 6 bits and counts up at the fall of the CL signal. At the high
level of FRM, the contents of the display start line register is preset at the Z counter.
Display Data Latch
The display data latch stores the display data temporarily that is output from display data RAM to the
liquid crystal driving circuit. Data is latched at the rise of the CL signal. The display on/off instruction
controls the data in this latch and does not influence data in display data RAM.
Liquid Crystal Display Driver Circuit
The combination of latched display data and M signal causes one of the 4 liquid crystal driver levels,
V1, V2, V3 and V4 to be output.
Reset
The system can be initialized by setting RST terminal at low level when turning power on.
1. Display off
2. Set display start line register line 0.
While RST is low level, no instruction except status read can be accepted. Therefore, execute other
instructions after making sure that DB4 = 0 (clear RESET) and DB7 = 0 (Ready) by status read
instruction. The conditions of power supply at initial power up are shown in table 1.
Table 1 Power Supply Initial Conditions
Item
Reset time
Rise time
Symbol
Min
t RST
1.0
Unit
Max
Typ
£g s
tr
ns
200
Do not fail to set the system again becaise RESET during operation may destroy the data in
all the registers except on/off register and in RAM.
4.5V
tr
t RST
RST
0.7Vcc
0.3Vcc
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Page 21
Display Control Instructions
Outline
Table 2 shows the instructions. Read/write (R/W) signal, data/instruction (D/I) signal, and data bus
signals (DB0 to DB7) are also called instructions because the internal operation depends on the signals
from the MPU.
These explanations are detailed in the following pages. Generally, there are following three kinds of
instructions :
1. Instruction to set addresses in the internal RAM.
2. Instruction to transfer data from/to the internal RAM.
3. Other instructions.
In general use, the second type of instruction is used most frequently. Since Y address of the internal
RAM is increased by 1 automatically after writing (reading) data, the program can be shortened.
During the execution of an instruction, the system cannot accept instructions other than status read
instruction. Send instructions from MPU after making sure that the busy flag is 0, which is proof that
an instruction is not being excuted.
-----------------------------------------------------------------------------------------------------------------------AX6108 Dot Matrix Liquid Crystal Graphic Display Column Driver
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Page22
Table 2 Instructions
Code
R/W D/I
DB5
1
DB4
1
DB3
1
Display on/off
0
0
DB7
0
Display start line
0
0
1
1
Display start line (0 - 63)
Set page (X address)
0
0
1
0
1
Set address
0
0
0
1
Y address (0 - 63)
Status read
1
0
Busy
0
ON/ Reset
OFF
Write display data
0
1
Write data
Read display data
1
1
Read data
Instructions
DB6
0
Note : 1. Busy time varies with the frequency (f
(1/f CLK ¡ØT BUSY ¡Ø3/f CLK )
1
1
0
DB2
1
DB1
1
DB0
1/0
Page (0 - 7)
Functions
Controls display on/off. RAM data and
internal status are not affected. 1: on, 0:off.
Specifies the RAM line displayed at the top
of the screen.
Sets the page (X address) of RAM at the
page (X address) register.
Sets the Y address in the Y address counter.
0
0
0
Reads the status.
RESET 1 : Reset
0 : Normal
ON/OFF 1 : Display off
0 : Display on
Busy
1 : Internal operation
0 : Ready
Writes data DB0 (LSB)
to DB7 (MSB) on the
data bus into display
RAM.
Has access to the
address of the display
RAM specified in
advance. After the
access, Y address is
Reads data DB0 (LSB) is increased by 1.
to DB7 (MSB) from the
display RAM to the data
bus.
CLK )
of £p1, and £p2.
4
-+
!
" #
$%&
"'()#
*+,
'()"&'+-'-)#
./ ************************************************************************************************************************
0(%
&.1/
2
/3
************************************************************************************************************************
4
-)
************************************************************************************************************************
0(%
&.1/
2
/3
************************************************************************************************************************
4
-9
0
" #
0
45&
&
67
8
" #
8
8
3
45
************************************************************************************************************************
0(%
&.1/
2
/3
************************************************************************************************************************
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Page 26
Status Read
R/W
D/I
0
0
Code
DB0
DB7
1
1
0
high-order bit
Busy
A
1
1
A
A
low-order bit
: When Busy is 1, the LSI is executing internal operations. No instructions are accepted
while Busy is 1, so you should make sure that Busy is 0 before writing the next
instruction.
ON/OFF : Shows the liquid crystal display conditions: on condition or off condition.
When ON/OFF is 1, the display is in off condition.
When ON/OFF is 0, the display is in on condition.
RESET
: RESET = 1 shows that the system is being initialized. In this condition, no instructions
except status read can be accepted.
RESET = 0 shows that initializing has finished and the system is in the usual operation
condition.
Write Display Data
Code
R/W
D/I
DB7
0
1
D
DB0
D
D
D
high-order bit
D
D
D
D
low-order bit
Writes 8-bit data DDDDDDDD (binary) into the display data RAM. Then Y address is increased by 1
automatically.
Read Display Data
Code
R/W
D/I
DB7
0
1
D
DB0
D
high-order bit
D
D
D
D
D
D
low-order bit
Reads out 8-bit data DDDDDDDD (binary) from the display data RAM. Then Y address is increased
by 1 automatically.
One dummy read is necessary right after the address setting. For details, refer to the explanation of
output register in "FUNCTION OF EACH BLOCK".
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Page 27
-----------------------------------------------------------------------------------------------------------------------AX6108 Dot Matrix Liquid Crystal Graphic Display Column Driver
-----------------------------------------------------------------------------------------------------------------------Use of AX6108
Interface with AX6103 (1/64 duty cycle)
Cf
Rf
¡´
¡´
¡´
¡´
¡´
¡´
¡´
LCD Panel
64x64 dots
COM64
X64
Y1
Y64
AX61203
Vcc
¡´
COM1
X1
SEG64
Vcc
V1L, V1R
V6L, V6R
V5L, V5R
V2L, V2R
VEE
GND
C
~
Vcc
V1
V6
V5
V2
VEE
CR
SEG1
R
SHL
DS1
DS2
TH
CL1
FS
M/S
FCS
STB
DL
DR
Open
Open
M
CL2
FRM
£
p1
£
p2
M
CL
FRM
£p1
£p2
AX61202
Power supply circuit
Vcc
+5V (Vcc)
¡´
ADC
RST
Vcc
V1L, V1R
V2L, V2R
V3L, V3R
V4L, V4R
VEE1, VEE2
GND
Vcc
V1
V2
V3
V4
VEE
¡´
R3 V1
R1
R3 V6
-
R1
R3
¡´
R2
R1
R3
V4
¡´
+
External CR
CPU
R3 V5
¡´
V3
¡´
+
¡´
¡´
+
¡´
CS1
CS2
CS3
R/W
D/I
E
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
¡´
+
R1
¡´
R3 V2
¡´
¡´
¡´
V EE
R3 = 15£[
Contrast
-10V
¡´
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Page28
----------------------------------------------------------------------------------------------------------------------
AX6102
Dot Matrix Liquid Crystal Graphic Display Column Driver
-------------------------------------------------------------------
---------------------------------------------------
Y64
~
Y1
~
!" #
$
%!
Figure 10 LCD Driver Timing Chart (1/64 duty cycle)
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Page29
AX6108 Dot Matrix Liquid Crystal Graphic Display Column Driver
-----------------------------------------------------------------------------------------------------------------------Interface with CPU
1. Example of connection with HD6800
Decoder
A15
~
CS1
CS2
A1
VMA
Vcc
CS3
D/I
R/W
A0
R/W
AX6108
HD6800
£p2
E
D0
DB0
~
~
D7
RES
¡´
¡´
Vcc
DB7
RST
Figure 11 Example of Connection with HD6800 Series
In this decoder, addresses of AX6108 in the address area of HD6800 are :
Read/write of the display data
$FFFF
write of display insstruction $FFFF
Read out of status
$FFFF
Therefore, you can control AX6108 by reading/writing the data at these addresses.
-----------------------------------------------------------------------------------------------------------------------AX6108 Dot Matrix Liquid Crystal Graphic Display Column Driver
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-----------------------------------------------------------------------------------------------------------------------2. Example of connection with HD6801
74LS154
P10
P11
P12
P13
A
Y0
B
Y1
C
DG1
Y15
G2
Vcc
(IOS)(SC1)
(R/W)(SC2)
P14
CS1
CS2
CS3
R/W
D/I
HD6801
E
AX6108
No.1
E
P30
P31
DB0
DB1
P37
DB7
(Date bus)
Set HD6801 to mode 5. P10 to P14 are used as the output port and P30 to P37 as the data bus.
¡ ´
74LS154 4-to-16 decoder generates chip select signal to make specified AX6108 active after
decoding 4 bits of P10 to P13.
¡ ´
Therefore, after enabling the operation by P10 to P13 and specifying D/I signal by P14, read/write
from/to the external memory area ($0100 to $01FE) to control AX6108. In this case, IOS signal is
output from SC1 and R/W signal from SC2.
¡ ´
For details of HD6800 and HD6801, refer to their manuals.
¡ ´
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Page31
-----------------------------------------------------------------------------------------------------------------------Example of Application
AX6108
No. 9
Y1
Y64
~
AX6108
No. 10
Y1 Y64
~
AX6108
No. 16
Y1
Y32
~
X1
X2
X3
~
X64
X1
X2
X3
COM64
LCD Panel
128 x 480 dots
COM65
COM66
COM67
~
AX6107
(Slave)
¡½
AX6107
(Master)
COM1
COM2
COM3
X64
COM128
~
Y1
Y64
AX6108
No. 1
~
Y1
Y64
AX6108
No. 2
~
Y1
Y64
AX6108
No. 8
Note : In this example, two AX6107s output the equivalent waveforms. So, stand-alone operation is
possible. In this case, connect COM1 and COM65 to X1, COM2 and COM66 to X2, ..., and
COM64 and COM128 to X64. However, for the large screen display, it is better to drive in 2
rows as in this example to guarantee display qualitty.