ETC AZP92

ARIZONA MICROTEK, INC.
AZP92
ECL/PECL ÷1, ÷2 Clock Generation Chip with Selectable Enable
FEATURES
•
•
•
•
•
•
•
Green and RoHS Compliant / Lead (Pb)
Free Package Available
3.0V to 5.5V Operation
Selectable Divide Ratio
Selectable Enable Polarity and
Threshold (CMOS/TTL or PECL)
Selectable Input Biasing
High Bandwidth for ≥1GHz
Available in a MLP 8 (2x2) Package
PACKAGE AVAILABILITY
PACKAGE
MLP 8 (2x2) Green
/ RoHS Compliant
/ Lead (Pb) Free
DIE
1
2
3
4
PART NO.
MARKING
NOTES
AZP92NAG
P1G
<Date Code>
1,2
AZP92X
N/A
3,4
Add R1 at end of part number for 7 inch (1K parts), R2 for 13 inch (2.5K parts)
Tape & Reel.
Date code format: “Y” for year followed by “WW” for week.
Waffle Pack
Contact factory for availability
DESCRIPTION
The AZP92 is a specialized ÷1 or ÷2 clock generation part including an enable/reset function. The divide ratio is
selected with the DIV-SEL pin/pad. When DIV-SEL is open (NC), the AZP92 functions as a standard receiver. If
DIV-SEL is connected to VEE, it functions as a ÷2 divider.
A selectable enable is provided which also functions as a reset when the ÷2 mode is selected. Enable (EN)
functionality is selected with the EN-SEL pin/pad which has three valid states: open (NC), VEE, or connected to VEE
via a 20kΩ resistor. Leaving EN-SEL open or connecting it to VEE will select the EN pin/pad to function as an active
high CMOS/TTL enable. When EN-SEL is open, an internal 75kΩ pull-up resistor is selected which enables the
outputs whenever EN is left open. When EN-SEL is connected to VEE, an internal 75kΩ pull-down resistor is
selected which disables the outputs whenever EN is left open.
Connecting the EN-SEL to VEE with a 20kΩ resistor will select the EN pin/pad to function as an active low
PECL/ECL enable with an internal 75kΩ pull-down resistor. In this mode, outputs are enabled when EN is left open
(NC). This default logic condition can be overridden by connecting the EN to VCC with an external resistor of
≤20kΩ. Refer to the enable truth table on the next page for detailed operation.
DIE (AZP92X)
¯ to BIAS.
The AZP92X provides a VBB and a BIAS pad with 940Ω internal resistors from D to BIAS and D
Connecting the BIAS pad to VBB allows D and D
¯ to be AC coupled with minimal external components. For single
ended applications, D or D
¯ may be connected directly to VBB to form a single 1880Ω bias resistor. The VBB pin
supports 1.5mA sink/source current. Whenever used, the VBB should be bypassed to ground or VCC with a 0.01 μF
capacitor.
MLP 8, 2x2 mm Package (AZP92NA)
The AZP92NA provides a VBB with an 1880Ω internal bias resistor from D to VBB. This feature allows AC
coupling with minimal external components. The VBB pin supports 1.5mA sink/source current and should be
bypassed to ground or VCC with a 0.01 μF capacitor.
NOTE: The specifications in the ECL/PECL tables are valid when thermal equilibrium has been established.
1630 S. STAPLEY DR., SUITE 125 • MESA, ARIZONA 85204 • USA • (480) 962-5881 • FAX (480) 890-2541
www.azmicrotek.com
AZP92
SIGNAL DESCRIPTION
PIN/PAD
D/D
¯
Q/Q
¯
VBB
BIAS
EN
EN-SEL
DIV-SEL
VEE
VCC
FUNCTION
Data Inputs
Data Outputs
Reference Voltage Output
Input Bias Return
Enable/Reset Input
Enable Logic Select
Divide Ratio Select
Negative Supply
Positive Supply
ENABLE TRUTH TABLE
EN-SEL
NC
NC
VEE
VEE
20kΩ to VEE
20kΩ to VEE
EN
CMOS Low or VEE
CMOS High, VCC or NC
CMOS Low, VEE or NC
CMOS High or VCC
PECL Low, VEE or NC
PECL High or VCC
DIVIDE TRUTH TABLE
Q
Low
Data
Low
Data
Data
Low
Q
¯
High
Data
High
Data
Data
High
DIV-SEL
DIVIDE
RATIO
NC
÷1
VEE1
÷2
1
DIV-SEL connection must
be ≤1Ω.
D
EN (EN-SEL CONNECTED TO
(PECL)
EN (EN-SEL OPEN OR
(CMOS)
VEE VIA 20k
RESISTOR)
CONNECTED TO VEE)
Q
(DIV-SEL
OPEN)
Q
(DIV-SEL
CONNECTED
TO VEE)
TIMING DIAGRAM
January 2006 REV - 1
www.azmicrotek.com
2
AZP92
DIE PAD COORDINATES
AZP92
A
B
L
M
SIGNAL
A
B
C
D
E
F
G
H
I
J
K
L
M
D
D
¯
BIAS
VBB
EN
VEE
DIV-SEL
Q
¯
Q
NC
VCC
VCC
EN-SEL
J
BOND PAD: 85u X 85u
D
Notes:
NAME
DIE SIZE: 950u X 940u
DIE THICKNESS: 14 MILS
C
K
E
F
I
H
G
1. Other die thicknesses available. Contact
factory for further information.
2. The die backside may be left open or
connected to VEE.
AZP92NA
MLP 8, 2x2 mm
TOP VIEW
January 2006 REV - 1
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3
X
(Microns)
-342.5
-342.5
-342.5
-342.5
-33.5
126.5
312.5
312.5
312.5
312.5
302.5
142.5
-140.5
Y
(Microns)
312.5
144.5
-87.0
-255.0
-312.5
-312.5
-248.5
-98.5
51.5
201.5
342.5
342.5
342.5
AZP92
Absolute Maximum Ratings are those values beyond which device life may be impaired.
Symbol
VCC
VI
VEE
VI
IHGOUT
TA
TSTG
Characteristic
PECL Power Supply
(VEE = 0V)
PECL Input Voltage
(VEE = 0V)
ECL Power Supply
(VCC = 0V)
ECL Input Voltage
(VCC = 0V)
Output Current
— Continuous
— Surge
Operating Temperature Range
Storage Temperature Range
Rating
0 to +6.0
0 to +6.0
-6.0 to 0
-6.0 to 0
50
100
-40 to +85
-65 to +150
Unit
Vdc
Vdc
Vdc
Vdc
mA
°C
°C
100K ECL DC Characteristics (VEE = -3.0V to -5.5V, VCC = GND)
Symbol
VOH
VOL
VIH
VIL
VBB
IIH
IIL
IEE
1.
2.
3.
4.
-40°C
Characteristic
1
Min
-1085
-1900
0°C
Max
-880
-1555
Min
-1025
-1900
Output HIGH Voltage
Output LOW Voltage1
Input HIGH Voltage
-1165
-390
D/D
¯ , EN (ECL)2
-1165
VCC
EN (CMOS)3 VEE+2000
VEE+2000
Input LOW Voltage
-2250
-1475
-2250
D/D
¯ , EN (ECL)2
VEE
VEE + 800
VEE
EN (CMOS)3
Reference Voltage
-1390
-1250
-1390
Input HIGH Current EN
150
Input LOW Current
0.5
0.5
EN (ECL)2
-150
-150
EN (CMOS)3
Power Supply Current4
31
Specified with outputs terminated through 50Ω resistors to VCC - 2V.
EN-SEL connected to VEE through a 20kΩ resistor.
EN-SEL connected VEE or left open (NC).
DIV-SEL left open (NC).
25°C
85°C
Unit
Max
-880
-1620
Min
-1025
-1900
Max
-880
-1620
Min
-1025
-1900
Max
-880
-1620
-390
VCC
-1165
VEE+2000
-390
VCC
-1165
VEE+2000
-390
VCC
mV
-1475
VEE + 800
-1250
150
-2250
VEE
-1390
-1475
VEE + 800
-1250
150
-2250
VEE
-1390
-1475
VEE + 800
-1250
150
mV
0.5
-150
mV
μA
μA
0.5
-150
31
mV
mV
31
34
mA
100K LVPECL DC Characteristics (VEE = GND, VCC = +3.3V)
Symbol
VOH
VOL
VIH
VIL
VBB
IIH
IIL
IEE
1.
2.
3.
4.
5.
-40°C
Characteristic
1,2
Min
2215
1400
0°C
Max
2420
1745
Min
2275
1400
25°C
Max
2420
1680
Output HIGH Voltage
Output LOW Voltage1,2
Input HIGH Voltage1
2135
2910
2135
2910
D/D
¯ , EN (PECL)3
EN (CMOS)4
2000
VCC
2000
VCC
Input LOW Voltage1
1050
1825
1050
1825
D/D
¯ , EN (PECL)3
EN (CMOS)4
GND
800
GND
800
1
Reference Voltage
1910
2050
1910
2050
Input HIGH Current EN
150
150
Input LOW Current
0.5
0.5
EN (PECL)3
-150
-150
EN (CMOS)4
Power Supply Current5
31
31
For supply voltages other that 3.3V, use the ECL table values and ADD supply voltage value.
Specified with outputs terminated through 50Ω resistors to VCC - 2V.
EN-SEL connected to VEE through a 20kΩ resistor.
EN-SEL connected VEE or left open (NC).
DIV-SEL left open (NC).
January 2006 REV - 1
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4
85°C
Unit
Min
2275
1400
Max
2420
1680
Min
2275
1400
Max
2420
1680
2135
2000
2910
VCC
2135
2000
2910
VCC
mV
1050
GND
1910
1825
800
2050
150
1050
GND
1910
1825
800
2050
150
mV
0.5
-150
mV
μA
μA
0.5
-150
31
mV
mV
34
mA
AZP92
100K PECL DC Characteristics (VEE = GND, VCC = +5.0V)
Symbol
VOH
VOL
VIH
VIL
VBB
IIH
IIL
IEE
1.
2.
3.
4.
5.
-40°C
Characteristic
0°C
Min
3915
3100
1,2
Max
4120
3445
Min
3975
3100
25°C
Max
4120
3380
Output HIGH Voltage
Output LOW Voltage1,2
Input HIGH Voltage1
3835
4610
3835
4610
D/D
¯ , EN (PECL)3
EN (CMOS)4
2000
VCC
2000
VCC
Input LOW Voltage1
2750
3525
2750
3525
D/D
¯ , EN (PECL)3
EN (CMOS)4
GND
800
GND
800
1
Reference Voltage
3610
3750
3610
3750
Input HIGH Current EN
150
150
Input LOW Current
0.5
0.5
EN (PECL)3
-150
-150
EN (CMOS)4
Power Supply Current5
31
31
For supply voltages other that 5.0V, use the ECL table values and ADD supply voltage value.
Specified with outputs terminated through 50Ω resistors to VCC - 2V.
EN-SEL connected to VEE through a 20kΩ resistor.
EN-SEL connected VEE or left open (NC).
DIV-SEL left open (NC).
85°C
Unit
Min
3975
3100
Max
4120
3380
Min
3975
3100
Max
4120
3380
3835
2000
4610
VCC
3835
2000
4610
VCC
mV
2750
GND
3610
3525
800
3750
150
2750
GND
3610
3525
800
3750
150
mV
0.5
-150
mV
mV
mV
μA
μA
0.5
-150
31
34
mA
AC Characteristics (VEE = -3.0V to -5.5V; VCC = GND or VEE = GND; VCC = +3.0V to +5.5V)
Symbol
Characteristic
Min
-40°C
Typ
Max
Min
0°C
Typ
Max
Min
Propagation Delay
450
450
D to Q/Q
¯ Outputs1
(SE)
600
600
EN to Q/Q
¯ Outputs1
tSKEW
Duty Cycle Skew2
(SE)
5
20
5
20
Input Swing3
150
1000
150
1000
150
VPP (AC)
Differential (D/D
¯)
300
2000
300
2000
300
Single Ended (D)4
Output Rise/Fall1
80
200
80
200
80
tr / t f
(20% - 80%)
1.
Specified with outputs terminated through 50Ω resistors to VCC - 2V.
2.
Duty cycle skew is the difference between a tPLH and tPHL propagation delay through a device.
3.
The peak-to-peak input swing is the range for which AC parameters are guaranteed.
4.
Range valid for AC coupled signals only.
25°C
Typ
Max
5
450
600
20
tPLH / tPHL
AC PP INPUT (Differential)
D
D
V PP (AC)
January 2006 REV - 1
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5
Min
85°C
Typ
Max
5
450
600
20
Unit
ps
ps
1000
2000
150
300
1000
2000
mV
200
80
200
ps
AZP92
PACKAGE DIAGRAM
MLP 8 2x2mm
Pin 1 Dot
By Marking
2.000±0.050
MLP 8
(2x2mm)
2.000±0.050
TOP VIEW
Pin 1 Identification
R0.100 TYP
0.350±0.050
0.250±0.050
0.500 bsc
8
1
7
6
2 1.200±0.050
exp. pad
3
5
4
0.600±0.050
exp. pad
BOTTOM VIEW
0.750±0.050
0.000-0.050
1
2
SIDE VIEW
Note: All dimensions are in mm
January 2006 REV - 1
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6
3 4
0.203±0.025
1.750
Ref.
AZP92
Arizona Microtek, Inc. reserves the right to change circuitry and specifications at any time without prior notice. Arizona Microtek, Inc.
makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Arizona
Microtek, Inc. assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all
liability, including without limitation special, consequential or incidental damages. Arizona Microtek, Inc. does not convey any license
rights nor the rights of others. Arizona Microtek, Inc. products are not designed, intended or authorized for use as components in systems
intended to support or sustain life, or for any other application in which the failure of the Arizona Microtek, Inc. product could create a
situation where personal injury or death may occur. Should Buyer purchase or use Arizona Microtek, Inc. products for any such
unintended or unauthorized application, Buyer shall indemnify and hold Arizona Microtek, Inc. and its officers, employees, subsidiaries,
affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly
or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that
Arizona Microtek, Inc. was negligent regarding the design or manufacture of the part.
January 2006 REV - 1
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