01W095A Clock generator for digital still camera BU2382FV Dimension (Units : mm) BU2382FV is a high-performance 2-channel PLL IC. PLL circuit generates necessary clocks by inputting standard clocks of crystal oscillator from outside. Changing a connection of wire can generate any clocks required for any applications of users. Jitter and S/N characteristic has achieved almost the same high-quality sound and vision as oscillating module because of optimization of PLL. Frequency can be changed by the internal dividing control. 1.15 ± 0.1 6.4 ± 0.3 0.1 4.4 ± 0.2 5.0 ± 0.2 16 9 1 8 0.3Min. Description 0.65 0.15 ± 0.1 0.1 0.22 ± 0.1 SSOP-B16 Features 1) Generate clocks for CDS, USB with standard clock input 2) No external elements required 3) Standard clocks apply to two kinds of NTSC/PAL 4) Power down control in each 2-channel PLL 5) Single power supply of 3.3V operating 6) SSOP-B16 small package Applications Digital still camera Absolute Maximum Ratings (Ta=25°C) Parameter Limits Symbol Applied voltage VDD –0.5 Input voltage –0.5 Storage temperature range VIN Tstg Power dissipation PD –30 ~ +7.0 ~ VDD+0.5 ~ +125 450 Unit V V °C mW *IC destruction is not occurred, however, operation can not be guaranteed. *Derating : 4.5mW/°C for operation above Ta=25°C *This product is not designed for protection against radioactive rays. *Power dissipation is the rate when the IC is mounted on the board. October, 2001 Recommended Operating Conditions (Ta=25°C) Parameter Symbol Min. Typ. Max. Unit Power supply voltage VDD 3.0 – 3.6 V Input H voltage range VIH 0.8VDD – VDD V Input L voltage range Operating temperature VIL 0 – 0.2VDD V Topr –5 – 70 °C CL – – 15 pF Output load Electrical Characteristics (Unless otherwise noted; Ta=25°C, Vcc=3.3V, Xtal frequency=14.318182MHz) Parameter Symbol Min. Typ. Output H voltage VOH 2.4 Output L voltage VOL – Input thL *3 VthL Input thH *3 Hysteresis width *3 Operating circuit current Max. Unit – – V IOH=–4.0mA – 0.4 V IOL=4.0mA 0.2VDD – – V *1 VthH – – 0.8VDD V *1 Vhys – 0.4 – V Vhys=VthH–VthL IDD – 30 45 mA CLK1_LL CLK1_LH CLK1 CLK1_HL CLK1_HH CLK2_L CLK2 CLK2_H 48.626786 – 70.937900 48.461539 – 47.998451 No load XTAL´170/31/2 (XTAL=17.734475MHz) – MHz 71.877274 47.998742 Conditions XTAL´360/45/2 (XTAL=17.734475MHz) XTAL´176/26/2 (XTAL=14.318182MHz) XTAL´502/50/2 (XTAL=14.318182MHz) – MHz XTAL´249/46/2 (XTAL=17.734475MHz) XTAL´295/44/2 (XTAL=14.38182MHz) Duty 45 50 55 % Jitter σ JsSD – 30 – psec 1σ short time jitter JsABS – 180 – psec Min.–Max. tr – 2.5 – nsec 20% ~ 80% time of VDD tf – 2.5 – nsec 20% ~ 80% time of VDD tlock – – 1 msec *2 Jitter Min.-Max. Rise time Fall time Output Lock time Note) Output frequency is determined by the operation expression (Frequency divide) input to XTAL IN. Output at 27MHz input is shown above. Jitter is value when using Time interval analyzer with 10000 sampling. ※1） Low and high limit voltage in the schmitt trigger input Pin having hysteresis features shown in ※3 diagram. ※2） Time that output takes to stabilize in the specific frequency range after the power supply reaches to 3.0V. ※3） Make reference to the diagram. 1/2VDD test Output (V) Duty Block Diagram N T:14.38182MHz PAL:17.734475MHz 0.2VDD VthL 1 VDD2 OE_CLK1 16 H or L 2 VSS2 CLK1 15 CLK1 output 3 REF_CLK SEL 14 H or L 4 TEST1 NT_PAL 13 H or L 5 AVDD DVDD 12 6 AVSS DVSS 11 7 XTALIN CLK2 10 8 XTALOUT OE_CLK2 BU2382FV 9 CLK2 output H or L Vhys 1/2VDD 0.8VDD VthH Input(V)