DM9101 10/100Mbps Ethernet Physical Layer Single Chip Transceiver General Description The DM9101 is a physical-layer, single-chip, low-power transceiver for 100Base-TX, and 10Base-T operations. On the media side, it provides a direct interface either to Unshielded Twisted Pair Category 5 Cable (UTP5) for 100Base-TX Fast Ethernet, or UTP5/UTP3 Cable for 10Base-T Ethernet. Through the IEEE 802.3u Media Independent Interface (MII), the DM9101 connects to the Medium Access Control (MAC) layer, ensuring a high interoperability among products from different vendors. The DM9101 uses a low-power and high-performance CMOS process. It contains the entire physical layer functions of 100Base-TX as defined by IEEE 802.3u, including the Physical Coding Sublayer (PCS), Physical Medium Attachment (PMA), 100Base-TX Twisted Pair Physical Medium Dependent Sublayer (TP-PMD), and a 10Base-T Encoder/Decoder (ENC/DEC). The DM9101 provides strong support for the Auto-negotiation function utilizing automatic media speed and protocol selection. The DM9101 incorporates an internal wave-shaping filter to control rise/fall time, eliminating the need for external filtering on the 10/100Mbps signals. Patent-Pending Circuitry Includes: Smart adaptive receiver equalizer Digital algorithm for high frequency clock/data recovery circuit High speed wave-shaping circuit Block Diagram 25M OSCI LED1-4# LED Driver TX CGM 4B/5B Encoder Scrambler Parallel to Serial NRZ to NRZI NRZI to MLT-3 MLT-3 Driver 100TXD+/- Rise/Fall Time CTL 25M CLK 125M CLK MII Signals MII Interface/ Control 4B/5B Decoder Codegroup Alignment Descrambler Serial to Parallel NRZI to NRZ MLT-3 to NRZI Adaptive EQ RXI+/- RX RXI+/- TX 10TXD+/- RX CRM Digital Logic 10BASE-T Module Register Final Version: DM9101-DS-F03 July 22, 1999 Collision Detection Carrier Sense AutoNegotiation 1 DM9101 10/100Mbps Ethernet Physical Layer Single Chip Transceiver Table of Contents General Description ................................................1 - Register 2 .......................................................... 23 Block Diagram ........................................................1 PHY ID Identifier Register #2 (PHYIDR2) - Register 3 .......................................................... 24 Features .................................................................3 Pin Configuration: DM9101E LQFP.........................3 Pin Configuration: DM9101F QFP...........................4 Auto-negotiation Advertisement Register (ANAR) - Register 4 .......................................................... 24 Auto-negotiation Link Partner Ability Register (ANLPAR) - Register 5 ......................................... 25 Pin Description .......................................................5 Functional Description MII Interface ......................................................12 100Base-TX Operation ......................................14 100Base-TX Transmit........................................14 100Base-TX Operation ......................................15 4B5B Encoder ...................................................15 Scrambler..........................................................15 Parallel to Serial Converter ................................15 NRZ to NRZI Encoder........................................15 MLT-3 Converter ...............................................15 MLT-3 Driver .....................................................15 4B5B Code Group .............................................16 100Base-TX Receiver........................................17 Signal Detect .....................................................17 Digital Adaptive Equalization..............................17 MLT-3 to NRZI Decoder.....................................17 Clock Recovery Module .....................................18 NRZI to NRZ .....................................................18 Serial to Parallel ................................................18 Descrambler......................................................18 Code Group Alignment ......................................18 4B5B Decoder ...................................................18 10Base-T Operation ..........................................18 Collision Detection.............................................18 Carrier Sense ....................................................18 Auto-Negotiation................................................18 MII Serial Management......................................19 Serial Management Interface .............................19 Management Interface – Read Frame Structure.19 Management Interface – Write Frame Structure.19 Register Description .............................................20 - Key To Default....................................................20 Basic Mode Control Register (BMCR) - Register 0...........................................................21 Auto-negotiation Expansion Register (ANER) - Register 6 .......................................................... 26 DAVICOM Specified Configuration Register (DSCR) - Register 16......................................................... 26 DAVICOM Specified Configuration and Status Register (DSCSR) - Register 17 ........................... 28 10Base-T Configuration / Status (10BTSCRCSR) - Register 18......................................................... 29 Absolute Maximum Ratings .................................. 30 DC Electrical Characteristics ................................ 31 AC Characteristics................................................ 32 Timing Waveforms MII-100Base-TX Transmit Timing Diagram ........ 33 MII-100Base-TX Receive Timing Diagram ......... 33 Auto-negotiation and Fast Link Pulse Timing ..... 34 MII-10Base-T Transmit Timing Diagram ............ 35 MII-10Base-T Receive Nibble Timing Diagram .. 35 10BASE-T SQE (Heartbeat) Timing Diagram..... 36 10BASE-T Jab and Unjab Timing Diagram ........ 36 MDIO Timing when OUTPUT by STA ................ 37 MDIO Timing when OUTPUT by DM9101.......... 37 Magnetics Selection Guide ................................... 38 Crystal Selection Guide ........................................ 38 Application Circuit (for reference only) .................. 40 Package Information............................................. 41 Ordering Information............................................. 42 Basic Mode Status Register (BMSR) - Register 1...........................................................22 Company Overview .............................................. 42 PHY ID Identifier Register #1 (PHYIDR1) Contact Windows.................................................. 42 2 Final Version: DM9101-DS-F03 July 22, 1999 DM9101 10/100Mbps Ethernet Physical Layer Single Chip Transceiver Features • • • • • • • • 10/100Base-TX physical-layer, single-chip transceiver Compliant with IEEE 802.3u 100Base-TX standard Compliant with ANSI X3T12 TP-PMD 1995 standard Compliant with IEEE 802.3u Auto-negotiation protocol for automatic link type selection Supports the MII with serial management interface Supports Full Duplex operation for 10 and 100Mbps High performance 100Mbps clock generator and data recovery circuitry Adaptive equalization circuitry for 100Mbps receiver • • • • • • • Controlled output edge rates in 100Mbps Supports a 10Base-T interface without the need for an external filter Provides Loop-back mode for system diagnostics Includes Flexible LED configuration capability Digital clock recovery circuit using advanced digital algorithm to reduce jitter Low-power, high-performance CMOS process Available in both a 100 pin LQFP and a 100 QFP package 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 8 1 80 79 78 77 76 NC AVCC AGND AGND 10BTSER BPSCR BP4B5B BPALIGN RPTR/NODE# OPMODE3 OPMODE2 OPMODE1 OPMODE0 PHYAD4 PHYAD3 DVCC DGND PHYAD2 PHYAD1 PHYAD0 TESTMODE RESET# RX_EN RX_ER/RXD4 RX_DV Pin Configuration: DM9101E LQFP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 DM9101E 75 74 73 72 71 70 69 68 67 66 65 64 63 62 6 1 60 59 58 57 56 55 54 53 52 5 1 COL CRS RX_CLK DVCC DGND RXD0 RXD1 RXD2 RXD3 DVCC DGND MDIO MDC TX_CLK TX_EN DVCC DGND TXD0 TXD1 TXD2 TXD3 TX_ER/TXD4 TXLED# RXLED# LINKLED# AVCC OSCI/X1 X2 AGND OSC/XTL# AVCC AGND BGREF BGRET DGND DGND DGND DVCC TRIDRV UTP SPEED10 RX_LOCK DGND NC LINKSTS CLK25M DVCC FDXLED# COLLED# DGND 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 NC NC NC AGND AVCC AVCC RXIRXI+ AGND AGND 10TXO10TXO+ AVCC AVCC AGND AGND NC NC AVCC AVCC AGND AGND 100TXO100TXO+ AVCC Final Version: DM9101-DS-F03 July 22, 1999 3 DM9101 10/100Mbps Ethernet Physical Layer Single Chip Transceiver 4 PHYAD2 PHYAD1 PHYAD0 TESTMODE RESET# 84 83 82 81 DGND 85 DVCC 86 OPMODE1 91 PHYAD3 OPMODE2 92 87 OPMODE3 93 88 RPTR/NODE# 94 OPMODE0 BPALIGN 95 PHYAD4 BP4B5B 96 89 BPSCR 97 90 AGND 10BTSER 98 AGND 99 100 Pin Configuration: DM9101F QFP AVCC 1 80 RX_EN NC 2 79 RX_ER/RXD4 NC 3 78 RX_DV NC 4 77 COL NC 5 76 CRS AGND 6 75 RX_CLK 7 74 DVCC AVCC 8 73 DGND RXI- 9 72 RXD0 RXI+ 10 71 RXD1 AGND 11 70 RXD2 AGND 12 69 RXD3 10TXO- 13 68 DVCC 10TXO+ 14 67 DGND AVCC 15 66 MDIO AVCC 16 65 MDC AGND 17 64 TX_CLK AGND 18 63 TX_EN NC 19 62 DVCC NC 20 61 DGND AVCC 21 60 TXD0 AVCC 22 59 TXD1 AGND 23 58 TXD2 AGND 24 57 TXD3 100TXO- 25 56 TX_ER/TXD4 100TXO+ 26 55 TXLED# AVCC 27 54 RXLED# AVCC 28 53 LINKLED# OSCI/X1 29 52 DGND X2 30 51 COLLED# 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 BGRET DGND DGND DGND DVCC TRIDRV UTP SPEED10 RX_LOCK DGND NC LINKSTS CLK25M DVCC FDXLED# 33 AVCC AGND 32 BGREF 31 AGND OSC/XTL# DM9101F Final Version: DM9101-DS-F03 July 22, 1999 DM9101 10/100Mbps Ethernet Physical Layer Single Chip Transceiver Pin Description Pin No. LQFP QFP MII Interface 54 56 Pin Name I/O TX_ER/ TXD4 I Transmit Error: In 100Mbps mode, if this signal is asserted high and TX_EN is active, the HALT symbol is substituted for the actual data nibble. In 10Mbps mode, this input is ignored. In bypass modes (BP4B5B or BPALIGN), TX_ER becomes the TXD4 pin, the fifth TXD data bit. Transmit Data: Transmit data input pins for nibble data from the MII in 100Mbps or 10Mbps nibble mode (25 MHz for 100Mbps mode, 2.5MHz for 10Mbps nibble mode). In 10Mbps serial mode, the TXD0 pin is used as the serial data input pin. TXD[3:1] are ignored. Transmit Enable: Active high input indicates the presence of valid nibble data on TXD[3:0] for both 100Mbps or 10Mbps nibble mode. In 10Mbps serial mode, active high indicates the presence of valid 10Mbps data on TXD0. Transmit Clock: Transmit clock output from the DM9101: - 25MHz nibble transmit clock derived from transmit Phase Locked Loop(TX PLL) in 100Base-TX mode - 2.5MHz transmit clock in 10Base-T nibble mode - 10MHz transmit clock in 10Base-T serial mode Management Data Clock: Synchronous clock to the MDIO management data input/output serial interface which is asynchronous to transmit and receive clocks. The maximum clock rate is 2.5MHz. Management Data I/O: Bi-directional management instruction/data signal that may be driven by the station management entity or the PHY. This pin requires a 1.5KΩ pull-up resistor. Receive Data: Nibble wide receive data (synchronous to RX_CLK - 25MHz for 100Base-TX mode, 2.5MHz for 10Base-T nibble mode). Data is driven on the falling edge of RX_CLK. In 10Mbps serial mode, the RXD0 pin is used as the data output pin. RXD[3:1] are ignored. Receive Clock: Provides the recovered receive clock for different modes of operation: - 25MHz nibble clock in 100Mbps mode - 2.5MHz nibble clock in 10Mbps nibble mode - 10MHz receive clock in 10Mbps serial mode 55-58 57 - 60 TXD3 TXD2 TXD1 TXD0 I 61 63 TX_EN I 62 64 TX_CLK O,Z 63 65 MDC I 64 66 MDIO I/O 67-70 69 - 72 RXD3 RXD2 RXD1 RXD0 O,Z 73 75 RX_CLK O,Z Final Version: DM9101-DS-F03 July 22, 1999 Description 5 DM9101 10/100Mbps Ethernet Physical Layer Single Chip Transceiver Pin Description (continued) Pin No. Pin Name LQFP QFP MII Interface (continued) 74 76 CRS Description O,Z Carrier Sense: This pin is asserted high to indicate the presence of carrier due to receive or transmit activities in 10Base-T or 100Base-TX Half Duplex modes. In Repeater, when Full Duplex or Loop-back mode is a logic 1, it indicates the presence of carrier due only to receive activity. Collision Detect: Asserted high to indicate detection of collision conditions in 10Mbps and 100Mbps Half Duplex modes. In 10Base-T Half Duplex mode with Heartbeat set active (bit 13, register 18h), it is also asserted for a duration of approximately 1ms at the end of transmission to indicate heartbeat. In Full Duplex mode, this signal is always logic 0. There is no heartbeat function in Full-Duplex mode. Receive Data Valid: Asserted high to indicate that valid data is present on RXD[3:0]. Receive Error: Asserted high to indicate that an invalid symbol has been detected inside a received packet in 100Mbps mode. In a bypass mode (BP4B5B or BPALIGN modes), RX_ER becomes RXD4, the fifth RXD data bit of the 5B symbols. Receive Enable: Active high enabled for receive signals RXD[3:0], RX_CLK, RX_DV and RX_ER. A low on this input tri-states these output pins. For normal operation in a NODE application, this pin should be pulled high. 75 77 COL O,Z 76 78 RX_DV O,Z 77 79 RX_ER/ RXD4 O,Z 78 80 RX_EN I RXI-, RXI+ I Media Interface 7, 8 9, 10 6 I/O 11, 12 13, 14 10 TXO-, 10 TXO+ O 23, 24 25, 26 100 TXO-, 100 TXO+ O 100/10Mbps Differential Input Pair: These pins are the differential receive input for 10Base-T and 100Base-TX. They are capable of receiving 100Base-TX MLT-3 or 10Base-T Manchester encoded data. 10Base-T Differential Output Pair: This output pair provides controlled rise and fall times designed to filter the transmitters output. 100Base-TX Differential Output Pair: This output pair drives MLT-3 encoded data to the 100M twisted pair interface and provides controlled rise and fall times designed to filter the transmitter output, reducing any associated EMI. Final Version: DM9101-DS-F03 July 22, 1999 DM9101 10/100Mbps Ethernet Physical Layer Single Chip Transceiver Pin Description (continued) Pin No. Pin Name I/O Description LQFP QFP LED Interface : These outputs can directly drive LEDs or provide status information to a network management device. Polarity/Full Duplex LED: 48 50 FDXLED# O (POLLED) Indicates Full Duplex mode status for 100Mbps and 10Mbps operation (Active low). If bit 4 of Register 16 (FDXLED_MODE) is set, the FDXLED# pin function will change to indicate the Polarity status for 10Mbps operation. If polarity is inverted, the POLLED will go ON. Collision LED: 49 51 COLLED# O Indicates the presence of collision activity for 10Mbps and 100Mbps operation. This LED has no meaning for 10Mbps or 100Mbps Full Duplex operation (Active low). Link LED: 51 53 LINKLED# O Indicates Good Link status for 10Mbps and 100Mbps operation (TRAFFIC LED) (Active low). It functions as the TRAFFIC LED when bit 5 of register 16 is set to 1. In TRAFFIC LED mode, it is always ON when the link is OK. The TRAFFIC LED flashes when transmitting or receiving. Receive LED: 52 54 RXLED# OD Indicates the presence of receive activity for 10Mbps and 100Mbps operation (Active low). The DM9101 incorporates a "monostable" function on the RXLED output. This ensures that even minimal receive activity will generate an adequate LED ON time. Transmit LED: 53 55 TXLED# OD Indicates the presence of transmit activity for 10Mbps and 100Mbps operation (Active low). The DM9101 incorporates a "monostable" function on the TXLED output. This ensures that even minimal transmit activity will generate an adequate LED ON time. Device Configuration/Control/Status Interface UTP Cable Indication: 40 42 UTP O UTP=1: Indicates UTP cable is used. Speed 10Mbps: 41 43 SPEED10 O When set high, this bit indicates a 10Mbps operation, when set low 100Mbps operation. This pin can drive a low current LED to indicate that 100Mbps operation is selected. Lock for Clock/Data Recovery PLL: 42 44 RX_LOCK O When this pin is high it indicates that the receiver recovery PLL logic has locked to the input data stream. Link Status Register Bit: 45 47 LINKSTS O This pin reflects the status of bit 2 register 1. Final Version: DM9101-DS-F03 July 22, 1999 7 DM9101 10/100Mbps Ethernet Physical Layer Single Chip Transceiver Pin Description (continued) Pin No. Pin Name I/O Description LQFP QFP Device Configuration/Control/Status Interface (continued) OPMODE0 - OPMODE3: 88-91 90 - 93 OPMODE0 I OPMODE1 These pins are used to control the forced or advertised operating OPMODE2 mode of the DM9101 (see table below). The value is latched into OPMODE3 the DM9101 registers at power-up/reset. OPMODE3 0 8 92 94 RTPR/NOD E# I 93 95 BPALIGN I OPMODE2 0 OPMODE1 0 OPMODE0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 Function Auto-neg enable with all capabilities with Flow Control Auto-neg enable without all capabilities without Flow Control Auto-neg 100TX FDX with Flow Control only Auto-neg 100TX FDX/HDX without Flow Control Auto-neg 10TP FDX with Flow Control only Auto-neg 10TX FDX/HDX without Flow Control Manual select 100TX FDX Manual select 100TX HDX Manual select 10TX FDX Manual select 10TX HDX Repeater/Node Mode: When set high, this bit selects REPEATER mode; when set low, it selects NODE. In REPEATER mode or NODE mode with Full Duplex configured, the Carrier Sense (CRS) output from the DM9101 will be asserted only during receive activity. In NODE mode or a mode not configured for Full Duplex operation, CRS will be asserted during receive or transmit activity. At power-up/reset, the value on this pin is latched into Register 16, bit 11. Bypass Alignment: Allows 100Mbps transmit and receive data streams to bypass all of the transmit and receive operations when set high. At power-up/reset, the value on this pin is latched into bit Register 16 ,bit 13. Final Version: DM9101-DS-F03 July 22, 1999 DM9101 10/100Mbps Ethernet Physical Layer Single Chip Transceiver Pin Description (continued) Pin No. Pin Name I/O Description LQFP QFP Device Configuration/Control/Status Interface (continued) Bypass 4B5B Encoder/Decoder: 94 96 BP4B5B I Allows 100Mbps transmit and receive data streams to bypass the 4B to 5B encoder and 5B to 4B decoder circuits when set high At power-up/reset, the value on this pin is latched into Register 16, bit 15. Bypass Scrambler/Descrambler: 95 97 BPSCR I Allows 100Mbps transmit and receive data streams to bypass the scrambler and descrambler circuits when set high. At power-up/reset, the value on this pin is latched into Register 16, bit 14. Serial/Nibble Select: 96 98 10BTSER I 10Mbps Serial Operation: When set high, this input selects a serial data transfer mode. Manchester encoded transmit and receive data is exchanged serially with a 10MHz clock rate on the least significant bits of the nibble-wide MII data buses, pin TXD[0] and RXD[0] respectively. This mode is intended for use with the DM9101 connected to a device (MAC or Repeater) that has a 10Mbps serial interface. Serial operation is not supported in 100Mbps mode. For 100Mbps, this input is ignored. 10 and 100Mbps Nibble Operation: When set low, this input selects the MII compliant nibble data transfer mode. Transmit and receive data is exchanged in nibbles on the TXD[3:0] and RXD[3:0] pins respectively. At power-up/reset, the value on this pin is latched into Register 18, bit 10. Clock Interface 27 29 OSCI/X1 I 28 30 X2 O 30 32 OSC/XTL# I 46 48 CLK25M O,Z Final Version: DM9101-DS-F03 July 22, 1999 Crystal or Oscillator Input: This pin should be connected to a 25MHz (±50 ppm) crystal if OSC/XTL#=0 or a 25MHz (±50ppm) external TTL oscillator input, if OSC/XTLB=1. Crystal Oscillator Output: An external 25MHz (±50 ppm) crystal should be connected to this pin if OSC/XTL#=0, or left unconnected if OSC/XTL#=1. Crystal or Oscillator Selector Pin: OSC/XTL#=0: An external 25MHz (±50ppm) crystal should be connected to X1 and X2 pins. OSC/XTL#=1: An external 25MHz (±50ppm) oscillator should be connected to X1 and X2 should be left unconnected. 25MHz Clock Output:. This clock is derived directly from the crystal circuit. 9 DM9101 10/100Mbps Ethernet Physical Layer Single Chip Transceiver Pin Description (continued) Pin No. Pin Name I/O Description LQFP QFP PHY Address Interface: PHYAD[4:0] provides up to 32 unique PHY address. An address selection of all zeros (00000) will result in a PHY isolation condition. See the isolate bit description in the BMCR, address 00. PHY Address 0: 81 83 PHYAD0 I PHY address bit 0 for multiple PHY address applications. The status of this pin is latched into Register 17, bit 8 during power up/reset. PHY Address 1: 82 84 PHYAD1 I PHY address bit 1 for multiple PHY address applications. The status of this pin is latched into Register 17, bit 7 during power up/reset. PHY Address 2: 83 85 PHYAD2 I PHY address bit 2 for multiple PHY address applications. The status of this pin is latched into Register 17, bit 6 during power up/reset. PHY Address 3: 86 88 PHYAD3 I PHY address bit 3 for multiple PHY address applications. The status of this pin is latched into Register 17, bit 5 during power up/reset. PHY Address 4: 87 89 PHYAD4 I PHY address bit 4 for multiple PHY address applications. The status of this pin is latched into Register 17, bit 4 during power up/reset. Miscellaneous No Connect: 1-3, 2 - 5, NC 17, 18, 19, 20, Leave these pins unconnected (floating). 44, 46 100 Bandgap Voltage Reference: 33 35 BGREF I Connect a 6.01KΩ, 1% resistor between this pin and the BGRET pin to provide an accurate current reference for the DM9101. Bandgap Voltage Reference Return: 34 36 BGRET I Return pin for 6.01KΩ resistor connection. Tri-state Digital Output Pins: 39 41 TRIDRV I When set high, all digital output pins are set to a high impedance state, and I/O pins, go to input mode. Reset: Active Low input that initializes the DM9101. It should 79 81 RESET# I remain low for 30ms after VCC has stabilized at 5Vdc (normal) before it transitions high. Test Mode Control Pin: 80 82 TESTMODE I TESTMODE=0: Normal operating mode. TESTMODE=1: Enable test mode. 10 Final Version: DM9101-DS-F03 July 22, 1999 DM9101 10/100Mbps Ethernet Physical Layer Single Chip Transceiver Pin Description (continued) Power and Ground Pins : The power (VCC) and ground (GND) pins of the DM9101 are grouped in pairs of two categories - Digital Circuitry Power/Ground Pairs and Analog Circuitry Power/Ground Pair. Pin No. Pin Name I/O Description LQFP QFP Group A - Digital Supply Pairs 35, 36, 37, 38, DGND P Digital Logic Ground. 37, 43, 39, 45, 50, 59, 52, 61, 65, 71, 67, 73, 84 86 Group A - Digital Supply Pairs (continued) 38, 47, 40, 49, DVCC P Digital Logic power supply 60, 72, 62, 74, 66, 85 68, 87 Group B - Analog Circuit Supply Pairs 4, 9, 6, 11, 12, AGND P Analog circuit ground 10, 15, 18, 17, 16, 21, 23, 24, 22, 29, 31, 34, 32, 97, 99, 100 98 5, 6, 1, 7, 8, AVCC P Analog circuit power supply 13, 14, 15, 16, 19, 20, 21, 22, 25, 26, 27, 28, 33 31, 99 Final Version: DM9101-DS-F03 July 22, 1999 11 DM9101 10/100Mbps Ethernet Physical Layer Single Chip Transceiver The DM9101 performs all PCS (Physical Coding Sublayer), PMA (Physical Media Access), TP-PMD (Twisted Pair Physical Medium Dependent) sublayer, 10Base-T Encoder/Decoder, and Twisted Pair Media Access Unit (TPMAU) functions. Figure 1 shows the major functional blocks implemented in the DM9101. Functional Description The DM9101 Fast Ethernet single-chip transceiver, provides the functionality as specified in IEEE 802.3u, integrates a complete 100Base-TX module and a complete 10Base-T module. The DM9101 provides a Media Independent Interface (MII) as defined in the IEEE 802.3u standard (Clause 22). 100Base-TX Transmitter 100Base-TX Receiver 10Base-T Tranceiver MII Interface Carrier Sense Collision Detection Auto Negotiation MII Serial Management Interface Figure 1 MII Interface The DM 9101 provides a Media Independent Interface (MII) as defined in the IEEE 802.3u standard (Clause 22). The purpose of the MII interface is to provide a simple, easy to implement connection between the MAC Reconciliation layer and the PHY. The MII is designed to make the differences between various media transparent to the MAC sublayer. The MII consists of a nibble wide receive data bus, a nibble wide transmit data bus, and control signals to facilitate data transfers between the PHY and the Reconciliation layer. 12 • TXD (transmit data) is a nibble (4 bits) of data that are driven by the reconciliation sublayer synchronously with respect to TX_CLK. For each TX_CLK period which TX_EN is asserted, TXD (3:0) are accepted for transmission by the PHY. • TX_CLK (transmit clock) output to the MAC reconciliation sublayer is a continuous clock that provides the timing reference for the transfer of the TX_EN, TXD, and TX_ER signals. • TX_EN (transmit enable) input from the MAC reconciliation sublayer to indicate nibbles are being presented on the MII for transmission on the physical medium. Final Version: DM9101-DS-F03 July 22, 1999 DM9101 10/100Mbps Ethernet Physical Layer Single Chip Transceiver • MII Interface (continued) • TX_ER (transmit coding error) transitions synchronously with respect to TX_CLK. If TX_ER is asserted for one or more clock periods, and TX_EN is asserted, the PHY will emit one or more symbols that are not part of the valid data delimiter set somewhere in the frame being transmitted. • RXD (receive data) is a nibble (4 bits) of data that are sampled by the reconciliation sublayer synchronously with respect to RX_CLK. For each RX_CLK period which RX_DV is asserted, RXD (3:0) are transferred from the PHY to the MAC reconciliation sublayer. • RX_CLK (receive clock) output to the MAC reconciliation sublayer is a continuous clock that provides the timing reference for the transfer of the RX_DV, RXD, and RX_ER signals. TXD IDLE SSD J/K Preamble CRS RX_DV (receive data valid) input from the PHY to indicate the PHY is presenting recovered and decoded nibbles to the MAC reconciliation sublayer. To interpret a receive frame correctly by the reconciliation sublayer, RX_DV must encompass the frame starting no later than the Start-of-Frame delimiter and excluding any End-Stream delimiter. • RX_ER (receive error) transitions synchronously with respect to RX_CLK. RX_ER will be asserted for 1 or more clock periods to indicate to the reconciliation sublayer that an error was detected somewhere in the frame being transmitted from the PHY to the reconciliation sublayer. • CRS (carrier sense) is asserted by the PHY when either the transmit or receive medium is non-idle and deasserted by the PHY when the transmit and receive medium are idle. Figure 2 depicts the behavior of CRS during 10Base-T and 100Base-TX transmission. SFD Data ESD T/R IDLE 100Base-TX CRS TXD • Preamble Data SFD EFD 10Base-T Figure 2 Final Version: DM9101-DS-F03 July 22, 1999 13 DM9101 10/100Mbps Ethernet Physical Layer Single Chip Transceiver 100Base-TX Operation The 100Base-TX transmitter receives 4-bit nibble data clocked in at 25MHz at the MII, and outputs a scrambled 5-bit encoded MLT-3 signal to the media at 100Mbps. The on-chip clock circuit converts the 25MHz clock into a 125MHz clock for internal use. The IEEE 802.3u specification defines the Media Independent Interface. The interface specification defines a dedicated receive data bus and a dedicated transmit data bus. These two busses include various controls and signal indications that facilitate data transfers between the DM9101 and the Reconciliation layer. 100Base-TX Transmit The 100Base-TX transmitter consists of the functional blocks shown in figure 3. The 100Base-TX transmit section converts 4-bit synchronous data provided by the MII to a scrambled MLT-3 125 million symbols per second serial data stream. 25M OSCI LED1-4# LED Driver TX CGM TXCLK 4B/5B Encoder Scrambler Parallel to Serial NRZ to NRZI NRZI to MLT-3 MLT-3 Driver 100TXD+/- TXEN Transmit MII Interface/ Control Rise/Fall Time CTL TXER 10BASE-T Module RX RXI+/- TX 10TXD+/- TXD (3:0 Register Collision Detection Carrier Sense Figure 3 14 Final Version: DM9101-DS-F03 July 22, 1999 DM9101 10/100Mbps Ethernet Physical Layer Single Chip Transceiver 100Base-TX Operation The block diagram in figure 3 provides an overview of the functional blocks contained in the transmit section. The transmitter section contains the following functional blocks: - 4B5B Encoder - Scrambler - Parallel to Serial Converter - NRZ to NRZI Converter - NRZI to MLT-3 - MLT-3 Driver 4B5B Encoder The 4B5B encoder converts 4-bit (4B) nibble data generated by the MAC Reconciliation Layer into a 5-bit (5B) code group for transmission, reference Table 1. This conversion is required for control and packet data to be combined in code groups. The 4B5B encoder substitutes the first 8 bits of the MAC preamble with a J/K code-group pair (11000 10001) upon transmit. The 4B5B encoder continues to replace subsequent 4B preamble and data nibbles with corresponding 5B code-groups. At the end of the transmit packet, upon the deassertion of the Transmit Enable signal from the MAC Reconciliation layer, the 4B5B encoder injects the T/R code-group pair (01101 00111) indicating end of frame. After the T/R code-group pair, the 4B5B encoder continuously injects IDLEs into the transmit data stream until Transmit Enable is asserted and the next transmit packet is detected. The DM9101 includes a Bypass 4B5B conversion option within the 100Base-TX Transmitter for support of applications like 100 Mbps repeaters which do not require 4B5B conversion. Scrambler The scrambler is required to control the radiated emissions (EMI) by spreading the transmit energy across the frequency spectrum at the media connector and on the twisted pair cable in 100Base-TX operation. Final Version: DM9101-DS-F03 July 22, 1999 By scrambling the data, the total energy presented to the cable is randomly distributed over a wide frequency range. Without the scrambler, energy levels on the cable could peak beyond FCC limitations at frequencies related to repeated 5B sequences like continuous transmission of IDLE symbols. The scrambler output is combined with the NRZ 5B data from the code-group encoder via an XOR logic function. The result is a scrambled data stream with sufficient randomization to decrease radiated emissions at critical frequencies. Parallel to Serial Converter The Parallel to Serial Converter receives parallel 5B scrambled data from the scrambler and serializes it (converts it from a parallel to a serial data stream). The serialized data stream is then presented to the NRZ to NRZI Encoder block NRZ to NRZI Encoder After the transmit data stream has been scrambled and serialized, the data must be NRZI encoded for compatibility with the TP-PMD standard for 100Base-TX transmission over Category-5 unshielded twisted pair cable. MLT-3 Converter The MLT-3 conversion is accomplished by converting the data stream output from the NRZI encoder into two binary data streams with alternately phased logic one events. MLT-3 Driver The two binary data streams created at the MLT-3 converter are fed to the twisted pair output driver which converts these streams to current sources and alternately drives either side of the transmit transformer primary winding resulting in a minimal current MLT-3 signal. Refer to figure 4 for the block diagram of the MLT-3 converter. 15 DM9101 10/100Mbps Ethernet Physical Layer Single Chip Transceiver 4B5B Code Group Symbol Meaning Data 0 Data 1 Data 2 Data 3 Data 4 Data 5 Data 6 Data 7 Data 8 Data 9 Data A Data B Data C Data D Data E Data F 4B code 3210 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 5B Code 43210 11110 01001 10100 10101 01010 01011 01110 01111 10010 10011 10110 10111 11010 11011 11100 11101 0 1 2 3 4 5 6 7 8 9 A B C D E F I J K T R H Idle SFD (1) SFD (2) ESD (1) ESD (2) Error undefined 0101 0101 undefined undefined undefined 11111 11000 10001 01101 00111 00100 V V V V V V V V V V Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid undefined undefined undefined undefined undefined undefined undefined undefined undefined undefined 00000 00001 00010 00011 00101 00110 01000 01100 10000 11001 Table 1 16 Final Version: DM9101-DS-F03 July 22, 1999 DM9101 10/100Mbps Ethernet Physical Layer Single Chip Transceiver D Q CK Binary In Q . . Binary plus Common driver MLT-3 Binary minus Binary In MLT-3 Figure 4 100Base-TX Receiver Digital Adaptive Equalization The 100Base-TX receiver contains several function blocks that convert the scrambled 125Mb/s serial data to synchronous 4-bit nibble data that is then provided to the MII. The receive section contains the following functional blocks: When transmitting data at high speeds over copper twisted pair cable, attenuation based on frequency becomes a concern. In high speed twisted pair signaling, the frequency content of the transmitted signal can vary greatly during normal operation based on the randomness of the scrambled data stream. This variation in signal attenuation caused by frequency variations must be compensated for to ensure the integrity of the received data. In order to ensure quality transmission when employing MLT-3 encoding, the compensation must be able to adapt to various cable lengths and cable types depending on the installed environment. The selection of long cable lengths for a given implementation, requires significant compensation which will be over-kill in a situation that includes shorter, less attenuating cable lengths. Conversely, the selection of short or intermediate cable lengths requiring less compensation will cause serious under-compensation for longer length cables. Therefore, the compensation or equalization must be adaptive to ensure proper conditioning of the received signal independent of the cable length. - Signal Detect - Digital Adaptive Equalization - MLT-3 to Binary Decoder - Clock Recovery Module - NRZI to NRZ Decoder - Serial to Parallel - Descrambler - Code Group Alignment - 4B5B Decoder Signal Detect The signal detect function meets the specifications mandated by the ANSI XT12 TP-PMD 100Base-TX Standards for both voltage thresholds and timing parameters. MLT-3 to NRZI Decoder The DM9101 decodes the MLT-3 information from the Digital Adaptive Equalizer into NRZI data. The relationship between NRZI and MLT-3 data is shown in figure 4. Final Version: DM9101-DS-F03 July 22, 1999 17 DM9101 10/100Mbps Ethernet Physical Layer Single Chip Transceiver Clock Recovery Module The Clock Recovery Module accepts NRZI data from the MLT-3 to NRZI decoder. The Clock Recovery Module locks onto the data stream and extracts the 125Mhz reference clock. The extracted and synchronized clock and data are presented to the NRZI to NRZ Decoder. NRZI to NRZ The transmit data stream is required to be NRZI encoded in for compatibility with the TP-PMD standard for 100Base-TX transmission over Category-5 unshielded twisted pair cable. This conversion process must be reversed on the receive end. The NRZI to NRZ decoder, receives the NRZI data stream from the Clock Recovery Module and converts it to a NRZ data stream to be presented to the Serial to Parallel conversion block. Serial to Parallel The Serial to Parallel Converter receives a serial data stream from the NRZI to NRZ converter, and converts the data stream to parallel data to be presented to the descrambler. Descrambler Because of the scrambling process required to control the radiated emissions of transmit data streams, the receiver must descramble the receive data streams. The descrambler receives scrambled parallel data streams from the Serial to Parallel converter, descrambles the data streams, and presents the data streams to the Code Group alignment block. Code Group Alignment The Code Group Alignment block receives unaligned 5B data from the descrambler and converts it into 5B code group data. Code Group Alignment occurs after the J/K is detected, and subsequent data is aligned on a fixed boundary. 4B5B Decoder The 4B5B Decoder functions as a look-up table that translates incoming 5B code groups into 4B (Nibble) data. When receiving a frame, the first 2 5-bit code groups received are the start-of-frame delimiter (J/K symbols). The J/K symbol pair is stripped and two nibbles of preamble pattern are substituted. The last two code groups are the end-of-frame delimiter (T/R symbols). 18 The T/R symbol pair is also stripped from the nibble presented to the Reconciliation layer. 10Base-T Operation The 10Base-T transceiver is IEEE 802.3u compliant. When the DM9101 is operating in 10Base-T mode, the coding scheme is Manchester. Data processed for transmit is presented to the MII interface in nibble format, converted to a serial bit stream, then Manchester encoded. When receiving, the Manchester encoded bit stream is decoded and converted into nibble format for presentation to the MII interface. Collision Detection For half-duplex operation, a collision is detected when the transmit and receive channels are active simultaneously. When a collision has been detected, it will be reported by the COL signal on the MII interface. Collision detection is disabled in Full Duplex operation. Carrier Sense Carrier Sense (CRS) is asserted in half-duplex operation during transmission or reception of data. During full-duplex mode, CRS is asserted only during receive operations. Auto-Negotiation The objective of Auto-negotiation is to provide a means to exchange information between segment linked devices and to automatically configure both devices to take maximum advantage of their abilities. It is important to note that Auto-negotiation does not test the link segment characteristics. The Auto-Negotiation function provides a means for a device to advertise supported modes of operation to a remote link partner, acknowledge the receipt and understanding of common modes of operation, and to reject un-shared modes of operation. This allows devices on both ends of a segment to establish a link at the best common mode of operation. If more than one common mode exists between the two devices, a mechanism is provided to allow the devices to resolve to a single mode of operation using a predetermined priority resolution function. Final Version: DM9101-DS-F03 July 22, 1999 DM9101 10/100Mbps Ethernet Physical Layer Single Chip Transceiver Auto-Negotiation (continued) In read/write operation, the management data frame is 64-bits long and starts with 32 contiguous logic one bits (preamble) synchronization clock cycles on MDC. The Start of Frame Delimiter (SFD) is indicated by a <01> pattern followed by the operation code (OP):<10> indicates Read operation and <01> indicates Write operation. For read operation, a 2-bit turnaround (TA) filing between Register Address field and Data field is provided for MDIO to avoid contention. Following the turnaround time, 16-bit data is read from or written onto management registers. Auto-negotiation also provides a parallel detection function for devices that do not support the Autonegotiation feature. During Parallel detection there is no exchange of configuration information, instead, the receive signal is examined. If it is discovered that the signal matches a technology that the receiving device supports, a connection will be automatically established using that technology. This allows devices that do not support Autonegotiation but support a common mode of operation to establish a link. MII Serial Management Serial Management Interface The MII serial management interface consists of a data interface, basic register set, and a serial management interface to the register set. Through this interface it is possible to control and configure multiple PHY devices, get status and error information, and determine the type and capabilities of the attached PHY device(s). The DM9101 management functions correspond to MII specification for IEEE 802.3u-1995 (Clause 22) for registers 0 through 6 with vendor-specific registers 16,17, and 18. The serial control interface uses a simple two-wired serial interface to obtain and control the status of the physical layer through the MII interface. The serial control interface consists of MDC (Management Data Clock), and MDI/O (Management Data Input/Output) signals. The MDIO pin is bi-directional and may be shared by up to 32 devices. Management Interface - Read Frame Structure MDC MDIO Read 32 "1"s Idle 0 Preamble 1 SFD 1 0 A4 Op Code A3 A0 PHY Address R4 R3 R0 Register Address // // 0 Z D15 D14 D1 Turn Around D0 Data Read Write Idle Management Interface - Write Frame Structure MDC MDIO Write 32 "1"s Idle Preamble 0 1 SFD 0 Op Code 1 A4 A3 PHY Address A0 R4 R3 Register Address Write R0 1 0 Turn Around D15 D14 D1 Data D0 Idle Figure 5 Final Version: DM9101-DS-F03 July 22, 1999 19 DM9101 10/100Mbps Ethernet Physical Layer Single Chip Transceiver Register Description Register Address 0 1 2 3 4 5 6 16 17 18 Others Register Name BMCR BMSR PHYIDR1 PHYIDR2 ANAR ANLPAR ANER DSCR DSCSR 10BTCSR Reserved Description Basic Mode Control Register Basic Mode Status Register PHY Identifier Register #1 PHY Identifier Register #2 Auto-Negotiation Advertisement Register Auto-Negotiation Link Partner Ability Register Auto-Negotiation Expansion Register DAVICOM Specified Configuration Register DAVICOM Specified Configuration/Status Register 10Base-T Configuration/Status Register Reserved For Future Use-Do Not Read/Write To These Registers Key to Default In the register description that follows, the default column takes the form: <Reset Value>, <Access Type> / <Attribute(s)> Where <Reset Value>: 1 0 X (PIN#) Bit set to logic one Bit set to logic zero No default value Value latched in from pin # at reset <Access Type>: RO = Read only RW = Read/Write <Attribute (s)>: SC = Self clearing P = Value permanently set LL = Latching low LH = Latching high 20 Final Version: DM9101-DS-F03 July 22, 1999 DM9101 10/100Mbps Ethernet Physical Layer Single Chip Transceiver Basic Mode Control Register (BMCR) - Register 0 Bit 0.15 Bit Name Reset Default 0, RW/SC 0.14 Loopback 0, RW 0.13 Speed Selection 1, RW 0.12 Auto-negotiation Enable 1, RW 0.11 Power Down 0, RW 0.10 Isolate (PHYAD= 00000), RW Final Version: DM9101-DS-F03 July 22, 1999 Description Reset: 1=Software reset 0=Normal operation When set this bit configures the PHY status and control registers to their default states. This bit will return a value of one until the reset process is complete Loopback: Loopback control register 1=Loopback enabled 0=Normal operation When in 100M operation is selected, setting this bit will cause the descrambler to lose synchronization. A 720ms "dead time" will occur before any valid data appears at the MII receive outputs Speed Select: 1=100Mbps 0=10Mbps Link speed may be selected either by this bit or by Autonegotiation if bit 12 of this register is set. When Autonegotiation is enabled, this bit will return Auto-negotiation link speed. Auto-negotiation Enable: 1= Auto-negotiation enabled: 0= Auto-negotiation disabled: When auto-negotiation is enabled bits 8 and 13 will contain the Auto-negotiation results. When Auto-negotiation is disabled bits 8 and 13 will determine the duplex mode and link speed Power Down: 1=Power Down 0=Normal Operation Setting this bit will power down the DM9101 with the exception of the crystal oscillator circuit Isolate: 1= Isolate 0= Normal Operation When this bit is set the data path will be isolated from the MII interface. TX_CLK, RX_CLK, RX_DV, RX_ER, RXD[3:0], COL and CRS will be placed in a high impedance state. The management interface is not effected by this bit. When the PHY Address is set to 00000 the isolate bit will be set upon power-up/reset 21 DM9101 10/100Mbps Ethernet Physical Layer Single Chip Transceiver Basic Mode Control Register (BMCR) - Register 0 (continued) Bit 0.9 Bit Name Restart Autonegotiation Default 0,RW/SC 0.8 Duplex Mode 1,RW 0.7 Collision Test 0,RW 0.6 Reserved 0,RO Description Restart Auto-negotiation: 1= Restart Auto-negotiation. 0= Normal Operation When this bit is set the Auto-negotiation process is re-initiated. When Auto-negotiation is disabled (bit 12 of this register cleared), this bit has no function and it should be cleared. This bit is self-clearing and will return a value of 1 until Autonegotiation is initiated. The operation of the Auto-negotiation process will not be affected by the management entity that clears this bit Duplex Mode: 1= Full Duplex operation. 0= Normal operation If Auto-negotiation is disabled, setting this bit will cause the DM9101 to operate in full duplex mode. When Auto-negotiation is enabled, this bit reflects the duplex selected by Autonegotiation Collision Test: 1= Collision Test enabled. 0= Normal Operation When set, this bit will cause the COL signal to be asserted in response to the assertion of TX_EN Reserved: Write as 0, ignore on read Basic Mode Status Register (BMSR) - Register 1 Bit 1.15 Bit Name 100Base-T4 Default 0,RO/P 1.14 100Base-TX Full Duplex 1,RO/P 1.13 100Base-TX Half Duplex 1,RO/P 1.12 10Base-T Full Duplex 1,RO/P 1.11 10Base-T Half Duplex 1,RO/P 1.10-1.7 Reserved 0,RO 22 Description 100Base-T4 Capable: 1=DM9101 is able to perform in 100Base-T4 mode 0=DM9101 is not able to perform in 100Base-T4 mode 100Base-TX Full Duplex Capable: 1= DM9101 is able to perform 100Base-TX in Full Duplex mode 0= DM9101 is not able to perform 100Base-TX in Full Duplex mode 100Base-TX Half Duplex Capable: 1=DM9101 is able to perform 100Base-TX in Half Duplex mode 0=DM9101 is not able to perform 100Base-TX in Half Duplex mode 10Base-T Full Duplex Capable: 1=DM9101 is able to perform 10Base-T in Full Duplex mode 0=DM9101 is not able to perform 10Base-T in Full Duplex mode 10Base-T Half Duplex Capable: 1=DM9101 is able to perform 10Base-T in Half Duplex mode 0=DM9101 is not able to perform 10Base-T in Half Duplex mode. Reserved: Write as 0, ignore on read Final Version: DM9101-DS-F03 July 22, 1999 DM9101 10/100Mbps Ethernet Physical Layer Single Chip Transceiver Basic Mode Status Register (BMSR) - Register 1 (continued) Bit 1.6 Bit Name MF Preamble Suppression Default 0,RO 1.5 Auto-negotiation Complete 0,RO 1.4 Remote Fault 0, RO/LH 1.3 Auto-negotiation Ability 1,RO/P 1.2 Link Status 0,RO/LL 1.1 Jabber Detect 0, RO/LH 1.0 Extended Capability 1,RO/P Description MII Frame Preamble Suppression: 1=PHY will accept management frames with preamble suppressed 0=PHY will not accept management frames with preamble suppressed Auto-negotiation Complete: 1=Auto-negotiation process completed 0=Auto-negotiation process not completed Remote Fault: 1= Remote fault condition detected (cleared on read or by a chip reset). Fault criteria and detection method is DM9101 implementation specific. This bit will set after the RF bit in the ANLPAR (bit 13, register address 05) is set 0= No remote fault condition detected Auto Configuration Ability: 1=DM9101 able to perform Auto-negotiation 0=DM9101 not able to perform Auto-negotiation Link Status: 1=Valid link established (for either 10Mbps or 100Mbps operation) 0=Link not established The link status bit is implemented with a latching function, so that the occurrence of a link failure condition causes the Link Status bit to be cleared and remain cleared until it is read via the management interface Jabber Detect: 1=Jabber condition detected 0=No jabber condition detected This bit is implemented with a latching function. Once Jabber conditions are detected this bit will remain set until a read operation is completed through a management interface or a DM9101 reset. This bit works only in 10Mbps mode Extended Capability: 1=Extended register capable 0=Basic register capable only PHY ID Identifier Register #1 (PHYIDR1) - Register 2 The PHY Identifier Registers #1 and #2 work together in a single identifier of the DM9101. The Identifier consists of a concatenation of the Organizationally Unique Identifier (OUI), a vendor's model number, and a model revision number. DAVICOM Semiconductor's IEEE assigned OUI is 00606E. Bit 2.15-2.0 Bit Name OUI_MSB Final Version: DM9101-DS-F03 July 22, 1999 Default <0181H> Description OUI Most Significant Bits: This register stores bits 3 - 18 of the OUI (00606E) to bits 15 0 of this register respectively. The most significant two bits of the OUI are ignored (the IEEE standard refers to these as bit 1 and 2) 23 DM9101 10/100Mbps Ethernet Physical Layer Single Chip Transceiver PHY Identifier Register #2 (PHYIDR2) - Register 3 Bit 3.15-3.10 Bit Name OUI_LSB Default <101110>,RO/P 3.9-3.4 VNDR_MDL <000000>,RO/P 3.3-3.0 MDL_REV <0010>,RO/P Description OUI Least Significant Bits: Bits 19 - 24 of the OUI (00606E) are mapped to bits 15 - 10 of this register respectively Vendor Model Number: Six bits of the vendor model number mapped to bits 9 - 4 (most significant bit to bit 9) Model Revision Number: Four bits of the vendor model revision number mapped to bits 3 - 0 (most significant bit to bit 3) Auto-negotiation Advertisement Register (ANAR) - Register 4 This register contains the advertised abilities of the DM9101 device as they will be transmitted to link partners during Autonegotiation. Bit 4.15 Bit Name NP Default 0,RO/P 4.14 ACK 0,RO 4.13 RF 0, RW 4.12-4.11 Reserved X, RW 4.10 FCS 0, RW 4.9 T4 0, RO/P 4.8 TX_FDX 1, RW 4.7 TX_HDX 1, RW 24 Description Next Page Indication: 0=No next page available 1=Next page available The DM9101 does not support the next page function. This bit is permanently set to 0 Acknowledge: 1=Link partner ability data reception acknowledged 0=Not acknowledged The DM9101's Auto-negotiation state machine will automatically control this bit in the outgoing FLP bursts and set it at the appropriate time during the Auto-negotiation process. Software should not attempt to write to this bit. Remote Fault: 1=Local Device senses a fault condition 0=No fault detected Reserved: Write as 0, ignore on read Flow Control Support: 1=Controller chip supports flow control ability 0=Controller chip doesn’t support flow control ability 100Base-T4 Support: 1=100Base-T4 supported by the local device 0=100Base-T4 not supported The DM9101 does not support 100Base-T4 so this bit is permanently set to 0 100Base-TX Full Duplex Support: 1=100Base-TX Full Duplex supported by the local device 0=100Base-TX Full Duplex not supported 100Base-TX Support: 1=100Base-TX supported by the local device 0=100Base-TX not supported Final Version: DM9101-DS-F03 July 22, 1999 DM9101 10/100Mbps Ethernet Physical Layer Single Chip Transceiver Auto-negotiation Advertisement Register (ANAR) - Register 4 (continued) Bit 4.6 Bit Name 10_FDX Default 1, RW 4.5 10_HDX 1, RW 4.4-4.0 Selector <00001>, RW Description 10Base-T Full Duplex Support: 1=10Base-T Full Duplex supported by the local device 0=10Base-T Full Duplex not supported 10Base-T Support: 1=10Base-T supported by the local device 0=10Base-T not supported Protocol Selection Bits: These bits contain the binary encoded protocol selector supported by this node. <00001> indicates that this device supports IEEE 802.3 CSMA/CD. Auto-negotiation Link Partner Ability Register (ANLPAR) - Register 5 This register contains the advertised abilities of the link partner as they are received during Auto-negotiation. Bit 5.15 Bit Name NP Default 0, RO 5.14 ACK 0, RO 5.13 RF 0, RO 5.12-5.10 Reserved X, RO 5.9 T4 0, RO 5.8 TX_FDX 0, RO 5.7 TX_HDX 0, RO 5.6 10_FDX 0, RO 5.5 10_HDX 0, RO 5.4-5.0 Selector <00000>, RO Final Version: DM9101-DS-F03 July 22, 1999 Description Next Page Indication: 0= Link partner, no next page available 1= Link partner, next page available Acknowledge: 1=Link partner ability data reception acknowledged 0=Not acknowledged The DM9101's Auto-negotiation state machine will automatically control this bit from the incoming FLP bursts. Software should not attempt to write to this bit. Remote Fault: 1=Remote fault indicated by link partner 0=No remote fault indicated by link partner Reserved: Write as 0, ignore on read 100Base-T4 Support: 1=100Base-T4 supported by the link partner 0=100Base-T4 not supported by the link partner 100Base-TX Full Duplex Support: 1=100Base-TX Full Duplex supported by the link partner 0=100Base-TX Full Duplex not supported by the link partner 100Base-TX Support: 1=100Base-TX Half Duplex supported by the link partner 0=100Base-TX Half Duplex not supported by the link partner 10Base-T Full Duplex Support: 1=10Base-T Full Duplex supported by the link partner 0=10Base-T Full Duplex not supported by the link partner 10Base-T Support: 1=10Base-T Half Duplex supported by the link partner 0=10Base-T Half Duplex not supported by the link partner Protocol Selection Bits: Link partner binary encoded protocol selector 25 DM9101 10/100Mbps Ethernet Physical Layer Single Chip Transceiver Auto-negotiation Expansion Register (ANER) - Register 6 Bit 6.15-6.5 Bit Name Reserved Default X, RO 6.4 PDF 0, RO/LH 6.3 LP_NP_ABLE 0, RO 6.2 NP_ABLE 0,RO/P 6.1 PAGE_RX 0, RO/LH 6.0 LP_AN_ABLE 0, RO Description Reserved: Write as 0, ignore on read Local Device Parallel Detection Fault: PDF=1: A fault detected via parallel detection function. PDF=0: No fault detected via parallel detection function Link Partner Next Page Able: LP_NP_ABLE=1: Link partner, next page available LP_NP_ABLE=0: Link partner, no next page Local Device Next Page Able: NP_ABLE=1: DM9101, next page available NP_ABLE=0: DM9101, no next page DM9101 does not support this function, so this bit is always 0. New Page Received: A new link code word page received. This bit will be automatically cleared when the register (Register 6) is read by management. Link Partner Auto-negotiation Able: LP_AN_ABLE=1 indicates that the link partner supports Autonegotiation. DAVICOM Specified Configuration Register (DSCR) - Register 16 26 Bit 16.15 Bit Name BP_4B5B Default Pin96, RW 16.14 BP_SCR Pin97, RW 16.13 BP_ALIGN Pin95, RW 16.12 Reserved 0, RW Description Bypass 4B5B Encoding and 5B4B Decoding: 1=4B5B encoder and 5B4B decoder function bypassed 0=Normal 4B5B and 5B4B operation The value of the pin is latched into this bit at power-up/reset. Bypass Scrambler/Descrambler Function: 1=Scrambler and descrambler function bypassed 0=Normal scrambler and descrambler operation The value of the input pin is latched into this bit at powerup/reset. Bypass Symbol Alignment Function: 1= Receive functions (descrambler, symbol alignment and symbol decoding functions) bypassed. Transmit functions (symbol encoder and scrambler) bypassed 0= Normal operation The value of the BPALIGN input pin is latched into this bit at power-up/reset. Reserved: This bit must be set as 0. Final Version: DM9101-DS-F03 July 22, 1999 DM9101 10/100Mbps Ethernet Physical Layer Single Chip Transceiver DAVICOM Specified Configuration Register (DSCR) - Register 16 (continued) Bit 16.11 Bit Name REPEATER Default 0, RW 16.10 TX 1, RW 16.9 UTP 1, RW 16.8 CLK25MDIS 0, RW 16.7 F_LINK_100 0, RW 16.6 16.5 Reserved LINKLED_CTL 1, RW 0, RW 16.4 FDXLED_MODE 0, RW 16.3 SMRST 0, RW 16.2 MFPSC 0, RW Final Version: DM9101-DS-F03 July 22, 1999 Description Repeater/Node Mode: 1=Repeater mode 0=Node mode In Repeater mode, the Carrier Sense (CRS) output from the DM9101 will be asserted only by receive activity. In NODE mode, or a mode not configured for Full Duplex operation, CRS will be asserted by either receive or transmit activity. The value of the RPTR/NODE input pin is latched into this bit at power-up reset. 100Base-TX or FX Mode Control: 1=100Base-TX operation 0=100Base-FX operation UTP Cable Control: 1=The media is a UTP cable, 0=STP CLK25M Disable: 1=CLK25M output clock signal tri-stated 0=CLK25M enabled This bit should be set to 1 to disable the 25Mhz output and reduce ground bounce and power consumption. For applications requiring the CLK25M output, set this bit to 0. Force Good Link in 100Mbps: 0=Normal 100Mbps operation 1=Force 100Mbps good link status This bit is useful for diagnostic purposes. Reserved: LINKLED Mode Select: 0= Link LED output configured to indicate link status only 1= Link LED output configured to indicate traffic status: When the link status is OK, the LED will be on. When the chip is in transmitting or receiving, it flashes. FDXLED Mode Select: 1= FDXLED output configured to indicate polarity in 10Base-T mode 0= FDXLED output configured to indicate Full Duplex mode status for 10Mbps and 100Mbps operation Reset State Machine: When this bit is set to 1, all state internal machines will be reset. This bit will clear after reset is completed. MF Preamble Suppression Control: 1= MF preamble suppression on 0= MF preamble suppression off MII frame preamble suppression control bit 27 DM9101 10/100Mbps Ethernet Physical Layer Single Chip Transceiver DAVICOM Specified Configuration Register (DSCR) - Register 16 (continued) Bit 16.1 Bit Name SLEEP Default 0, RW Description Sleep Mode: Writing a 1 to this bit will cause DM9101 to enter Sleep mode and power down all circuits except the oscillator and clock generator circuit. To exit Sleep mode, write 0 to this bit position. The prior configuration will be retained when the sleep state is terminated, but the state machine will be reset 16.0 RLOUT 0, RW Remote Loopout Control: When this bit is set to 1, the received data will loop out to the transmit channel. This is useful for bit error rate testing DAVICOM Specified Configuration and Status Register (DSCSR) - Register 17 Bit 17.15 Bit Name 100FDX Default 1, RO 17.14 100HDX 1, RO 17.13 10FDX 1, RO 17.12 10HDX 1, RO 17.1117.10 17.8-17.4 Reserved 0, RW PHYAD[4:0] (PHYAD), RW 28 Description 100M Full Duplex Operation: After Auto-negotiation is completed, the results will be written to this bit. A “1” in this bit position indicates 100M Full Duplex operation. The software can read bits [15:12] to determine which mode is selected after Auto-negotiation. This bit is invalid when Auto-negotiation is disabled. 100M Half Duplex Operation: After Auto-negotiation is completed, the results will be written to this bit. A “1” in this bit position indicates 100M Half Duplex operation. The software can read bits [15:12] to determine which mode is selected after Auto-negotiation. This bit is invalid when Auto-negotiation is disabled. 10M Full Duplex Operation: After Auto-negotiation is completed, the results will be written to this bit. A “1” in this bit position indicates 10M Full Duplex operation. The software can read bits [15:12] to determine which mode is selected after Auto-negotiation. This bit is invalid when Auto-negotiation is disabled. 10M Half Duplex Operation: After Auto-negotiation is completed, the results will be written to this bit. A “1” in this bit position indicates 10M Half Duplex operation. The software can read bits [15:12] to determine which mode is selected after Auto-negotiation. This bit is invalid when Auto-negotiation is disabled. Reserved: Write as 0, ignore on read PHY Address Bit 4:0: The values of the PHYAD[4:0] pins are latched to this register at power-up/reset. The first PHY address bit transmitted or received is the MSB (bit 4). A station management entity connected to multiple PHY entities must know the appropriate address of each PHY. A PHY address of <00000> will cause the isolate bit of the BMCR (bit 10, Register Address 00) to be set. Final Version: DM9101-DS-F03 July 22, 1999 DM9101 10/100Mbps Ethernet Physical Layer Single Chip Transceiver DAVICOM Specified Configuration and Status Register (DSCSR) - Register 17 (continued) Bit 17.3-17.0 Bit Name ANMB[3:0] Default 0, RO Description Auto-negotiation Monitor Bits: These bits are for debug only. The Auto-negotiation status will be written to these bits. b3 b2 b1 b0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 In IDLE state Ability match Acknowledge match Acknowledge match fail Consistency match Consistency match fail Parallel detect signal_link_ready Parallel detect signal_link_ready fail Auto-negotiation completed successfully 10Base-T Configuration/Status (10BTCSRCSR) - Register 18 Bit 18.15 Bit Name Reserved Default 0, RO 18.14 LP_EN 1, RW 18.13 HBE (inverse Pin94),RW 18.12 Reserved 0, RO 18.11 JABEN 1, RW 18.10 10BT_SER Pin98, RW 18.9-18.1 Reserved 0, RO Final Version: DM9101-DS-F03 July 22, 1999 Description Reserved: Write as 0, ignore on read Link Pulse Enable: 1=Transmission of link pulses enabled 0=Link pulses disabled, good link condition forced This bit is valid only in 10Mbps operation. Heartbeat Enable: 1=Heartbeat function enabled 0=Heartbeat function disabled When the DM9101 is configured for Full Duplex operation, this bit will be ignored (the collision/heartbeat function is invalid in Full Duplex mode). The initial state of this bit is the inverse value of RPTR/NODE input pin at power on reset. Reserved: Write as 0, ignore on read Jabber Enable: 1= Jabber function enabled 0= Jabber function disabled Enables or disables the Jabber function when the DM9101 is in 10Base-T Full Duplex or 10Base-T Transceiver Loop-back mode 10Base-T Serial Mode: 1=10Base-T serial mode selected 0=10Base-T nibble mode selected The value on the 10BTSER input pin is latched into this bit at power-up/reset Serial mode not supported for 100Mbps operation. Reserved: Write as 0, ignore on read 29 DM9101 10/100Mbps Ethernet Physical Layer Single Chip Transceiver 10Base-T Configuration/Status (10BTCSRCSR) - Register 18 (continued) Bit 18.0 Bit Name POLR Default 0, RO Description Polarity Reversed: When this bit is set to 1, it indicates that the 10M cable polarity is reversed. This bit is set and cleared by 10Base-T module automatically. Absolute Maximum Ratings* Power Consumption: (continued) Operating Voltage (VCC) 4.75V to 5.25V Non-Operating Voltage (VCC) -0.5V to 7.00V DC Input Voltage (VIN) -0.5V to VCC +0.5V DC Output Voltage (VOUT) -0.5V to VCC +0.5V Storage Temperature Range (Tstg)-65 to +150 Operating Ambient Temperature Range 0 to 70 Lead Temp (TL) (Soldering 10 sec.) 235 ESD rating (Rzap=1.5K, Czap=100pF) 4000V Power Consumption: 100Base-TX Full Duplex 185 mA (Measured using Unscrambled IDLE transmission looped back to RXIN, includes external termination circuitry) 10Base-T Full Duplex 222 mA (Measured using Maximum packet size, minimum I.P.G. transmission looped back to RXIN, includes external termination circuitry). 30 Auto-Negotiation 165mA (Measured during Parallel Detect until link established) Idle 120mA (Measured with no link established) Power Down Mode 40mA (Measured while MII Register 0 Bit 11 set true) *Comments Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only. Functional operation of this device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Final Version: DM9101-DS-F03 July 22, 1999 DM9101 10/100Mbps Ethernet Physical Layer Single Chip Transceiver DC Electrical Characteristics (VCC = 5Vdc, ±5%, TA = 0 to 70, unless specified otherwise) Symbol I100TX Parameter Min. Typ. Max. Unit Conditions Supply Current 100Base-TX 180 185 mA Vcc = 5.0V active I10TTP Supply Current 10Base-TX active 120 mA Vcc = 5.0V (Random data, Random IPG and Random size) I10TWC Supply Current 10Base-TX active 220 mA Vcc = 5.0V (Max. Packet size, Min. IPG and Worst case data patern) IPDM Supply Current Power Down 40 mA Vcc = 5.0V Mode IAN Supply Current during Auto-Neg. 165 mA Vcc = 5.0V IRST Supply Current during Reset. 115 mA Vcc = 5.0V TTL Inputs (TXD0-TXD3, TX_CLK, MDIO, TX_EN, TX_DV, TX_ER, TESTMODE, PHYAD0-4, OPMODE0-4, RPTR, BPALIGN, BP4B5B, BPSCR, 10BTSER, RESET# ) VIL Input Low Voltage 0.8 V IIL = -400uA VIH Input High Voltage 2.0 V IIH = 100uA IIL Input Low Current -200 uA VIN = 0.4V IIH Input High Current 100 uA VIN = 2.7V MII TTL Outputs ( RXD0-3, RX_EN, RX_DV, RX_ER, CRS, COL, MDIO ) VOL Output Low Voltage 0.4 V IOL = 4mA VOH Output High Voltage 2.4 V IOH = -4mA Non-MII TTL Outputs (TXLED#, RXLED#, LINKLED#, COLLED#, FDXLED#, RX_LOCK) VOL Output Low Voltage 0.4 V IOL = 1mA VOH Output High Voltage 2.4 V IOH = -0.1mA Receiver VICM RXI+/RXI- Input Common-Mode 1.5 2.0 2.5 V 100 Ω Termination Across Voltage Transmitter ITD100 100TXO+/- 100Base-TX Mode 19 21 mA Differential Output Current ITD10 10TX+/- 10Base-T Differential 44 50 56 mA Output Current Final Version: DM9101-DS-F03 July 22, 1999 31 DM9101 10/100Mbps Ethernet Physical Layer Single Chip Transceiver AC Electrical Characteristics (Over full range of operating condition unless specified otherwise) Symbol Parameter Transmitter tTR/F 100TXO+/- Differential Rise/Fall Time tTM 100TXO+/- Differential Rise/Fall Time Mismatch tTDC 100TXO+/- Differential Output Duty Cycle Distortion tT/T 100TXO+/- Differential Output Peak-to-Peak Jitter XOST 100TXO+/- Differential Voltage Overshoot MII (Media-Independent Interface) XNTOL TX Input Clock Frequency Tolerance XBTOL TX Output Clock Frequency Tolerance tPWH OSC Pulse Width High tPWL OSC Pulse Width Low tRPWH RX_CLK Pulse Width High tRPWL RX_CLK Pulse Width Low 32 Min. Typ. Max. Unit 3.0 5.0 ns -0.5 0.5 ns -0.5 0.5 ns 300 ps 5 -100 14 14 14 14 Conditions +100 % ppm 25MHz Frequency ppm 25MHz Frequency ns ns ns ns Final Version: DM9101-DS-F03 July 22, 1999 DM9101 10/100Mbps Ethernet Physical Layer Single Chip Transceiver MII-100Base-TX Transmit Timing Diagram TX_CLK tT X h t T XS TXD [0:3], TX_EN, TX_ER t2 t1 CRS t T X r/f t T X pd 100TX+/- MII-100Base-TX Transmit Timing Parameters Max. Unit 11 Typ1. - - ns 0 - - ns - 4 - BT - 4 - BT - 8 - BT 3 4 5 ns Symbol Parameter Min. tTXs TXD[0:3], TX_EN, TX_ER Setup To TX_CLK High TXD[0:3], TX_EN, TX_ER Hold From TX_CLK High TX_EN Sampled To CRS Asserted TX_EN Sampled To CRS Deasserted TX_EN Sampled To TPO Out (Tx Latency) 100TX Driver Rise/Fall Time tTXh t1 t2 tTXpd tTXr/f (Half Duplex) Conditions 90% To 10%, Into 100ohm Differential 1. Typical values are at 25 and are for design aid only; not guaranteed and not subject to production testing. MII-100Base-TX Receive Timing Diagram RX_CLK t T X pd tR XS tR Xh RXD [0:3], RX_DV, RX_ER t1 CRS t2 t4 t3 RXI+/- t5 COL Final Version: DM9101-DS-F03 July 22, 1999 33 DM9101 10/100Mbps Ethernet Physical Layer Single Chip Transceiver MII-100Base-TX Receive Timing Parameter Symbol Parameter Min. Typ1. - tRXs Max. (Half Duplex) Conditions Unit RXD[0:3), RX_DV, RX_ER Setup 10 ns To RX_CLK High tRXh RXD[0:3], RX_DV, RX_ER Hold 10 ns From RX_CLK High tRXpd RXI In To RXD[0:3] Out (Rx 15 BT Latency) t1 CRS Asserted To RXD[0:3], 4 BT RX_DV, RX_ER t2 CRS De-asserted To RXD[0:3], 0 BT RX_DV, RX_ER t3 RXI In To CRS Asserted 10 14 BT t4 RXI Quiet To CRS De-asserted 14 18 BT t5 RXI In To COL De-Asserted 14 18 BT 1. Typical values are at 25and are for design aid only; not guaranteed and not subject to production testing. Auto-negotiation and Fast Link Pulse Timing Diagram Clock Pulse FAST LINK PULSES Data Pulse Clock Pulse t1 t2 t3 FLP Burst FLP Burst 10TX0+/t4 t5 Auto-negotiation and Fast Link Pulse Timing Parameters Symbol t1 t2 t3 t4 t5 - 34 Parameter Clock/Data Pulse Width Clock Pulse To Data Pulse Period Clock Pulse To Clock Pulse Period FLP Burst Width FLP Burst To FLP Burst Period Clock/Data Pulses Per Burst Min. - Typ. 100 62.5 Max. - Unit ns us - 125 - us 33 2 13.93 33 33 ms ms ea Conditions DATA = 1 Final Version: DM9101-DS-F03 July 22, 1999 DM9101 10/100Mbps Ethernet Physical Layer Single Chip Transceiver MII-10Base-T Nibble Transmit Timing Diagram TX_CLK tT X h tT XS TXD [0:3], TX_EN, TX_ER t2 t1 CRS t T X pd 10TX+/- MII-10Base-T Nibble Transmit Timing Parameters Symbol tTXs tTXh t1 t2 tTXpd Parameter TXD[0:3), TX_EN, TX_ER Setup To TX_CLK High TXD[0:3], TX_EN, TX_ER Hold From TX_CLK High TX_EN Sampled To CRS Asserted TX_EN Sampled To CRS Deasserted TX_EN Sampled To 10TXO Out (Tx Latency) Min. 11 Typ. - Max. - Unit ns 0 - - ns - 2 4 BT - 15 20 BT - 2 4 BT Conditions MII-10Base-T Receive Nibble Timing Diagram RX_CLK t T X pd tR XS tR Xh RXD [0:3], RX_DV, RX_ER t1 t2 t4 CRS t3 RXI+/- Final Version: DM9101-DS-F03 July 22, 1999 35 DM9101 10/100Mbps Ethernet Physical Layer Single Chip Transceiver MII-10Base-T Receive Nibble Timing Parameters Symbol tRXs tRXh tRXpd t1 t2 t3 t4 Parameter RXD[0:3), RX_DV, RX_ER Setup To RX_CLK High RXD[0:3], RX_DV, RX_ER Hold From RX_CLK High RXI In To RXD[0:3] Out (Rx Latency) CRS Asserted To RXD[0:3], RX_DV, RX_ER CRS De-asserted To RXD[0:3], RX_DV, RX_ER RXI In To CRS Asserted RXI Quiet To CRS De-asserted Min. 10 Typ. - Max. - Unit ns 10 - - ns - 7 - BT 1 14 20 BT - - 3 BT 1 1 2 10 4 15 BT BT Conditions 10Base-T SQE (Heartbeat) Timing Diagram TX_CLK TX_EN t1 t2 COL 10Base-T SQE (Heartbeat) Timing Parameters Symbol t1 t2 Parameter COL (SQE) Delay After TX_EN Off COL (SQE) Pulse Duration Min. 0.65 Typ. 1.3 Max. 1.6 Unit ms 0.5 1.1 1.5 ms Conditions 10Base-T Jab and Unjab Timing Diagram TX_EN t1 TDX COL 36 t2 Final Version: DM9101-DS-F03 July 22, 1999 DM9101 10/100Mbps Ethernet Physical Layer Single Chip Transceiver 10Base-T Jab and Unjab Timing Parameters Symbol t1 t2 Parameter Maximum Transmit Time Unjab Time Min. 20 250 Typ. 48 505 Max. 150 1500 Unit ms ms Conditions MDIO Timing when OUTPUT by STA MDC 10ns (Min) t1 10ns (Min) t2 MDIO MDIO Timing when OUTPUT by DM9101 MDC 0 - 300 ns t3 MDIO MII Timing Parameters Symbol t1 t2 t3 Parameter MDIO Setup Before MDC MDIO Hold After MDC MDC To MDIO Output Delay Final Version: DM9101-DS-F03 July 22, 1999 Min. 10 10 0 Typ. - Max. 100 Unit ns ns ns Conditions When OUTPUT By STA When OUTPUT By STA When OUTPTU By DM9101 37 DM9101 10/100Mbps Ethernet Physical Layer Single Chip Transceiver Magnetics Selection Guide The DM9101 requires a 1:1 ratio for both the receive and the transmit transformers. Refer to Table 2 for transformer requirements. Transformers meeting these requirements are available from a variety of magnetic manufacturers. Designers should test and qualify all magnetics before using them in an application. The transformers listed in Table 2 are electrical equivalent, but may not be pin-to-pin equivalent. Manufacturer Part Number Bel Fuse Delta Fil-Mag Halo S558-5999-01 LF8200, LF8221 PT41715 TG22-3506ND, TD22-3506G1, TG22-S010ND TG22-S012ND NPI 6181-37, NPI 6120-30, NPI 6120-37 NPI 6170-30 PE-68517, PE-68515, H1019, H1012 ----Single Port H1027, H1028 ---- Dual Port PE-69037, H1001, H1036, H1044 ---- Quad Port ST6114, ST6118 20PMT04, 20PMT05 Nano Pulse Inc. Pulse Engineering Valor YCL Table 2 Crystal Selection Guide A crystal can be used to generate the 25Mhz reference clock instead of a crystal oscillator. An M-TRON crystal, part number is 00301-00169, MP-1 Fund, @ 25.000000Mhz, ±50ppm or equivalent may be used. The crystal must be a fundamental type, parallel resonant. Connect to X1 and X2, shunt each crystal lead to ground with an 18pf capacitor (see figure 6). 32 OSC/XTLB 31 X2 AGND 30 29 X1 OSCGND Y1 2 5 M C18 C19 18pf AGND 18pf AGND Figure 6 Crystal Circuit Diagram 38 Final Version: DM9101-DS-F03 July 22, 1999 DM9101 10/100Mbps Ethernet Physical Layer Single Chip Transceiver Item No. Qty. 1 11 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 1 4 1 1 1 2 2 1 1 1 1 4 1 4 2 1 1 Reference Number C1,C2,C3,C4,C5,C6,C7,C8,C9, C10,C11 C12 D1,D2,D3,D4 J1 L1 OSC1 Q2,Q1 R1,R2 R3 R4 R5 R6 R7,R8,R14,R15 R9 R10,R11,R12,R13 R17,R16 U1 U2 Part Description Capacitor, Decoupling, 0.1uf, 50V Capacitor,.01uf,2KV LED, General Purpose Connector, RJ45 Ferrite, PanasonicEXCCL4532U Oscillator, Crystal, 25Mhz, ±50ppm Transistor, NNP, General Purpose, 2N2222 Resistor, 470Ω, 5% Resistor, 820Ω, 5% Resistor, 33Ω, 5% Resistor, 510Ω, 5% Resistor, 6.01KΩ, 1% Resistor, 49.9Ω, 1% Resistor, 1.5KΩ, 5% Resistor, 75Ω, 1% Resistor, 10KΩ, 5% DM9101F, PHY/Transceiver, 100pin QFP Magnetics, Pulse Engineering, PE68515 Table 3 Parts List for Example Design Table 3 is a list of materials used in the design example shown on the next page. Where a specific vendor name has been called out, the designer can substitute an equivalent part. Final Version: DM9101-DS-F03 July 22, 1999 39 40 C7 .1u C6 .1u BPSCR RPTR/NODE# DGND OPMODE3 BPALIGN OPMODE2 OPMODE1 OPMODE0 PHYAD4 RX_LOCK DVCC DGND PHYAD3 DGND NC PHYAD2 LINKSTS PHYAD1 TESTMODE PHYAD0 RESET# R17 FDXLED# VCC BP4B5B GND 10BTSER 10K Q2 AGND 2N2222 AGND OSC/XTL# GPIO7 14 X2 AVCC AVCC OSCI/X1 8 98 100 99 95 96 97 94 93 92 89 91 90 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 .1u C1 26 L1 33 R4 VCC C4 GND C12 VCC VCC .1u C5 .1u 9 16 15 14 13 12 11 10 49.9 1% R8 GND 49.9 1% R15 49.9 1% R7 .1u 49.9 1% R14 C3 .1u C2 .1u DECOUPLING FOR DM9101 MII Example Schematic U1 AVCC NC NC NC NC AGND AVCC AVCC RXI- RXI+ AGND AGND 10TXO- 10TXO+ AVCC AVCC AGND AGND NC NC AVCC AVCC AGND AGND 100TXO- 100TXO+ OUT +VDD O S C 1 25Mhz NC GND AGND 10K R16 CLK25M /RESET SPEED10 RX_EN BGGND 80 RX_DV BGRES RX_ER/RXD4 AGND RX_EN 78 79 COL CRS RX_CLK DVCC DGND RXD0 RXD1 RXD2 RXD3 DVCC DGND MDIO AVCC RX_ER 77 76 75 74 73 72 71 70 69 68 67 66 DVCC RX_DV COL CRS RX_CLK RXD0 RXD1 RXD2 RXD3 1.5K R9 UTP MDIO DGND DM9101F TRIDRV MDC TX_CLK TX_EN DVCC DVCC 65 64 63 62 DGND TXD0 DGND MDC TX_CLK TX_EN 61 60 50 TXD0 49 TXD1 48 TXD2 47 59 46 58 45 TXD1 44 TXD3 43 TX_ER/TXD4 42 TXLED# 41 57 40 56 39 RXLED# 38 55 37 LINKLED# 36 53 35 54 7 1 6.01K 1% R6 GND 10M LED D4 510 R5 2N2222 Q1 34 DGND COLLED# 100M LED D3 820 R3 33 52 51 FDX LED D2 470 R2 32 TXD2 .1u C9 VCC ACT LED D1 470 R1 31 TXD3 .1u C8 DECOUPLING FOR GND VCC GND TX_ER GND VCC 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 X1 PE68515 C10 GND .1u R10 R13 75 1% .01u/2KV C11 R11 75 1% CHASSIS GND 75 1% R12 75 1% 1 2 3 4 5 6 7 8 J1 RJ45 DM9101 10/100Mbps Ethernet Physical Layer Single Chip Transceiver 88 87 85 84 86 83 81 82 MII INTERFACE Final Version: DM9101-DS-F03 July 22, 1999 DM9101 10/100Mbps Ethernet Physical Layer Single Chip Transceiver Package Information LQFP 100L Outline Dimensions Unit: Inches/mm HD D 75 51 F E HE 50 76 100 26 1 25 GD b ~~ e y A A1 See Detail F Seating Plane D A2 c GD L L1 Symbol Dimensions In Inches Dimensions In mm A 0.063 Max. 1.60 Max. A1 0.004 ± 0.002 0.1 ± 0.05 A2 0.055 ± 0.002 1.40 ± 0.05 b 0.009 ± 0.002 0.22 ± 0.05 c 0.006 ± 0.002 0.15 ± 0.05 D 0.551 ± 0.005 14.00 ± 0.13 E 0.551 ± 0.005 0.020 BSC. 14.00 ± 0.13 0.50 BSC. GD 0.481 NOM. 0.606 NOM. 12.22 NOM. 15.40 NOM. HD 0.630 ± 0.006 16.00 ± 0.15 HE 0.630 ± 0.006 16.00 ± 0.15 L 0.024 ± 0.006 0.60 ± 0.15 L1 0.039 Ref. 1.00 Ref. y 0.004 Max. 0.1 Max. θ 0° ~ 12° 0° ~ 12° e F Detail F Notes: 1. Dimension D & E do not include resin fins. 2. Dimension GD is for PC Board surface mount pad pitch design reference only. 3. All dimensions are based on metric system. Final Version: DM9101-DS-F03 July 22, 1999 41 DM9101 10/100Mbps Ethernet Physical Layer Single Chip Transceiver Package Information QFP 100L Outline Dimensions Unit: Inches/mm HD D 100 81 1 HE E F GE 80 51 30 31 50 GD ~~ e c b D See Detail F Seating Plane y A A1 A2 GD L L1 Symbol Dimensions In Inches Dimensions In mm A 0.130 Max. 3.30 Max. A1 0.004 Min. 0.10 Min. A2 0.1120.005 2.850.13 b 0.012 +0.004 -0.002 0.31 +0.10 -0.05 c 0.006 +0.004 -0.002 0.15 +0.10 -0.05 D 0.5510.005 14.000.13 E 0.7870.005 20.000.13 e 0.026 0.006 0.650.15 F 0.742 NOM. 18.85 NOM. GD 0.693 NOM. 17.60 NOM. GE 0.929 NOM. 23.60 NOM. HD 0.7400.012 18.800.31 HE 0.9760.012 24.790.31 L 0.0470.008 1.190.20 L1 0.0950.008 2.410.20 y 0.006 Max. 0.15 Max. θ 0° ~ 12° 0° ~ 12° Detail F Note: 1. Dimension D & E do not include resin fins. 2. Dimension GD & GE are for PC Board surface mount pad pitch design reference only. 3. All dimensions are based on metric system. 42 Final Version: DM9101-DS-F03 July 22, 1999 DM9101 10/100Mbps Ethernet Physical Layer Single Chip Transceiver Ordering Information Part Number DM9101E DM9101F Pin Count 100 100 Package LQFP QFP DAVICOM’s terms and conditions printed on the order acknowledgment govern all sales by DAVICOM. DAVICOM will not be bound by any terms inconsistent with these unless DAVICOM agrees otherwise in writing. Acceptance of the buyer’s orders shall be based on these terms. Disclaimer Company Overview The information appearing in this publication is believed to be accurate. Integrated circuits sold by DAVICOM Semiconductor are covered by the warranty and patent indemnification provisions stipulated in the terms of sale only. DAVICOM makes no warranty, express, statutory, implied or by description regarding the information in this publication or regarding the information in this publication or regarding the freedom of the described chip(s) from patent infringement. FURTHER, DAVICOM MAKES NO WARRANTY OF MERCHANTABILITY OR FITNESS FOR ANY PURPOSE. DAVICOM reserves the right to halt production or alter the specifications and prices at any time without notice. Accordingly, the reader is cautioned to verify that the data sheets and other information in this publication are current before placing orders. Products described herein are intended for use in normal commercial applications. Applications involving unusual environmental or reliability requirements, e.g. military equipment or medical life support equipment, are specifically not recommended without additional processing by DAVICOM for such applications. Please note that application circuits illustrated in this document are for reference purposes only. DAVICOM Semiconductor, Inc. develops and manufactures integrated circuits for integration into data communication products. Our mission is to design and produce IC products that are the industry’s best value for Data, Audio, Video, and Internet/Intranet applications. To achieve this goal, we have built an organization that is able to develop chipsets in response to the evolving technology requirements of our customers while still delivering products that meet their cost requirements. Products We offer only products that satisfy high performance requirements and which are compatible with major hardware and software standards. Our currently available and soon to be released products are based on our proprietary designs and deliver high quality, high performance chipsets that comply with modem communication standards and Ethernet networking standards. Contact Windows For additional information about DAVICOM products, contact the sales department at: Headquarters: Hsin-chu Office: 4F, No. 17, Park Avenue II, Science-based Park, Hsin-chu City, Taiwan, R.O.C. TEL: 886-3-579-8797 FAX: 886-3-579-8858 Taipei Sales Office: 8F, No. 3, Lane 235, Bao-chiao Road, Hsin-tien City, Taipei, Taiwan, R.O.C. TEL: 886-2-2915-3030 FAX: 886-2-2915-7575 Email: [email protected] WARNING Conditions beyond those listed for the absolute maximum may destroy or damage the products. In addition, conditions for sustained periods at near the limits of the operating ranges will stress and may temporarily (and permanently) affect and damage structure, performance and/or function. Final Version: DM9101-DS-F03 July 22, 1999 43