ETC EMP202

EMP202
Single-Chip Dual-Channel AC’97
Audio Codec for PC Audio Systems
1.
2.
3.
4.
5.
Features ....................................................................2
General Description .................................................2
Block Diagram ..........................................................3
Pin Assignments ......................................................4
Pin Description.........................................................5
5.1. Digital I/O Pins ....................................................5
5.2. Analog I/O Pins ...................................................5
5.3. Filter/References.................................................6
5.4. Power/Ground.....................................................6
5.5. Crystal Selection .................................................6
6. Registers...................................................................7
6.1. Mixer Registers ...................................................8
6.1.1. MX00 Reset .................................................8
6.1.2. MX02 Master Volume ..................................8
6.1.3. MX04 Headphone Volume...........................9
6.1.4. MX06 MONO_OUT Volume.........................9
6.1.5. MX0A PC BEEP Volume .............................9
6.1.6. MX0C PHONE Volume ..............................10
6.1.7. MX0E MIC Volume ....................................10
6.1.8. MX10 LINE_IN Volume..............................10
6.1.9. MX12 CD Volume ......................................11
6.1.10. MX14 VIDEO Volume ................................11
6.1.11. MX16 AUX Volume ....................................12
6.1.12. MX18 PCM_OUT Volume..........................12
6.1.13. MX1A Record Select..................................13
6.1.14. MX1C Record Gain....................................13
6.1.15. MX20 General Purpose Register ...............14
6.1.16. MX22 3D Control .......................................14
6.1.17. MX26 Powerdown Control/Status ..............15
6.1.18. MX28 Extended Audio ID...........................16
6.1.19. MX2A Extended Audio Status and Control 16
6.1.20. MX2C PCM Output Sample Rate ..............17
6.1.21. MX32 PCM Input Sample Rate..................17
6.1.22. MX3A S/PDIF Output Channel
Status and Control .................................................18
6.2. GPIO Registers.................................................18
6.2.1. MX3E Extended Modem Status and Control18
6.2.2. MX4C GPIO Pin Configuration ................. 19
6.2.3. MX4E GPIO Pin Polarity/Type ................. 19
6.2.4. MX50 GPIO Pin Sticky ............................. 19
6.2.5. MX50 GPIO Pin Status............................. 19
6.3. Extended Registers .......................................... 20
6.3.1. MX6A SPDIF Output Select ...................... 20
6.3.2. MX72 Antipop............................................ 20
6.3.3. MX74 EAPD Access.................................. 20
6.3.4. MX7C VENDOR ID1 ................................. 20
6.3.5. MX7E VENDOR ID2.................................. 21
7. Electrical Characteristics...................................... 21
7.1. DC Characteristics ........................................... 21
7.2. AC Timing Characteristics ................................ 21
7.2.1. Cold Reset ................................................ 21
7.2.2. Warm Reset .............................................. 22
7.2.3. AC-Link Clocks.......................................... 22
7.2.4. Data Output and Input Times .................... 23
7.2.5. Signal Rise and Fall Times........................ 23
7.2.6. AC-Link Low Power Mode Timing ............. 24
7.2.7. ATE Test Mode ......................................... 24
7.2.8. AC-Link IO Pin Capacitance and Loading . 24
7.2.9. BIT-CLK and SDATA-IN State .................. 24
8. Analog Performance Characteristics................... 25
9. Design Suggestions .............................................. 26
9.1. Clocking............................................................ 26
9.2. AC-Link............................................................. 26
9.3. Reset ................................................................ 26
9.4. CD Input ........................................................... 27
9.5. Odd Addressed Register Access...................... 27
9.6. Power-down Mode ........................................... 27
9.7. Test Mode ........................................................ 27
9.7.1. ATE In Circuit Test Mode .......................... 27
9.7.2. Vendor Specific Test Mode ....................... 27
10. Package Dimensions............................................. 28
1
8/7/2003
Single-Chip Dual-Channel AC’97 Audio Codec
EMP202
EMPIA Technology
Features
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High performance CODEC with high S/N ratio (>90 dB).
Compliant with AC’97 2.2 specifications
20-bit stereo Digital-to-Analog Converter with variable sampling rate.
20-bit stereo Analog-to-Digital Converter with variable sampling rate.
4 analog line-level stereo inputs with 5-bit volume control: LINE_IN, CD,
VIDEO, AUX.
2 analog line-level mono inputs: PC_BEEP, PHONE_IN.
Mono output with 5-bit volume control.
Stereo output with 5-bit volume control.
2 MIC inputs are software selectable.
Power management capabilities.
3D Stereo Enhancement
Embedded 50mW/20 Ω OP at LINE output.
External amplifier power down capability.
Digital S/PDIF output.
Built in 14.318M 24.576MHz PLL to save external 24.576MHz crystal
Supports 2 general-purpose I/O pins.
Power supply: Digital: 3.3V; Analog: 5V/3.3V
Standard 48-Pin LQFP Package
1. General Description
The EMP202 is a 2 channel, 20-bit DAC and 20-bit ADC, full duplex AC'97 2.2 compatible stereo
audio CODEC designed for PC multimedia systems, including soft/host audio and riser card based
designs. The EMP202 incorporates proprietary converter technology. The EMP202 AC'97 CODEC
supports with independent variable hardware sampling rates. The EMP202 CODEC provides two
pairs of stereo outputs with independent volume controls, a mono output, a headphone output, and
multiple stereo and mono inputs, along with flexible mixing, gain and mute functions to provide a
complete integrated audio solution for PCs. The EMP202 CODEC operates from a 3.3V power supply
with EAPD (External Amplifier Power Down) control for use in notebook and PC applications. To save
BOM costs, the EMP202 integrates a 50mW/20 Ω headset audio amplifier into the CODEC with
Headphone Output. The EMP202 also supports an AC’97 2.2 compliant SPDIF out function which
allows easy connection from the PC to consumer electronic products. The EMP202 CODEC supports
soft/host audio from Intel 810/815/820/845 chipsets as well as audio controller based VIA/SIS/ALI
chipsets. Windows WDM drivers that support Win95/98.ME/2K/NT and XP provide a complete
solution. Finally, internal PLL circuits generate required timing signals, eliminating the need for
external clocking devices.
7/15/2002
2
7/15/2002
MX18
3
Mixer Functional Diagram
*
default setting
stereo digital
stereo analog
MX16
KEY
MX14
AUX-IN
MX10
MX0E
VIDEO-IN
+20 Db
MX12
mono analog
MX20.8
0*
1
CD-IN
LINE-IN
MIC1
MIC2
MX0C
DAC
PHONE
SRC
MX0A
PCM Out
PC-BEEP
MUX
MX1A
MX1C
Record
Gain
MX20.9
1
0*
ADC
SPDIF Out
Control
MX2A / MX3A
No
Yes
HP-Out
MONO-OUT
LINE-OUT
PCM in
RESET#
OP
AMP
EMP202
SRC
MX06
Mono
Volume
Master
Volume
MX02
MX04
HP
Volume
SPDIF Output
EMP202
aux
CD
video
line
mic
phone
mono mix
stereo mix
MX20.13
MX22
3D
PCM Out
Single-Chip Dual-Channel AC’97 Audio Codec
EMPIA Technology
2. Block Diagram
Single-Chip Dual-Channel AC’97 Audio Codec
EMP202
EMPIA Technology
EMP202
13
14
15
16
17
18
19
20
21
22
23
24
1
2
3
4
5
6
7
8
9
10
11
12
PHONE
AUX-L
AUX-R
VIDEO-L
VIDEO-R
CD-L
CD-GND
CD-R
MIC1
MIC2
LINE-IN-L
LINE-IN-R
DVDD1
XTL-IN
XTL-OUT
DVSS1
SDATA-OUT
BIT-CLK
DVSS2
SDATA-IN
DVDD2
SYNC
RESET#
PC-BEEP
48
47
46
45
44
43
42
41
40
39
38
37
SPDIFOUT
EAPD
ID1
ID0
GPIO1
GPIO0
AVSS2
HP-OUT-R
HP-COMM
HP-OUT-L
AVDD2
MONO-OUT
3. Pin Assignments
Pin Assignment Diagram
7/15/2002
4
36
35
34
33
32
31
30
29
28
27
26
25
LINE-OUT-R
LINE-OUT-L
NC
NC
CAP2
NC
AFILT2
AFILT1
VREFOUT
VREF
AVSS1
AVDD1
Single-Chip Dual-Channel AC’97 Audio Codec
EMP202
EMPIA Technology
4. Pin Description
4.1. Digital I/O Pins
Name
RESET#
Type
I
Pin No
11
Description
AC'97 master H/W reset
XTL-IN
XTL-OUT
SYNC
I
O
I
2
3
10
Crystal input pad (24.576Mhz)
Crystal output pad
Sample Sync (48Khz)
BIT-CLK
IO
6
Bit clock output (12.288Mhz)
SDATA-OUT
I
5
Serial TDM AC’97 output
SDATA-IN
O
8
Serial TDM AC’97 input
GPIO0
GPIO1
ID1
ID0
EAPD
I/O
I/O
I
I
I/O
43
44
46
45
47
SPDIFOUT
O
48
General Purpose Input/Output
General Purpose Input/Output
XTAL Elim Select
XTAL Elim Select
External Amplifier power down
control/GPIO
S/PDIF output
Characteristic Definition
Schmitt input, VL=0.3Vdd,
VH=0.4Vdd
Crystal input pad
Crystal output pad
Schmitt input, VL=0.3Vdd,
VH=0.4Vdd
CMOS input/output, Vt=0.35Vdd,
internal pull low by a 100K resistor.
Schmitt input, VL=0.3Vdd,
VH=0.4Vdd
CMOS output, internal pull low by a
100K resistor.
Digital input/output
Digital input/output
Digital input
Digital input
Digital output
Digital output
TOTAL: 13 Pins
4.2. Analog I/O Pins
Name
PC-BEEP
PHONE
AUX-L
AUX-R
VIDEO-L
VIDEO-R
CD-L
CD-GND
CD-R
MIC1
MIC2
LINE-L
LINE-R
LINE-OUT-L
LINE-OUT-R
MONO-OUT
HP-OUT-L
HP-COMM
HP-OUT-R
Type
I
I
I
I
I
I
I
I
I
I
I
I
I
O
O
O
O
O
O
Pin No
12
13
14
15
16
17
18
19
20
21
22
23
24
35
36
37
39
40
41
Description
PC speaker input
Speaker phone input
AUX Left channel
AUX Right channel
Video audio Left channel
Video audio Right channel
CD audio Left channel
CD audio analog GND
CD audio Right channel
First Mic input
Second Mic input
Line-In Left channel
Line-In Right channel
Line-Out Left channel
Line-Out Right channel
Speaker Phone output
Headphone Out Left channel
Headphone Ground Return
Headphone Out Right channel
TOTAL: 19 Pins
7/15/2002
5
Characteristic Definition
Analog input (1Vrms)
Analog input (1Vrms)
Analog input (1Vrms)
Analog input (1Vrms)
Analog input (1Vrms)
Analog input (1Vrms)
Analog input (1Vrms)
Analog input (1Vrms)
Analog input (1Vrms)
Analog input (1Vrms)
Analog input (1Vrms)
Analog input (1Vrms)
Analog input (1Vrms)
Analog output (1Vrms ~ 1.7Vrms)
Analog output (1Vrms ~ 1.7Vrms)
Analog output (1Vrms)
Analog output (1Vrms)
Analog output (1Vrms)
Analog output (1Vrms)
Single-Chip Dual-Channel AC’97 Audio Codec
EMP202
EMPIA Technology
4.3. Filter/References
Name
VREF
VREFOUT
AFILT1
Type
O
O
O
Pin No
27
28
29
AFILT2
O
30
CAP2
O
32
NC
-
31,33,34
Description
Reference voltage
Ref. voltage out with 5mA drive
ADC left anti-aliasing filter
capacitor
ADC right anti-aliasing filter
capacitor
Characteristic Definition
Analog output
Analog output
Analog output
ADC reference Cap
Analog output
Analog output
No Connect
TOTAL: 8 Pins
4.4. Power/Ground
Name
AVDD1
AVDD2
AVSS1
AVSS2
VDD1
Type
I
I
I
I
I
Pin No
25
38
26
42
1
Description
Analog VDD (5.0V)
Analog VDD (5.0V)
Analog GND
Analog GND
Digital VDD (3.3V)
VDD2
I
9
Digital VDD (3.3V)
VSS1
VSS2
I
I
4
7
Digital GND
Digital GND
Characteristic Definition
The minimum value is 3.0V, the maximum value is 5.5V
The minimum value is 3.0V, the maximum value is 5.5V
The minimum value is 3.0V (DVdd-0.3), the maximum value is
3.6V (DVdd+0.3)
The minimum value is 3.0V (DVdd-0.3), the maximum value is
3.6V (DVdd+0.3)
TOTAL: 8 Pins
4.5. Crystal Selection
XTL-OUT Status
XTAL connected
XTAL connected or open
XTAL connected or open
XTAL connected or open
XTAL shorted to GND
XTAL shorted to GND
XTAL shorted to GND
XTAL shorted to GND
7/15/2002
ID1 Config
Float
Float
Pulldown
Pulldown
Float
Float
Pulldown
Pulldown
ID0 Config
Float
Pulldown
Float
Pulldown
Float
Pulldown
Float
Pulldown
6
Input Clock Source
24.576MHz XTAL
12.2888MHz BIT-CLK
12.2888MHz BIT-CLK
12.2888MHz BIT-CLK
14.31818MHz Source
27MHz Source
48MHz Source
24.576MHz Source
EMP202
Single-Chip Dual-Channel AC’97 Audio Codec
EMPIA Technology
5. Registers
Access to registers with an odd number will return a 0. Reading unimplemented registers will also return a 0.
REG.
(HEX)
00h
NAME
D15
D14
D13
D12
Reset
X
SE4
SE3
SE2
D11 D10
D9
D8
D7
SE1
SE0
ID9
ID8
ID7
ML2
ML1
ML0
D6
ID6
D5
ID5
D4
ID4
D3
D2
D1
ID3
ID2
ID1
MR2
MR1
D0 DEFAULT
ID0
6A90h
MR0
8000h
02h
Master Volume
Mute
X
X
ML4
ML3
X
X
X
MR4
MR3
04H
HEADPHONE
Volume
Mute
X
X
HPL4
HPL3 HPL2 HPL1 HPL0 X
X
X
HPL4
HPL3 HPL2 HPL1
HPL0 8000h
06h
Mono-Out Volume
Mute
X
X
X
X
X
X
X
X
X
X
MM4
MM3
MM2
MM1
MM0
8000h
0Ah
PC_BEEP Volume
Mute
X
X
X
X
X
X
X
X
X
X
PB3
PB2
PB1
PB0
X
0000h
0Ch
PHONE Volume
Mute
X
X
X
X
X
X
X
X
X
X
PH4
PH3
PH2
PH1
PH0
8008h
0Eh
MIC Volume
Mute
X
X
X
X
X
X
X
X
X
MI4
MI3
MI2
MI1
MI0
8008h
10h
Line-In Volume
Mute
X
X
NL4
NL3
NL2
NL1
NL0
X
X
X
NR4
NR3
NR2
NR1
NR0
8808h
12h
CD Volume
Mute
X
X
CL4
CL3
CL2
CL1
CL0
X
X
X
CR4
CR3
CR2
CR1
CR0
8808h
14h
Video Volume
Mute
X
X
VL4
VL3
VL2
VL1
VL0
X
X
X
VR4
VR3
VR2
VR1
VR0
8808h
16h
Aux Volume
Mute
X
X
AL4
AL3
AL2
AL1
AL0
X
X
X
AR4
AR3
AR2
AR1
AR0
8808h
PL1
PL0
PR1
PR0
8808h
20dB
18h
PCM Out Volume
Mute
X
X
PL4
PL3
PL2
X
X
X
PR4
PR3
PR2
1Ah
Record Select
X
X
X
X
X
LRS2 LRS1 LRS0 X
X
X
X
X
RRS2 RRS1
RRS0 0000h
1Ch
Record Gain
Mute
X
X
X
LRG3 LRG2 LRG1 LRG0 X
X
X
X
RRG3 RRG2 RRG1
RRG0 8000h
20h
General Purpose
POP
X
3D
X
X
X
MIX
MS
LBK
X
X
X
X
X
X
22h
3D Control
X
X
X
X
X
X
X
X
X
X
X
X
DP3
DP2
26h
Power Down
Ctrl/Status
EAPD PR6
PR5
PR4
PR3
PR2
PR1
PR0
X
X
X
X
REF
ANL
Extended Audio ID
ID1
ID0
X
X
REV1 REV0 AMAP X
X
X
X
DSA1 DSA0 SPDIF X
X
X
X
X
X
X
X
SPSA1 SPSA0 X
28h
2Ah
2Ch
32h
Extended Audio
Status
PCM Out Sample
Rate
PCM Input Sample
Rate
FSR
15
FSR1 4
ISR 15 ISR 14
SPCV X
X
X
0000h
0000h
DAC
SPDIF X
FSR1 FSR1 FSR1
3
2
1
ISR
ISR 13 ISR 12
11
FSR1
FSR9 FSR8 FSR7 FSR6 FSR5 FSR4 FSR3 FSR2 FSR1
0
ISR
ISR 9 ISR 8 ISR 7 ISR 6 ISR 5 ISR 4 ISR 3 ISR 2 ISR 1
10
ADC
000Fh
VRA
0605h
VRA
0400h
FSR0 BB80h
ISR 0 BB80h
3Ah
S/PDIF Ctl
V
DRS
SPSR1 SPSR0 L
CC6
CC5
CC4
CC3
CC2
CC1
CC0
PRE
COPY /AUDIO PRO
3Eh
Ext’d Modem
Stat/Ctrl
X
X
X
X
X
X
X
PRA
X
X
X
X
X
X
X
GPIO 0100h
2000h
4Ch
GPIO Pin Config
X
X
X
X
X
X
X
X
X
X
X
X
X
X
GC1
GC0
0300h
4Eh
GPIO Pin
Polarity/Type
X
X
X
X
X
X
X
X
X
X
X
X
X
X
GP1
GP0
FFFFh
0000h
50h
GPIO Pin Sticky
X
X
X
X
X
X
X
X
X
X
X
X
X
X
GS1
GS0
52h
GPIO Mask
X
X
X
X
X
X
X
X
X
X
X
X
X
X
GW1
GW0 0000h
54h
GPIO Pin Status
X
X
X
X
X
X
X
X
X
X
X
X
X
X
GI1
GI0
6Ah
SPDIF Output Select X
X
X
X
X
X
X
X
X
X
X
X
X
X
DO1
X
0000h
72h
Antipop
X
X
X
X
X
X
X
APOP X
X
X
X
X
X
X
0000H
74h
EAPD/GPIO Access EAPD X
X
X
EAPD
X
OEN
X
X
X
X
X
X
X
INTDIS
GPIO
ACC
GPIO
0800H
SLT12
7Ch
Vendor ID1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
FFFFh
7Eh
Vendor ID2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
FFFFh
X
X: Reserved bit
7/15/2002
7
0000h
Single-Chip Dual-Channel AC’97 Audio Codec
EMP202
EMPIA Technology
5.1. Mixer Registers
5.1.1. MX00 Reset
Default: 6A90H
Writing any value to this register will start a register reset, and causes all of the registers to revert to
their default values. The written data is ignored. Reading this register returns the ID code of the
specific part.
Bit
15
14:10
9
8
7
6
5
4
3
2
1
0
R
R
R
R
R
R
R
R
R
R
R
Type
Function
Reserved
3D Code
Read as 1 (Support 20-bit ADC)
Read as 0
Read as 1 (Support 20-bit DAC)
Read as 0 (Support 18-bit DAC)
Read as 0 (No Loudness support)
Read as 1 (Support Headphone output)
Read as 0 (No simulated stereo, for analog 3D block use)
Read as 0 (No Bass & Treble Control)
Read as 0 (No Modem Line support)
Read as 0 (No Dedicated Mic PCM input channel)
5.1.2. MX02 Master Volume
Default: 8000H
These registers control the overall volume level of the output functions. Each step on the left and right
channels corresponds to 1.5dB in increase/decrease in volume.
Bit
Function
Mute Control:
0: Normal
1: Mute (- ‡dB)
14:13
Reserved
12:8
R/W
Master Left Volume: (ML[4:0]) in 1.5 dB steps
7:5
Reserved
4:0
R/W
Master Right Volume: (MR[4:0]) in 1.5 dB steps
1) For MR/ML: 00h
0 dB attenuation
1Fh
46.5 dB attenuation
2) MR/ML are 5-bit R/W variables. The 6th bit implementation is optional. For this reason, when the 6th bit is
written with a 1, it is the equivalent to writing the low 5-bits with 1. For example, writing 1xxxxx will read back
01111.
15
7/15/2002
Type
R/W
8
Single-Chip Dual-Channel AC’97 Audio Codec
EMP202
EMPIA Technology
5.1.3. MX04 Headphone Volume
Default: 8000H
These registers control the overall volume level of the output functions. Each step on the left and right
channels corresponds to 1.5dB in increase/decrease in volume.
Bit
Function
Mute Control:
0: Normal
1: Mute (- ‡dB)
14:13
Reserved
12:8
R/W
Headphone Left Volume: (HPL[4:0]) in 1.5 dB steps
7:5
Reserved
4:0
R/W
Headphone Right Volume: (HPR[4:0]) in 1.5 dB steps
1) For HPL/HPR:
00h
0 dB attenuation
1Fh
46.5 dB attenuation
2 HPL/HPR are 5-bit R/W variables. The 6th bit implementation is optional. For this reason, when the 6th bit is
written with a 1, it is the equivalent to writing the low 5-bits with 1. For example, writing 1xxxxx will read
back 01111.
15
Type
R/W
5.1.4. MX06 MONO_OUT Volume
Default: 8000H
Mono output is the same data sent on all output channels. Each step in bits 4:0 corresponds to 1.5dB
in increase/decrease in volume, allowing 32 levels of volume from 00000 to 11111.
Bit
Function
Mute Control:
0: Normal
1: Mute (- ‡dB)
14:5
Reserved
4:0
R/W
Mono Master Volume: (MM[4:0]) in 1.5 dB steps
1) For MM:
00h
0 dB attenuation
1Fh
46.5 dB attenuation
2) Implements 5-bit volume control only. Writing 1xxxxx will be interpreted as x11111 and will respond, when read,
with x11111.
15
Type
R/W
5.1.5. MX0A PC BEEP Volume
Default: 8000H
This register controls the input volume for the PC beep signal. Each step in bits 4:1 corresponds to a
3dB increase/decrease in volume. 16 levels of volume are available, from 0000 to 1111.
The purpose of this register is to allow the PC Beep signals to pass through the EMP202, eliminating
the need for an external system speaker/buzzer. The PC BEEP pin is directly routed (internally
hardwired) to the LINE-OUTL & R pins. If the PC speaker/buzzer is eliminated, it is recommended to
connect the external speakers at all times so the POST codes can be heard during reset.
Bit
15
14:5
4:1
0
1) For PB:
7/15/2002
Type
R/W
R/W
00h
0Fh
Function
Mute Control:
0: Normal
1: Mute (- ‡dB)
Reserved
PC Beep Volume: (PB[3:0]) in 3 dB steps
Reserved
0 dB attenuation
45 dB attenuation
9
Single-Chip Dual-Channel AC’97 Audio Codec
EMP202
EMPIA Technology
5.1.6. MX0C PHONE Volume
Default: 8008H
Register 0Ch controls the telephone input volume for software modem applications. Because
software modem applications may not have a speaker, the CODEC can offer a speaker-out service.
Each step in bits 4:0 corresponds to 1.5dB in increase/decrease in volume, allowing 32 levels of
volume, from 00000 to 11111.
Bit
15
14:5
4:0
1) For PV:
Type
R/W
R/W
00h
08h
1Fh
Function
Mute Control:
0: Normal
1: Mute (- ‡dB)
Reserved
Phone Volume: (PV[4:0]) in 1.5 dB steps
+12 dB Gain
0dB gain
-34.5dB Gain
5.1.7. MX0E MIC Volume
Default: 8008H
Register 0Eh controls the microphone input volume. Each step in bits 4:0 corresponds to 1.5dB in
increase/decrease in volume, allowing 32 levels of volume, from 00000 to 11111. Each step in bit 6
corresponds to a magnification of 20dB increase in volume.
15
Bit
Type
R/W
14:7
6
R/W
5
4:0
1) For MV:
R/W
00h
08h
1Fh
Function
Mute Control:
0: Normal
1: Mute (- ‡dB)
Reserved
Mic Boost
0 0dB
1 20dB
Reserved
Mic Volume: (MV[4:0]) in 1.5 dB steps
+12 dB Gain
0dB gain
-34.5dB Gain
5.1.8. MX10 LINE_IN Volume
Default: 8808H
Each step in bits 0..4 correspond to 1.5dB in increase/decrease in volume for the right channel,
allowing 32 levels of volume, from 00000 to 11111. Each step in bits 12:8 correspond to 1.5dB in
increase/decrease in volume for the left channel, allowing 32 levels of volume, from 00000 to 11111.
Bit
15
Type
R/W
14:13
12:8
R/W
7:5
4:0
R/W
1) For NL/NR: 00h
08h
1Fh
7/15/2002
Function
Mute Control:
0: Normal
1: Mute (- ‡dB)
Reserved
Line-In Left Volume: (NL[4:0]) in 1.5 dB steps
Reserved
Line-In Right Volume: (NR[4:0]) in 1.5 dB steps
+12 dB Gain
0dB gain
-34.5dB Gain
10
Single-Chip Dual-Channel AC’97 Audio Codec
EMP202
EMPIA Technology
5.1.9. MX12 CD Volume
Default: 8808H
Each step in bits 44:0 correspond to 1.5dB in increase/decrease in volume for the right channel,
allowing 32 levels of volume, from 00000 to 11111. Each step in bits 12:8 correspond to 1.5dB in
increase/decrease in volume for the left channel, allowing 32 levels of volume, from 00000 to 11111.
Bit
15
Type
R/W
14:13
12:8
R/W
7:5
4:0
R/W
1) For CL/CR: 00h
08h
1Fh
Function
Mute Control:
0: Normal
1: Mute (- ‡dB)
Reserved
CD Left Volume: (CL[4:0]) in 1.5 dB steps
Reserved
CD Right Volume: (CR[4:0]) in 1.5 dB steps
+12 dB Gain
0dB gain
-34.5dB Gain
5.1.10. MX14 VIDEO Volume
Default: 8808H
Each step in bits 4:0 correspond to 1.5dB in increase/decrease in volume for the right channel,
allowing 32 levels of volume, from 00000 to 11111. Each step in bits 12:8 correspond to 1.5dB in
increase/decrease in volume for the left channel, allowing 32 levels of volume, from 00000 to 11111.
Bit
15
Type
R/W
14:13
12:8
R/W
7:5
4:0
R/W
1) For VL/VR: 00h
08h
1Fh
7/15/2002
Function
Mute Control:
0: Normal
1: Mute (- ‡dB)
Reserved
Video Left Volume: (VL[4:0]) in 1.5 dB steps
Reserved
Video Right Volume: (VR[4:0]) in 1.5 dB steps
+12 dB Gain
0dB gain
-34.5dB Gain
11
Single-Chip Dual-Channel AC’97 Audio Codec
EMP202
EMPIA Technology
5.1.11. MX16 AUX Volume
Default: 8808H
Each step in bits 4:0 correspond to 1.5dB in increase/decrease in volume for the right channel,
allowing 32 levels of volume, from 00000 to 11111. Each step in bits 12:8 correspond to 1.5dB in
increase/decrease in volume for the left channel, allowing 32 levels of volume, from 00000 to 11111.
Bit
15
Type
R/W
14:13
12:8
R/W
7:5
4:0
R/W
1) For AL/AR: 00h
08h
1Fh
Function
Mute Control:
0: Normal
1: Mute (- ‡dB)
Reserved
AUX Left Volume: (AL[4:0]) in 1.5 dB steps
Reserved
AUX Right Volume: (AR[4:0]) in 1.5 dB steps
+12 dB Gain
0dB gain
-34.5dB Gain
5.1.12. MX18 PCM_OUT Volume
Default: 8808H
Each step in bits 4:0 correspond to 1.5dB in increase/decrease in volume for the right channel,
allowing 32 levels of volume, from 00000 to 11111. Each step in bits 12:8 correspond to 1.5dB in
increase/decrease in volume for the left channel, allowing 32 levels of volume, from 00000 to 11111.
15
Bit
Type
R/W
14:13
12:8
7:5
4:0
R/W
R/W
1) For PL/PR:
7/15/2002
00h
08h
1Fh
Function
Mute Control:
0: Normal
1: Mute (- ‡dB)
Reserved
PCM Left Volume: (PL[4:0]) in 1.5 dB steps
Reserved
PCM Right Volume: (PR[4:0]) in 1.5 dB steps
+12 dB Gain
0dB gain
-34.5dB Gain
12
Single-Chip Dual-Channel AC’97 Audio Codec
EMP202
EMPIA Technology
5.1.13. MX1A Record Select
Default: 0000H
Each step in bits 2:0 correspond to 1.5dB in increase/decrease in volume for the right channel,
allowing 7 levels of volume, from 000 to 111. Each step in bits 10:8 correspond to 1.5dB in
increase/decrease in volume for the left channel, allowing 7 levels of volume, from 000 to 111.
Bit
Type
Function
15:11
Reserved
10:8
R/W
Left Record Source Select: (LRS[2:0])
7:3
Reserved
2:0
R/W
Right Record Source Select: (RRS[2:0])
1) For LRS:
0 MIC
1 CD LEFT
2 VIDEO LEFT
3 AUX LEFT
4 LINE LEFT
5 STEREO MIXER OUTPUT LEFT
6 MONO MIXER OUTPUT
7 PHONE
2) For RRS:
0 MIC
1 CD RIGHT
2 VIDEO RIGHT
3 AUX RIGHT
4 LINE RIGHT
5 STEREO MIXER OUTPUT RIGHT
6 MONO MIXER OUTPUT
7 PHONE
5.1.14. MX1C Record Gain
Default: 8000H
Each step in bits 3:0 correspond to 1.5dB in increase/decrease in gain for the right channel, allowing
16 levels of gain, from 0000 to 1111. Each step in bits 11:8 correspond to 1.5dB in increase/decrease
in gain for the left channel, allowing 16 levels of gain, from 0000 to 1111.
Bit
15
Type
R/W
14:12
11:8
R/W
7:4
3:0
R/W
1) For LRG/RRG:
7/15/2002
Function
Mute Control:
0: Normal
1: Mute (- ‡dB)
Reserved
Left Record Gain Select: (LRG[3:0]) in 1.5 dB steps
Reserved
Right Record Gain Select: (RRG[3:0]) in 1.5 dB steps
0Fh
+22.5dB
00h
0 dB (No Gain)
13
Single-Chip Dual-Channel AC’97 Audio Codec
EMP202
EMPIA Technology
5.1.15. MX20 General Purpose Register
Default: 0000H
Bit
15:14
13
Type
R/W
12:10
9
R/W
8
R/W
7
R/W
6:0
-
Function
Reserved, read as 0
3D Control: Used to enable or disable 3D effects.
1: On
0: Off
Reserved, Read as 0
Mono Output Select:
0: MIX
1: MIC
Mic Select:
0: Mic 1
1: Mic 2
AD to DA Loop-back Control: Used to enable or disable ADC to front DAC loop-back.
0: Disable
1: Enable
Reserved
5.1.16. MX22 3D Control
Default: 0000H
Bit
15:4
3:2
Type
R/W
1:0
-
7/15/2002
Function
Reserved, read as 0
LINE_OUT Separation Ration
00 0(off)
01 3(low)
10 4.3(med)
11 6(high)
Reserved, read as 0
14
Single-Chip Dual-Channel AC’97 Audio Codec
EMP202
EMPIA Technology
5.1.17. MX26 Powerdown Control/Status
Default: 0000H
This read/write register is used to program powerdown states and monitor subsystem readiness. The
lower half of this register is read only status; a “1” indicating that the subsection is “ready.” Ready is
defined as the subsection’s ability to perform in its nominal state. When this register is written, the bit
values that come in on AC-Link will have no effect on read only bits 0-7 and bit 15.
When the AC-Link “CODEC Ready” indicator bit (SDATA_IN slot 0, bit 15) is a 1, it indicates that the
AC-Link and AC’97 control and status registers are in a fully operational state. The AC’97 controller
must further probe this powerdown control/status register to determine exactly which subsections, if
any are ready.
Bit
15
Type
R/W
14
R/W
13
R/W
12
R/W
11
R/W
10
R/W
9
R/W
8
R/W
7:4
3
R
2
R
1
R
0
R
7/15/2002
Function
PR7 External Amplifier Power Down: (EAPD).
0: EAPD output low (enable external amplifier).
1: EAPD output high (shut down external amplifier)
PR6:
0: Normal
1: Power down Headphone
PR5:
0: Normal.
1: Disable internal clock usage (BITCLK still be output for modem CODEC)
PR4:
0: Normal
1: Power down AC-Link
R3:
0: Normal
1: Power down Mixer (VREF off)
PR2:
0: Normal
1: Power down Mixer (VREF on)
PR1:
0: Normal
1: Power down PCM DAC
PR0:
0: Normal
1: Power down PCM ADC and input MUX
Reserved, read as 0
VREF Status:
1: VREF normal level
0: Not yet
Analog Mixer Status:
1: Ready
0: Not yet
DAC Status:
1: Ready
0: Not yet
ADC Status:
1: Ready
0: Not yet
15
Single-Chip Dual-Channel AC’97 Audio Codec
EMP202
EMPIA Technology
5.1.18. MX28 Extended Audio ID
Default: 0607H
Bit
15:14
Type
R
13:12
11:10
9
8:6
5:4
R
R
NA
R/W
3
2
1
0
R
R
R
Function
ID[1:0]: 00=XTAL Out grounded
ID13, ID0#=XTAL OUT crystal or floating
Reserved, read as 0
REV[1:0]=01 to indicates EMP202 is AC’97 rev2.2 compliant.
AMAP: Read as 1 (DAC mapping base on CODEC ID)
Reserved, read as 0
DSA{1:0], DAC Slot Assignment
ID[1:0]=00 – DSA[1:0] reset =00 where left slot 3, right slot 4
ID[1:0]=01 – DSA[1:0] reset =01 where left slot 7, right slot 8
ID[1:0]=10 – DSA[1:0] reset =01 where left slot 6, right slot 9
ID[1:0]=11 – DSA[1:0] reset =10 where left slot 10, right slot 11
Reserved, read as 0
SPDIF: Read as 1 (S/PDIF is supported)
DRA: Read as 1 (Double Rate Audio is supported)
VRA: Read as 1 (Variable Rate Audio is supported)
5.1.19. MX2A Extended Audio Status and Control
Default: 01F0H
This register contains two active bits for powerdown and status of the surrounding DACs. Bits 0, 1 & 2
are read/write bits which are used to enable or disable VRA, DRA and SPDIF respectively. Bits 4 & 5
are read/write bits used to determine the AC-LINK slot assignment of the S/PDIF. Bit 10 is a read only
bit which tells the controller if the S/PDIF configuration is valid.
Bit
15:11
10
Function
Reserved
SPCV: (S/PDIF Configuration Valid).
0: Current S/PDIF configuration {SPSA,SPSR,DAC/slot rate} is not valid.
1: Current S/PDIF configuration {SPSA,SPSR,DAC/slot rate} is valid
9:6
NA
Reserved
5:4
R/W
SPSA[1:0]: (S/PDIF Slot Assignment).
00: S/PDIF source data assigned to AC-LINK slot3/4.
01: S/PDIF source data assigned to AC-LINK slot7/8.
10: S/PDIF source data assigned to AC-LINK slot6/9.
11: S/PDIF source data assigned to AC-LINK slot10/11 (default).
3
Reserved
2
R/W
SPDIF Enable:
1: Enable
0: Disable (Hi-Z)
1
Reserved
0
R/W
VRA Enable:
1: Enable
0: Disable
1) If VRA = 0, the EMP202 AD/DA operates at a fixed 48KHz sampling rate. Otherwise, it operates with variable
sampling rates as defined in MX2C and MX32.
2.) If pin 48 is held high at power up, SPDIF is not available and D15:D1 cannot be written and will read back 0.
7/15/2002
Type
NA
R
16
Single-Chip Dual-Channel AC’97 Audio Codec
EMP202
EMPIA Technology
5.1.20. MX2C PCM Output Sample Rate
Default: BB80H
Bit
Type
Function
15:0
R/W
FOSR[15:0]: Output sampling rate
1) The EMP202 supports the following sampling rates as required in the PC99/PC2001 design guide.
Sampling rate
FOSR[15:0]
8000
1F40h
11025
2B11h
12000
2EE0h
16000
3E80h
22050
5622h
24000
5DC0h
32000
7D00h
44100
AC44h
48000
BB80h
If the value written is not supported, the closest value is returned.
5.1.21. MX32 PCM Input Sample Rate
Default: BB80H
Bit
Type
Function
15:0
R/W
ISR[15:0]: Output sampling rate
1) The EMP202 supports the following sampling rates as required in the PC99/PC2001 design guide.
Sampling rate
ISR[15:0]
8000
1F40h
11025
2B11h
12000
2EE0h
16000
3E80h
22050
5622h
24000
5DC0h
32000
7D00h
44100
AC44h
48000
BB80h
If the value written is not supported, the closest value is returned.
7/15/2002
17
Single-Chip Dual-Channel AC’97 Audio Codec
EMP202
EMPIA Technology
5.1.22. MX3A S/PDIF Output Channel Status and Control
Default: 2000H
15
Bit
Type
R/W
14
13:12
R
R/W
11
10:4
3
R/W
R/W
R/W
2
R/W
1
R/W
0
R
Function
Validity Control: (control V bit in Sub-Frame).
0: The V bit (valid flag) in sub-frame depends on whether or not the S/PDIF data is
under-run.
1: The V bit in sub-frame is always sent as 1 to indicate the invalid data is not suitable
for the receiver.
Double Rate S/PDIF: (DRS) This bit is always 0.
S/PDIF Sample Rate: (SPSR[1:0]).
00: Sample rate set to 44.1KHz, Fs[0:3]=0000.
01: Reserved.
10: Sample rate set to 48.0KHz, Fs[0:3]=0100 (default).
11: Sample rate set to 32.0KHz, Fs[0:3]=1100.
Generation Level: (LEVEL)
Category Code: (CC[6:0])
Preemphasis: (PRE).
0: None
1: Filter preemphasis is 50/15 µsec
Copyright: (COPY).
0: Asserted
1: Not asserted
Non-Audio Data Type: (/AUDIO).
0: PCM data
1: AC3 or other digital non-audio data.
Professional or Consumer Format: (PRO).
0: Consumer format
1: Professional format.
1) To ensure the control and status information started up correctly at the beginning of S/PDIF transmission,
MX3A.[14:0] should only be written to when S/PDIF transmitter is disabled (MX2A.2=0).
2) If validity control is set (MX3A.15=1), those data bits (bit 8 ~ bit 27) should be forced to 0 to obtain better
compatibility with mini disc devices.
5.2. GPIO Registers
5.2.1. MX3E Extended Modem Status and Control
Default: 0100H
Bit
15:9
8
Type
R/W
7:1
0
R
R
7/15/2002
Function
Reserved
PRA
0 GPIO powered up/enabled
1 GPIO powered down/disabled
Reserved
GPIO
0 GPIO not ready (powered down)
1 GPIO Ready (powered up)
18
Single-Chip Dual-Channel AC’97 Audio Codec
EMP202
EMPIA Technology
5.2.2. MX4C GPIO Pin Configuration
Default: 0003H
Bit
15:2
1
Type
R/W
0
R/W
Function
Reserved
GC1
0 GPIO1 configured as output
1 GPIO1 configured as input
GC0
0 GPIO0 configured as output
1 GPIO0 configured as input
5.2.3. MX4E GPIO Pin Polarity/Type
Default: FFFFH
Bit
15:2
1
Type
R/W
0
R/W
Function
Reserved
GP1
0 GPIO1 polarity inverted
1 GPIO1 polarity inverted
GP0
0 GPIO0 polarity inverted
1 GPIO0 polarity inverted
5.2.4. MX50 GPIO Pin Sticky
Default: 0000H
Bit
15:2
1
Type
R/W
0
R/W
Function
Reserved
GS1
0 GPIO1 non sticky
1 GPIO1 sticky
GS0
0 GPIO1 non sticky
1 GPIO1 sticky
5.2.5. MX50 GPIO Pin Status
Default: 0000H
Bit
15:2
1:0
7/15/2002
Type
R/W
Function
Reserved
GI1 (GPIO1/0)
As output, use with MX74:D0 to set
If D0=0, the respective register value placed on pad (D1 for GPIO1, D0 for
GPIO0)
If D0=1, pad get value from slot 12
As input and sticky
0 clears this bit
1 does nothing
As input and non sticky
This register gives GPIO1 value from pad.
19
Single-Chip Dual-Channel AC’97 Audio Codec
EMP202
EMPIA Technology
5.3. Extended Registers
5.3.1. MX6A SPDIF Output Select
Default: 0000H
Bit
15:2
1
Type
R/W
0
-
Function
Reserved
SPDIF Output Source Select
0 PCM data from ACLINK to SPDIF
1 ADC record data to SPDIF
Reserved
5.3.2. MX72 Antipop
Default: 0000H
Bit
15:8
7
Type
R/W
6:0
-
Function
Reserved
Internal Antipop
0 enabled
1 disabled
Reserved
5.3.3. MX74 EAPD Access
Default: 0800H
15
Bit
Type
R/W
14:12
11
R/W
10:3
2
R/W
1
R/W
0
R/W
Function
EAPD, Use with D11
If D11=1, EAPD data output
If D11=0, EAPD data input
Reserved
EAPD Pin Enable
0 EAPD as input
1 EAPD as output
Reserved
Interrupt Disable
0 clear GPIO interrupts
1 clear GPIO interrupts with MX54
GPIO Access
0 ACLINK access from GPIO pad
1 ACLINK access from MX54
GPIOSLT12
0 GPIO0 and GPIO1 access from MX54, if GPIO is set as output, input Slot 12
will be 0h.
1 GPIO0 and GPIO1 access from Slot 12, if GPIO is set as output, input MX54
not updated.
5.3.4. MX7C VENDOR ID1
Default: FFFFH
Bit
15:0
7/15/2002
Type
R
Function
Vendor ID: FFFFH
20
EMP202
Single-Chip Dual-Channel AC’97 Audio Codec
EMPIA Technology
5.3.5. MX7E VENDOR ID2
Default: FFFFH
Bit
15:0
Type
R
Function
Vendor ID: FFFFH
6. Electrical Characteristics
6.1. DC Characteristics
Dvdd= 3.3V ±5%, Tambient=25 0 C, with 50pF external load.Parameter
Input voltage range
Low level input voltage
SYNC,SDATA_OUT,RESET#
XTAL_IN,BIT_CLK ID1#,ID0#
High level input voltage
SYNC,SDATA_OUT,RESET#
XTAL_IN,BIT_CLK ID1#,ID0#
High level output voltage
Low level output voltage
Pull up resistance
Input leakage current
Output leakage current (Hi-Z)
Output buffer drive current
Symbol
Vin
VIL
VIH
VOH
VOL
-
Min
-0.30
0.40*DVdd
0.90DVdd
50K
-10
-10
-
Typical
1.2 / 0.7
1.7 / 1.0
2.0 / 1.2
2.1 / 1.7
3.2 / 2.2
2.5 / 1.7
100K
5
Max
DVdd+0.30
0.30*DVdd
0.1DVdd
200K
10
10
-
Units
V
V
Max
-
Units
us
ns
V
V
V
uA
uA
mA
6.2. AC Timing Characteristics
6.2.1. Cold Reset
Parameter
RESET# active low pulse width
RESET# inactive to BIT_CLK Startup
delay
Symbol
Trst_low
Trst2clk
Min
1.0
162.8
Typical
-
Trst2clk
Tres_low
RESET#
Ttri2actv
BIT_CLK
Ttri2actv
SDATA_IN
Cold reset timing diagram
7/15/2002
21
Single-Chip Dual-Channel AC’97 Audio Codec
EMP202
EMPIA Technology
6.2.2. Warm Reset
Tsync_high
Tsync_2clk
SYNC
BIT_CLK
Warm reset timing diagram
Parameter
SYNC active high pulse width
SYNC inactive to BIT_CLK Startup
delay
Symbol
Tsync_high
Tsync2clk
Min
1.0
162.8
Typical
1.3
-
Max
-
Units
us
ns
Max
750
45
45
-
Units
MHz
ns
ps
ns
ns
KHz
us
us
us
6.2.3. AC-Link Clocks
Tsync_high
Tsync_2clk
SYNC
BIT_CLK
BIT_CLK and SYNC timing diagram
Parameter
Symbol
BIT_CLK frequency
BIT_CLK period
Tclk_period
BIT_CLK output jitter
BIT_CLK high pulse width (note 1)
Tclk_high
BIT_CLK low pulse width (note 1)
Tclk_low
SYNC frequency
SYNC period
Tsync_period
SYNC high pulse width
Tsync_high
SYNC low pulse width
Tsync_low
Note 1: Worse case duty cycle restricted to 45/55.
7/15/2002
Min
36
36
-
22
Typical
12.288
81.4
750
40.7
40.7
48.0
20.8
1.3
19.5
EMP202
Single-Chip Dual-Channel AC’97 Audio Codec
EMPIA Technology
6.2.4. Data Output and Input Times
tco
BIT_CLK
T setup
V ih
V il
SDATA_OUT
SDATA_IN
SYNC
V oh
V ol
T hold
Data Output and Input timing diagram
Parameter
Symbol
Min
Typical
Max
Units
Output Valid Delay from rising edge of BIT_CLK
tco
15
ns
Input Setup to falling edge of BIT_CLK
tsetup
10
ns
Input Hold from falling edge of BIT_CLK
thold
10
ns
Note 1: Timing is for SDATA and SYNC outputs with respect to BIT_CLK at the Device driving the output.
Note 2: 50pF external load
Note 3: Timing is for SDATA and SYNC outputs with respect to BIT_CLK at the device driving the output.
6.2.5. Signal Rise and Fall Times
BIT_CLK
Triseclk
Tfallclk
Trisedin
Tfalldin
SDATA_IN
Signal Rise and Fall timing diagram
Parameter
BIT_CLK rise time
BIT_CLK fall time
SYNC rise time
SYNC fall time
SDATA_IN rise time
SDATA_IN fall time
SDATA_OUT rise time
SDATA_OUT fall time
Note 1: 75pF external load
Note 2: rise is from 10% to 90% of Vdd (Vol to Voh)
Note 3: fall is from 90% to 10% of Vdd (Voh to Vol)
Symbol
Triseclk
Tfallclk
Trisesync
Tfallsync
Trisedin
Tfalldin
Trisedout
Tfalldout
7/15/2002
23
Min
-
Typical
-
Max
6
6
6
6
6
6
6
6
Units
ns
ns
ns
ns
ns
ns
ns
ns
EMP202
Single-Chip Dual-Channel AC’97 Audio Codec
EMPIA Technology
6.2.6. AC-Link Low Power Mode Timing
SYNC
Slot 1
Slot 2
Write to
0x20
Data PR4
BIT_CLK
SDATA_OUT
Don't care
Ts2_pdown
SDATA_IN
Note: BIT_CLK not to scale
AC-Link low power mode timing diagram
Parameter
End of slot 2 to BIT_CLK, SDATA_IN low
Symbol
Ts2_pdown
Min
-
Typical
-
Max
1.0
Units
us
6.2.7. ATE Test Mode
RESET#
SDATA_OUT
Tsetup2rst
Hi-Z
SDATA_IN, BIT_CLK
Toff
ATE test mode timing diagram
To meet AC’97 rev2.2 requirements, EAPD, SPDIFO, BIT_CLK and SDATA_IN should be floating in
test mode.
Parameter
Setup to trailing edge of RESET# (also applies to
SYNC)
Rising edge of RESET# to Hi-Z delay
Symbol
Tsetup2rst
Min
15.0
Typical
-
Max
-
Units
ns
Toff
-
-
25.0
ns
6.2.8. AC-Link IO Pin Capacitance and Loading
Output Pin
BIT_CLK (must support ≥ 2 CODECs)
SDATA_IN
1 CODEC
47.5pF
47.5pF
2 CODEC
62.5pF
55pF
3 CODEC
75pF
60pF
4 CODEC
85pF
62.5pF
6.2.9. BIT-CLK and SDATA-IN State
When RESET# is active, BIT-CLK and SDATA-IN must be floating by internal pull low 100K resistors.
The ac-link signals are driven by another AC’97 on CNR board. This requirement is not mentioned in
AC’97 specifications Rev 2.1. Please refer to CNR (Communication Network Riser) specifications
Rev. 1.0 pages 23~25 or AC’97 Rev. 2.2 for detailed information.
7/15/2002
24
Single-Chip Dual-Channel AC’97 Audio Codec
EMP202
EMPIA Technology
7. Analog Performance Characteristics
Standard test condition:
Tambient=25 0 C, Dvdd=5.0 or 3.3V ±5%,Avdd=5.0V ±5%
Input Voltage Level: Logic Low=0.35*Vdd, Logic High=0.65Vdd
1KHz input sine wave; Sampling frequency=48KHz; 0dB=1Vrms
10K §Ù/50pF load; Testbench Characterization BW:20Hz~20KHz
0dB attenuation; tone and 3D disabled
Parameter
Full scale input voltage
Mixer (except for MIC)
Mic input (gain=0dB)
Mic input (gain=20dB)
ADC
Full scale output voltage
DAC
S/N (A weighted)
CD to LINE_OUT
Other to LINE_OUT
ADC DAC
Total Harmonic Distortion + Noise
ADC
DAC
Frequency Response
Mixers
ADC & DAC
Power Supply Rejection (DAC,ADC)
Total Out-of-Band Noise (28.8K~100KHz)
Mic 20dB gain is selected
Crosstalk between inputs channels
Attenuation, Gain Step Size
Input impedance (gain=0dB)
PC_BEEP only
Others (PHONE,LINE,CD,AUX,VIDEO)
MIC1 and MIC2
Power Supply Current (normal operation)
VA=5v
VD=3.3v
Power Supply Current (power down mode)
VA=5v
VD=3.3v
VREFOUT
Digital Filter Characteristics
ADC Low pass Filter
Pass band
Stop band
Stop band Rejection
Pass band Frequency Response
DAC Low pass Filter
Pass band
Stop band
Stop band Rejection
Pass band Frequency Response
7/15/2002
Min
Typical
Max
Units
-
1.6
1.6
0.16
1.0
-
Vrms
Vrms
Vrms
Vrms
-
1.0
95
92
85
88
1.41
-
-
-80
-80
-
Vrms
dB FSA
dB FSA
dB FSA
dB FSA
dB FS
dB FS
20
20
18
-
-68
-63
20
1.5
20,000
19,200
22
-70
-
-
32
32
16
-
-
50
20
-
2.25
1
2
2.50
mA
mA
2.75
V
0
28.8
-
-76.0
+- 0.15
19.2
-
KHz
KHz
dB
dB
0
28.8
-
-78.5
+- 0.15
19.2
-
KHz
KHz
dB
dB
Hz
25
dB
dB
dB
dB
dB
K　mA
mA
EMP202
Single-Chip Dual-Channel AC’97 Audio Codec
EMPIA Technology
8. Design Suggestions
8.1. Clocking
The clock source for different configurations is listed below.
CODEC ID[1:0]
00
01,10,11
BIT-CLK
Output
BIT CLK
Clock source
Crystal or external clock (XTAL-IN) BITCLK is output
BIT CLK always an input, XTAL-IN (pin 2) ignored
8.2. AC-Link
When the EMP202 takes serial data from the AC’97 controller, it samples SDATA_OUT on the falling
edge of BIT_CLK. When the EMP202 sends serial data to the AC’97 controller, it starts to drive
SDATA_IN on the rising edge of BIT_CLK.
The EMP202 will return any uninstalled bits or registers with 0 for read operations. The EMP202 also
stuffs the unimplemented slot or bit with 0 in SDATA-IN. Note that AC-LINK is MSB-justified.
Please refer to “Audio CODEC ’97 Component Specification Revision 2.2” for details
SYNC
OUTGOING STREAMS
TAG
CMD
ADR
CMD
DATA
PCM
LEFT
PCM
RT
NA
PCM
CTR
PCM
LSURR
PCM
RSURR
PCM
LFE
PCM
LALT
PCM
RALT
RSVD
INCOMING STREAMS
TAG
STATUS
ADR
STATUS
DATA
PCM
LEFT
PCM
RT
NA
NA
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
TAG PHASE
DATA PHASE
5.1 Channel Slot Arrangement Defined in AC’97 Specification rev2.2
8.3. Reset
There are 3 types of reset operations: Cold, Warm and Register reset, which are listed below:
Reset Type
Cold
Warm
Register
7/15/2002
Trigger condition
Assert RESET# for a specified period
CODEC response
Reset all hardware logic and all registers to their
default value.
Driven SYNC high for specified period
Reactivates AC-LINK, no change to register
without BIT_CLK
values.
Write register indexed 00h
Reset all registers to their default value.
The AC’97 controller should drive SYNC and SDATA-OUT low during the period of RESET#
assertion to guarantee that the EMP202 resets successfully.
26
EMP202
Single-Chip Dual-Channel AC’97 Audio Codec
EMPIA Technology
8.4. CD Input
Pay attention to differential CD input. Below is an example of differential CD input.
Example of differential CD input
8.5. Odd Addressed Register Access
The EMP202 will return “0000h” when odd-addressed registers and unimplemented registers are
read.
8.6. Power-down Mode
PR0=1
Normal
PR1=1
ADCs off PR0
PR0=0 & ADC=1
PR2=1
DACs off PR1
PR1=0 & DAC=1
Ready =1
PR4=1
Analog off
PR2 or PR3
PR2=0 & ANL=1
Default
Digital I/F off
PR4
Shut off
AC-Link
Warm Reset
Cold Reset
Example of the EMP202 power-down/power-up flow
8.7. Test Mode
8.7.1. ATE In Circuit Test Mode
SDATA_OUT is sampled high at the trailing edge of RESET#. In this mode, the EMP202 will drive
BIT_CLK, SDATA_IN, EAPD, GPIOs, IDs, and SPDIFO to high impedance.
8.7.2. Vendor Specific Test Mode
All other modes are reserved.
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27
EMP202
Single-Chip Dual-Channel AC’97 Audio Codec
EMPIA Technology
9. Package Dimensions
SYMBOL
MILLIMETER
TYPICAL
MIN.
A
A1
A2
c
D
D1
D2
E
E1
E2
b
e
TH
L
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0.05
1.35
0.09
1.40
9.00 BSC
7.00 BSC
5.50
9.00 BSC
7.00BSC
5.50
0.20
0.50 BSC
3.5º
0.60
0.17
0º
0.45
28
MAX.
1.60
0.15
1.45
0.20
0.27
7º
0.75