Pre-Production FM3204/16/64/256 Integrated Processor Companion with Memory Features High Integration Device Replaces Multiple Parts • Serial Nonvolatile Memory • Low Voltage Reset • Watchdog Timer • Early Power-Fail Warning/NMI • Two 16-bit Event Counters • Serial Number with Write-lock for Security Processor Companion • Active-low Reset Output for VDD and Watchdog • Programmable VDD Reset Trip Point • Manual Reset Filtered and Debounced • Programmable Watchdog Timer • Dual Battery-backed Event Counter Tracks System Intrusions or other Events • Comparator for Early Power-Fail Interrupt • 64-bit Programmable Serial Number with Lock Description The FM32xx is a family of integrated devices that includes the most commonly needed functions for processor-based systems. Major features include nonvolatile memory available in various sizes, lowVDD reset, watchdog timer, nonvolatile event counter, lockable 64-bit serial number area, and general purpose comparator that can be used for an early power-fail (NMI) interrupt or other purpose. The family operates from 2.7 to 5.5V. The FM32xx family is software and pinout compatible with the FM31xx family which also includes a real-time clock. The common features allow a system design that easily can be assembled with or without timekeeping by simply selecting the FM31xx or FM32xx, respectively. Each FM32xx provides nonvolatile RAM available in sizes including 4Kb, 16Kb, 64Kb, and 256Kb versions. Fast write speed and unlimited endurance allow the memory to serve as extra RAM or conventional nonvolatile storage. This memory is truly nonvolatile rather than battery backed. Ferroelectric Nonvolatile RAM • 4Kb, 16Kb, 64Kb, and 256Kb versions • Unlimited Read/Write Endurance • 10 year Data Retention • NoDelay™ Writes Fast Two-wire Serial Interface • Up to 1 MHz Maximum Bus Frequency • Supports Legacy Timing for 100 kHz & 400 kHz • Device Select Pins for up to 4 Memory Devices • Companion Controlled via 2-wire Interface Easy to Use Configurations • Operates from 2.7 to 5.5V • Small Footprint 14-pin SOIC (-S) o “Green” 14-pin SOIC (-G) • Pin Compatible with FM31xx Series • Low Operating Current • -40°C to +85°C Operation active when VDD drops below a programmable threshold and remains active for 100 ms after VDD rises above the trip point. A programmable watchdog timer runs from 100 ms to 3 seconds. The watchdog timer is optional, but if enabled it will assert the reset signal for 100 ms if not restarted by the host before the timeout. A flag-bit indicates the source of the reset. A general-purpose comparator compares an external input pin to the onboard 1.2V reference. This is useful for generating an early warning power-fail interrupt (NMI) but can be used for any purpose. The family also includes a programmable 64-bit serial number that can be locked making it unalterable. Additionally the FM32xx offers a dual event counter that tracks the number of rising or falling edges detected on dedicated input pins. The counter can optionally be battery backed and even battery operated by attaching a backup power source to the VBAK pin. If VBAK is connected to a battery or capacitor, then events will be counted even in the absence of VDD. The processor companion includes commonly needed CPU support functions. Supervisory functions include a reset output signal controlled by either a low VDD condition or a watchdog timeout. /RST goes This is a product in pre-production phase of development. Device characterization is complete and Ramtron does not expect to change the specifications. Ramtron will issue a Product Change Notice if any specification changes are made. Rev 2.1 Dec. 2004 Ramtron International Corporation 1850 Ramtron Drive, Colorado Springs, CO 80921 (800) 545-FRAM, (719) 481-7000 www.ramtron.com Page 1 of 20 FM3204/16/64/256 Pin Configuration CNT1 1 14 VDD CNT2 2 13 SCL A0 3 12 SDA A1 4 11 NC PFO 5 10 NC RST 6 9 PFI VSS 7 8 VBAK Pin Name CNT1, CNT2 A0, A1 PFO /RST PFI SDA SCL VBAK VDD VSS Function Event Counter Inputs Device Select inputs Early Power-fail Output Reset Input/Output Early Power-fail Input Serial Data Serial Clock Battery-Backup Supply Supply Voltage Ground Ordering Information Base Configuration FM32256 Memory Size 256Kb Operating Voltage 2.7-5.5V Reset Threshold 2.6V, 2.9, 3.9, 4.4V FM3264 64Kb 2.7-5.5V 2.6V, 2.9, 3.9, 4.4V FM3216 16Kb 2.7-5.5V 2.6V, 2.9, 3.9, 4.4V FM3204 4Kb 2.7-5.5V 2.6V, 2.9, 3.9, 4.4V Ordering Part Number FM32256-S FM32256-G FM3264-S FM3264-G FM3216-S FM3216-G FM3204-S FM3204-G Other memory configurations may be available. Please contact the factory for more information. Rev 2.1 Dec. 2004 Page 2 of 20 FM3204/16/64/256 SCL 2-Wire Interface SDA LockOut A1, A0 FRAM Array LockOut RST Watchdog Special Function Registers LV Detect S/N PFI Event Counters + PFO 2.5V 1.2V CNT1 CNT2 + VDD Switched Power VBAK Nonvolatile Battery Backed Figure 1. Block Diagram Pin Descriptions Pin Name A0, A1 Type Input CNT1, CNT2 Input PFO /RST SDA Output I/O I/O SCL Input PFI Input VBAK Supply VDD VSS Supply Supply Rev 2.1 Dec. 2004 Pin Description Device select inputs are used to address multiple memories on a serial bus. To select the device the address value on the two pins must match the corresponding bits contained in the device address. The device select pins are pulled down internally. Event Counter Inputs: These battery-backed inputs increment counters when an edge is detected on the corresponding CNT pin. The polarity is programmable. Power Fail Output: This is the early power-fail output. Active low reset output with weak pull-up. Also input for manual reset. Serial Data & Address: This is a bi-directional line for the two-wire interface. It is open-drain and is intended to be wire-OR’d with other devices on the two-wire bus. The input buffer incorporates a Schmitt trigger for noise immunity and the output driver includes slope control for falling edges. A pull-up resistor is required. Serial Clock: The serial clock line for the two-wire interface. Data is clocked out of the part on the falling edge, and in on the rising edge. The SCL input also incorporates a Schmitt trigger input for noise immunity. Early Power-fail Input: Typically connected to an unregulated power supply to detect an early power failure. This pin should not be left floating. Backup supply voltage: A 3V battery or a large value capacitor. If VDD<3.6V and no backup supply is used, this pin should be tied to VDD. If VDD>3.6V and no backup supply is used, this pin should be left floating and the VBC bit should be set. Supply Voltage. Ground Page 3 of 20 FM3204/16/64/256 Overview The FM32xx family combines a serial nonvolatile RAM with a processor companion. The companion is a highly integrated peripheral including a processor supervisor, a comparator used for early power-fail warning, nonvolatile event counters, and a 64-bit serial number. The FM32xx integrates these complementary but distinct functions that share a common interface in a single package. Although monolithic, the product is organized as two logical devices, the FRAM memory and the companion. From the system perspective they appear to be two separate devices with unique IDs on the serial bus. The FM32xx provides the same functions as the FM31xx with the exception of the real-time clock. This makes it easy to develop a common design that can either include timekeeping by using the FM31xx or exclude it by using the FM32xx. All other features are identical. The register address map is even preserved so that software can be identical. The memory is organized as a stand-alone 2-wire nonvolatile memory with a standard device ID value. The companion functions are accessed under their own 2-wire device ID. This allows the companion functions to be read while maintaining the most recently used memory address. The companion functions are controlled by 16 special function registers. The event counter circuits and related registers are maintained by the power source on the VBAK pin, allowing them to operate from battery or backup capacitor power when VDD drops below a set threshold. Each functional block is described below. Memory Operation The FM32xx is a family of products available in different memory sizes including 4Kb, 16Kb, 64Kb, and 256Kb. The family is software compatible, all versions use consistent two-byte addressing for the memory device. This makes the lowest density device different from its stand-alone memory counterparts but makes them compatible within the entire family. Memory is organized in bytes, for example the 4Kb memory is 512 x 8 and the 256Kb memory is 32,768 x 8. The memory is based on FRAM technology. Therefore it can be treated as RAM and is read or written at the speed of the two-wire bus with no delays for write operations. It also offers effectively unlimited write endurance unlike other nonvolatile memory technologies. The 2-wire interface protocol is described further on page 13. setting as shown in the following table. Based on the setting, the protected addresses cannot be written and the 2-wire interface will not acknowledge any data to protected addresses. The special function registers containing these bits are described in detail below. Write protect addresses None Bottom 1/4 Bottom 1/2 Full array WP1 0 0 1 1 WP0 0 1 0 1 Processor Companion In addition to nonvolatile RAM, the FM32xx family incorporates a highly integrated processor companion. It includes a low voltage reset, a programmable watchdog timer, battery-backed event counters, a comparator for early power-fail detection or other purposes, and a 64-bit serial number. Processor Supervisor Supervisors provide a host processor two basic functions: detection of power supply fault conditions and a watchdog timer to escape a software lockup condition. All FM32xx devices have a reset pin (/RST) to drive the processor reset input during power faults (and power-up) and software lockups. It is an open drain output with a weak internal pull-up to VDD. This allows other reset sources to be wireOR’d to the /RST pin. When VDD is above the programmed trip point, /RST output is pulled weakly to VDD. If VDD drops below the reset trip point voltage level (VTP) the /RST pin will be driven low. It will remain low until VDD falls too low for circuit operation which is the VRST level. When VDD rises again above VTP, /RST will continue to drive low for at least 100 ms (tRPU) to ensure a robust system reset at a reliable VDD level. After tRPU has been met, the /RST pin will return to the weak high state. While /RST is asserted, serial bus activity is locked out even if a transaction occurred as VDD dropped below VTP. A memory operation started while VDD is above VTP will be completed internally. The bits VTP1 and VTP0 control the trip point of the low voltage detect circuit. They are located in register 0Bh, bits 1 and 0. The figure below illustrates the reset operation in response to the VDD voltage. VTP 2.6V 2.9V 3.9V 4.4V VTP1 0 0 1 1 VTP0 0 1 0 1 The memory array can be write-protected by software. Two bits in the processor companion area (WP0, WP1 in register 0Bh) control the protection Rev 2.1 Dec. 2004 Page 4 of 20 FM3204/16/64/256 VDD tRPU VTP RST Figure 2. Low Voltage Reset MCU The watchdog timer can also be used to assert the reset signal (/RST). The watchdog is a free running programmable timer. The period can be software programmed from 100 ms to 3 seconds in 100 ms increments via a 5-bit nonvolatile register. All programmed settings are minimum values and vary with temperature according to the operating specifications. The watchdog has two additional controls associated with its operation, a watchdog enable bit (WDE) and timer restart bits (WR). Both the enable bit must be set and the watchdog must timeout in order to drive /RST active. If a reset event occurs, the timer will automatically restart on the rising edge of the reset pulse. If not enabled, the watchdog timer runs but has no effect on /RST. Note that setting the maximum timeout setting (11111b) disables the counter to save power. The second control is a nibble that restarts the timer preventing a reset. The timer should be restarted after changing the timeout value. The watchdog timeout value is located in register 0Ah, bits 4-0, and the watchdog enable is bit 7. The watchdog is restarted by writing the pattern 1010b to the lower nibble of register 09h. Writing this pattern will also cause the timer to load new timeout values. Writing other patterns to this address will not affect its operation. Note the watchdog timer is freerunning. Prior to enabling it, users should restart the timer as described above. This assures that the full timeout period will be set immediately after enabling. The watchdog is disabled when VDD is below VTP. The following table summarizes the watchdog bits. A block diagram follows. Watchdog timeout Watchdog enable Watchdog restart 100 ms clock Timebase WDT4-0 WDE WR3-0 0Ah, bits 4-0 0Ah, bit 7 09h, bits 3-0 WR3-0 = 1010b to restart Counter Watchdog timeout Manual Reset The /RST pin is bi-directional and allows the FM32xx to filter and de-bounce a manual reset switch. The /RST input detects an external low condition and responds by driving the /RST signal low for 100 ms. RST FM32xx Reset Switch Switch Behavior RST FM32xx drives 100 ms Figure 4. Manual Reset Note that an internal weak pull-up on /RST eliminates the need for additional external components. Reset Flags In case of a reset condition, a flag will be set to indicate the source of the reset. A low VDD reset or manual reset is indicated by the POR flag, register 09h bit 6. A watchdog reset is indicated by the WTR flag, register 09h bit 7. Note that the flags are internally set in response to reset sources, but they must be cleared by the user. When the register is read, it is possible that both flags are set if both have occurred since the user last cleared them. Early Power Fail Comparator An early power fail warning can be provided to the processor well before VDD drops out of spec. The comparator is used to create a power fail interrupt (NMI). This can be accomplished by connecting the PFI pin to the unregulated power supply via a resistor divider. An application circuit is shown below. The voltage on the PFI input pin is compared to an onboard 1.2V reference. When the PFI input voltage drops below this threshold, the comparator will drive the PFO pin to a low state. The comparator has 100 mV (max) of hysteresis to reduce noise sensitivity, only for a rising PFI signal. For a falling PFI edge, there is no hysteresis. /RST WDE Figure 3. Watchdog Timer Rev 2.1 Dec. 2004 Page 5 of 20 FM3204/16/64/256 Regulator VDD FM32xx PFI + To MCU CAL/PFO NMI input - 1.2V ref Figure 5. Comparator as Early Power-Fail Warning The comparator is a general purpose device and its application is not limited to the NMI function. Note: The maximum voltage on the comparator input PFI is limited to 3.75V under normal operating conditions. Event Counter The FM32xx offers the user two battery-backed event counters. Input pins CNT1 and CNT2 are programmable edge detectors. Each clocks a 16-bit counter. When an edge occurs, the counters will increment their respective registers. Counter 1 is located in registers 0Dh and 0Eh, Counter 2 is located in registers 0Fh and 10h. These register values can be read anytime VDD is above VTP, and they will be incremented as long as a valid VBAK power source is provided. To read, set the RC bit register 0Ch bit 3 to 1. This takes a snapshot of all four counter bytes allowing a stable value even if a count occurs during the read. The registers can be written by software allowing the counters to be cleared or initialized by the system. Counts are blocked during a write operation. The two counters can be cascaded to create a single 32-bit counter by setting the CC control bit (register 0Ch). When cascaded, the CNT1 input will cause the counter to increment. CNT2 is not used in this mode. The control bits for event counting are located in register 0Ch. Counter 1 Polarity is bit C1P, bit 0; Counter 2 Polarity is C2P, bit 1; the Cascade Control is CC, bit 2; and the Read Counter bit is RC bit 3. C1P The polarity bits must be set prior to setting the counter value(s). If a polarity bit is changed, the counter may inadvertently increment. Serial Number A memory location to write a 64-bit serial number is provided. It is a writeable nonvolatile memory block that can be locked by the user once the serial number is set. The 8 bytes of data and the lock bit are all accessed via the device ID for the processor companion. Therefore the serial number area is separate and distinct from the memory array. The serial number registers can be written an unlimited number of times, so these locations are general purpose memory. However once the lock bit is set the values cannot be altered and the lock cannot be removed. Once locked the serial number registers can still be read by the system. The serial number is located in registers 11h to 18h. The lock bit is SNL, register 0Bh bit 7. Setting the SNL bit to a 1 disables writes to the serial number registers, and the SNL bit cannot be cleared. Backup Power The event counter and battery-backed registers may be powered with a backup power source. When the primary system power fails, the voltage on the VDD pin will drop. When VDD is less than 2.5V, the event counters and battery-backed registers will switch to the backup power supply on VBAK. When a battery is used as a backup source, VDD must be applied prior to inserting the battery to prevent battery drain. Once VDD is applied and a battery is inserted, the current drain on the battery is guaranteed to be less than IBAK(max). Trickle Charger To facilitate capacitor backup the VBAK pin can optionally provide a trickle charge current. When the VBC bit, register 0Bh bit 2, is set to 1 the VBAK pin will source approximately 15 µA until VBAK reaches VDD or 3.75V whichever is less. In 3V systems, this charges the capacitor to VDD without an external diode and resistor charger. In 5V systems, it provides the same convenience and also prevents the user from exceeding the VBAK maximum voltage specification. 16-bit Counter CNT1 In the case where no battery is used, the VBAK pin should be tied according to the following conditions: C2P CNT2 16-bit Counter CC Figure 6. Event Counter Rev 2.1 Dec. 2004 • For 3.3V systems, VBAK should be tied to VDD. This assumes VDD does not exceed 3.75V. • For 5V systems, attach a 1 µF capacitor to VBAK and turn the trickle charger on. The VBAK pin will charge to the internal backup voltage which regulates itself to about 3.6V. VBAK should not Page 6 of 20 FM3204/16/64/256 be tied to 5V since the VBAK (max) specification will be exceeded. A 1 µF capacitor will keep the companion functions working for about 1.5 second. Although VBAK may be connected to VSS, this is not recommended if the companion is used. None of the companion functions will operate below about 2.5V. ! Note: systems using lithium batteries should clear the VBC bit to 0 to prevent battery charging. The VBAK circuitry includes an internal 1 KΩ series resistor as a safety element. Register Map The processor companion functions are accessed via 16 special function registers that are mapped to a separate 2wire device ID. The interface protocol is described below. The registers contain control bits, or information flags. A description of each register follows. Register Map Summary Table Nonvolatile = Battery-backed = Address 18h 17h 16h 15h 14h 13h 12h 11h 10h 0Fh 0Eh 0Dh 0Ch 0Bh 0Ah 09h 00-08h D7 D6 SNL WDE WTR POR Data D5 D4 D3 Serial Number Byte 7 Serial Number Byte 6 Serial Number Byte 5 Serial Number Byte 4 Serial Number Byte 3 Serial Number Byte 2 Serial Number Byte 1 Serial Number Byte 0 Counter 2 MSB Counter 2 LSB Counter 1 MSB Counter 1 LSB RC WP1 WP0 WDT4 WDT3 LB WR3 DO NOT USE D2 D1 D0 CC VBC WDT2 WR2 C2P VTP1 WDT1 WR1 C1P VTP0 WDT0 WR0 Function Serial Number 7 Serial Number 6 Serial Number 5 Serial Number 4 Serial Number 3 Serial Number 2 Serial Number 1 Serial Number 0 Event Counter 2 MSB Event Counter 2 LSB Event Counter 1 MSB Event Counter 1 LSB Event Count Control Companion Control Watchdog Control Watchdog Restart/Flags RESERVED Range FFh FFh FFh FFh FFh FFh FFh FFh FFh FFh FFh FFh *Note that the usable address range starts at address 09h to preserve software compatibility with the FM31xx device family, which includes a real-time clock in registers 00-08h. Note: When the device is first powered up and programmed, all registers must be written because the batterybacked register values cannot be guaranteed. The table below shows the default values of the non-volatile registers. All other register values should be treated as unknown. Default Register Values Address 18h 17h 16h 15h 14h 13h 12h 11h 0Bh 0Ah Rev 2.1 Dec. 2004 Hex Value 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x1F Page 7 of 20 FM3204/16/64/256 Register Description Address Description 18h Serial Number Byte 7 D7 D6 D5 D4 D3 D2 D1 D0 SN.63 SN.62 SN.61 SN.60 SN.59 SN.58 SN.57 SN.56 Upper byte of the serial number. Read/write when SNL=0, read-only when SNL=1. Nonvolatile. 17h Serial Number Byte 6 D7 D6 D5 D4 D3 D2 D1 D0 SN.55 SN.54 SN.53 SN.52 SN.51 SN.50 SN.49 SN.48 Byte 6 of the serial number. Read/write when SNL=0, read-only when SNL=1. Nonvolatile. 16h Serial Number Byte 5 D7 D6 D5 D4 D3 D2 D1 D0 SN.47 SN.46 SN.45 SN.44 SN.43 SN.42 SN.41 SN.40 Byte 5 of the serial number. Read/write when SNL=0, read-only when SNL=1. Nonvolatile. 15h Serial Number Byte 4 D7 D6 D5 D4 D3 D2 D1 D0 SN.39 SN.38 SN.37 SN.36 SN.35 SN.34 SN.33 SN.32 Byte 4 of the serial number. Read/write when SNL=0, read-only when SNL=1. Nonvolatile. 14h Serial Number Byte 3 D7 D6 D5 D4 D3 D2 D1 D0 SN.31 SN.30 SN.29 SN.28 SN.27 SN.26 SN.25 SN.24 Byte 3 of the serial number. Read/write when SNL=0, read-only when SNL=1. Nonvolatile. 13h Serial Number Byte 2 D7 D6 D5 D4 D3 D2 D1 D0 SN.23 SN.22 SN.21 SN.20 SN.19 SN.18 SN.17 SN.16 Byte 2 of the serial number. Read/write when SNL=0, read-only when SNL=1. Nonvolatile. 12h Serial Number Byte 1 D7 D6 D5 D4 D3 D2 D1 D0 SN.15 SN.14 SN.13 SN.12 SN.11 SN.10 SN.9 SN.8 Byte 1 of the serial number. Read/write when SNL=0, read-only when SNL=1. Nonvolatile. 11h Serial Number Byte 0 D7 D6 D5 D4 D3 D2 D1 D0 SN.7 SN.6 SN.5 SN.4 SN.3 SN.2 SN.1 SN.0 LSB of the serial number. Read/write when SNL=0, read-only when SNL=1. Nonvolatile. 10h Counter 2 MSB D7 D6 D5 D4 D3 D2 D1 D0 C2.15 C2.14 C2.13 C2.12 C2.11 C2.10 C2.9 C2.8 Event Counter 2 MSB. Increments on overflows from Counter 2 LSB. Battery-backed, read/write. 0Fh Counter 2 LSB D7 D6 D5 D4 D3 D2 D1 D0 C2.7 C2.6 C2.5 C2.4 C2.3 C2.2 C2.1 C2.0 Event Counter 2 LSB. Increments on programmed edge event on CNT2 input or overflows from Counter 1 MSB when CC=1. Battery-backed, read/write . 0Eh Counter 1 MSB D7 D6 D5 D4 D3 D2 D1 D0 C1.15 C1.14 C1.13 C1.12 C1.11 C1.10 C1.9 C1.8 Event Counter 1 MSB. Increments on overflows from Counter 1 LSB. Battery-backed, read/write. 0Dh Counter 1 LSB D7 D6 D5 D4 D3 D2 D1 D0 C1.7 C1.6 C1.5 C1.4 C1.3 C1.2 C1.1 C1.0 Event Counter 1 LSB. Increments on programmed edge event on CNT1 input. Battery-backed, read/write. Rev 2.1 Dec. 2004 Page 8 of 20 FM3204/16/64/256 0Ch RC CC C2P C1P 0Bh SNL WP1-0 Event Counter Control D7 D6 D5 D4 D3 D2 D1 D0 - - - - RC CC C2P C1P Read Counter. Setting this bit to 1 takes a snapshot of the four counters bytes allowing the system to read the values without missing count events. The RC bit will be automatically cleared. Counter Cascade. When CC=0, the event counters operate independently according to the edge programmed by C1P and C2P respectively. When CC=1, the counters are cascaded to create one 32-bit counter. The registers of Counter 2 represent the most significant 16-bits of the counter and CNT1 is the controlling input. Bit C2P is “don’t care” when CC=1. Battery-backed, read/write. CNT2 detects falling edges when C2P = 0, rising edges when C2P = 1. C2P is “don’t care” when CC=1. The value of Event Counter 2 may inadvertently increment if C2P is changed. Battery-backed, read/write. CNT1 detects falling edges when C1P = 0, rising edges when C1P = 1. The value of Event Counter 1 may inadvertently increment if C1P is changed. Battery-backed, read/write. Companion Control D7 D6 D5 D4 D3 D2 D1 D0 SNL - - WP1 WP0 VBC VTP1 VTP0 Serial Number Lock. Setting to a 1 makes registers 11h to 18h and SNL permanently read-only. SNL cannot be cleared once set to 1. Nonvolatile, read/write. Write Protect. These bits control the write protection of the memory array. Nonvolatile, read/write. Write protect addresses None Bottom 1/4 Bottom 1/2 Full array VBC WP1 0 0 1 1 WP0 0 1 0 1 VTP1-0 VBAK Charger Control. Setting VBC to 1 causes a 15 µA trickle charge current to be supplied on VBAK. Clearing VBC to 0 disables the charge current. Nonvolatile, read/write. VTP select. These bits control the reset trip point for the low VDD reset function. Nonvolatile, read/write. 0Ah VTP 2.6V 2.9V 3.9V 4.4V Watchdog Control WDE WDT4-0 VTP1 0 0 1 1 D7 D6 D5 D4 D3 D2 D1 D0 WDE - - WDT4 WDT3 WDT2 WDT1 WDT0 Watchdog Enable. When WDE=1 the watchdog timer can cause the /RST signal to go active. When WDE = 0 the timer runs but has no effect on /RST. Note as the timer is free-running, users should restart the timer using WR3-0 prior to setting WDE=1. This assures a full watchdog timeout interval occurs. Nonvolatile, read/write. Watchdog Timeout. Indicates the minimum watchdog timeout interval with 100 ms resolution. New watchdog timeouts are loaded when the timer is restarted by writing the 1010b pattern to WR3-0. Nonvolatile, read/write. Watchdog timeout Invalid – default 100 ms 100 ms 200 ms 300 ms . . . 2000 ms 2100 ms 2200 ms . . . 2900 ms 3000 ms Disable counter Rev 2.1 Dec. 2004 VTP0 0 1 0 1 WDT4 WDT3 WDT2 WDT1 WDT0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 1 1 1 1 1 0 0 0 1 1 1 0 0 1 0 1 0 1 1 1 1 1 1 1 1 1 0 1 1 1 0 1 Page 9 of 20 FM3204/16/64/256 09h WTR POR LB WR3-0 00-08h Rev 2.1 Dec. 2004 Watchdog Restart & Flags D7 D6 D5 D4 D3 D2 D1 D0 WTR POR LB - WR3 WR2 WR1 WR0 Watchdog Timer Reset Flag: When the /RST signal is activated by the watchdog the WTR bit will be set to 1. It must be cleared by the user. Note that both WTR and POR could be set if both reset sources have occurred since the flags were cleared by the user. Battery-backed. Read/Write (internally set, user can clear bit). Power-on Reset Flag: When the /RST pin is activated by either VDD < VTP or a manual reset, the POR bit will be set to 1. It must be cleared by the user. Note that both WTR and POR could be set if both reset sources have occurred since the flags were cleared by the user. Battery-backed. Read/Write (internally set, user can clear bit). Low Backup Flag: On power up, if the VBAK source is below the minimum voltage to operate the event counters, this bit will be set to 1. The user should clear it to 0 when initializing the system. Battery-backed. Read/Write (internally set, user can clear bit). Watchdog Restart: Writing a pattern 1010b to WR3-0 restarts the watchdog timer. The upper nibble contents do not affect this operation. Writing any pattern other than 1010b to WR3-0 has no effect on the timer. This allows users to clear the WTR, POR, and LB flags without affecting the watchdog timer. Write-only. Reserved – DO NOT USE THIS ADDRESS SPACE Page 10 of 20 FM3204/16/64/256 By convention, any device that is sending data onto the bus is the transmitter while the target device for this data is the receiver. The device that is controlling the bus is the master. The master is responsible for generating the clock signal for all operations. Any device on the bus that is being controlled is a slave. The FM32xx is always a slave device. Two-wire Interface The FM32xx employs an industry standard two-wire bus that is familiar to many users. This product is unique since it incorporates two logical devices in one chip. Each logical device can be accessed individually. Although monolithic, it appears to the system software to be two separate products. One is a memory device. It has a Slave Address (Slave ID = 1010b) that operates the same as a stand-alone memory device. The second device is a real-time clock and processor companion which have a unique Slave Address (Slave ID = 1101b). The bus protocol is controlled by transition states in the SDA and SCL signals. There are four conditions: Start, Stop, Data bit, and Acknowledge. The figure below illustrates the signal conditions that specify the four states. Detailed timing diagrams are shown in the Electrical Specifications section. SCL 7 SDA Stop (Master) 0 Start Data bits Data bit Acknowledge (Master) (Transmitter) (Transmitter) (Receiver) Figure 7. Data Transfer Protocol Start Condition A Start condition is indicated when the bus master drives SDA from high to low while the SCL signal is high. All read and write transactions begin with a Start condition. An operation in progress can be aborted by asserting a Start condition at any time. Aborting an operation using the Start condition will ready the FM32xx for a new operation. If the power supply drops below the specified VTP during operation, any 2-wire transaction in progress will be aborted and the system must issue a Start condition prior to performing another operation. Stop Condition A Stop condition is indicated when the bus master drives SDA from low to high while the SCL signal is high. All operations must end with a Stop condition. If an operation is pending when a stop is asserted, the operation will be aborted. The master must have control of SDA (not a memory read) in order to assert a Stop condition. Data/Address Transfer All data transfers (including addresses) take place while the SCL signal is high. Except under the two conditions described above, the SDA signal should not change while SCL is high. Rev 2.1 Dec. 2004 6 Acknowledge The Acknowledge (ACK) takes place after the 8th data bit has been transferred in any transaction. During this state the transmitter must release the SDA bus to allow the receiver to drive it. The receiver drives the SDA signal low to acknowledge receipt of the byte. If the receiver does not drive SDA low, the condition is a No-Acknowledge (NACK) and the operation is aborted. The receiver might NACK for two distinct reasons. First is that a byte transfer fails. In this case, the NACK ends the current operation so that the part can be addressed again. This allows the last byte to be recovered in the event of a communication error. Second and most common, the receiver does not send an ACK to deliberately terminate an operation. For example, during a read operation, the FM32xx will continue to place data onto the bus as long as the receiver sends ACKs (and clocks). When a read operation is complete and no more data is needed, the receiver must NACK the last byte. If the receiver ACKs the last byte, this will cause the FM32xx to attempt to drive the bus on the next clock while the master is sending a new command such as a Stop. Page 11 of 20 FM3204/16/64/256 Slave Address The first byte that the FM32xx expects after a Start condition is the slave address. As shown in figures below, the slave address contains the Slave ID, Device Select address, and a bit that specifies if the transaction is a read or a write. The FM32xx has two Slave Addresses (Slave IDs) associated with two logical devices. To access the memory device, bits 7-4 should be set to 1010b. The other logical device within the FM32xx is the realtime clock and companion. To access this device, bits 7-4 of the slave address should be set to 1101b. A bus transaction with this slave address will not affect the memory in any way. The figures below illustrate the two Slave Addresses. The Device Select bits allow multiple devices of the same type to reside on the 2-wire bus. The device select bits (bits 2-1) select one of four parts on a twowire bus. They must match the corresponding value on the external address pins in order to select the device. Bit 0 is the read/write bit. A “1” indicates a read operation, and a “0” indicates a write operation. Device Select Slave ID 1 7 0 1 0 X A1 A0 R/W 6 5 4 3 2 1 0 Figure 8. Slave Address - Memory Device Select Slave ID 1 7 1 0 1 X A1 A0 R/W 6 5 4 3 2 1 0 Figure 9. Slave Address – Companion Addressing Overview – Memory After the FM32xx acknowledges the Slave Address, the master can place the memory address on the bus for a write operation. The address requires two bytes. This is true for all members of the family. Therefore the 4Kb and 16Kb configurations will be addressed differently from stand alone serial memories but the entire family will be upwardly compatible with no software changes. The first is the MSB (upper byte). For a given density unused address bits are don’t cares, but should be set to 0 to maintain upward compatibility. Rev 2.1 Dec. 2004 Following the MSB is the LSB (lower byte) which contains the remaining eight address bits. The address is latched internally. Each access causes the latched address to be incremented automatically. The current address is the value that is held in the latch, either a newly written value or the address following the last access. The current address will be held as long as VDD > VTP or until a new value is written. Accesses to the clock do not affect the current memory address. Reads always use the current address. A random read address can be loaded by beginning a write operation as explained below. After transmission of each data byte, just prior to the Acknowledge, the FM32xx increments the internal address. This allows the next sequential byte to be accessed with no additional addressing externally. After the last address is reached, the address latch will roll over to 0000h. There is no limit to the number of bytes that can be accessed with a single read or write operation. Addressing Overview – Companion The Processor Companion operate in a similar manner to the memory, except that it uses only one byte of address. Addresses 00h to 18h correspond to special function registers. Attempting to load addresses above 18h is an illegal condition; the FM32xx will return a NACK and abort the 2-wire transaction. Data Transfer After the address information has been transmitted, data transfer between the bus master and the FM32xx begins. For a read, the FM32xx will place 8 data bits on the bus then wait for an ACK from the master. If the ACK occurs, the FM32xx will transfer the next byte. If the ACK is not sent, the FM32xx will end the read operation. For a write operation, the FM32xx will accept 8 data bits from the master then send an Acknowledge. All data transfer occurs MSB (most significant bit) first. Memory Write Operation All memory writes begin with a Slave Address, then a memory address. The bus master indicates a write operation by setting the slave address LSB to a 0. After addressing, the bus master sends each byte of data to the memory and the memory generates an Acknowledge condition. Any number of sequential bytes may be written. If the end of the address range is reached internally, the address counter will wrap to 0000h. Internally, the actual memory write occurs after the 8th data bit is transferred. It will be complete before the Acknowledge is sent. Therefore, if the user desires to abort a write without altering the memory contents, this should be done using a Start Page 12 of 20 FM3204/16/64/256 or Stop condition prior to the 8th data bit. The figures below illustrate a single- and multiple-writes to Start By Master S memory. Stop Address & Data Slave Address 0 A Address MSB By FM32xx A Address LSB A Data Byte A P Acknowledge Figure 10. Single Byte Memory Write Start Stop Address & Data By Master S By FM32xx Slave Address 0 A Address MSB A Address LSB A Data Byte A Data Byte A P Acknowledge Figure 11. Multiple Byte Memory Write Memory Read Operation There are two types of memory read operations. They are current address read and selective address read. In a current address read, the FM32xx uses the internal address latch to supply the address. In a selective read, the user performs a procedure to first set the address to a specific value. Current Address & Sequential Read As mentioned above the FM32xx uses an internal latch to supply the address for a read operation. A current address read uses the existing value in the address latch as a starting place for the read operation. The system reads from the address immediately following that of the last operation. To perform a current address read, the bus master supplies a slave address with the LSB set to 1. This indicates that a read operation is requested. After receiving the complete device address, the FM32xx will begin shifting data out from the current address on the next clock. The current address is the value held in the internal address latch. Beginning with the current address, the bus master can read any number of bytes. Thus, a sequential read is simply a current address read with multiple byte transfers. After each byte the internal address counter will be incremented. Rev 2.1 Dec. 2004 Each time the bus master acknowledges a byte, this indicates that the FM32xx should read out the next sequential byte. There are four ways to terminate a read operation. Failing to properly terminate the read will most likely create a bus contention as the FM32xx attempts to read out additional data onto the bus. The four valid methods follow. 1. 2. 3. 4. The bus master issues a NACK in the 9th clock cycle and a Stop in the 10th clock cycle. This is illustrated in the diagrams below and is preferred. The bus master issues a NACK in the 9th clock cycle and a Start in the 10th. The bus master issues a Stop in the 9th clock cycle. The bus master issues a Start in the 9th clock cycle. If the internal address reaches the top of memory, it will wrap around to 0000h on the next read cycle. The figures below show the proper operation for current address reads. Selective (Random) Read There is a simple technique that allows a user to select a random address location as the starting point for a read operation. This involves using the first Page 13 of 20 FM3204/16/64/256 master supplies a Slave Address with the LSB set to 1. This indicates that a read operation is requested. After receiving the complete Slave Address, the FM32xx will begin shifting data out from the current register address on the next clock. Auto-increment operates for the special function registers as with the memory address. A current address read for the registers look exactly like the memory except that the device ID is different. three bytes of a write operation to set the internal address followed by subsequent read operations. To perform a selective read, the bus master sends out the slave address with the LSB set to 0. This specifies a write operation. According to the write protocol, the bus master then sends the address bytes that are loaded into the internal address latch. After the FM32xx acknowledges the address, the bus master issues a Start condition. This simultaneously aborts the write operation and allows the read command to be issued with the slave address LSB set to a 1. The operation is now a read from the current address. Read operations are illustrated below. The FM32xx contains two separate address registers, one for the memory address and the other for the register address. This allows the contents of one address register to be modified without affecting the current address of the other register. For example, this would allow an interrupted read to the memory while still providing fast access to a companion register. A subsequent memory read will then continue from the memory address where it previously left off, without requiring the load of a new memory address. However, a write sequence always requires an address to be supplied. Companion Write Operation All Companion writes operate in a similar manner to memory writes. The distinction is that a different device ID is used and only one byte of address is needed instead of two. Figure 15 illustrates a single byte write to this device. Companion Read Operation As with writes, a read operation begins with the Slave Address. To perform a register read, the bus By Master Start No Acknowledge Address Stop Slave Address S By FM32xx 1 A Acknowledge Data Byte 1 P Data Figure 12. Current Address Memory Read By Master Start Address No Acknowledge Acknowledge Stop S By FM32xx Slave Address 1 A Acknowledge Data Byte A Data Byte 1 P Data Figure 13. Sequential Memory Read Rev 2.1 Dec. 2004 Page 14 of 20 FM3204/16/64/256 Start Address By Master Start No Acknowledge Address Stop S Slave Address 0 A Address MSB A By FM32xx A Address LSB S Slave Address 1 A 1 P Data Byte Data Acknowledge Figure 14. Selective (Random) Memory Read By Master Address & Data Start Slave Address S 0 A 0 0 0 Address By FM32xx Stop Data Byte A A P Acknowledge Figure 15. Byte Register Write * Although not required, it is recommended that A5-A7 in the Register Address byte are zeros in order to preserve compatibility with future devices. Addressing FRAM Array in the FM32xx Family The FM32xx family includes 256Kb, 64Kb, 16Kb, and 4Kb memory densities. The following 2-byte address field is shown for each density. Table 4. Two-Byte Memory Address Part # 1st Address Byte FM32256 FM3264 FM3216 FM3204 Rev 2.1 Dec. 2004 x x x x A14 x x x A13 x x x A12 A12 x x A11 A11 x x 2nd Address Byte A10 A10 A10 x A9 A9 A9 x A8 A8 A8 A8 A7 A7 A7 A7 A6 A6 A6 A6 A5 A5 A5 A5 A4 A4 A4 A4 A3 A3 A3 A3 A2 A2 A2 A2 A1 A1 A1 A1 A0 A0 A0 A0 Page 15 of 20 FM3204/16/64/256 Electrical Specifications Absolute Maximum Ratings Symbol Description VDD Power Supply Voltage with respect to VSS VIN Voltage on any signal pin with respect to VSS VBAK TSTG TLEAD Backup Supply Voltage Storage Temperature Lead Temperature (Soldering, 10 seconds) Ratings -1.0V to +7.0V -1.0V to +7.0V * and VIN ≤ VDD+1.0V ** -1.0V to +4.5V -55°C to + 125°C 300° C * PFI input voltage must not exceed 4.5V. ** The “VIN < VDD+1.0V” restriction does not apply to the SCL and SDA inputs which do not employ a diode to VDD. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only, and the functional operation of the device at these or any other conditions above those listed in the operational section of this specification is not implied. Exposure to absolute maximum ratings conditions for extended periods may affect device reliability. DC Operating Conditions (TA = -40° C to + 85° C, VDD = 2.7V to 5.5V unless otherwise specified) Symbol Parameter Min Typ Max VDD Main Power Supply 2.7 5.5 IDD VDD Supply Current 500 @ SCL = 100 kHz 900 @ SCL = 400 kHz 1500 @ SCL = 1 MHz ISB Standby Current For VDD < 5.5V 150 For VDD < 3.6V 120 VBAK Backup Supply Voltage 2.0 3.0 3.75 IBAK Backup Supply Current 1 IBAKTC Trickle Charge Current 5 25 VTP0 VDD Trip Point Voltage, VTP(1:0) = 00b 2.55 2.6 2.70 VTP1 VDD Trip Point Voltage, VTP(1:0) = 01b 2.85 2.9 3.00 VTP2 VDD Trip Point Voltage, VTP(1:0) = 10b 3.80 3.9 4.00 VTP3 VDD Trip Point Voltage, VTP(1:0) = 11b 4.25 4.4 4.50 VRST VDD for valid /RST @ IOL = 80 µA at VOL 0 VBAK > VBAK min 1.6 VBAK < VBAK min ILI Input Leakage Current 1 ILO Output Leakage Current 1 VIL Input Low Voltage 0.3 VDD -0.3 All inputs except those listed below -0.3 CNT1-2 battery backed (VDD < 2.5V) 0.5 -0.3 CNT1-2 (VDD > 2.5V) 0.8 VIH Input High Voltage 0.7 VDD VDD + 0.3 All inputs except those listed below PFI (comparator input) 3.75 CNT1-2 battery backed (VDD < 2.5V) VBAK + 0.3 VBAK – 0.5 CNT1-2 VDD > 2.5V 0.7 VDD VDD + 0.3 VOL Output Low Voltage (IOL = 3 mA) 0.4 VOH Output High Voltage (IOH = -2 mA) 2.4 RRST Pull-up resistance for /RST inactive 50 400 RIN Input Resistance (pulldown) A1-A0 for VIN = VIL max 20 1 A1-A0 for VIN = VIH min VPFI Power Fail Input Reference Voltage 1.175 1.20 1.225 VHYS Power Fail Input (PFI) Hysteresis (Rising) 100 Rev 2.1 Dec. 2004 Units V Notes 7 1 µA µA µA 2 µA µA V µA µA V V V V V V µA µA V V V 9 4 10 5 5 5 5 6 3 3 8 V V V V V V KΩ KΩ MΩ V mV Page 16 of 20 FM3204/16/64/256 Notes 1. SCL toggling between VDD-0.3V and VSS, other inputs VSS or VDD-0.3V. 2. All inputs at VSS or VDD, static. Stop command issued. 3. VIN or VOUT = VSS to VDD. Does not apply to A0, A1, PFI, or /RST pins. 4. VBAK = 3.0V, VDD < 2.4V, CNT1-2 at VBAK. 5. /RST is asserted low when VDD < VTP. 6. The minimum VDD to guarantee the level of /RST remains a valid VOL level. 7. Full complete operation. Supervisory circuits operate to lower voltages as specified. 8. Includes /RST input detection of external reset condition to trigger driving of /RST signal by FM32xx. 9. The VBAK trickle charger automatically regulates the maximum voltage on this pin for capacitor backup applications. 10. VBAK will source current when trickle charge is enabled (VBC bit=1), VDD > VBAK, and VBAK < VBAK max. AC Parameters (TA = -40° C to + 85° C, VDD = 2.7V to 5.5V, CL = 100 pF unless otherwise specified) Symbol Parameter Min Max Min Max Min Max fSCL SCL Clock Frequency 0 100 0 400 0 1000 tLOW Clock Low Period 4.7 1.3 0.6 tHIGH Clock High Period 4.0 0.6 0.4 tAA SCL Low to SDA Data Out Valid 3 0.9 0.55 tBUF tHD:STA tSU:STA tHD:DAT tSU:DAT tR tF tSU:STO tDH tSP Bus Free Before New Transmission Start Condition Hold Time Start Condition Setup for Repeated Start Data In Hold Time Data In Setup Time Input Rise Time Input Fall Time Stop Condition Setup Time Data Output Hold (from SCL @ VIL) Noise Suppression Time Constant on SCL, SDA Units kHz µs µs µs 4.7 4.0 4.7 1.3 0.6 0.6 0.5 0.25 0.25 µs µs µs 0 250 0 100 0 100 ns ns ns ns µs ns ns 1000 300 4.0 0 300 300 0.6 0 50 300 100 0.25 0 50 50 Notes 1 1 All SCL specifications as well as start and stop conditions apply to both read and write operations. Supervisor Timing (TA = -40° C to + 85° C, VDD = 2.7V to 5.5V) Symbol Parameter tRPU Reset active after VDD>VTP tRNR VDD < VTP noise immunity tVR VDD Rise Time tVF VDD Fall Time tWDP Pulse Width of /RST for Watchdog Reset tWDOG Timeout of Watchdog fCNT Frequency of Event Counters Data Retention (TA = -40° C to + 85° C, VDD = 2.7V to 5.5V) Parameter Min Data Retention 10 Capacitance (TA = 25° C, f=1.0 MHz, VDD = 3.0V) Symbol Parameter CIO Input/output capacitance Max 8 Min 100 10 50 100 100 tDOG 0 Units Years Max 200 25 200 2*tDOG 10 Units ms µs µs/V µs/V ms ms MHz Notes 1 1,2 1,2 3 Notes Units pF Notes 1 Notes 1 This parameter is characterized but not tested. 2 Slope measured at any point on VDD waveform. 3 tDOG is the programmed time in register 0Ah, VDD > VTP and tRPU satisfied. Rev 2.1 Dec. 2004 Page 17 of 20 FM3204/16/64/256 AC Test Conditions Equivalent AC Load Circuit Input Pulse Levels Input rise and fall times Input and output timing levels 5.5V 0.1 VDD to 0.9 VDD 10 ns 0.5 VDD 1700 Ω Diagram Notes All start and stop timing parameters apply to both read and write cycles. Clock specifications are identical for read and write cycles. Write timing parameters apply to slave address, word address, and write data bits. Functional relationships are illustrated in the relevant data sheet sections. These diagrams illustrate the timing parameters only. Output 100 pF Read Bus Timing tR ` tF tHIGH tSP tLOW tSP SCL tSU:SDA 1/fSCL tBUF tHD:DAT tSU:DAT SDA Start tDH tAA Stop Start Acknowledge Write Bus Timing tHD:DAT SCL tHD:STA tSU:STO tSU:DAT tAA SDA Start Stop Start Acknowledge /RST Timing VDD VTP VRST t RNR t RPU RST Rev 2.1 Dec. 2004 Page 18 of 20 FM3204/16/64/256 Mechanical Drawing 14-pin SOIC (JEDEC Standard MS-012 variation AB) Refer to JEDEC MS-012 for complete dimensions and notes. All dimensions in millimeters. SOIC Package Marking Scheme XXXXXXX-P LLLLLLL RIC YYWW Legend: XXXX= part number, P= package type (-S, -G) LLLLLLL= lot code RIC=Ramtron Int’l Corp, YY=year, WW=work week Example: FM32256, Standard SOIC package, Year 2004, Work Week 40 FM32256-S A40003S RIC 0440 Rev 2.1 Dec. 2004 Page 19 of 20 FM3204/16/64/256 Revision History Revision 0.2 0.21 1.0 Date 5/22/03 11/25/03 3/30/04 2.0 10/25/04 2.1 12/8/04 Rev 2.1 Dec. 2004 Summary Initial release. Fixed package drawing dimensions. Changed product status to Preliminary. Added VTP and VPFI parameters in DC Operating table. Changed VHYS limits. Added “green” package. Changed to Pre-Production status. Added text to Trickle Charger section. Improved spec limits on VTP, VPFI, and VHYS parameters and changed VIH max limits in DC Operating table. Added companion register table with default values. Added Package Marking Scheme and board footprint. Devices marked with Date Codes 0440 and higher comply with the revision of the datasheet. Changed description of POR flag and manual reset (pg. 5, 10). Added notes to Absolute Maximum Ratings. Page 20 of 20