ETC GF9105ACQQ

MultiGENTM GF9105A
Component Digital Transcoder
DATA SHEET
FEATURES
DEVICE OVERVIEW
• drop in replacement for the GF9105 with lower power
and increased functionality
The GF9105A is a drop in replacement for the GF9105 with
lower power and increased functionality. This increased
functionality gives the user the option of having HVF output
signals and the option of using a low frequency clock when
operating with non-multiplexed input and output data. The
GF9105A is a flexible VDSP engine capable of performing a
variety of format conversions. The flexible architecture of
the GF9105A also allows the user to perform a wide range
of DSP functions that require a general 3X3 multiplier
structure and/or high performance 1:2 interpolation and 2:1
decimation filters. Device configuration is selected by
writing
configuration words through an asynchronous
parallel interface (HOST IF).
• new mode for HVF output
• new mode for using low frequency clocks with nonmultiplexed I/O data
• optimized HOST IF control signals for ensured shared
bus compatibility
• multiple format conversions from one device
4:2:2:4 <-> 4:4:4:4
4:2:2:4 <-> R/G/B/KEY
4:2:2:4 <-> Y/U/V/KEY
Y/U/V/KEY <-> R/G/B/KEY
4:4:4:4 <-> R/G/B/KEY
4:4:4:4 <-> Y/U/V/KEY
• ITU-R-601 compliant interpolation/decimation filters
• supports both single link 4:4:4:4 (SMPTE RP174) and
dual link 4:4:4:4 (SMPTE RP175) compliant I/O
• transparent conversions between Y/U/V and R/G/B
color spaces.
• fully programmable 3X3 Color Space Converter (CSC)
• 13 bit Color Space Converter coefficients
• 13 bit KEY Channel scaling coefficient
• multiplexed and non-multiplexed I/O data
• bi-directional I/O data ports with tri-stating
• parallel HOST IF for reading and writing multiplier
coefficients and device configuration words
• single +5V power supply.
ORDERING INFORMATION
PART NUMBER
PACKAGE
GF9105ACQQ
Y/G, CB/B, CR/R, KEY OR
Y/G, CB/B, CR/R, OR Y/G
The GF9105A accepts either multiplexed or nonmultiplexed input data and may produce either multiplexed
or non-multiplexed output data. External H, V and F inputs
allow for the insertion of TRS words into multiplexed output
data streams.
All interpolation and decimation filtering required for ITU-R601 compliant 4:2:2:4 <-> 4:4:4:4 sample rate conversions
has been integrated into the GF9105A. In addition, all input
and output offset adjustments required for transparent
conversions between the Y/U/V and R/G/B color spaces
have been included within the GF9105A.
The color space converter within the GF9105A has 13 bit
multiplier coefficients, has 13 bit output resolution,
maintains full precision throughout the 3X3 calculation and
has a true unity gain by-pass mode. Sufficient resolution is
maintained within the color space converter to ensure that
truly transparent Y/U/V <-> R/G/B conversions may be
achieved. A user programmable output clipper allows the
GF9105A to output a variety of word lengths to meet
specific system requirements.
The GF9105A is packaged in a 160 pin MQFP package,
operates from a single +5V supply.
160 Pin MQFP
13
13
Y/G
13
XX OR CB/B
13
XX OR CR/R
DEMUX
4:4:4:4
OR
4:2:2:4
CB/B
CR/R
Y/G
H_BLANK
AND
INPUT
OFFSET
ADJUST
Y/G
INT
CB/B
CB/B
Y/G
3X3
MATRIX
MULTIPLIER
Y/G
CB/B
KEY
KEY
Y/G, CB/B, CR/R, KEY OR
Y/G, CB/B, CR/R, OR Y/G
13
CB/B
DEC
CR/R
Y/G
DEC
INT
CR/R
Y/G
CR/R
CR/R
KEY
KEY
OUTPUT
OFFSET
ADJUST
CB/B
OUTPUT
CLIP
CB/B
OUTPUT
MULTIPLEXER
CB/B OR XX
13
CR/R OR XX
CR/R
CR/R
KEY
KEY
11
11
KEY OR KEY, CB/B, CR/R
KEY SCALER
KEY, CB/B, CR/R OR KEY
KEY
GENERAL FUNCTIONALITY OF GF9105A CORE
Revision Date: March 2000
Document No. 521 - 88 - 03
GENNUM CORPORATION P.O. Box 489, Stn. A, Burlington, Ontario, Canada L7R 3Y3
Tel. +1 (905) 632-2996 Fax. +1 (905) 632-5946 E-mail: [email protected]
www.gennum.com
PIN DESCRIPTION
PIN NO.
SYMBOL
DESCRIPTION
11, 20, 51, 60, 80,
101, 121, 141, 150
VDD
+5 V ±5% power supply.
4, 7, 10, 14, 21, 43,
52, 61, 63, 72, 81, 88,
96, 100, 105, 113,
120, 129, 138, 140,
149, 158
GND
Ground.
147, 148, 151-157,
159, 160, 1, 2
P112..0
Data Port No. 1: Depending on device configuration, P112..0 may operate as an input data port or
an output data port. Note: When HVF output is enabled H is always presented on P112 regardless
of the state of INPUT/OUTPUT.
131-137, 139, 142146
P212..0
Data Port No. 2: Depending on device configuration, P212..0 may operate as an input data port or
an output data port. Note: When HVF output is enabled V is always presented on P212 regardless
of the state of INPUT/OUTPUT.
115-119, 122-128,
130
P312..0
Data Port No. 3: Depending on device configuration, P312..0 may operate as an input data port or
an output data port. Note: When HVF output is enabled F is always presented on P312 regardless
of the state of INPUT/OUTPUT.
102-104, 106-112,
114
P410..0
54, 53, 50-44, 42-39
P512..0
Data Port No. 4: Depending on device configuration, P410..0 may operate as an input data port or
an output data port.
Data Port No. 5: Depending on device configuration, P512..0 may operate as an input data port or
an output data port.
70-64, 62, 59-55
P612..0
Data Port No. 6: Depending on device configuration, P612..0 may operate as an input data port or
an output data port.
86-82, 79-73, 71
P712..0
Data Port No. 7: Depending on device configuration, P712..0 may operate as an input data port or
an output data port.
P810..0
Data Port No. 8: Depending on device configuration, P810..0 may operate as an input data port or
an output data port.
22
SYNC_CB
Synchronization: Control signal input. SYNC_CB is used to synchronize the GF9105A to
the incoming data stream.
24
H_BLANK
Horizontal Blanking: Control signal input. H_BLANK is used to replace portions of the
input data with a user selectable set of blanking levels.
25
DP_EN
Data Port Enable: Control signal input. DP_EN is used to enable and disable data
ports P1 - P8.
17
H
Horizontal: Control signal input. H identifies the horizontal blanking interval for the
output multiplexer.
16
V
Vertical: Control signal input. V identifies the vertical blanking interval for the output
multiplexer.
18
F
Field: Control signal input. F is used to identify field information for the output
multiplexer.
26
CS
Chip Select: Host interface control signal input.
23
R/W
Read/Write: Host interface control signal input.
99-97, 95-89, 87
27-31
3, 5, 6, 8, 9, 12, 13,
15
ADDR4..0
COEFF_PORT7..0
Coefficient Address: Input port to identify which GF9105A device address shall be
written to/read from.
Coefficient Port: Host interface bi-directional data port for Color Space Converter
coefficients, KEY scaler coefficient and device configuration words.
19
CLK
System Clock: All timing information is relative to the rising edge of CLK.
32
TCK
JTAG Test Clock Input: Independent clock signal for JTAG.
521 - 88 - 03
2
PIN DESCRIPTION
PIN NO.
SYMBOL
DESCRIPTION
33
TDI
JTAG Test Data Input: Serial input for JTAG test data.
34
TMS
JTAG Test Mode Select: Serial input for selecting JTAG test mode.
35
TRST
JTAG Test Reset: Connect to GND for normal operation.
36
TDO
JTAG Test Data Output: Serial output for JTAG test data.
37
TN_IN
38
PTO
54
53
50
49
48
47
46
45
44
42
41
40
39
131
132
133
134
135
136
137
139
142
143
144
145
146
P212/VOUT
P211
P210
P29
P28
P27
P26
P25
P24
P23
P22
P21
P20
P612
P611
P610
P69
P68
P67
P66
P65
P64
P63
P62
P61
P60
70
69
68
67
66
65
64
62
59
58
57
56
55
115
116
117
118
119
122
123
124
125
126
127
128
130
P312/FOUT
P311
P310
P39
P38
P37
P36
P35
P34
P33
P32
P31
P30
P712
P711
P710
P79
P78
P77
P76
P75
P74
P73
P72
P71
P70
86
85
84
83
82
79
78
77
76
75
74
73
71
P810
P89
P88
P87
P86
P85
P84
P83
P82
P81
P80
99
98
97
95
94
93
92
91
90
89
87
JTAG
P712..0
P810..0
37
38
COEFF_PORT7
COEFF_PORT6
COEFF_PORT5
COEFF_PORT4
COEFF_PORT3
COEFF_PORT2
COEFF_PORT1
COEFF_PORT0
P612..0
VDD
N.C
3
5
6
8
9
12
13
15
TCK
TDI
TMS
TRST
TDO
ADDR4
ADDR3
ADDR2
ADDR1
ADDR0
CS
R/W
27
28
29
30
31
CLK
P410
P49
P48
P47
P46
P45
P44
P43
P42
P41
P40
32
33
34
35
36
102
103
104
106
107
108
109
110
111
112
114
GF9105A
P512..0
TN_IN
PTO
P512
P511
P510
P59
P58
P57
P56
P55
P54
P53
P52
P51
P50
19
P410..0
P112/HOUT
P111
P110
P19
P18
P17
P16
P15
P14
P13
P12
P11
P10
26
23
P312..0
147
148
151
152
153
154
155
156
157
159
160
1
2
SYNC_CB
H_BLANK
DP_EN
H
V
F
P212..0
No Connect.
22
24
25
17
16
18
P112..0
Connect to VDD.
Fig. 1 GF9105A Data Pin Designations
3
521 - 88 - 03
8
GND
P7
9
10
P7
P7
12
0
1
P711
P7
P8
2
3
GND
P8
P8
4
121
91 90 89 88 87 86 85 84 83 82 81
80
P3
122
79
P77
P36
123
78
P76
P35
124
77
P75
P34
125
76
P74
P3
126
75
P73
127
74
P72
P31
128
73
P7
GND
129
72
GND
P30
130
71
P70
P212/VOUT
131
70
P612
132
69
P611
P210
133
68
P610
P2
134
67
P69
P28
135
66
P6
P27
136
65
P6
P26
137
64
P6
GND
138
63
GND
62
P65
61
GND
60
VDD
P3
P2
7
3
2
11
9
120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92
P8
6
5
P8
P8
7
P8
P8
8
9
GND
P8
10
P8
P8
GND
10
9
8
VDD
P4
P4
P4
GND
6
5
4
P47
P4
P4
P4
2
1
P43
P4
P4
GND
OUT
12
P40
11
P3 /F
P3
9
8
P310
P3
P3
GND
VDD
VDD
1
8
7
6
P25
139
GND
140
VDD
141
P24
142
59
P64
P2
143
58
P63
P22
144
57
P62
P21
145
56
P61
P20
146
55
P60
P112/HOUT
147
54
P512
P111
148
53
P511
GND
149
52
GND
VDD
150
51
VDD
P110
151
50
P5
P19
152
49
P59
P18
153
48
P58
P1
154
47
P57
P16
155
46
P56
P15
156
45
P55
P14
157
44
P5
GND
158
43
GND
P13
159
42
P53
P12
160
1 2
41
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
P52
10
1
4
P5
P5
0
PT0
TN_IN
TDO
TMS
TRST
TDI
TCK
0
ADDR
ADDR1
2
ADDR
ADDR3
4
CS
ADDR
DP_EN
HBLANK
R/W
GND
SYNC_CB
DD
V
CLK
F
V
H
0
COEFF
GND
1
COEFF
COEFF2
DD
V
GND
3
COEFF
4
8
COEFF
7
GND
5
COEFF
6
6
5
COEFF
4
GND
0
3
COEFF7
P1
1
7
P1
3
GF9105A
TOP VIEW
Fig. 2 GF9105A Pin Connections
VDD
VDD
n substrate
n substrate
D1
p
D1
p
p+
p+
INPUT
n+
OUTPUT
n+
D2
n
n
D2
p WELL
p WELL
GND
GND
Fig. 3a GF9105A Equivalent Input Circuit
521 - 88 - 03
Fig. 3b GF9105A Equivalent Output Circuit
4
OUTPUT/INPUT = 1
C1
PROCESSING
CORE INPUT
P212..0
C2
13
13
P312..0
C3
11
P410..0
13
13
13
C6
13
C7
11
11
P810..0
13
13
11
11
C1
C2
C4
P410..0
13
13
13
13
13
13
11
11
P512..0
PROCESSING
CORE OUTPUT
13
P712..0
13
C3
C5
P612..0
13
P312..0
C4
13
13
P212..0
11
P512..0
13
P112..0
C5
P612..0
C6
P712..0
C7
C8
P810..0
C8
GF9105A SIGNAL
PROCESSING CORE
BI-DIRECTIONAL
DATA PORTS
Fig. 4b Functional Block Diagram of GF9105A
(OUTPUT/INPUT = 1, HVF_OUT = 0)
OUTPUT/INPUT = 0
OUTPUT/INPUT = 1
12
12
P211..0
P312/FOUT
12
12
11
11
P311..0
P410..0
P512
P511..0
P612
12
12
12
12
P611..0
P712
P711..0
P810..0
12
12
11
11
BI-DIRECTIONAL
DATA PORTS
}
}
}
C1
C2
P112/HOUT
PROCESSING
CORE INPUT
P212/VOUT
12
12
12
12
12
12
12
11
11
P111..0
P212/VOUT
P211..0
P312/FOUT
C3
P311..0
} C4
}
}
}
P410..0
P512
C5
C6
C7
12
12
12
12
12
12
11
11
P511..0
PROCESSING
CORE OUTPUT
P112/HOUT
12
GF9105A SIGNAL
PROCESSING CORE
BI-DIRECTIONAL
DATA PORTS
Fig. 4a Functional Block Diagram of GF9105A
(OUTPUT/INPUT = 0, HVF_OUT = 0)
P111..0
PROCESSING
CORE OUTPUT
13
13
P612
P611..0
P712
P711..0
} C8
P810..0
GF9105A SIGNAL
PROCESSING CORE
BI-DIRECTIONAL
DATA PORTS
Fig. 4c Functional Block Diagram of GF9105A
(OUTPUT/INPUT = 0, HVF_OUT = 1)
}
}
}
C1
C2
PROCESSING
CORE INPUT
13
13
C3
} C4
}
}
}
C5
C6
PROCESSING
CORE OUTPUT
P112..0
PROCESSING
CORE INPUT
OUTPUT/INPUT = 0
C7
} C8
GF9105A SIGNAL
PROCESSING CORE
Fig. 4d Functional Block Diagram of GF9105A
(OUTPUT/INPUT = 1, HVF_OUT = 1)
5
521 - 88 - 03
SL/DL_IN
MUXED_IN
XX OR CB/B
XX OR CR/R
KEY, CB/B, CR/R OR KEY
13 C3
OOA[1:0]
OUTPUT/INPUT
CLP_D[1:0]
MUXED OUT 4:4:4:4/4:2:2:4_OUT
GS9001 SL/DL_OUT
S
RND8/10
2
2
10
13 C1
13 C2
RND8/10
2
2
Y/G, CB/B, CR/R, KEY
OR Y/G, CB/B, CR/R,OR Y/G
MATRIX &
KEY SCALER
COEFFICIENTS
LOWF
BYPASS_F
FIL_RND
HB[1:0] IOA[1:0]
RND8/10
GS9001
Y/G
Y/G
10
DEMUX
4:4:4:4
OR
4:2:2:4
CB/B
10
CR/R
11 C4
H_BLANK
CB/B
AND
INPUT
OFFSET
ADJUST CR/R
C5
Y/G
INT
CB/B
CB/B
INT
CR/R
OUTPUT
OFFSET
ADJUST
CB/B
OUTPUT
CLIPPING
CB/B
OUTPUT
MULTIPLEXER
C7
CR/R
CR/R
CR/R
KEY
KEY
KEY
KEY
H_BLANK
SYNC_CB
H
CLOCK
V
CB/B OR XX
13
CR/R OR XX
C8 11
KEY SCALER
KEY
Y/G, CB/B, CR/R,KEY OR
Y/G, CB/B, CR/R, OR Y/G
C6 13
10
KEY
13
Y/G
Y/G
Y/G
3X3
MATRIX
MULTIPLIER
KEY OR KEY, CB/B, CR/R
F
DP_EN
Fig. 5a Functionality of GF9105A Processing Core when INT/DEC = 1, HVF_OUT = 0
SL/DL_IN
MUXED_IN
HB [1:0] IOA [1:0]
GS9001
2
Y/G, CB/B, CR/R, KEY OR
Y/G, CB/B, CR/R, OR Y/G
XX OR CB/B
XX OR CR/R
13 C3
BYPASS_F
RND8/10
LOWF RND8/10
FIL_RND
2
OOA [1:0]
CLP_D [1:0]
OUTPUT/INPUT
MUXED OUT 4:4:4:4/4:2:2:4_OUT
GS9001 SL/DL_OUT
S
RND8/10
2
2
13
13 C1
13 C2
MATRIX &
KEY SCALER
COEFFICIENTS
Y/G
13
DEMUX
4:4:4:4
OR
4:2:2:4
11 C4
CB/B
13
C5
Y/G
H_BLANK
AND
INPUT
OFFSET
ADJUST
3X3
MATRIX
MULTIPLIER
CB/B
SYNC_CB
DEC
CB/B
OUTPUT
OFFSET
ADJUST
CB/B
CR/R
CR/R
CR/R
KEY
KEY
KEY
OUTPUT
CLIPPING
CB/B
OUTPUT
MULTIPLEXER
C7
KEY SCALER
KEY
H_BLANK
CLOCK
13
CR/R OR XX
11
KEY OR KEY, CB/B, CR/R
KEY
H
DP_EN
V
Fig. 5b Functionality of GF9105A Processing Core when INT/DEC = 0, HVF_OUT = 0
521 - 88 - 03
CB/B OR XX
CR/R
C8
11
KEY
Y/G, CB/B, CR/R, KEY OR
Y/G, CB/B, CR/R, OR Y/G
C6 13
DEC
KEY, CB/B, CR/R OR KEY
13
Y/G
Y/G
Y/G
CB/B
CR/R
CR/R
Y/G
6
F
SL/DL_IN
MUXED_IN
GS9001
2
H
Y/G, CB/B, CR/R, KEY OR
Y/G, CB/B, CR/R,OR Y/G
12 C2
F
XX OR CR/R
RND8/10
OOA[1:0]
OUTPUT/INPUT
2
CLP_D[1:0]
MUXED OUT 4:4:4:4/4:2:2:4_OUT
GS9001 SL/DL_OUT
S
RND8/10
2
2
10
12 C1
12 C3
11
Y/G
Y/G
10
V
XX OR CB/B
MATRIX &
KEY SCALER
COEFFICIENTS
LOWF
BYPASS_F
FIL_RND
HB[1:0] IOA[1:0]
RND8/10
DEMUX
4:4:4:4
OR
4:2:2:4
CB/B
10
CR/R
H_BLANK
CB/B
AND
INPUT
OFFSET
ADJUST CR/R
C5
Y/G
INT
CB/B
CB/B
INT
CR/R
OUTPUT
OFFSET
ADJUST
CB/B
OUTPUT
CLIPPING
CB/B
OUTPUT
MULTIPLEXER
C7
CR/R
CR/R
CR/R
KEY
KEY
KEY
KEY
H_BLANK
SYNC_CB
CLOCK
H
V
CB/B OR XX
13
CR/R OR XX
C8 11
KEY SCALER
KEY
KEY
Y/G, CB/B, CR/R, KEY OR
Y/G, CB/B, CR/R, OR Y/G
C6 13
10
C4
KEY, CB/B, CR/R OR KEY
13
Y/G
Y/G
Y/G
3X3
MATRIX
MULTIPLIER
KEY OR KEY, CB/B, CR/R
F
DP_EN
Fig. 5c Functionality of GF9105A Processing Core when INT/DEC = 1, HVF_OUT = 1
SL/DL_IN
MUXED_IN
HB [1:0] IOA [1:0]
GS9001
2
XX OR CB/B
12 C1
12 C2
F
XX OR CR/R
BYPASS_F
RND8/10
LOWF RND8/10
FIL_RND
2
OOA [1:0]
CLP_D [1:0]
OUTPUT/INPUT
MUXED OUT 4:4:4:4/4:2:2:4_OUT
GS9001 SL/DL_OUT
S
RND8/10
2
2
12
H
Y/G, CB/B, CR/R, KEY OR
Y/G, CB/B, CR/R, OR Y/G
V
MATRIX &
KEY SCALER
COEFFICIENTS
12 C3
11
Y/G
12
DEMUX
4:4:4:4
OR
4:2:2:4
CB/B
12
C5
Y/G
H_BLANK
AND
INPUT
OFFSET
ADJUST
3X3
MATRIX
MULTIPLIER
CB/B
SYNC_CB
CB/B
OUTPUT
OFFSET
ADJUST
CB/B
CR/R
CR/R
CR/R
KEY
KEY
KEY
OUTPUT
CLIPPING
CB/B
OUTPUT
MULTIPLEXER
C7
C8
H_BLANK
CLOCK
CB/B OR XX
13
CR/R OR XX
CR/R
KEY SCALER
KEY
KEY
Y/G, CB/B, CR/R, KEY OR
Y/G, CB/B, CR/R, OR Y/G
C6 13
DEC
DEC
11
C4
KEY, CB/B, CR/R OR KEY
13
Y/G
Y/G
Y/G
CB/B
CR/R
CR/R
Y/G
11
KEY OR KEY, CB/B, CR/R
KEY
H
DP_EN
V
F
Fig. 5d Functionality of GF9105A Processing Core when INT/DEC = 0, HVF_OUT = 1
7
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GF9105A DETAILED DEVICE DESCRIPTION
INPUT/OUTPUT DATA PORTS
The GF9105A has 8 bi-directional data ports, labelled P1 to P8. P1 to P3 and P5 to P7 are 13-bit data ports while P4 and P8
are 11-bit data ports. The OUTPUT/INPUT control bit and the HVF_OUT control bit (See Host Programming Section and
figures 4a - 4d) control how P1 to P8 are configured.
When OUTPUT/INPUT is set low and when HVF_OUT is set low, P112..0, P212..0, P312..0, P410..0 are configured as input video
data ports and P512..0, P612..0, P712..0, P810..0 are configured as output video data ports (refer to Figure 4a).
When OUTPUT/INPUT is set low and when HVF_OUT is set high, P111..0, P211..0, P311..0, P410..0 are configured as input video
data ports and P512..0, P612..0, P712..0, P810..0 are configured as output video data ports. In this mode, P112, P212, P312 are
configured as outputs for H, V, and F output data. P112 carries H data, P212 carries V data and P312 carries F data (refer to
Figure 4c).
When OUTPUT/INPUT is set high and when HVF_OUT is set low, P112..0, P212..0, P312..0, P410..0 are configured as output
video data ports and P512..0, P612..0, P712..0, P810..0 are configured as input video data ports (refer to Figure 4b).
When OUTPUT/INPUT is set high and when HVF_OUT is set high, P111..0, P211..0, P311..0, P410..0 are configured as output
video data ports and P512..0, P612..0, P712..0, P810..0 are configured as input video data ports. In this mode, P112, P212, P312
are configured as outputs for HVF output data. P112 carries H data, P212 carries V data and P312 carries F data (refer to
Figure 4d).
Note: No bi-directional I/Os should be driven until after the OUTPUT/INPUT and the HVF_OUT control bits have been set
(unless DP_EN is set high to tri-state the outputs). This will ensure that any potential conflicts between input and output data
buses are avoided.
OUTPUT/INPUT AND HVF CONTROL BIT
OUTPUT/INPUT
HVF_OUT
0
0
DESCRIPTION
P112..0, P212..0, P312..0, P410..0 are configured as input video data ports.
P512..0, P612..0, P712..0, P810..0 are configured as output video data ports.
Refer to Figure 4a.
0
1
P111..0, P211..0, P311..0, P410..0 are configured as input video data ports.
P112, P212, P312 are configured as H, V and F outputs, respectively.
P512..0, P612..0, P712..0, P810..0 are configured as output video data ports.
Refer to Figure 4c.
1
0
P112..0, P212..0, P312..0, P410..0 are configured as output video data ports.
P512..0, P612..0, P712..0, P810..0 are configured as input video data ports.
Refer to Figure 4b.
1
1
P111..0, P211..0, P311..0, P410..0 are configured as output video data ports.
P112, P212, P312 are configured as H, V and F outputs, respectively.
P512..0, P612..0, P712..0, P810..0 are configured as input video data ports.
Refer to Figure 4d.
For H, V, F output timing refer to the Timing Reference Signal Section of this data sheet.
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8
DATA PORT ENABLE
DP_EN is used for synchronously enabling and disabling the bi-directional data ports of the GF9105A. When DP_EN is set
high, the data ports are disabled and set to a high impedance state. When DP_EN is set low, all data ports are enabled.
DP_EN CONTROL PIN
DP_EN
DESCRIPTION
0
Output data ports enabled.
1
Output data ports disabled (high impedance state).
INPUT CLOCK (CLK)
For standard video signals, the clock input (CLK) of the GF9105A runs at one of three rates: 13.5/18MHz, 27/36MHz or
54MHz. The 18 MHz and 36 MHz variations on main clock frequencies are used in 16 x 9 video applications where luminance
is sampled at 18 MHz. The use of a 27/36MHz clock with the GF9105A is the most common application. These clocks can be
used with any format of input or output data with the exception of single link mode. Figures 7a and 7c show multiplexed and
non-multiplexed input data with a 27/36MHz clock. When the GF9105A is used with either SMPTE RP174 compliant single link
input or output data, the input clock must run at 54 MHz (see Figure 7b).
A 13.5/18 MHz input clock speed can only be used when both the input and output data are in a non multiplexed format (see
Figure 7d). This clock rate was added to the GF9105A for use when the device is operating with non-multiplexed input and
output data, since in this case a 27.0MHz clock may not be available. To use the 13.5 MHz input clock rate, the LOWF control
bit must be set HIGH. When input clock rates of 27.0 MHz or 54.0 MHz are used, the LOWF control bit must be set LOW.
Please note, when using the GF9105A with non-multiplexed 4:2:2:4 or 4:4:4:4 input data and an input clock rate of 27/36MHz,
two rising edges of the 27/36MHz input clock are required to latch in a 13.5/18MHz input data rate (see Figure 7c).
INPUT CLOCK SUMMARY
INPUT CLOCK RATE (MHz)
MODES
13.5/18 MHz
Non-multiplexed Input Data
AND
Non-multiplexed Output Data (LOWF=1)
27/36 MHz
All Input / Output Data Formats
EXCEPT Single Link
54 MHz
SMPTE RP174 Single Link Input
OR Output Data
BASIC OPERATION OF THE GF9105A
The basic operating mode for the GF9105A is selected via the INT/DEC control bit (See Host Programming Section). The
effective block diagram of the GF9105A Processing Core depends on the state of INT/DEC. When INT/DEC is set high, the
internal FIR filters are set for interpolation and are placed in front of the programmable 3X3 color space converter. Refer to
Figures 5a and 5c for a functional block diagram of the GF9105A processing core when INT/DEC is set high. When INT/DEC
is set low, the internal FIR filters are set for decimation and are placed after the programmable 3X3 color space converter.
Refer to Figures 5b and 5d for a functional block diagram of the GF9105A with INT/DEC set low. In these figures, static
control bits (signals loaded via the asynchronous parallel interface) are shown at the top of the diagram and control signals
with dedicated input pins are shown at the bottom of the diagram.
INT/DEC CONTROL BIT
INT/DEC
0
DESCRIPTION
FIR filters set for decimation.
FIR filters placed after the 3X3 multiplier as in Figure 5b and 5d.
1
FIR filters set for interpolation.
FIR filters placed before the 3x3 multiplier as in Figure 5a and 5c.
9
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There are seven basic blocks that make up the GF9105A. These are:
• Input De-multiplexer
• Horizontal Blanking and Input Offset Adjustment
• FIR Filters
• 3x3 Color Space Converter and KEY Scaler
• Output Offset Adjustment
• Output Clipping
• Output Multiplexer
Since the GF9105A Processing Core functionality depends on the state of INT/DEC, device operation will be described first
for the case where INT/DEC is set high and then for the case where INT/DEC is set low.
GF9105A OPERATION IN INTERPOLATION MODE (INT/DEC = 1)
Refer to Figures 5a and 5c for a functional block diagram of GF9105A operation with INT/DEC = 1
BIT WEIGHTING
Although the input data ports are physically 13 bits or 11 bits wide, the GF9105A Processing Core is limited to processing
10 or 8-bit unsigned input data while INT/DEC is set high. It should be noted that while INT/DEC is set low, the GF9105A
Processing Core will accept up to 13 bit input data. Refer to later sections for a description of Processing Core functionality
while INT/DEC is set low.
As mentioned above, the GF9105A is limited to processing 10 or 8-bit unsigned input data while INT/DEC is set high. This
input data must be properly embedded within the input data ports. The following table illustrates how to properly embed 10
or 8-bit data within the 13 bit data ports. Note that when OUTPUT/INPUT=0 and HVF_OUT=1, P112, P212 and P312 (which
corresponds to b12) are outputs rather than inputs. These 3 outputs are used for presenting output H, V and F output signals.
The user should be careful to ensure that P112, P212 and P312,are not driven by upstream logic when OUTPUT/INPUT=0 and
HVF_OUT=1. Other unused inputs should be set low by the user.
OUTPUT/INPUT = 0, HVF_OUT = 0
DATA PORT REFERENCE
Input Port: P112..0 to P312..0
13 BIT PHYSICAL INTERFACE
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
0
0
0
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
NA
NA
0
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
0
0
0
b7
b6
b5
b4
b3
b2
b1
b0
0
0
NA
NA
0
b7
b6
b5
b4
b3
b2
b1
b0
0
0
Embedded 10 bit signal
Input Port: P410..0
Embedded 10 bit signal
Input Port: P112..0 to P312..0
Embedded 8 bit signal
Input Port: P410..0
Embedded 8 bit signal
INPUT DE-MULTIPLEXER
The MUXED_IN and SL/DL_IN control bits (See Host Programming Section) determine the input data format. The MUXED_IN
control bit is used to identify whether the incoming data is in a multiplexed or non-multiplexed format. The SL/DL_IN control
bit is used to identify whether the incoming data is in a single link or dual link format.
Dual Link (SL/DL_IN = 0)
While MUXED_IN is set low, input data is assumed to be two 10 bit streams in 4:2:2:4 or 4:4:4:4 data format as shown in
Figure 7a. The input de-multiplexer separates the 4:2:2:4 or 4:4:4:4 input signals into four channels of Y/G, CB/B, CR/R and
KEY data. These four data streams are then passed to the next processing section.
When operating with multiplexed 4:2:2:4 or 4:4:4:4 input data, the 4:2:2 data stream enters the GF9105A Processing Core
from Processing Core input port C1. While OUTPUT/INPUT=0 Processing Core port C1 corresponds to device data port P1
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10
OUTPUT/INPUT = 0, HVF_OUT = 1
DATA PORT REFERENCE
Input Port: P112..0 to P312..0
Embedded 10 bit signal
Input Port: P410..0
13 BIT PHYSICAL INTERFACE
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
H, V, or F
output
0
0
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
NA
NA
0
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
H, V, or F
output
0
0
b7
b6
b5
b4
b3
b2
b1
b0
0
0
NA
NA
0
b7
b6
b5
b4
b3
b2
b1
b0
0
0
Embedded 10 bit signal
Input Port: P112..0 to P312..0
Embedded 8 bit signal
Input Port: P410..0
Embedded 8 bit signal
OUTPUT/INPUT = 1, HVF_OUT = 0
DATA PORT REFERENCE
Input Port: P512..0 to P712..0
13 BIT PHYSICAL INTERFACE
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
0
0
0
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
NA
NA
0
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
0
0
0
b7
b6
b5
b4
b3
b2
b1
b0
0
0
NA
NA
0
b7
b6
b5
b4
b3
b2
b1
b0
0
0
Embedded 10 bit signal
Input Port: P810..0
Embedded 10 bit signal
Input Port: P512..0 to P712..0
Embedded 8 bit signal
Input Port: P810..0
Embedded 8 bit signal
OUTPUT/INPUT = 1, HVF_OUT = 1
DATA PORT REFERENCE
Input Port: P512..0 to P712..0
13 BIT PHYSICAL INTERFACE
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
0
0
0
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
NA
NA
0
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
0
0
0
b7
b6
b5
b4
b3
b2
b1
b0
0
0
NA
NA
0
b7
b6
b5
b4
b3
b2
b1
b0
0
0
Embedded 10 bit signal
Input Port: P810..0
Embedded 10 bit signal
Input Port: P512..0 to P712..0
Embedded 8 bit signal
Input Port: P810..0
Embedded 8 bit signal
(refer to Figures 4a and 4c). While OUTPUT/INPUT=1 Processing Core port C1 corresponds to device data port P5 (Refer to
Figures 4b and 4d).
The KEY:2:2 or KEY:XX:XX data enters the GF9105A Processing Core from Processing Core input port C4. While OUTPUT/
INPUT=0, Processing Core port C4 corresponds to device data port P4 (Refer to Figures 4a and 4c). While OUTPUT/
INPUT=1, Processing Core port C4 corresponds to device data port P8 (Refer to Figures 4b and 4d).
When MUXED_IN is set high, input data is assumed to be 4:2:2:4 or 4:4:4:4 data in a non-multiplexed format as shown in
Figure 7c. Since the incoming data is already non-multiplexed, the input data is passed on to the next processing section
unmodified. In this mode of operation, input data is presented to all four Processing Core input ports. While OUTPUT/
INPUT=0, Processing Core ports C1-C4 correspond to device data ports P1-P4 (Refer to Figures 4a and 4c). While OUTPUT/
INPUT=1 Processing Core ports C1-C4 correspond to device data ports P5-P8 (Refer to Figure 4b and 4d).
11
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Single Link (SL/DL_IN = 1)
When operating with single link input data, the 4:4:4:4 data stream (SMPTE
Processing Core from Processing Core input C1.
RP174 compliant) enters the GF9105A
While OUTPUT/INPUT = 0 Processing Core Port C1 corresponds to device data port P1 (refer to Figures 4a and 4c). While
OUTPUT/INPUT = 1 Processing Core Port C1 corresponds to device data port P5 (refer to Figures 4b and 4d). In this
mode, the input clock (CLK) is operating at 54 MHz. Also, note that the MUXED_IN control bit must be set low (MUXED_IN
= 0).
MUXED_IN AND SL/DL_IN CONTROL BITS
MUXED_IN
SL/DL_IN
DESCRIPTION
0
0
Input is in a dual link multiplexed format.
0
1
Input is in a single link multiplexed format.
1
XX
Input is in a non-multiplexed format.
SYNCHRONIZATION
In order to properly synchronize the input de-multiplexer, the GF9105A requires a SYNC_CB control signal input. For
multiplexed input data, SYNC_CB should change from high to low at the start of an even numbered CB sample. After
synchronizing the device with the incoming data stream, SYNC_CB can remain low until re-synchronization is desired. Refer
to Figure 7a for timing of SYNC_CB with a dual link multiplexed input data stream. Refer to Figure 7b for timing of SYNC_CB
with a single link multiplexed input data signal. The timing shown may be referred to as “standard SYNC_CB timing”.
In order to simplify overall system design, the HSYNC output from the GS9001 EDH Coprocessor may be used as a
SYNC_CB signal when operated with a 4:2:2 or dual link 4:4:4:4 input signal. In this mode of operation, the 10 bit multiplexed
data entering the GF9105A must be fed from the output of the GS9001 and the GF9105A’s SYNC_CB input must be fed from
the GS9001’s HSYNC output (Refer to Figure 8a). To use this mode of operation the GF9105A’s GS9001 control bit (Refer to
Host Programming Section) must be set high. When operated with a 4:2:2 or a dual link 4:4:4:4 input signal and when the
GS9001 control bit is set high, the GS9001’s HSYNC, VSYNC, and FIELD output signals may also be used to drive the
GS9105A’s output multiplexer. Refer to the Timing Reference Signal section for information regarding this.
When dealing with single link 4:4:4:4 input or output signals “standard” SYNC_CB timing above must be used. When using
standard SYNC_CB and HVF timing, the GS9001 control must be set low. The GS9020 may be used to provide such
standard SYNC_CB timing and HVF. When operated in this manner, the 10 bit multiplexed data entering the GF9105A must
be fed from the output of the GS9020 and the GF9105A’s SYNC_CB and HVF inputs must be fed from the GS9020’s H, V, F
outputs. The same GS9020/GF9105A configuration may also be used when interfacing the GF9105A to a standard 4:2:2 or
dual link 4:4:4:4 link input signal. In this case, the GS9001 control bit must still be set low.
GS9001 CONTROL BIT
GS9001
DESCRIPTION
0
Standard SYNC_CB and H,V,F timing. Simple interface to GS9020.
1
Modified SYNC_CB and H, V, F timing. Simple interface to GS9001.
NOTE: Standard SYNC_CB and H, V, F timing must be used when receiving or generating single link 4:4:4:4 signals.
With non-multiplexed input data, SYNC_CB must change from high to low at the start of an even-numbered CB sample. It is
important to note that SYNC_CB changes from high to low on an even-numbered CB sample and not an odd-numbered
sample. After synchronizing the device with the incoming data stream, the SYNC_CB signal can remain low until resynchronization is desired. Refer to Figure 7c for timing of SYNC_CB with non-multiplexed input data. Following the input demultiplexer, data is passed to the Horizontal Blanking section of the device.
HORIZONTAL BLANKING
When H_BLANK is high, all four channels of input are forced to a user selectable set of levels. When H_BLANK is low data is
passed through the Horizontal Blanking section of the device unmodified. Refer to Figures 10a and 10b for typical timing of
H_BLANK with multiplexed input data and Figure 10c for typical timing with non-multiplexed input data. In these figures, a
521 - 88 - 03
12
prime (´) indicates to which samples the H blanking will be applied. The HB1 and HB0 control bits (See Host Programming
Section) determine which of the four sets of blanking levels are selected.
HB1 AND HB0 CONTROL BITS
HB1
HB0
0
0
Blanking levels of 64, 512, 512 and 64 applied to Y/G, CB/B, CR/R and KEY channels respectively.
0
1
Blanking levels of 64, 64, 64 and 64 applied to Y/G, CB/B, CR/R and KEY channels respectively.
1
0
Blanking levels of 0, 0, 0 and 0 applied to Y/G, CB/B, CR/R and KEY channels respectively.
1
1
Blanking levels of 0, 512, 512 and 0 applied to Y/G, CB/B, CR/R and KEY channels respectively.
DESCRIPTION
INPUT OFFSET ADJUSTMENT
Following the Horizontal Blanking function, a fixed set of offsets may be added to the input data. The IOA1 and IOA0 control
bits (See Host Programming Section) specify which of the four possible input offset adjustments will be applied to the data.
As an example, the interpolation/decimation filters operate on two’s complement data, so for Y/CB/CR input, IOA1 and IOA0
should both be set low to remove the inherent offset from the incoming data.
IOA1 AND IOA0 CONTROL BITS
IOA1
IOA0
0
0
Offsets of -64, -512, -512 and -64 added to the Y/G, CB/B, CR/R and KEY channels respectively.
0
1
Offsets of -64, -64, -64 and -64 added to the Y/G, CB/B, CR/R and KEY channels respectively.
1
0
Offsets of 0, 0, 0 and 0 added to the Y/G, CB/B, CR/R and KEY channels respectively.
1
1
Offsets of 0, -512, -512 and 0 added to the Y/G, CB/B, CR/R and KEY channels respectively.
DESCRIPTION
FIR FILTERS
Following the Input Offset Adjustment, data is passed to the FIR filtering section of the device. These filters, when enabled,
will up-sample CB and CR data by a factor of two so that 4:2:2:4 data is sample-rate converted to 4:4:4:4 data. Subsequent
processing of co-sited Y, CB and CR samples may take place on such 4:4:4:4 data. The frequency response of these CCIR601 compliant FIR filters is shown in Figures 6a and 6b and the characteristics are listed in Figure 6c. In order to maintain
proper synchronization between all four channels of input data, the Y/G and KEY channels are passed through a digital delay
line that matches the FIR filter latency. Output resolution from the FIR filters depends on the state of the RND8/10 and
FIL_RND control bits (See Host Programming Section). RND8/10 should always be set to match the data format being output
by the device (high for 8 bit data or low for 10 bit data). FIL_RND should be set low unless the GF9105A is being used in a
mode where the 3X3 matrix is set for unity gain bypass mode. (See 3X3 Color Space Converter and KEY Scaler Section). In
this case, FIL_RND should be set high. The FIR filter only takes 10-bit input in interpolation mode and proper input offset has
to be used.
RND8/10 AND FIL_RND CONTROL BITS
RND8/10
FIL_RND
DESCRIPTION
0
0
Output has minimum rounding for high accuracy for a non-identity matrix, using 10-bit input data.
0
1
More rounding is performed to increase overall accuracy when matrix is being bypassed, using 10-bit
input data.
1
0
Output has minimum rounding for high accuracy for a non-identity matrix, using 8-bit input data.
1
1
More rounding is performed to increase overall accuracy when matrix is being bypassed, using 8-bit
input data.
13
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The BYPASS_F control bit (See Host Programming Section) can be used to bypass the interpolation filters. When this bit is
set low, the filters are enabled and normal operation occurs. When this bit is set high, the filters are bypassed and the data is
passed through the filter section unmodified. FIL_RND should be set low when BYPASS_F is set high. Total latency through
the filter is independent of the BYPASS_F control signal. Note that after changing the state of BYPASS_F, an initialization
period corresponding to the device’s latency is required before valid data is available at the output of the device.
BYPASS_F CONTROL BIT
BYPASS_F
DESCRIPTION
0
Filters are enabled. Data is sample-rate converted from 4:2:2:4 to 4:4:4:4 data.
1
Filters are disabled. Data is passed through the filter section unmodified.
3X3 COLOR SPACE CONVERTER AND KEY SCALER
In this section, a 3X3 matrix multiplication (color space conversion) may be performed on the Y/G, CB/B and CR/R data. The
3X3 matrix multiplier has 13-bit two’s complement coefficients and maintains full precision throughout the 3X3 calculation.
The nine 13-bit coefficients (See Host Programming Section) used in this 3X3 calculation determine the color space
conversion that the GF9105A will perform. These coefficients are referred to as CMij, where i refers to the row and j refers to
the column in which CMij is found. The matrix multiplication can be shown as:
Y/G OUT
CM 11 CM 12 CM 13
Y/GIN
C B /BOUT = CM 21 CM 22 CM 23 C B /BIN
C R /ROUT
CM 31 CM 32 CM 33 C R /RIN
The nine matrix coefficients have 13-bit two’s complement resolution and cover a range from -4 to +3.9990234375. Bit
weighting for the coefficients is as follows:
Coefficient Bit
b12
Weighting
-2
2
b11
2
1
b10
2
0
b9
2
-1
b8
2
-2
b7
2
-3
b6
2
b5
-4
2
-5
b4
2
-6
b3
2
-7
b2
2
-8
b1
2
-9
b0
2
-10
Matrix bypassing can be accomplished by setting FIL_RND high and loading an identity matrix, by setting CM11, CM22 and
CM33 to unity and setting the remaining six coefficients to zero. In this mode, gain through the matrix stage is 1.000.
Typical examples of matrix coefficients that will provide full range RGB to YCBCR, and YCBCR to full range RGB conversions
are:
Y
0.5027 0.0976
C B = – 0.2899 0.4376
CR
– 0.3633 – 0.0711
0.2561
– 0.1477
0.4374
G
B =
R
– 0.8164 Y
0 CB
1.6025 C R
1.1677 – 0.3931
1.1677 2.0248
1.1677
0
G
B
R
KEY signals may also be scaled by a programmable scaling factor. The KEY scaling coefficient (See HOST Programming
Section) has the same resolution and bit weighting as the nine 3X3 matrix multiplier coefficients.
Typical examples of KEY scaler values that could be used are:
KEY scaler = 0.8563 for full range RGB to YCBCR conversions.
KEY scaler = 1.1677 for YCBCR to full range RGB conversions.
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14
MATRIX OUTPUT RESOLUTION
Full precision is maintained within the 3X3 matrix multiplier until the output is rounded to a 13-bit or 11-bit word, depending on
the state of the RND8/10 control bit.
3X3 MATRIX MULITPLIER OUTPUT RESOLUTION FOR Y/G, CB/B AND CR/R CHANNELS
RND8/10
DESCRIPTION
0
Matrix output channels rounded to 13 bits.
1
Matrix output channels rounded to 11 bits.
Output from the KEY scaler is also rounded and clipped based on the state of the RND8/10 control bit.
KEY SCALER OUTPUT
RND8/10
DESCRIPTION
0
Output of KEY Scaler rounded to 11 bits.
1
Output of KEY Scaler rounded to 9 bits.
OUTPUT OFFSET ADJUSTMENT
Output offset adjustment is provided to allow a specified set of offsets to be added to the data streams. The control bits
OOA1 and OOA0 (See Host Programming Section) determine which set of offsets is applied to the data.
OOA1 AND OOA0 CONTROL BITS
OOA1
OOA0
0
0
Offsets of 64, 512, 512 and 64 are added to the Y/G, CB/B, CR/R and KEY channels respectively.
0
1
Offsets of 64, 64, 64 and 64 are added to the Y/G, CB/B, CR/R and KEY channels respectively.
1
0
Offsets of 0, 0, 0 and 0 are added to the Y/G, CB/B, CR/R and KEY channels respectively.
1
1
Offsets of 0, 512, 512 and 0 are added to the Y/G, CB/B, CR/R and KEY channels respectively.
DESCRIPTION
OUTPUT CLIPPING
In the output clipping block, the data is clipped to a specific number of bits. The CLP_D1 and CLP_D0 control bits (See Host
Programming Section) determine the clipping mode that will occur.
OUTPUT MULTIPLEXER
The MUXED_OUT, 4:4:4:4/4:2:2:4_OUT, SL/DL_OUT and HVF_OUT control bits (See Host Programming Section) determine
the output data format.
Dual Link (SL/DL_OUT = 0)
When MUXED_OUT and 4:4:4:4/4:2:2:4_OUT are both set low, the device will multiplex the three channels of Y/G, CB/B and
CR/R data into a single channel of 4:2:2 data as prescribed by SMPTE 125M. KEY information will be presented in a KEY:2:2
format where the CB/CR samples in the key channel are set to color blanking levels as outlined in ITU-R-601. This mode can
only be used when the output data has been rounded to 10-bit or 8-bit unsigned data. The 4:2:2 data stream is presented
on Processing Core output data port C5 and the KEY:2:2 data is presented on Processing Core output data port C8.
When MUXED_OUT is set low and 4:4:4:4/4:2:2:4_OUT is set high, the device will multiplex the four channels of Y/G, CB/B,
CR/R and KEY information into two streams of 4:2:2 and KEY:2:2 data as prescribed by SMPTE 125M. This mode can only be
used when the output data has been clipped to 10-bit or 8-bit unsigned data. The 4:2:2 data stream is presented on
Processing Core output data port C5 and the KEY:2:2 data is output on Processing Core output data port C8. Timing
Reference Signals (TRS) may be inserted into the output data streams with such TRS signals conforming to the EAV/SAV
15
521 - 88 - 03
CLP_D1 AND CLP_D0 CONTROL BIT OPERATION
RND8/10
CLP_D1
CLP_D0
DESCRIPTION
0
0
0
Y/G, CB/B, CR/R Channels: Clipped to a 13-bit two’s complement number (Values -4096 to 4095)
KEY Channel: Clipped to an 11-bit two’s complement number (Values -1024 to +1023)
0
0
Y/G, CB/B, CR/R Channels: Clipped to a 12-bit two’s complement number (Values -2048 to 2047)
1
KEY Channel: Clipped to an 11-bit two’s complement number (Values -1024 to +1023)
0
1
0
Y/G, CB/B, CR/R, KEY Channels: Clipped to a 10-bit unsigned number (Values 0 to +1023)
0
1
1
Y/G, CB/B, CR/R, KEY Channels: Clipped to a 10-bit unsigned number (Values +4 to +1019)
1
0
0
Y/G, CB/B, CR/R Channels: Clipped to a 11-bit two’s complement number (Values -1024 to 1023)
KEY Channel: Clipped to an 9-bit two’s complement number (Values -256 to +255)
1
0
Y/G, CB/B, CR/R Channels: Clipped to a 10-bit two’s complement number (Values -512 to +511)
1
KEY Channel: Clipped to an 9-bit two’s complement number (Values -256 to +255)
1
1
0
Y/G, CB/B, CR/R, KEY Channels: Clipped to a 8-bit unsigned number (Values 0 to +255)
1
1
1
Y/G, CB/B, CR/R, KEY Channels: Clipped to a 8-bit unsigned number (Values +1 to +254)
formats as outlined in SMPTE 125M. (See TRS Insertion Section).
When OUTPUT/INPUT is set high, Processing Core output port C5 corresponds to device data port P1 and Processing Core
output port C8 corresponds to device data port P4. While OUTPUT/INPUT is set low, Processing Core output port C5
corresponds to device data port P5 and Processing Core output port C8 corresponds to device data port P8.
Single Link (SL/DL_OUT = 1)
When generating single link output data, the 4:4:4:4 data stream (SMPTE RP174 compliant) exits the GF9105A Processing
Core from Processing Core output C5. While OUTPUT/INPUT = 0 Processing Core port C5 corresponds to device data port
P5(refer to Figure 4a). While OUTPUT/INPUT = 1 Processing Core Port C5 corresponds to device data port P1 (refer to
Figure 4b). In this mode, the input clock (CLK) is operating at 54 MHz. Also, note that the MUXED_OUT control bit must be
set LOW (MUXED_OUT = 0) and the 4:4:4:4/4:2:2:4_OUT control bit must be set HIGH (4:4:4:4/4:2:2:4_OUT = 1)
.
MUXED_OUT, 4:4:4:4/4:2:2:4_OUT AND SL/DL_OUT CONTROL BITS
MUXED_OUT
4:4:4:4/4:2:2:4_OUT
SL/DL_OUT
DESCRIPTION
0
0
0
Output data in a 4:2:2:4 dual link multiplexed format.
0
1
0
Output data in a 4:4:4:4 dual link multiplexed format.
0
1
1
Output data in a 4:4:4:4 single link multiplexed format.
1
0
XX
Output 4:2:2:4 data in a non-multiplexed format.
1
1
XX
Output 4:4:4:4 data in a non-multiplexed format.
When the device is configured for outputting non-multiplexed data and RND8/10 is set low, 13-bit two’s complement,12-bit
two’s complement, or 10-bit unsigned data may be output on Processing Core output data ports C5-C7 and 11-bit two’s
complement or 10-bit unsigned data output on the Processing Core output data port C8. The output data will be embedded
within the physical 13-bit output ports as shown in the following tables. Note that when HVF_OUT=1 and OUTPUT/INPUT=1
b12 of the GF9105As 13-bit two’s complement output is not available. In this case, the 13-bit output data is clipped to a 12-bit
two’s complement number. Bit 12 (b12) of the 13 bit physical interface is used to output the H, V and F output signals. In this
case, 13 bit output data is clipped 13 bit to a 12 bit two’s complement number.
521 - 88 - 03
16
OUTPUT/INPUT = 0, HVF_OUT = 0
DATA PORT REFERENCE
Output Port: P512..0 to P712..0
13 BIT PHYSICAL INTERFACE
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
b11
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
0
0
0
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
NA
NA
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
NA
NA
0
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
13-bit Two’s Complement output
Output Port: P512..0 to P712..0
12 bit Two’s Complement output (b11
extended)
Output Port: P512..0 to P712..0
10 bit unsigned output
Output Port: P810..0
11-bit Two’s Complement output
Output Port: P810..0
10 bit unsigned output
OUTPUT/INPUT = 0, HVF_OUT = 1
DATA PORT REFERENCE
Output Port: P112, P212 or P312
Output Port: P512..0 to P712..0
13 BIT PHYSICAL INTERFACE
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
H, V or F
output
-
-
-
-
-
-
-
-
-
-
-
-
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
b11
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
0
0
0
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
NA
NA
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
NA
NA
0
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
13-bit Two’s Complement output
Output Port: P512..0 to P712..0
12-bit Two’s Complement output (b11
extended)
Output Port: P512..0 to P712..0
10 bit unsigned output
Output Port: P810..0
11 bit Two’s Complement output
Output Port: P810..0
10 bit unsigned output
When the device is configured for outputting non-multiplexed data and RND8/10 is set high, the output bit weighting is
slightly modified. For non-multiplexed output formats, the device may output 11-bit two’s complement,10-bit two’s
complement or 8-bit unsigned data on Processing Core output data ports C5-C7, and 9-bit two’s complement or 8-bit
unsigned data may be output on Processing Core output data port C8. Note that when HVF_OUT=1 and OUTPUT/INPUT=1
the MSB of the 11-bit two’s complement output is not available. In this case, the output data is clipped to a 10-bit two’s
complement number (-512 to + 511). Bit 12 (b12) of the physical interface is used to output the H, V and F output signals.
The output data will be embedded within the physical 13-bit output ports as shown below.
17
521 - 88 - 03
OUTPUT/INPUT = 1, HVF_OUT = 0
DATA PORT REFERENCE
Output Port: P112..0 to P312..0
13 BIT PHYSICAL INTERFACE
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
b11
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
0
0
0
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
NA
NA
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
NA
NA
0
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
13 bit Two’s Complement output
Output Port: P112..0 to P312..0
12-bit Two’s Complement output (b11
extended)
Output Port: P112..0 to P312..0
10 bit unsigned output
Output Port: P410..0
11 bit Two’s Complement output
Output Port: P410..0
10 bit unsigned output
OUTPUT/INPUT = 1, HVF_OUT = 1
DATA PORT REFERENCE
Output Port: P112..0 to P312..0
12 bit Two’s Complement output
Output Port: P112..0 to P312..0
10 bit unsigned output
Output Port: P410..0
13 BIT PHYSICAL INTERFACE
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
H, V or F
output
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
H, V or F
output
0
0
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
NA
NA
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
NA
NA
0
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
11 bit Two’s Complement output
Output Port: P410..0
10 bit unsigned output
OUTPUT/INPUT = 0, HVF_OUT = 0
DATA PORT REFERENCE
Output Port: P512..0 to P712..0
13 BIT PHYSICAL INTERFACE
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
0
0
b9
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
0
0
0
0
0
b7
b6
b5
b4
b3
b2
b1
b0
0
0
NA
NA
b8
b7
b6
b5
b4
b3
b2
b1
b0
0
0
NA
NA
0
b7
b6
b5
b4
b3
b2
b1
b0
0
0
11 bit Two’s Complement output
Output Port: P512..0 to P712..0
10 bit Two’s Complement output (b9
extended)
Output Port: P512..0 to P712..0
8 bit unsigned output
Output Port: P810..0
9 bit Two’s Complement output
Output Port: P810..0
8 bit unsigned output
When the device is configured for outputting multiplexed data, 8-bit or 10-bit unsigned data is transferred to the output data
ports. Consult the tables of the Bit Weighting section for embedding 8 or 10 bits within 13 bit data ports. Note that when
HVF_OUT=1 and OUTPUT/INPUT=1, the MSB of the GF9105As 13 bit of the physical interfaces are used to output the H, V
and F output signals.
521 - 88 - 03
18
OUTPUT/INPUT = 0, HVF_OUT = 1
DATA PORT REFERENCE
Output Port: P112, P212 or P312
Output Port: P512..0 to P712..0
13 BIT PHYSICAL INTERFACE
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
H, V or F
output
-
-
-
-
-
-
-
-
-
-
-
-
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
0
0
b9
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
0
0
0
0
0
b7
b6
b5
b4
b3
b2
b1
b0
0
0
NA
NA
b8
b7
b6
b5
b4
b3
b2
b1
b0
0
0
NA
NA
0
b7
b6
b5
b4
b3
b2
b1
b0
0
0
11 bit Two’s Complement output
Output Port: P512..0 to P712..0
10 bit Two’s Complement output (b9
extended)
Output Port: P512..0 to P712..0
8 bit unsigned output
Output Port: P810..0
9 bit Two’s Complement output
Output Port: P810..0
8 bit unsigned output
OUTPUT/INPUT = 1, HVF_OUT = 0
DATA PORT REFERENCE
Output Port: P112..0 to P312..0
13 BIT PHYSICAL INTERFACE
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
0
0
b9
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
0
0
0
0
0
b7
b6
b5
b4
b3
b2
b1
b0
0
0
NA
NA
b8
b7
b6
b5
b4
b3
b2
b1
b0
0
0
NA
NA
0
b7
b6
b5
b4
b3
b2
b1
b0
0
0
11 bit Two’s Complement output
Output Port: P112..0 to P312..0
10 bit Two’s Complement output (b11
extended)
Output Port: P112..0 to P312..0
8 bit unsigned output
Output Port: P410..0
9 bit Two’s Complement output
Output Port: P410..0
8 bit unsigned output
OUTPUT/INPUT = 1, HVF_OUT = 1
DATA PORT REFERENCE
Output Port: P112..0 to P312..0
10 bit Two’s Complement output
Output Port: P112..0 to P312..0
8 bit unsigned output
Output Port: P410..0
13 BIT PHYSICAL INTERFACE
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
H, V or F
output
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
0
0
H, V or F
output
0
0
b7
b6
b5
b4
b3
b2
b1
b0
0
0
NA
NA
b8
b7
b6
b5
b4
b3
b2
b1
b0
0
0
NA
NA
0
b7
b6
b5
b4
b3
b2
b1
b0
0
0
9 bit Two’s Complement output
Output Port: P410..0
8 bit unsigned output
19
521 - 88 - 03
GF9105A OPERATION IN DECIMATION MODE (INT/DEC=0)
Refer to Figure 5b for a functional block diagram of the GF9105A operation with INT/DEC=0
BIT WEIGHTING
When using multiplexed input data, the Processing Core is limited to processing either 8-bit or 10-bit unsigned input data.
The input data should be embedded within the 13-bit data port as shown in the tables of the Bit Weighting subsection of the
Interpolation Mode Section. Note that when HVF_OUT=1, P112, P212 and P312 (which corresponds to b12) are outputs rather
than inputs. These 3 outputs are used for presenting H, V and F output signals. The user should be careful to ensure that
P112, P212 and P312 are not driven by upstream logic when HVF_OUT=1. Other unused inputs should be set low.
When using non-multiplexed input data, the GF9105A Processing Core can accept up to 13-bit two’s complement data from
Processing Core input ports C1-C3 and up to 11-bit two’s complement data from Processing Core input port C4. Note that
signed or unsigned numbers that fit within the relevant 13-bit or 11-bit dynamic range may also be presented to the device
inputs. This type of input data must still be formatted as a 13-bit or 11-bit two’s complement number, with appropriate sign
extensions. Input bit weighting is as shown below.
OUTPUT/INPUT = 0, HVF_OUT = 0
DATA PORT REFERENCE
Input Port: P112..0 to P312..0
13 BIT PHYSICAL INTERFACE
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
0
0
NA
NA
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
NA
NA
b8
b7
b6
b5
b4
b3
b2
b1
b0
0
0
13 bit Two’s Complement input (10
bit based data)
Input Port: P112..0 to P312..0
11 bit Two’s Complement input (8 bit
based data)
Input Port: P410..0
11 bit Two’s Complement input (10
bit based data)
Input Port: P410..0
9 bit unsigned input (8 bit based
data)
OUTPUT/INPUT = 0, HVF_OUT = 1
DATA PORT REFERENCE
Output Port: P112 P212 or P312
Input Port: P111..0 to P311..0
13 BIT PHYSICAL INTERFACE
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
H, V or F
output
-
-
-
-
-
-
-
-
-
-
-
-
-
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
-
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
0
0
NA
NA
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
NA
NA
b8
b7
b6
b5
b4
b3
b2
b1
b0
0
0
12 bit Two’s Complement input (10
bit based data)
Input Port: P111..0 to P311..0
10 bit Two’s Complement input (8 bit
based data)
Input Port: P410..0
11 bit Two’s Complement input (10
bit based data)
Input Port: P410..0
9 bit unsigned input (8 bit based
data)
521 - 88 - 03
20
OUTPUT/INPUT = 1, HVF_OUT = 0
DATA PORT REFERENCE
Input Port: P512..0 to P712..0
13 BIT PHYSICAL INTERFACE
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
0
0
NA
NA
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
NA
NA
b8
b7
b6
b5
b4
b3
b2
b1
b0
0
0
13 bit Two’s Complement input (10
bit based data)
Input Port: P512..0 to P712..0
11 bit Two’s Complement input (8 bit
based data)
Input Port: P810..0
11 bit Two’s Complement input (10
bit based data)
Input Port: P810..0
9 bit unsigned input (8 bit based
data)
OUTPUT/INPUT = 1, HVF_OUT = 1
DATA PORT REFERENCE
Input Port: P512..0 to P712..0
13 BIT PHYSICAL INTERFACE
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
0
0
NA
NA
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
NA
NA
b8
b7
b6
b5
b4
b3
b2
b1
b0
0
0
13 bit Two’s Complement input (10
bit based data)
Input Port: P512..0 to P712..0
11 bit Two’s Complement input (8 bit
based data)
Input Port: P810..0
11 bit Two’s Complement input (10
bit based data)
Input Port: P810..0
9 bit unsigned input (8 bit based
data)
Input De-multiplexer
Refer to the Input De-multiplexer discussion in the interpolation mode section.
Horizontal Blanking
Refer to the Horizontal Blanking discussion in the interpolation mode section.
Input Offset Adjustment
Refer to the Input Offset Adjustment discussion in the interpolation mode section.
3X3 Color Space Converter and KEY Scaler
Refer to the 3X3 Color Space Converter and KEY scaler discussion in the interpolation mode section.
MATRIX OUTPUT RESOLUTION
Full precision is maintained throughout the 3X3 matrix multiplication. To ensure that maximum precision is maintained by the
GF9105A, rounding of the Y/G, CB/B and CR/R channels depends on the state of the RND8/10 and BYPASS_F control bits
(See HOST Programming Section).
21
521 - 88 - 03
3X3 MATRIX MULTIPLIER RESOLUTION FOR Y/G, CB/B AND CR/R CHANNELS
RND8/10
BYPASS_F
DESCRIPTION
0
X
LSBs are rounded off leaving 10-bit core data and 2 MSB extension bits.
1
0
Minimal rounding is performed, leaving the 8-bit core data and MSB/LSB extensions for high accuracy
when filter is not bypassed.
1
1
More rounding is performed, leaving 8-bit core data and MSB extension bits to increase overall accuracy
when filter is being bypassed.
FIR FILTERS
With INT/DEC set low, the internal FIR filters will be set for decimation of up to 12 input bits, and the CB/B and CR/R channels
will be decimated by a factor of two. As a result, 4:4:4:4 data will be sample rate converted to 4:2:2:4 data. The frequency
response of the decimation filters are shown in Figure 6a and Figure 6b and the characteristics are listed in Figure 6c.
Resolution out of the FIR filters is 13 bits when the device is operated with 10-bit input data and 11 bits when the device is
operated with 8-bit data. The FIL_RND control bit (See HOST Programming Section) should always be set low while INT/DEC
is set low.
FILTER OUTPUT ROUNDING FOR CB/B AND CR/R CHANNELS
RND8/10
DESCRIPTION
0
CB/B and CR/R channels rounded to 13-bit output resolution.
1
CB/B and CR/R channels rounded to 11-bit output resolution.
The BYPASS_F control bit (See Host Programming Section) can be used to bypass the decimation filters. When this bit is set
low, the filters are enabled and normal operation occurs. When this bit is set high, the filters are bypassed and the data is
passed through the filter section unmodified. Total latency through the filter is independent of the BYPASS_F control signal.
Note that after changing the state of BYPASS_F, an initialization period corresponding to the latency of the chip is required
before valid data is available at the output of the device.
BYPASS_F CONTROL BIT OPERATION
BYPASS_F
DESCRIPTION
0
Filters are enabled. Data is sample-rate converted from 4:4:4:4 to 4:2:2:4 data.
1
Filters are disabled. Data is passed through the filter section unmodified.
Output Offset Adjustment
Refer to the Output Offset Adjustment discussion in the interpolation mode section.
Output Clipping
Refer to the Output Clipping discussion in the interpolation mode section.
Output Multiplexer
Refer to the Output Multiplexer discussion in the interpolation mode section.
TIMING REFERENCE SIGNAL (TRS)
Timing Reference Signals (TRS) may be inserted into the output data stream of the GF9105A. In order for the TRS signals to
be inserted, the GF9105A’s H, V and F inputs must be driven with external Horizontal (H), Vertical (V) and Field (F) signals.
Such signals should be synchronized with the incoming data stream. A low to high transition of H triggers the insertion of an
EAV sequence and a high to low transition triggers the insertion of an SAV sequence. Figures 9a, 9b and 9c show the
standard timing (GS9001 control bit is set low) relationships between input data and the H, V and F inputs for multiplexed
data, non-multiplexed data, and single link (4:4:4:4) data, respectively.
521 - 88 - 03
22
When the GS9001 control bit is set high and when operating with a multiplexed 4:2:2 data stream or a dual link (4:4:4:4) data
stream, HVF input signals required for TRS insertion may be supplied by the GS9001. In this case, the multiplexed data
being fed to the GF9105A comes from the GS9001output data bus and the H input of the GF9105A is fed from the HSYNC
output of the GS9001. In addition, the V and F inputs of the GF9105A are fed from the VBLANK and the FIELD outputs of
the GS9001. The relative timing of the input data and the H, V and F input signals in this mode of operation is shown in
Figure 9d.
The H, V and F output signals of the GF9105A are derived from the H, V and F input signals. Figures 9e, 9f and 9g show the
timing relationship between the data output and the H, V and F output signals for multiplexed, non-multiplexed and single link
output data. These timing relationships will be valid provided the timing relationships between the input data and the input H,
V and F input signals are maintained as shown in Figures 9a through to 9e. Note the GS9001 bit does not affect the output
H, V and F timing.
DEVICE LATENCY
When the device is working with dual link input and output data, latency through the device is 68 clock cycles and is constant
regardless of which mode the device is in. When the device is working with single link input or output data, latency through
the device is 136 clock cycles and is constant regardless of which mode the device is in. The latency is counted by starting
at the clock cycle that latches in the input data, and counting the number of clock cycles that occur until the corresponding
output data is clocked out of the device, as illustrated in Figure 13.
HOST PROGRAMMING
The GF9105A has a host interface that allows programming of the 9 matrix coefficients, the key scaler coefficient, and several
static control bits that are used to set the operating mode of the GF9105A. This data is loaded into 23 memory locations. The
host interface consists of a 5-bit address bus (ADDR[4:0]), an 8-bit bi-directional coefficient port (COEFF_PORT[7:0]), a read/
write pin (R/W), and a chip select pin (CS).
To write to a specific memory location, the R/W pin must be set low (putting the coefficient port in input mode). In addition,
the address and coefficient buses must be set. Following this, the CS pin should be changed from high to low. Data will
then be clocked into the specified address.
The settings of a specific memory location can be observed by performing a read operation. This is carried out by setting
the R/W pin high (thus putting the coefficient bus in output mode) and setting the address bus before changing the CS pin
from high to low to clock-in the address. This causes the data stored in the corresponding address to be output on the
coefficient bus.
The standard timing for host writing and reading is shown in Figures 11a and 11b. This is the simplest method of using the
host interface because R/W and the address bus (and coefficient bus when writing) all change at the same time, a minimum
of 20 ns before and after the falling edge of CS. The maximum frequency for CS using this mode of operation is 25 MHz.
Faster (more advanced) reading and writing can be achieved by meeting certain timing requirements, as shown in Figures
12a and 12b. The R/W signal setup time must be met before the first falling edge of CS. In addition, normal setup and hold
times must be provided on the address bus (and the data bus when writing) with respect to the falling edge of CS. The
maximum frequency using this timing is 40 MHz.
Note that the coefficient (COEFF_PORT[7:0]) I/O are tri-stated when CS=1 or when R/W=0.
Since the memory is random access, it is not necessary to write to or read from memory locations sequentially. The memory
can be considered as separate from the GF9105A Processing Core and can be programmed independently of the system
clock.
Since the nine matrix coefficients and the KEY scaler coefficient are 13 bits wide and the memory locations are only 8 bits
wide, each coefficient requires 2 memory locations. For each coefficient, the 5 LSBs are loaded into the MSBs of the first
memory location and the 8 MSBs are loaded into the second memory location.
For example, when loading a 13-bit coefficient into address N and address N+1, bit placement shall be as follows:
The memory is organized such that the 9 matrix coefficients and the key scaler coefficient occupy addresses 0 through 19
(ADDR[4:0]=00000 through ADDR[4:0]=10011). Addresses 20 (ADDR[4:0]=10100), 21 (ADDR[4:0]=10101), and 22
(ADDR[4:0]=10110) contain the static control bits that control the operation of the GF9105A. Note that even if only one
control bit is to be altered, the entire word must be reprogrammed.
23
521 - 88 - 03
ADDRESSING OF SPLIT-UP COEFFICIENTS
ADDRESS
ADDR[4:0] = N
COEFFICIENT PORT ASSIGNMENT
COEFF_PORT[7] = b4
COEFF_PORT[6] = b3
COEFF_PORT[5] = b2
COEFF_PORT[4] = b1
COEFF_PORT[3] = b0
COEFF_PORT[2] = X (don’t care)
COEFF_PORT[1] = X (don’t care)
COEFF_PORT[0] = X (don’t care)
ADDR[4:0] = N+1
COEFF_PORT[7] = b12
COEFF_PORT[6] = b11
COEFF_PORT[5] = b10
COEFF_PORT[4] = b9
COEFF_PORT[3] = b8
COEFF_PORT[2] = b7
COEFF_PORT[1] = b6
COEFF_PORT[0] = b5
MEMORY LOCATION ASSIGNMENTS FOR PROGRAMMING THE HOST INTERFACE
ADDRESS PORT
COEFFICIENT PORT ASSIGNMENT
ADDR[4:0] = 00000
COEFF_PORT[7:3] = CM11[4:0]
ADDR[4:0] = 00001
COEFF_PORT[7:0] = CM11[12:5]
ADDR[4:0] = 00010
COEFF_PORT[7:3] = CM12[4:0]
ADDR[4:0] = 00011
COEFF_PORT[7:0] = CM12[12:5]
ADDR[4:0] = 00100
COEFF_PORT[7:3] = CM13[4:0]
ADDR[4:0] = 00101
COEFF_PORT[7:0] = CM13[12:5]
ADDR[4:0] = 00110
COEFF_PORT[7:3] = CM21[4:0]
ADDR[4:0] = 00111
COEFF_PORT[7:0] = CM21[12:5]
ADDR[4:0] = 01000
COEFF_PORT[7:3] = CM22[4:0]
ADDR[4:0] = 01001
COEFF_PORT[7:0] = CM22[12:5]
ADDR[4:0] = 01010
COEFF_PORT[7:3] = CM23[4:0]
ADDR[4:0] = 01011
COEFF_PORT[7:0] = CM23[12:5]
ADDR[4:0] = 01100
COEFF_PORT[7:3] = CM31[4:0]
ADDR[4:0] = 01101
COEFF_PORT[7:0] = CM31[12:5]
ADDR[4:0] = 01110
COEFF_PORT[7:3] = CM32[4:0]
ADDR[4:0] = 01111
COEFF_PORT[7:0] = CM32[12:5]
ADDR[4:0] = 10000
COEFF_PORT[7:3] = CM33[4:0]
ADDR[4:0] = 10001
COEFF_PORT[7:0] = CM33[12:5]
ADDR[4:0] = 10010
COEFF_PORT[7:3] = KEY[4:0]
ADDR[4:0] = 10011
COEFF_PORT[7:0] = KEY[12:5]
521 - 88 - 03
24
MEMORY LOCATION ASSIGNMENTS FOR PROGRAMMING THE HOST INTERFACE
ADDRESS PORT
ADDR[4:0] = 10100
COEFFICIENT PORT ASSIGNMENT
COEFF_PORT[7] = OUTPUT/INPUT
COEFF_PORT[6] = INT/DEC
COEFF_PORT[5] = BYPASS_F
COEFF_PORT[4] = MUXED_IN
COEFF_PORT[3] = MUXED_OUT
COEFF_PORT[2] = RND8/10
COEFF_PORT[1] = FIL_RND
COEFF_PORT[0] = 4:4:4:4/4:2:2:4_OUT
ADDR[4:0] = 10101
COEFF_PORT[7] = HB1
COEFF_PORT[6] = HB0
COEFF_PORT[5] = IOA1
COEFF_PORT[4] = IOA0
COEFF_PORT[3] = OOA1
COEFF_PORT[2] = OOA0
COEFF_PORT[1] = CLP_D1
COEFF_PORT[0] = CLP_D0
ADDR[4:0] = 10110
COEFF_PORT[7] = GS9001
COEFF_PORT[6] = SL/DL_IN
COEFF_PORT[5] = SL/DL_OUT
COEFF_PORT[4] = S*
COEFF_PORT[3] = 0 (RESERVED)
COEFF_PORT[2] = HVF_OUT
COEFF_PORT[1] = 0 (RESERVED)
COEFF_PORT[0] = LOWF
With single link output data, the S control bit should be set LOW for GBR signals
(S=0) and set HIGH for Y, CB, CR signals (S=1).
25
521 - 88 - 03
20.00
MAGNITUDE (dB)
0.00
-20.00
-40.00
-60.00
-80.00
-100.00
-120.00
-140.00
0.00
1.00
2.00
3.00
4.00
5.00
6.00
7.00
FREQUENCY (MHz)
Fig. 6a Interpolation/Decimation filter Frequency Response
(Sampling at 13.5 MHz)
0.030
MAGNITUDE (dB)
0.020
0.010
0.00
-0.010
-0.020
-0.030
0.00
0.50
1.00
1.50
2.00
2.50
3.00
FREQUENCY (MHz)
Fig. 6b Interpolation/Decimation Filter Pass band
(Sampling at 13.5 MHz)
PARAMETER
VALUE
Filter Order
57
Pass Band Ripple
< ±0.0089 dB
Pass Band Edge
2.850 MHz
DC Gain
0.000 dB
3.375 MHz (ƒS/4) Attenuation
12.058 dB
Minimum Stop Band Attenuation
58.615 dB
Stop Band Edge
3.669 MHz
Fig. 6c Interpolation/Decimation filter Characteristics at Sampling Frequency of 13.5 MHz
521 - 88 - 03
26
27/36MHz CLK
4:2:2 DATA
KEY:X:X or
KEY:2:2 DATA
Y0
CB0
XXX or CB1
KEY0
CR0
Y1
CB2
XXX or CR1
KEY1
Y2
XXX OR CB3
KEY2
CR2
Y3
XXX OR CR3
KEY3
SYNC_CB
Fig. 7a Timing of SYNC_CB Signal with Dual Link 4:2:2:4 or Dual Link 4:4:4:4 Input Data
54 MHz CLK
4:4:4:4 DATA
Y0/G0
CB0/B0
CR0/R0
CB1/B1
KEY0
Y1/G1
CR1 /R1
KEY1
SYNC_CB
Fig. 7b Timing of SYNC_CB Signal with Single Link Multiplexed 4:4:4:4 Input Data
27/36MHz CLK
Y/G
Y0/G0
Y1 /G1
Y2 /G2
CB/B
CB0/B0
XXX OR CB1/B1
CB2 /B2
XXX OR CB3/B3
CR/R
CR0/R0
CR2 /R2
XXX OR CR3/R3
KEY2
KEY3
KEY
KEY0
XXX OR CR1/R1
KEY1
Y3/G3
SYNC_CB
Fig. 7c Timing of SYNC_CB Signal with Non-Multiplexed 4:2:2:4 or 4:4:4:4 Input Data
27
521 - 88 - 03
13.5/18MHz CLK
Y0/G0
Y/G
CB0/B0
CB/B
KEY
Y2 /G2
XXX OR CB1/B1
CR0/R0
CR/R
Y1 /G1
CB2 /B2
XXX OR CR1/R1
XXX OR CB3/B3
CR2/R2
KEY1
KEY0
Y3/G3
XXX OR CR3 /R3
KEY2
KEY3
SYNC_CB
Fig. 7d Timing of SYNC_CB Signal with Non-Multiplexed 4:2:2:4 or 4:4:4:4 Input Data (Low Frequency Mode)
GENNUM
GS9001
4:2:2
DATA IN
GENNUM
GS9001
HSYNC
DATA OUT
SYNC_CB
C5
C1
C6
4:2:2
GENNUM
GF9105A
DATA
OUT
KEY:X:X
C4
C7
C8
OR KEY:2:2
KEY:X:X
DATA IN
OR KEY:2:2
Fig. 8a GF9105A Optionally Coupled to the GS9001 EDH Coprocessor for Multiplexed Input and Non-Multiplexed Output Data, GS9001
Control Bit set High
SYNC_CB
GENNUM
GS9001
HSYNC
H
V BLANK
V
F
FIELD
4:2:2
DATA IN
GENNUM
GS9001
DATA OUT
DATA
OUT
C5
4:2:2
KEY:X:X
C1
GENNUM
GF9105A
C8
C4
OR KEY:2:2
KEY:X:X
DATA IN
OR KEY:2:2
Fig. 8b GF9105A Optionally Coupled to the GS9001 EDH Coprocessor for Multiplexed Input and Output Data, GS9001 Control Bit set High
521 - 88 - 03
28
4:2:2 DATA IN
3FF
000
000
TRS-ID
3FF
000
000
TRS-ID
H IN
V IN
F IN
Fig. 9a Relative Timing of Multiplexed Input Data and H, V and F Inputs (GS9001 = 0)
Y/G
LAS
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
FAS
CB/B
LAS
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
FAS
CR/R
LAS
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
FAS
K
LAS
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
FAS
H IN
V IN
F IN
LAS = Last Active Sample
FAS = First Active Sample
Fig. 9b Relative Timing of Non-Multiplexed Input Data and H, V and F Inputs
29
521 - 88 - 03
4:4:4:4 DATA IN
3FF
000
000
TRS-ID
3FF
000
000
TRS-ID
H IN
V IN
F IN
Fig. 9c Relative Timing of Single Link Input Data and H, V and F Inputs
4:2:2 DATA IN
FROM DATA
OUTPUT OF GS9001
3FF
000
000
TRS-ID
3FF
000
000
TRS-ID
SYNC_CB AND H
FROM HSYNC
OUTPUT OF GS9001
V FROM VERTICAL
OUTPUT OF GS9001
F FROM FIELD
OUTPUT OF GS9001
Fig. 9d Relative Timing of Data, SYNC_CB, H, V and F Inputs (GS9001 = 1)
4:2:2 DATA OUT
3FF
000
000
TRS-ID
3FF
000
000
TRS-ID
H OUT
V OUT
F OUT
Fig. 9e Relative Timing of Dual Link 4:2:2:4 or Dual Link 4:4:4:4 Multiplexed Output Data and H, V and F Output Signals
521 - 88 - 03
30
Y/G
LAS
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
FAS
CB/B
LAS
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
FAS
CR/R
LAS
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
FAS
K
LAS
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
FAS
H OUT
V OUT
F OUT
LAS = Last Active Sample
FAS = First Active Sample
Fig. 9f Relative Timing of Non-Multiplexed Output Data and H, V and F Output Signals
4:4:4:4 DATA OUT
3FF
000
000
TRS-ID
3FF
000
000
TRS-ID
H OUT
V OUT
F OUT
Fig. 9g Relative Timing of Single Link 4:4:4:4 Multiplexed Output Data and H, V and F Output Signals
31
521 - 88 - 03
4:2:2 DATA
KEY:X:X OR KEY:2:2
DATA_IN
CB'N
Y'N
XXX OR CB'N+1
KEY'N
CR'N
XXX OR CR'N+1
Y'N+1
CBN+2
KEY'N+1
XXX OR CBN+3
YN+2
KEYN+2
CRN+2
YN+3
XXX OR CRN+3
KEYN+3
HBLANK
Fig. 10a Typical Timing of H_BLANK Signal with Dual Link Multiplexed 4:2:2:4 or 4:4:4:4 Input Data
4:4:4:4 DATA
CB'N /B'N
Y'N /G'N
CR'N /R'N
KEY'N
CBN+1 /BN+1
YN+1 /GN+1
CRN+1 /RN+1
KEYN+1
HBLANK
Fig. 10b Typical Timing of H_BLANK Signal with Single Link Multiplexed 4:4:4:4 Input Data
Y/G
Y'N /GN
CB/B
CB'N /BN
CR/R
CR'N /RN
KEY
KEY'N
YN+1/GN+1
XXX OR CBN+1 /BN+1
XXX OR CRN+1/RN+1
KEYN+1
YN+2 /GN+2
YN+3/GN+3
CBN+2 /BN+2
XXX OR CBN+3 /BN+3
CRN+2/RN+2
XXX OR CRN+3 /RN+3
KEYN+2
KEYN+3
H_BLANK
Fig. 10c Typical Timing of H_BLANK Signal with Non-Multiplexed 4:2:2:4 or 4:4:4:4 Input Data
521 - 88 - 03
32
20ns
20ns
20ns
20ns
R/W
CS
ADDR
N
N+1
N+2
COEFF_PORT
N
N+1
N+2
Fig. 11a Standard Host Interface Timing for Writing to the GF9105A
20ns
20ns
20ns
20ns
R/W
CS
N
ADDR
N+1
N+2
tHEN
tHDIS
N
COEFF_PORT
N+1
N+2
Fig. 11b Standard Host Interface Timing for Reading from the GF9105A
tRWS
R/W
tH
tS
CS
ADDR
COEFF_PORT
N
N+1
N+2
N
N+1
N+2
Fig. 12a Advanced Host Interface Timing for Writing to the GF9105A
33
521 - 88 - 03
tRWS
R/W
tH
tS
CS
N
ADDR
N+1
N+2
tHEN
tHDIS
COEFF_PORT
N
N+1
N+2
Fig. 12b Advanced Host Interface Timing for Reading from the GF9105A
0
CLK
1
2
tS
3
4
69
70
71
tCY
tOD
tH
DATA IN
1
2
3
4
tOH
DATA OUT
1
Fig. 13 Illustration of Device Latency and I/O Timing
521 - 88 - 03
72
34
2
3
4
ABSOLUTE MAXIMUM RATINGS
PARAMETER
VALUE/UNITS
Supply Voltage (VDD)
-0.3 to +7.0 V
-0.5 V to (VDD+0.5) V
Input Voltage Range (any input)
Operating Temperature Range
0°C to 70°C
0 MHz <= ƒCLK <= 54MHz
Storage Temperature Range
-65°C <= TS <= 150°C
Lead Temperature (soldering, 10 seconds)
260°C
ELECTRICAL CHARACTERISTICS
Conditions: VDD = 5 V, TA = 0° to 70° C unless otherwise shown.
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
4.75
5
5.25
V
Supply Voltage
VDD
Supply Current Quiescent
IDDQ
VDD = Max, VIN = 0V
-
0.5
Supply Current Unloaded
IDDU
VDD = Max, DP_EN = VDD, ƒ = 27 MHz
-
73
-
mA
Input Voltage, Logic Low
VIL
-
-
0.8
V
Input Voltage, Logic High
VIH
2
-
-
V
Output Voltage, Logic Low
VOL
VDD = Min, IOL = 2 mA
-
-
0.4
V
Output Voltage, Logic High
VOH
VDD = Min, IOH = -2 mA
2.4
-
-
V
Input Capacitance
CIN
TA = 25°C, ƒ = 1 MHz
-
-
10
pF
COUT
TA = 25°C, ƒ = 1MHz
-
-
10
pF
MIN
TYP
MAX
UNITS
Output Capacitance
mA
SWITCHING CHARACTERISTICS
Conditions: VDD = 5 V, TA = 0° to 70° C unless otherwise shown.
PARAMETER
SYMBOL
CONDITIONS
Input Setup Time
tS
6
-
-
ns
Input Hold Time
tH
2
-
-
ns
Output Delay Time
tOD
VDD = Min, CL = 25 pF
-
-
13
ns
Output Hold Time
tOH
VDD = Max, CL = 25 pF
4
-
-
ns
Output Enable Time
tEN
VDD = Min, CL = 25 pF
-
-
12
ns
Output Disable Time
tDIS
VDD = Min, CL = 25 pF
-
-
12
ns
Host Interface R/W Setup
Time
tRWS
20
-
-
ns
Host Interface Output Enable
Time
tHEN
VDD = Min, CL = 25 pF
-
-
12
ns
Host Interface Output
Disable Time
tHDIS
VDD = Max, CL = 25 pF
-
-
12
ns
35
521 - 88 - 03
SWITCHING CHARACTERISTICS
Conditions: VDD = 5 V, TA = 0° to 70° C unless otherwise shown.
PARAMETER
Clock Cycle Time
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
tCY
Non-Multiplexed Input Data AND NonMultiplexed Output Data LOWF=1
55
-
-
ns
All Input/Output Data Formats Except
Single Link
27
-
-
ns
SMPTE RP174 Single Link Input OR
Output Data
18
-
-
ns
Clock Pulse Width Low
tPWL
As a percentage of Min. Clock Cycle
Time
40
-
60
%
Clock Pulse Width High
tPWH
As a percentage of Min. Clock Cycle
Time
40
-
60
%
Low Frequency Mode (LOWF = 1)
34
34
34
clks
Dual link input and output data
68
68
68
clks
Single link input or output data
136
136
136
clks
Device Latency
1
Note 1: Latency is defined as the number of clock cycles between the time when the data is latched into the device and when the
corresponding output data is clocked out of the device. Refer to Figure 13.
521 - 88 - 03
36
31.20
28.00 ±0.10
10 ±2˚
0.40 MIN
8˚ MAX
0˚ MIN
31.20 ±0.25
28.00 ±0.10
0.13/0.30 MAX
RADIUS
0˚ MIN
7˚ MAX
10 ±2˚
0.13 MIN
RADIUS
0.88 ±0.15
1.6
REF
160
1
3.42 ±0.25
4.10 MAX
0.65 BSC
0.30 ±0.08
Fig. 14 160 Pin MQFP
CAUTION
ELECTROSTATIC
SENSITIVE DEVICES
DO NOT OPEN PACKAGES OR HANDLE
EXCEPT AT A STATIC-FREE WORKSTATION
REVISION NOTES:
Updated Input Clock (CLK) information.
DOCUMENT IDENTIFICATION
DATA SHEET
The product is in production. Gennum reserves the right to make
changes at any time to improve reliability, function or design, in order to
provide the best product possible.
GENNUM CORPORATION
MAILING ADDRESS:
P.O. Box 489, Stn. A, Burlington, Ontario, Canada L7R 3Y3
Tel. +1 (905) 632-2996 Fax. +1 (905) 632-5946
SHIPPING ADDRESS:
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For latest product information, visit www.gennum.com
GENNUM JAPAN CORPORATION
C-101, Miyamae Village, 2-10-42 Miyamae, Suginami-ku
Tokyo 168-0081, Japan
Tel. +81 (03) 3334-7700 Fax. +81 (03) 3247-8839
GENNUM UK LIMITED
25 Long Garden Walk, Farnham, Surrey, England GU9 7HX
Tel. +44 (0)1252 747 000 Fax +44 (0)1252 726 523
Gennum Corporation assumes no responsibility for the use of any circuits described herein and makes no representations that they are free from patent infringement.
© Copyright June 1999 Gennum Corporation. All rights reserved. Printed in Canada.
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