ETC KAD5512HP

KAD5512HP
Preliminary
High Performance 12-Bit, 250/210/170/125MSPS ADC
General Description
The KAD5512HP is the high-performance member of
the KAD5512 family of 12-bit analog-to-digital
converters. Designed with Kenet’s proprietary
FemtoCharge® technology on a standard CMOS
process, the family supports sampling rates of up to
250MSPS. The KAD5512HP is part of a pin-compatible
portfolio of 10, 12 and 14-bit A/Ds with sample rates
ranging from 125MSPS to 500MSPS.
A serial peripheral interface (SPI) port allows for
extensive configurability, as well as fine control of
various parameters such as gain and offset.
Digital output data is presented in selectable LVDS
or CMOS formats. The KAD5512HP is available in 72and 48-contact QFN packages with an exposed
paddle. Operating from a 1.8V supply, performance
is specified over the full industrial temperature range
(-40 to +85°C).
Features
•
•
•
•
•
•
•
•
•
•
•
•
Pin-Compatible with the KAD5512P family,
offering 2.5dB higher SNR
Programmable gain and offset control
950MHz analog input bandwidth
52fs Clock Jitter
Over-range indicator
Selectable Clock Divider: ÷1, ÷2 or ÷4
Clock Phase Selection
Nap and Sleep modes
Two’s complement, Gray code or Binary data
format
SDR/DDR LVDS-compatible or LVCMOS outputs
Programmable Built-in Test Patterns
1.8V Analog and Digital Supplies
Applications
•
•
•
•
•
•
Power Amplifier Linearization
Radar and Satellite Antenna Array Processing
Broadband Communications
High-Performance Data Acquisition
Communications Test Equipment
WiMAX and Microwave Receivers
Key Specifications
•
•
•
SNR = 67.2dBFS for fIN = 124MHz (-1dBFS)
SFDR = 81dBc for fIN = 124MHz (-1dBFS)
Power consumption
• 400/313mW @ 250/125MSPS (SDR Mode)
• 347/269mW @ 250/125MSPS (DDR Mode)
Pin-Compatible Family
Model
Resolution
Speed (MSPS)
KAD5514P-25
14
250
KAD5514P-21
14
210
KAD5514P-17
14
170
KAD5514P-12
14
125
KAD5512P-50
12
500
KAD5512P-25, KAD5512HP-25
12
250
KAD5512P-21, KAD5512HP-21
12
210
KAD5512P-17, KAD5512HP-17
12
170
KAD5512P-12, KAD5512HP-12
12
125
KAD5510P-50
10
500
300 Unicorn Park Dr., Woburn, MA 01801
Sales: 1-781-497-0060
FemtoCharge is a registered trademark of Kenet, Inc.
Rev 0.5
[email protected]
Copyright © 2008, Kenet, Inc.
Page 1
KAD5512HP
Table of Contents
Section
Electrical Specifications
Pages
3–7
Section
Serial Peripheral Interface
Pages
20–26
DC Specifications
3
SPI Physical Interface
21
AC Specifications
4
SPI Configuration
22
Digital Specifications
5
DUT Information
23
Switching Specifications
6
DUT Configuration/Control
23
Timing Diagrams
6
DUT Test
25
Absolute Maximum Ratings
7
SPI Memory Map
26
Thermal Impedance
7
Equivalent Circuits
27
ESD
7
Layout Considerations
27
Definitions
28
Pinout/Package Information
8–11
Pin Descriptions—72QFN
8
Outline Dimensions—72QFN
29
Pin Configuration—72QFN
9
Outline Dimensions—72QFN
30
Pin Descriptions—48QFN
10
Ordering Guide
31
Pin Configuration—48QFN
11
Revision History
31
Typical Performance Characteristics
12–15
Theory of Operation
16–19
Functional Description
16
Power-On Calibration
16
User-Initiated Reset
17
Analog Input
17
Clock Input
18
Jitter
18
Voltage Reference
18
Digital Outputs
18
Power Dissipation
19
Nap/Sleep
19
Data Format
19
Rev 0.5 Preliminary
Page 2
KAD5512HP
Electrical Specifications
All specifications apply under the following conditions unless otherwise noted: AVDD = 1.8V, OVDD = 1.8V, TA =
-40°C to +85°C, AIN = -1dBFS, fSAMPLE = Maximum Conversion Rate (per speed grade).
DC Specifications
KAD5512HP-25
Parameter
KAD5512HP-21
KAD5512HP-17
KAD5512HP-12
Symbol
Conditions
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Units
VFS
Differential
1.38
1.45
1.59
1.38
1.45
1.59
1.38
1.45
1.59
1.38
1.45
1.59
VPP
Analog Input
Full-Scale Analog Input Range
Input Resistance
RIN
Differential
1000
1000
1000
1000
Ω
Input Capacitance
CIN
Differential
4
4
4
4
pF
Full Scale Range Temp. Drift
AVTC
Full Temp
90
90
90
90
ppm/°C
Input Offset Voltage
VOS
±1.5
±1.5
±1.5
±1.5
mV
Gain Error
EG
±0.6
±0.6
±0.6
±0.6
%
VCM
0.535
0.535
0.535
0.535
V
Common-Mode Output Voltage
Power Requirements
1.8V Analog Supply Voltage
AVDD
1.7
1.8
1.9
1.7
1.8
1.9
1.7
1.8
1.9
1.7
1.8
1.9
V
1.8V Digital Supply Voltage
OVDD
1.7
1.8
1.9
1.7
1.8
1.9
1.7
1.8
1.9
1.7
1.8
1.9
V
1.8V Analog Supply Current
IAVDD
154
TBD
142
TBD
130
TBD
116
TBD
mA
1.8V Digital Supply Current (SDR)
IOVDD
68.0
TBD
64.6
TBD
61.7
TBD
58.1
TBD
mA
1.8V Digital Supply Current (DDR)
IOVDD
38.9
TBD
36.9
TBD
35.3
TBD
33.2
TBD
mA
Power Supply Rejection Ratio
PSRR
0.5
Normal Mode (SDR)
PD
400
TBD
372
TBD
345
TBD
313
TBD
mW
Normal Mode (DDR)
PD
347
TBD
322
TBD
298
TBD
269
TBD
mW
Nap Mode
PD
40
TBD
40
TBD
40
TBD
40
TBD
mW
Sleep Mode
PD
10
TBD
10
TBD
10
TBD
10
TBD
mW
0.5
0.5
0.5
mV/V
Power Dissipation
Rev 0.5 Preliminary
Page 3
KAD5512HP
AC Specifications
KAD5512HP-25
Parameter
Symbol
Conditions
Min
Differential Nonlinearity
DNL
fIN = 10MHz
Integral Nonlinearity
INL
fIN = 10MHz
Minimum Conversion Rate
fS MIN
Maximum Conversion Rate
fS MAX
Signal-to-Noise Ratio
SNR
SINAD
Max
Min
TBD
TBD
TBD
TBD
SFDR
Two-Tone SFDR
IMD
2TSFDR
Full Power Bandwidth
Rev 0.5 Preliminary
FPBW
Max
Min
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
210
Typ
Max
Units
TBD
TBD
LSB
TBD
TBD
LSB
TBD
170
TBD
125
MSPS
MSPS
68.7
dBFS
fIN = 70MHz
67.4
67.8
68.3
68.6
dBFS
68.2
dBFS
68.0
dBFS
TBD
67.2
TBD
67.6
TBD
68.0
TBD
fIN = 230MHz
66.9
67.6
fIN = 400MHz
65.9
TBD
TBD
TBD
dBFS
fIN = 974MHz
62.2
TBD
TBD
TBD
dBFS
fIN = 10MHz
66.2
66.7
67.0
67.3
dBFS
fIN = 70MHz
66.1
66.5
67.0
67.3
dBFS
66.6
dBFS
67.3
dBFS
TBD
65.6
TBD
65.4
68.0
66.0
TBD
66.9
66.4
TBD
67.3
fIN = 400MHz
63.4
TBD
TBD
TBD
dBFS
fIN = 974MHz
54.0
TBD
TBD
TBD
dBFS
fIN = 10MHz
10.7
10.8
10.8
10.9
Bits
fIN = 70MHz
10.7
10.8
10.8
10.9
Bits
10.8
Bits
10.9
Bits
TBD
10.6
TBD
10.7
TBD
10.7
TBD
fIN = 230MHz
10.6
10.8
fIN = 400MHz
10.2
TBD
TBD
TBD
Bits
fIN = 974MHz
8.7
TBD
TBD
TBD
Bits
fIN = 10MHz
85
84
85
84
dBc
fIN = 70MHz
84
83
82
82
dBc
77
dBc
76
dBc
TBD
83
TBD
10.9
80
TBD
78
TBD
fIN = 230MHz
77
77
fIN = 400MHz
71
TBD
TBD
TBD
dBc
fIN = 974MHz
57
TBD
TBD
TBD
dBc
fIN = 10MHz
TBD
TBD
TBD
TBD
dBFS
fIN = 70MHz
-91.5
fIN = 170MHz
-86.5
TBD
TBD
TBD
dBFS
fIN = 10MHz
TBD
TBD
TBD
TBD
dBc
fIN = 124MHz
TBD
fIN = 170MHz
Word Error Rate
TBD
Typ
68.4
fIN = 140MHz
Intermodulation Distortion
Min
68.0
fIN = 140MHz
Spurious-Free Dynamic Range
Max
KAD5512HP-12
67.5
fIN = 230MHz
ENOB
KAD5512HP-17
fIN = 10MHz
fIN = 140MHz
Effective Number of Bits
Typ
TBD
250
fIN = 140MHz
Signal-to-Noise and Distortion
Typ
KAD5512HP-21
TBD
TBD
TBD
TBD
76
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
10-12
10-12
10-12
10-12
950
950
950
950
TBD
TBD
dBFS
dBc
dBc
MHz
Page 4
KAD5512HP
Digital Specifications
Parameter
Symbol
Conditions
Min
Typ
Max
Units
Inputs
Input Current High (RESETN)
IIH
VIN = 1.8V
0
1
10
µA
Input Current Low (RESETN)
IIL
VIN = 0V
25
50
75
µA
Input Current High (OUTMODE,
NAP/SLP, CLKDIV, OUTFMT )
IIH
TBD
25
TBD
µA
Input Current Low (OUTMODE,
NAP/SLP, CLKDIV, OUTFMT )
IIL
TBD
25
TBD
µA
Input Capacitance
CDI
3
pF
Differential Output Voltage
VT
210
mV
Output Offset Voltage
VOS
TBD
mV
Output Rise Time
tR
500
ps
Output Fall Time
tF
500
ps
Voltage Output High
VOH
OVDD-0.1
V
Voltage Output Low
VOL
0.1
V
Output Rise Time
tR
TBD
ns
Output Fall Time
tF
TBD
ns
LVDS Outputs
CMOS Outputs
Rev 0.5 Preliminary
Page 5
KAD5512HP
Switching Specifications
Parameter
Symbol
Min
Typ
Max
Units
ADC
Aperture Delay
tA
375
ps
RMS Aperture Jitter
jA
52
fs
Input Clock to Output Clock Propagation Delay
tCPD
TBD
TBD
TBD
ps
Input Clock to Data Propagation Delay
tPD
TBD
TBD
TBD
ps
Output Clock to Data Propagation Delay
tDC
TBD
TBD
TBD
ps
Latency (Pipeline Delay)
L
7.5
cycles
Over Voltage Recovery
tOVR
1
cycles
Timing Diagrams
Sample N
Sample N
INP
INP
INN
INN
tA
tA
CLKN
CLKP
CLKN
CLKP
tCPD
Latency = L Cycles
tCPD
CLKOUTN
CLKOUTP
Latency = L Cycles
CLKOUT
tDC
tDC
tPD
tPD
D[10/8/6/4/2/0]P
D[10/8/6/4/2/0]N
Odd Bits
N-L
Even Bits
N-L
Odd Bits
N-L+1
Even Bits
N-L+1
Odd Bits
N-L+2
Even Bits
N-L+2
Odd Bits
N
Figure 1a. LVDS Timing Diagram—DDR
D[10/8/6/4/2/0]
Odd Bits
N-L
Even Bits
N-L
Odd Bits
N-L+1
Even Bits
N-L+1
Odd Bits
N-L+2
Even Bits
N-L+2
Odd Bits
N
Figure 2a. CMOS Timing Diagram—DDR
Sample N
Sample N
INP
INP
INN
INN
tA
tA
CLKN
CLKP
CLKN
CLKP
tCPD
Latency = L Cycles
tCPD
CLKOUTN
CLKOUTP
CLKOUT
tDC
D[11:0]P
D[11:0]N
tDC
tPD
tPD
Data
N-L
Data
N-L+1
Data
N-L+2
Figure 1b. LVDS Timing Diagram—SDR
Rev 0.5 Preliminary
Latency = L Cycles
Data
N
D[11:0]
Data
N-L
Data
N-L+1
Data
N-L+2
Data
N
Figure 2b. CMOS Timing Diagram—SDR
Page 6
KAD5512HP
Absolute Maximum Ratings1
Parameter
Min
Max
Unit
AVDD to AVSS
-0.4
2.1
V
OVDD to OVSS
-0.4
2.1
V
AVSS to OVSS
-0.3
0.3
V
Analog Inputs to AVSS
-0.4
AVDD + 0.3
V
Clock Inputs to AVSS
-0.4
AVDD + 0.3
V
Logic Input to AVSS
-0.4
OVDD + 0.3
V
Logic Inputs to OVSS
-0.4
OVDD + 0.3
V
Operating Temperature
-40
85
°C
Storage Temperature
-65
150
°C
150
°C
Junction Temperature
1. Exposing the device to levels in excess of the maximum ratings may cause permanent damage. Exposure to
maximum conditions for extended periods may affect device reliability.
Thermal Impedance
Parameter
Symbol
Typ
Unit
Junction to Paddle2
ΦJP
30
°C/W
Junction to Case2
ΦJC
TBD
°C/W
Junction to Ambient2
ΦJA
TBD
°C/W
2. Paddle soldered to ground plane.
ESD
Electrostatic charge accumulates on humans, tools and equipment and may discharge
through any metallic package contacts (pins, balls, exposed paddle, etc.) of an integrated
circuit. Industry-standard protection techniques have been utilized in the design of this product. However, reasonable care must be taken in the storage and handling of ESD sensitive
products. Contact Kenet for the specific ESD sensitivity rating of this product.
Rev 0.5 Preliminary
Page 7
KAD5512HP
Pin Descriptions—72QFN
Pin #
LVDS [LVCMOS] Name
LVDS [LVCMOS] Function
1, 6, 19, 24, 71
AVDD
1.8V Analog Supply
2-5, 13, 14, 17, 18, 28-31 DNC
Do Not Connect
7, 8, 11, 12, 72
AVSS
Analog Ground
9, 10
VINN, VINP
Analog Input Negative, Positive
15
VCM
Common Mode Output
16
CLKDIV
Clock Divider Control
20, 21
CLKP, CLKN
Clock Input True, Complement
22
OUTMODE
Output Mode (LVDS, LVCMOS)
23
NAPSLP
Power Control (Nap, Sleep modes)
25
RESETN
Power On Reset (Active Low)
26, 45, 55, 65
OVSS
Output Ground
27, 36, 56
OVDD
1.8V Output Supply
32, 33
D0N, D0P [NC, D0]
LVDS Bit 0 (LSB) Output Complement, True [NC, LVCMOS Bit 0]
34, 35
D1N, D1P [NC, D1]
LVDS Bit 1 Output Complement, True [NC, LVCMOS Bit 1]
37, 38
D2N, D2P [NC, D2]
LVDS Bit 2 Output Complement, True [NC, LVCMOS Bit 2]
39, 40
D3N, D3P [NC, D3]
LVDS Bit 3 Output Complement, True [NC, LVCMOS Bit 3]
41, 42
D4N, D4P [NC, D4]
LVDS Bit 4 Output Complement, True [NC, LVCMOS Bit 4]
43, 44
D5N, D5P [NC, D5]
LVDS Bit 5 Output Complement, True [NC, LVCMOS Bit 5]
46
RLVDS
LVDS Bias Resistor (connect to OVSS with a 10kΩ, 1% resistor)
47, 48
CLKOUTN, CLKOUTP [NC, CLKOUT]
LVDS Clock Output Complement, True [NC, LVCMOS CLKOUT]
49, 50
D6N, D6P [NC, D6]
LVDS Bit 6 Output Complement, True [NC, LVCMOS Bit 6]
51, 52
D7N, D7P [NC, D7]
LVDS Bit 7 Output Complement, True [NC, LVCMOS Bit 7]
53, 54
D8N, D8P [NC, D8]
LVDS Bit 8 Output Complement, True [NC, LVCMOS Bit 8]
57, 58
D9N, D9P [NC, D9]
LVDS Bit 9 Output Complement, True [NC, LVCMOS Bit 9]
59, 60
D10N, D10P [NC, D10]
LVDS Bit 10 Output Complement, True [NC, LVCMOS Bit 10]
61, 62
D11N, D11P [NC, D11]
LVDS Bit 11(MSB) Output Complement, True [NC, LVCMOS Bit 11]
63, 64
ORN, ORP [NC, OR]
LVDS Over Range Complement, True [NC, LVCMOS Over Range]
66
SDO
SPI Serial Data Output (4.7kΩ pull-up to OVDD is required)
67
CSB
SPI Chip Select (active low)
68
SCLK
SPI Clock
69
SDIO
SPI Serial Data Input/Output
70
OUTFMT
Output Data Format (Two’s Comp., Gray Code, Offset Binary)
Exposed Paddle
AVSS
Analog Ground
LVCMOS Output Mode Functionality is shown in brackets (NC = No Connection)
Rev 0.5 Preliminary
Page 8
KAD5512HP
Pin Configuration—72QFN
AVDD
DNC
DNC
DNC
DNC
AVDD
AVSS
AVSS
VINN
VINP
AVSS
AVDD
DNC
DNC
VCM
CLKDIV
DNC
DNC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
KAD5512
72 QFN
Top View
Not to Scale
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
D8P
D8N
D7P
D7N
D6P
D6N
CLKOUTP
CLKOUTN
RLVDS
OVSS
D5P
D5N
D4P
D4N
D3P
D3N
D2P
D2N
Figure 3. 72 QFN Pin Configuration
Rev 0.5 Preliminary
Page 9
KAD5512HP
Pin Descriptions—48QFN
Pin #
LVDS [LVCMOS] Name
LVDS [LVCMOS] Function
1, 9, 13, 17, 47
AVDD
1.8V Analog Supply
2-4, 11, 21, 22
DNC
Do Not Connect
5, 8, 12, 48
AVSS
Analog Ground
6, 7
VINN, VINP
Analog Input Negative, Positive
10
VCM
Common Mode Output
14, 15
CLKP, CLKN
Clock Input True, Complement
16
NAPSLP
Power Control (Nap, Sleep modes)
18
RESETN
Power On Reset (Active Low)
19, 29, 41
OVSS
Output Ground
20, 42
OVDD
1.8V Output Supply
23, 24
D0N, D0P [NC, D0]
LVDS Bit 0 (LSB) Output Complement, True [NC, LVCMOS Bit 0]
25, 26
D1N, D1P [NC, D1]
LVDS Bit 1 Output Complement, True [NC, LVCMOS Bit 1]
27, 28
D2N, D2P [NC, D2]
LVDS Bit 2 Output Complement, True [NC, LVCMOS Bit 2]
30
RLVDS
LVDS Bias Resistor (connect to OVSS with a 10kΩ, 1% resistor)
31, 32
CLKOUTN, CLKOUTP [NC, CLKOUT]
LVDS Clock Output Complement, True [NC, LVCMOS CLKOUT]
33, 34
D3N, D3P [NC, D3]
LVDS Bit 3 Output Complement, True [NC, LVCMOS Bit 3]
35, 36
D4N, D4P [NC, D4]
LVDS Bit 4 Output Complement, True [NC, LVCMOS Bit 4]
37, 38
D5N, D5P [NC, D5]
LVDS Bit 5 Output Complement, True [NC, LVCMOS Bit 5]
39, 40
ORN, ORP [NC, OR]
LVDS Over Range Complement, True [NC, LVCMOS Over Range]
43
SDO
SPI Serial Data Output (4.7kΩ pull-up to OVDD is required)
44
CSB
SPI Chip Select (active low)
45
SCLK
SPI Clock
46
SDIO
SPI Serial Data Input/Output
Exposed Paddle
AVSS
Analog Ground
LVCMOS Output Mode Functionality is shown in brackets (NC = No Connection)
Rev 0.5 Preliminary
Page 10
KAD5512HP
48
47
46
45
44
43
42
41
40
39
38
37
AVSS
AVDD
SDIO
SCLK
CSB
SDO
OVSS
ORP
ORN
D5P
D5N
OVDD
Pin Configuration—48QFN
1
2
3
4
5
6
7
8
9
10
11
12
KAD5512
48 QFN
Top View
Not to Scale
36
35
34
33
32
31
30
29
28
27
26
25
D4P
D4N
D3P
D3N
CLKOUTP
CLKOUTN
RLVDS
OVSS
D2P
D2N
D1P
D1N
AVDD
CLKP
CLKN
NAPSLP
AVDD
RESETN
OVSS
OVDD
DNC
DNC
D0N
D0P
13
14
15
16
17
18
19
20
21
22
23
24
AVDD
DNC
DNC
DNC
AVSS
VINN
VINP
AVSS
AVDD
VCM
DNC
AVSS
Figure 4. 48QFN Pin Configuration
Rev 0.5 Preliminary
Page 11
KAD5512HP
Typical Performance Curves
SNRFS (dBFS) & SFDR (dBc)
90
85
SFDR
80
75
70
TBD
65
60
55
SNRFS
50
0
200
400
600
800
1000
INPUT FREQUENCY (MHz)
Figure 5. SNR & SFDR vs. fIN
Figure 6. HD2 & HD3 vs. fIN
TBD
TBD
Figure 7. SNR & SFDR vs. AIN
Figure 8. HD2 & HD3 vs. AIN
SNRFS (dBFS) & SFDR (dBc)
90
85
80
SFDR
75
SNRFS
TBD
70
65
60
30
80
130
180
230
SAMPLE RATE (MSPS)
Figure 9. SNR & SFDR vs. fSAMPLE
Rev 0.5 Preliminary
Figure 10. HD2 & HD3 vs. fSAMPLE
Page 12
KAD5512HP
Typical Performance Curves
TOTAL POWER (mW)
450
400
350
TBD
300
250
200
30
80
130
180
230
SAMPLE RATE (MSPS)
Figure 11. Power vs. fSAMPLE (LVDS Mode)
Figure 12. Differential Nonlinearity
TBD
TBD
Figure 13. Integral Nonlinearity
Figure 14. SNR & SFDR vs. VCM
TBD
TBD
Figure 15. Noise Histogram
Figure 16. Single Tone Spectrum @ 10 MHz
Rev 0.5 Preliminary
Page 13
KAD5512HP
Typical Performance Curves
TBD
TBD
Figure 17. Single Tone Spectrum @ 70 MHz
Figure 18. Single Tone Spectrum @ 140 MHz
TBD
TBD
Figure 19. Single Tone Spectrum @ 240 MHz
Figure 20. Single Tone Spectrum @ 500 MHz
TBD
TBD
Figure 21. Two-Tone Spectrum @ 10 MHz
Figure 22. Two-Tone Spectrum @ 70 MHz
Rev 0.5 Preliminary
Page 14
KAD5512HP
Typical Performance Curves
TBD
TBD
Figure 23. Two-Tone Spectrum @ 140 MHz
Figure 24. Two-Tone Spectrum @ 240 MHz
SNRFS (dBFS) & SFDR (dBc)
90
TBD
85
80
SFDR
75
SNRFS
70
65
60
-40
-20
0
20
40
60
80
TEMPERATURE (°C)
Figure 25. Two-Tone Spectrum @ 500 MHz
Figure 26. SNR & SFDR vs. Temperature
SNRFS (dBFS) & SFDR (dBc)
90
85
80
75
SFDR
SNRFS
70
65
60
1.6
1.65
1.7
1.75
1.8
1.85
1.9
1.95
2
AVDD & OVDD (V)
Figure 27. SNR & SFDR vs. Power Supply Voltage
Rev 0.5 Preliminary
Page 15
KAD5512HP
Power-On Calibration
Functional Description
The KAD5512HP is based upon a 12-bit, 250MSPS A/D
converter core that utilizes a pipelined successive
approximation architecture (Figure 28). The input
voltage is captured by a Sample-Hold Amplifier (SHA)
and converted to a unit of charge. Proprietary
charge domain techniques are used to successively
compare the input to a series of reference charges.
Decisions made during the successive approximation
operations determine the digital code for each input
value. The converter pipeline requires six samples to
produce a result. Digital error correction is also applied, resulting in a total latency of seven and a half
clock cycles. This is evident to the user as a time lag
between the start of a conversion and the data being available on the digital outputs.
The KAD5512HP family offers 2.5dB improvement in
SNR over the KAD5512P by simultaneously sampling
the input signal with two ADC cores in parallel and
summing the digital result. Since the input signal is
correlated between the two cores and noise is not,
an increase in SNR is achieved. As a result of this architecture, indexed SPI operations must be executed
on each core in series. Refer to the Indexed DUT Configuration/Control section for more details.
At start-up, the core performs a self-calibration to
minimize gain and offset errors. An internal power-onreset (POR) circuit detects the supply voltage ramps
and initiates the calibration when the analog and
digital supply voltages are above a threshold. The
following conditions must be adhered to for the
power-on calibration to execute successfully:
•
A frequency-stable conversion clock must be
applied to the CLKP/CLKN pins
• DNC pins (especially 3, 4 and 18) must not be
pulled up or down
• SDO (pin 66) must be high
• RESETN (pin 25) must begin low
• SPI communications must not be attempted
A user-initiated reset can subsequently be invoked in
the event that the above conditions cannot be met
at power-up.
The SDO pin requires an external 4.7kΩ pull-up to
OVDD. If the SDO pin is pulled low externally during
power-up, calibration will not be executed properly.
After the power supply has stabilized the internal POR
releases RESETN and an internal pull-up pulls it high,
which starts the calibration sequence. The RESETN pin
should be connected to an open-drain driver with a
drive strength of less than 0.5mA.
Figure 28. ADC Core Block Diagram
Rev 0.5 Preliminary
Page 16
KAD5512HP
The calibration sequence is initiated on the rising
edge of RESETN, as shown in Figure 29. The overrange output (OR) is set high once RESETN is pulled
low, and remains in that state until calibration is complete. The OR output returns to normal operation at
that time, so it’s important that the analog input be
within the converter’s full-scale range in order to observe the transition. If the input is in an over-range
condition the OR pin will stay high and it will not be
possible to detect the end of the calibration cycle.
While RESETN is low, the output clock
(CLKOUTP/CLKOUTN) stops toggling and is set low.
Normal operation of the output clock resumes at the
next input clock edge (CLKP/CLKN) after RESETN is
deasserted. At 250MSPS the nominal calibration time
is TBDms.
Figure 29. Calibration Timing
User Initiated Reset
Recalibration of the ADC can be initiated at any
time by driving the RESETN pin low for a minimum of
one clock cycle. An open-drain driver with a drive
strength of less than 0.5mA is recommended. As is the
case during power-on reset, the SDO, RESETN and
DNC pins must be in the proper state for the calibration to successfully execute.
Analog Input
The ADC core contains a fully differential input
(VINP/VINN) to the sample and hold amplifier (SHA).
The ideal full-scale input voltage is 1.45V, centered at
the VCM voltage of 0.535V as shown in Figure 30.
Figure 30. Analog Input Range
Best performance is obtained when the analog inputs are driven differentially. The common mode output voltage, VCM, should be used to properly bias
the inputs as shown in Figures 31 through 33. An RF
transformer will give the best noise and distortion performance for wideband and/or high intermediate
frequency (IF) inputs. Two different transformer input
schemes are shown in Figures 31 and 32.
Figure 31. Transformer Input for General Purpose
Applications
Figure 32. Transmission-line Transformer Input for High
IF Applications
A back-to-back transformer scheme is used to improve common mode rejection, which keeps the
common mode level of the input matched to VCM.
The value of the shunt resistor should be determined
based on the desired load impedance. The differential input resistance of the KAD5512HP is 1000Ω.
The SHA design uses a switched capacitor input
stage, which creates charge kick-back when the
sampling capacitance is reconnected to the input
voltage. This kick-back creates a disturbance at the
input which must settle before the next sampling
point. Lower source impedance will result in faster
Rev 0.5 Preliminary
Page 17
KAD5512HP
settling and improved performance. Therefore a 1:1
transformer and low shunt resistance are recommended for optimal performance.
Table 1. CLKDIV Pin Settings
The clock divider can also be controlled through the
SPI port, which overrides the CLKDIV pin setting. Details on this are contained in the Serial Peripheral Interface section.
A delay-locked loop (DLL) generates internal clock
signals for various stages within the charge pipeline. If
the frequency of the input clock changes, the DLL
may take up to 52µs to regain lock at 250MSPS. The
lock time is inversely proportional to the sample rate.
Jitter
Figure 33. Differential Amplifier Input
A differential amplifier, as shown in Figure 33, can be
used in applications that require dc-coupling. In this
configuration the amplifier will typically dominate the
achievable SNR and distortion performance.
In a sampled data system, clock jitter directly impacts the achievable SNR performance. The theoretical relationship between clock jitter (tJ) and SNR is
shown in Equation 1 and is illustrated in Figure 35.
⎛
1
SNR = 20 log 10 ⎜⎜
⎝ 2 π fIN t J
Clock Input
Equation 1.
The clock input circuit is a differential pair (see Figure
36). Driving these inputs with a high level (up to 1.8VPP
on each input) sine or square wave will provide the
lowest jitter performance. A transformer with 4:1 impedance ratio will provide increased drive levels.
100
95
tj=0.1ps
90
14 Bits
85
SNR - dB
The recommended drive circuit is shown in Figure 34.
The clock can be driven single-ended, but this will
reduce the edge rate and may impact SNR performance. The clock inputs are internally self-biased to
AVDD/2 to facilitate ac coupling.
⎞
⎟
⎟
⎠
80
tj=1ps
12 Bits
75
70
tj=10ps
65
60
10 Bits
tj=100ps
55
50
1
10
100
1000
Input Frequency - MHz
Figure 35. SNR vs. Clock Jitter
Figure 34. Recommended Clock drive
A selectable 2X/4X divider is provided in series with
the clock input. The divider can be used in the 2X
mode with a sample clock equal to twice the desired
sample rate. This will result in a clock input with 50%
duty cycle and will maximize the converter’s performance.
CLKDIV Pin
Divide Ratio
AVSS
2
Float
1
AVDD
4
Rev 0.5 Preliminary
This relationship shows the SNR that would be
achieved if clock jitter were the only non-ideal factor. In reality, achievable SNR is limited by internal
factors such as linearity, aperture jitter and thermal
noise. Internal aperture jitter is the uncertainty in the
sampling instant shown in Figure 1. The internal aperture jitter combines with the input clock jitter in a rootsum-square fashion, since they are not statistically
correlated, and this determines the total jitter in the
system. The total jitter, combined with other noise
sources, then determines the achievable SNR.
Voltage Reference
A temperature compensated voltage reference provides the reference charges used in the successive
approximation operations. The full-scale range of
Page 18
KAD5512HP
each A/D is proportional to the reference voltage.
The voltage reference is internally bypassed and is
not accessible to the user.
lated to the clock frequency in CMOS mode. Figures
36 and 37 illustrate these relationships.
Digital Outputs
Output data is available as a parallel bus in LVDScompatible or CMOS modes. Additionally, the data
can be presented in either double data rate (DDR) or
single data rate (SDR) formats. The even numbered
output bits are active in DDR mode. When CLKOUT is
low the MSB and all odd bits are output, while on the
high phase the LSB and all even bits are presented.
Figures 1 and 2 show the timing relationships for
LVDS/CMOS and DDR/SDR modes.
The 48-QFN package option contains six LVDS data
outputs, and therefore can only support DDR mode.
TBD
Figure 36. Power vs. Sample Rate, LVDS Mode
Additionally, the drive current for LVDS mode can be
set to a nominal 3 mA or a power-saving 2 mA. The
lower current setting can be used in designs where
the receiver is in close physical proximity to the ADC.
The applicability of this setting is dependent upon the
PCB layout, therefore the user should experiment to
determine if performance degradation is observed.
TBD
The output mode and LVDS drive current are selected via the OUTMODE pin as shown in Table 3.
OUTMODE Pin
Mode
AVSS
LVCMOS
Float
LVDS, 3 mA
AVDD
LVDS, 2 mA
Table 2. OUTMODE Pin Settings
The output mode can also be controlled through the
SPI port, which overrides the OUTMODE pin setting.
Details on this are contained in the Serial Peripheral
Interface section.
An external resistor creates the bias for the LVDS drivers. A 10kΩ, 1% resistor must be connected from the
RLVDS pin to OVSS.
Power Dissipation
The power dissipated by the KAD5512HP is primarily
dependent on the sample rate, but is also related to
the input signal in CMOS output mode. There is a
static bias in the analog supply, while the remaining
power dissipation is linearly related to the sample
rate. The output supply dissipation changes to a
lesser degree in LVDS mode, but is more strongly re-
Rev 0.5 Preliminary
Figure 37. Power vs. Sample Rate, CMOS Mode
Nap/Sleep
Portions of the device may be shut down to save
power during times when operation of the ADC is not
required. Two power saving modes are available:
nap, and sleep. Nap mode reduces power dissipation to 40mW and recovers to normal operation in
approximately 1µs. Sleep mode reduces power dissipation to 10mW but requires 1ms to recover. The
clock should remain running and at a fixed frequency during Nap or Sleep. Recovery time from
Nap mode will increase if the clock is stopped, since
the internal DLL can take up to 52µs to regain lock at
250MSPS.
By default after the device is powered on, the operational state is controlled by the NAPSLP pin as shown
in Table 4.
Page 19
KAD5512HP
NAPSLP Pin
Mode
AVSS
Normal
Float
Sleep
AVDD
Nap
Figure 38. Binary to Gray Code Conversion
Converting back to offset binary from gray code
must be done recursively, using the result of each bit
for the next lower bit as shown in Figure 39.
Table 3. NAPSLP Pin Settings
The power down mode can also be controlled
through the SPI port, which overrides the NAPSLP pin
setting. Details on this are contained in the Serial Peripheral Interface section. This is an indexed function
when controlled from the SPI, but a global function
when driven from the pin.
Data Format
Output data can be presented in three formats:
two’s complement, Gray code and offset binary. The
data format is selected via the OUTFMT pin as shown
in Table 5.
OUTFMT Pin
Mode
AVSS
Offset Binary
Float
Two’s Complement
Figure 39. Gray Code to Binary Conversion
Gray Code
Mapping of the input voltage to the various data formats is shown in Table 6.
AVDD
Table 4. OUTFMT Pin Settings
The data format can also be controlled through the
SPI port, which overrides the OUTFMT pin setting. Details on this are contained in the Serial Peripheral Interface section.
Offset binary coding maps the most negative input
voltage to code 0x000 (all zeros) and the most positive input to 0xFFF (all ones). Two’s complement coding simply complements the MSB of the offset binary
representation.
When calculating Gray code the MSB is unchanged.
The remaining bits are computed as the XOR of the
current bit position and the next most significant bit.
Figure 38 shows this operation.
Input
Voltage
Offset
Binary
Two’s
Complement
Gray
Code
–Full Scale
000000000000
100000000000
000000000000
–Full Scale
+ 1LSB
000000000001
100000000001
000000000001
Mid–Scale
100000000000
000000000000
110000000000
+Full Scale
– 1LSB
111111111110
011111111110
100000000001
+Full Scale
111111111111
011111111111
100000000000
Table 5. Input Voltage to Output Code Mapping
Serial Peripheral Interface
A serial peripheral interface (SPI) bus is used to facilitate configuration of the device and to optimize performance. The SPI bus consists of chip select (CSB),
serial clock (SCLK) and serial data input/output
(SDIO). The maximum SCLK rate is equal to the ADC
sample rate (fSAMPLE) divided by 16 for write operations and fSAMPLE divided by 66 for reads. At fSAMPLE =
250MHz, maximum SCLK is 15.63MHz for writing and
Rev 0.5 Preliminary
Page 20
KAD5512HP
3.79MHz for write operations. There is no minimum
SCLK rate.
The following sections describe various registers that
are used to configure the SPI or adjust performance
or functional parameters. Many registers in the available address space (0x00 to 0xFF) are not defined in
this document. Additionally, within a defined register
there may be certain bits or bit combinations that
are reserved. Undefined registers and undefined values within defined registers are reserved and should
not be selected. Setting any reserved register or
value may produce indeterminate results.
SPI Physical Interface
The SPI port operates in a half or full duplex master/slave configuration, with the KAD5512HP functioning as a slave. Multiple slave devices can interface to
a single master. The chip-select bar (CSB) pin determines when a slave device is being addressed. Multiple slave devices can be written to concurrently, but
only one slave device can be read from at a given
time. If multiple slave devices are selected for reading at the same time, the results will be indeterminate.
The serial clock pin (SCLK) provides synchronization
for the data transfer. By default, all data is presented
on the serial data input/output (SDIO) pin. The state
of the SDIO pin is set automatically in the communication protocol (described below). A dedicated serial data output pin (SDO) can be activated by setting 0x00[7] high to allow operation in full duplex
mode.
The communication protocol begins with an instruction/address phase. The first rising SCLK edge following a high to low transition on CSB determines the
beginning of the two-byte instruction/address command. Data can be presented in MSB-first order or
LSB-first order. The default is MSB-first, but this can be
changed by setting 0x00[6] high. Figures 40 and 41
show the appropriate bit ordering for the MSB-first
and LSB-first modes, respectively. In MSB-first mode
the address is incremented for multi-byte transfers,
while in LSB-first mode it’s decremented.
In the default mode the MSB is R/W, which determines if the data is to be read (active high) or written. The next two bits, W1 and W0, determine the
number of data bytes to be read or written (see Table 6). The lower 13 bits contain the first address for
the data transfer. This relationship is illustrated in Figure 42, and timing values are given in the Switching
Specifications section.
After the instruction/address bytes have been read,
the appropriate number of data bytes are written to
or read from the ADC (based on the R/W bit status).
The data transfer will continue as long as CSB remains
low and SCLK is active. Stalling of the CSB pin is allowed at any byte boundary (instruction/address or
data) if the number of bytes being transferred is three
or less. For transfers of four bytes or more, CSB is allowed stall in the middle of the instruction/address
bytes or before the first data byte. If CSB transitions to
a high state after that point the state machine will
reset and terminate the data transfer.
Figure 40. MSB-First Addressing
Figure 41. LSB-First Addressing
Rev 0.5 Preliminary
Page 21
KAD5512HP
[W1:W0]
Bytes Transferred
00
1
01
2
10
3
11
or LSB to MSB (LSB first) to accommodate various microcontrollers.
Bit 7
Bit 6
SDO Active
LSB First
Setting this bit high configures the SPI to interpret serial data as arriving in LSB to MSB order.
4 or more
Table 6. Byte Transfer Selection
Bit 5
Figures 43 and 44 illustrate the timing relationships for
2-byte and N-byte transfers, respectively. The operation for a 3-byte transfer can be inferred from these
diagrams.
SPI Configuration
Soft Reset
Setting this bit high resets all SPI registers to
default values.
Bit 4
Reserved
This bit should always be set high.
Bits 3:0 These bits should always mirror bits 4:7 to
avoid ambiguity in bit ordering.
Address 0x00: chip_port_config
Bit ordering and SPI reset are controlled by this register. Bit order can be selected as MSB to LSB (MSB first)
Figure 42. Instruction/Address Phase
Figure 43. 2-Byte Transfer
Figure 44. N-Byte Transfer
Rev 0.5 Preliminary
Page 22
KAD5512HP
Address 0x02: burst_end
If a series of sequential registers are to be set, burst
mode can improve throughput by eliminating redundant addressing. In 3-wire SPI mode the burst is
ended by pulling the CSB pin high. If the device is
operated in 2-wire mode the CSB pin is not available.
In that case, setting the burst_end address determines the end of the transfer. During a write operation, the user must be cautious to transmit the correct
number of bytes based on the starting and ending
addresses.
Bits 7:0 Burst End Address
This register value determines the ending address of the burst data.
DUT Information
Address 0x08: chip_id
Address 0x09: chip_version
The generic die identifier and a revision number, respectively, can be read from these two registers.
Indexed DUT Configuration/Control
Address 0x10: device_index_A
A common SPI map, which can accommodate single-channel or multi-channel devices, is used for all
Kenet ADC products. Certain configuration commands (identified as Indexed in the SPI map) can be
executed on a per-converter basis. This register determines which converter is being addressed for an
Indexed command. It is important to note that only a
single converter can be addressed at a time.
This register defaults to 00h, indicating that no ADC is
addressed. Single-channel ADCs must set Bit 0 of this
register high in order to execute any Indexed commands.
Address 0x20: offset_coarse
Address 0x21: offset_fine
The input offset of each ADC core can be adjusted
in fine and coarse steps. Both adjustments are made
via an 8-bit word as detailed in Table 7. The data format is twos complement.
The default value of each register will be the result of
the self-calibration after initial power-up. If a register is
to be incremented or decremented, the user should
first read the register value then write the incremented or decremented value back to the same
register.
Parameter
0x20[7:0]
0x21[7:0]
Coarse Offset
Fine Offset
Steps
256
256
–Full Scale (0x80)
-24.0mV
-1.7mV
Mid–Scale (0x00)
0.0mV
0.0mV
+Full Scale (0x7F)
+23.8mV
+1.7mV
Nominal Step Size
187.5µV
13.3µV
Table 7. Offset Adjustments
Address 0x22: gain_coarse
Address 0x23: gain_medium
Address 0x24: gain_fine
Gain of each ADC core can be adjusted in coarse,
medium and fine steps. Coarse gain is a 4-bit adjustment while medium and fine are 8-bit. The data format is twos complement for all three registers.
The default value of each register will be the result of
the self-calibration after initial power-up. If a register is
to be incremented or decremented, the user should
first read the register value then write the incremented or decremented value back to the same
register.
Parameter
0x22[3:0]
Coarse Gain
Steps
16
–Full Scale (0x08)
-11.2%
Mid–Scale (0x00)
0.0%
+Full Scale (0x07)
+9.8%
Nominal Step Size
1.4%
Table 8. Coarse Gain Adjustment
Parameter
0x23[7:0]
Medium Gain
0x24[7:0]
Fine Gain
Steps
256
256
–Full Scale (0x80)
-10.56%
-1.06%
Mid–Scale (0x00)
0.0%
0.0%
+Full Scale (0x7F)
+10.48%
+1.05%
Nominal Step Size
0.0825%
0.00825%
Table 9. Medium and Fine Gain Adjustments
Address 0x25: modes
Two distinct reduced power modes can be selected.
By default, the tri-level NAPSLP pin can select normal
Rev 0.5 Preliminary
Page 23
KAD5512HP
operation, nap or sleep modes (refer to Nap/Sleep
section). This functionality can be overridden and
controlled through the SPI. This is an indexed function
when controlled from the SPI, but a global function
when driven from the pin. This register is not changed
by a Soft Reset.
Value
0x25[2:0]
Power Down Mode
000
Pin Control
001
Normal Operation
010
Nap Mode
100
Sleep Mode
Table 10. Power Down Control
Global DUT Configuration/Control
Address 0x70: skew_diff
The value in the skew_diff register adjusts the timing
skew between the two ADCs cores. The nominal
range and resolution of this adjustment are given in
Table 11. The default value of this register after powerup is 00h.
Parameter
0x70[7:0]
Differential Skew
Steps
256
–Full Scale (0x08)
-6.5ps
Mid–Scale (0x00)
0.0ps
+Full Scale (0x07)
+6.5ps
Nominal Step Size
51fs
Table 11. Differential Skew Adjustment
Address 0x71: phase_slip
When using a clock divider, it’s not possible to determine the synchronization of the incoming and divided
clock phases. This is particularly important when multiple ADCs are used in a time-interleaved system. The
phase slip feature allows the rising edge of the divided
clock to be advanced by one input clock cycle, as
shown in Figure 45.
Rev 0.5 Preliminary
Figure 45. Phase Slip
Address 0x72: clock_divide
The KAD5512HP has a selectable clock divider that
can be set to divide by four, two or one (no division).
By default, the tri-level CLKDIV pin selects the divisor
(refer to Clock Input section). This functionality can be
overridden and controlled through the SPI, as shown
in Table 12. This register is not changed by a Soft Reset.
Value
0x72[2:0]
Clock Divider
000
Pin Control
001
Divide by 1
010
Divide by 2
100
Divide by 4
Table 12. Clock Divider Selection
Address 0x73: output_mode_A
The output_mode_A register controls the physical output format of the data, as well as the logical coding.
The KAD5512HP can present output data in two physical formats: LVDS or LVCMOS. Additionally, the drive
strength in LVDS mode can be set high (3mA) or low
(2mA). By default, the tri-level OUTMODE pin selects
the mode and drive level (refer to Digital Outputs section). This functionality can be overridden and controlled through the SPI, as shown in Table 13.
Data can be coded in three possible formats: two’s
complement, Gray code or offset binary. By default,
the tri-level OUTFMT pin selects the data format (refer
to Data Format section). This functionality can be overridden and controlled through the SPI, as shown in Table 14.
This register is not changed by a Soft Reset.
Page 24
KAD5512HP
Value
0x93[7:5]
Output Mode
000
Pin Control
001
LVDS 2mA
ing. A static word can be placed on the output bus,
or two different words can alternate. In the alternate
mode, the values defined as Word 1 and Word 2 (as
shown in Table 13) are set on the output bus on alternating clock phases.
010
LVDS 3mA
Address 0xC0: test_io
100
LVCMOS
Table 13. Output Mode Control
Value
0x93[2:0]
Output Format
000
Pin Control
001
Two’s Complement
010
Gray Code
100
Offset Binary
Table 14. Output Format Control
Bits 7:6 User Test Mode
These bits set the test mode to static (0x00) or
alternate (0x01) mode. Other values are reserved.
The four LSBs in this register (Output Test Mode) determine the test pattern in combination with registers
0xC2 through 0xC5. Refer to Table 15.
Value
0xC0[3:0]
Output Test Mode
0000
Off
Word 1
Word 2
0001
Midscale
0x8000
N/A
Address 0x74: output_mode_B
0010
Positive Full-Scale
0xFFFF
N/A
Address 0x75: config_status
0011
Negative Full-Scale
0x0000
N/A
Bit 6
0100
Checkerboard
0xAAAA
0x5555
0101
Reserved
N/A
N/A
0110
Reserved
N/A
N/A
DDR Enable
0111
One/Zero
0xFFFF
0x0000
Setting this bit enables Double Data-Rate
mode.
1000
User Pattern
user_patt1
user_patt2
DLL Range
This bit sets the DLL operating range to fast
(T B D 2 M S P S t o 2 5 0 MS P S ) o r s l o w (4 0 t o
TBD1MSPS).
Bit 4
The output_mode_B and config_status registers are
used in conjunction to enable DDR mode and select
the frequency range of the DLL clock generator. The
method of setting these options is different from the
other registers.
Table 15. Output Test Modes
Address 0xC2: user_patt1_lsb
Address 0xC3: user_patt1_msb
These registers define the lower and upper eight bits,
respectively, of the first user-defined test word.
Address 0xC2: user_patt2_lsb
Address 0xC3: user_patt2_msb
These registers define the lower and upper eight bits,
respectively, of the second user-defined test word.
Figure 46. Setting output_mode_B register
The procedure for setting output_mode_B is shown in
Figure 46. Read the contents of output_mode_B and
config_status and XOR them. Then XOR this result with
the desired value for output_mode_B and write that
XOR result to the register.
DUT Test
The KAD5512HP can produce preset or user defined
patterns on the digital outputs to facilitate in-situ testRev 0.5 Preliminary
Page 25
KAD5512HP
DUT Test
Global DUT Config/Control
Indexed DUT Config/Control
DUT
SPI Config
Info
SPI Memory Map
Addr
(Hex)
Parameter Name
Bit 7 (MSB)
00
01
02
03-07
08
09
10
11-1F
20
21
22
23
24
25
port_config
reserved
burst_end
reserved
chip_id
chip_version
device_index_A
reserved
offset_coarse
offset_fine
gain_coarse
gain_medium
gain_fine
modes
SDO Active LSB First
26-5F
60-6F
reserved
reserved
70
71
reserved
phase_slip
72
clock_divide
73
output_mode_A
74
output_mode_B
75
76-BF
C0
config_status
reserved
test_io
C1
C2
C3
C4
C5
C6-FF
Reserved
user_patt1_lsb
user_patt1_msb
user_patt2_lsb
user_patt2_msb
reserved
Bit 6
Bit 5
Bit 4
Bit 3
Soft Reset
Bit 2
Bit 1
Bit 0 (LSB)
Mirror (bit5)
Mirror (bit6)
Mirror (bit7)
Reserved
Burst end address [7:0]
Reserved
Chip ID #
Chip Version #
Reserved
Reserved
Coarse Offset
Fine Offset
ADC00
Reserved
Coarse Gain
Medium Gain
Fine Gain
Power Down Mode [2:0]
000=Pin Control
001=Normal Operation
010=Nap
100=Sleep
other codes=reserved
Def. Value Indexed/
(Hex) Global
00h
G
00h
G
Read only
Read only
00h
G
G
I
cal. value
cal. value
cal. value
cal. value
cal. value
00h
NOT
affected
by Soft
Reset
I
I
I
I
I
I
Reserved
Reserved
Reserved
Reserved
Clock Divide [2:0]
000=Pin Control
001=divide by 1
010=divide by 2
100=divide by 4
other codes=reserved
Output Format [2:0]
000=Pin Control
001=Twos Complement
010=Gray Code
100=Offset Binary
other codes=reserved
Output Mode [2:0]
000=Pin Control
001=LVDS 2mA
010=LVDS 3mA
100=LVCMOS
other codes=reserved
DLL Range
0=fast
1=slow
DDR Enable
XOR Result
User Test Mode [2:0]
00=Single
01=Alternate
10=Single Once
11=Alternate Once
Reset PN
Long Gen
B7
B15
B7
B15
B5
B13
B5
B13
B6
B14
B6
B14
Next Clock
Edge
XOR Result
Reserved
Reset PN
Short Gen
0=Off
Output Test Mode [3:0]
1=Midscale Short
2=+FS Short
3=−FS Short
4=Checker Board
5=reserved
6=reserved
B4
B12
B4
B12
Reserved
B3
B11
B3
B11
Reserved
B2
B10
B2
B10
00h
G
00h
NOT
affected
by Soft
Reset
G
00h
NOT
affected
by Soft
Reset
G
00h
NOT
affected
by Soft
Reset
Read Only
G
00h
G
00h
00h
00h
00h
00h
G
G
G
G
G
G
7=One/Zero Word Toggle
8=User Input
9-15=reserved
B1
B9
B1
B9
B0
B8
B0
B8
Table 16. SPI Memory Map
Rev 0.5 Preliminary
Page 26
KAD5512HP
Equivalent Circuits
Figure 47. Analog Inputs
AVDD
Figure 51. LVDS Outputs
To
Charge
Pipeline
AVDD
CLKP
AVDD
11kΩ
18kΩ
AVDD
11kΩ
Figure 52. CMOS Outputs
18kΩ
CLKN
Figure 53. VCM_OUT Output
Figure 48. Clock Inputs
Layout Considerations
Split Ground and Power Planes
Figure 49. Tri-Level Digital Inputs
Data converters operating at high sampling frequencies require extra care in PC board layout. Many
complex board designs benefit from isolating the
analog and digital sections. Analog supply and
ground planes should be laid out under signal and
clock inputs. Locate the digital planes under outputs
and logic pins. Grounds should be joined under the
chip.
Clock Input Considerations
Use matched transmission lines to the transformer inputs for the analog input and clock signals. Locate
transformers and terminations as close to the chip as
possible.
Figure 50. Digital Inputs
Rev 0.5 Preliminary
Page 27
KAD5512HP
Exposed Paddle
The exposed paddle must be electrically connected
to analog ground (AVSS) and should be connected
to a large copper plane using numerous vias for optimal thermal performance.
Bypass and Filtering
Bulk capacitors should have low equivalent series resistance. Tantalum is a good choice. For best performance, keep ceramic bypass capacitors very
close to device pins. Longer traces will increase inductance, resulting in diminished dynamic performance and accuracy. Make sure that connections to
ground are direct and low impedance. Avoid forming ground loops.
LVDS Outputs
Output traces and connections must be designed for
50Ω (100Ω differential) characteristic impedance.
Keep traces direct and minimize bends where possible. Avoid crossing ground and power plane breaks
with signal traces.
LVCMOS Outputs
Output traces and connections must be designed for
50Ω characteristic impedance.
Unused Inputs
Standard logic inputs (RESETN, CSB, SCLK, SDIO, SDO)
which will not be operated do not require connection to ensure optimal ADC performance. These inputs can be left floating if they are not used. Tri-level
inputs (NAPSLP, OUTMODE, OUTFMT, CLKDIV) accept
a floating input as a valid state, and therefore should
be biased according to the desired functionality.
Definitions
Analog Input Bandwidth is the analog input frequency at which the spectral output power at the
fundamental frequency (as determined by FFT analysis) is reduced by 3dB from its full-scale low-frequency
value. This is also referred to as Full Power Bandwidth.
Aperture Delay or Sampling Delay is the time required after the rise of the clock input for the sampling switch to open, at which time the signal is held
for conversion.
Aperture Jitter is the RMS variation in aperture delay
for a set of samples.
Rev 0.5 Preliminary
Clock Duty Cycle is the ratio of the time the clock
wave is at logic high to the total time of one clock
period.
Differential Non-Linearity (DNL) is the deviation of any
code width from an ideal 1 LSB step.
Effective Number of Bits (ENOB) is an alternate
method of specifying Signal to Noise-and-Distortion
Ratio (SINAD). In dB, it is calculated as: ENOB =
(SINAD-1.76) / 6.02
Gain Error is the ratio of the difference between the
voltages that cause the lowest and highest code
transitions to the full-scale voltage (less 2 LSB). It is
typically expressed in percent.
Integral Non-Linearity (INL) is the deviation of each
individual code from a line drawn from negative fullscale (1/2 LSB below the first code transition) through
positive full-scale (1/2 LSB above the last code transition). The deviation of any given code from this line is
measured from the center of that code.
Least Significant Bit (LSB) is the bit that has the smallest value or weight in a digital word. Its value in terms
of input voltage is VFS/(2N-1) where N is the resolution
in bits.
Missing Codes are output codes that are skipped
and will never appear at the ADC output. These
codes cannot be reached with any input value.
Most Significant Bit (MSB) is the bit that has the largest
value or weight.
Pipeline Delay is the number of clock cycles between
the initiation of a conversion and the appearance at
the output pins of the data.
Power Supply Rejection Ratio (PSRR) is the ratio of a
change in input voltage necessary to correct a
change in output code that results from a change in
power supply voltage.
Signal to Noise-and-Distortion (SINAD) is the ratio of
the RMS signal amplitude to the RMS value of the sum
of all other spectral components below one half the
clock frequency, including harmonics but excluding
DC.
Signal-to-Noise Ratio (without Harmonics) is the ratio
of the RMS signal amplitude to the sum of all other
spectral components below one-half the sampling
frequency, excluding harmonics and DC.
SNR and SINAD are either given in units of dBc (dB to
carrier) when the absolute power of the fundamental
is used as the reference, or dBFS (dB to full scale)
when the converter’s full-scale input power is used as
the reference.
Page 28
KAD5512HP
Spurious-Free-Dynamic Range (SFDR) is the ratio of
the RMS signal amplitude to the RMS value of the
peak spurious spectral component. The peak spurious spectral component may or may not be a harmonic.
Two-Tone SFDR is the ratio of the RMS value of the
lowest power input tone to the RMS value of the
peak spurious component, which may or may not be
an IMD product.
Outline Dimensions—72QFN
Figure 54. 72QFN Dimensions
Rev 0.5 Preliminary
Page 29
KAD5512HP
Outline Dimensions—48QFN
Figure 55. 48QFN Dimensions
Rev 0.5 Preliminary
Page 30
KAD5512HP
Ordering Guide
The KAD5512HP is compliant with EU directive 2002/95/EC regarding the Restriction of Hazardous Substances (RoHS). Contact Kenet for a materials declaration for this product.
Model
Speed
Package
Temp. Range
KAD5512HP-25Q72
250MSPS
72-QFN
-40°C to +85°C
KAD5512HP-21Q72
210MSPS
72-QFN
-40°C to +85°C
KAD5512HP-17Q72
170MSPS
72-QFN
-40°C to +85°C
KAD5512HP-12Q72
125MSPS
72-QFN
-40°C to +85°C
KAD5512HP-25Q48
250MSPS
48-QFN
-40°C to +85°C
KAD5512HP-21Q48
210MSPS
48-QFN
-40°C to +85°C
KAD5512HP-17Q48
170MSPS
48-QFN
-40°C to +85°C
KAD5512HP-12Q48
125MSPS
48-QFN
-40°C to +85°C
Revision History
21-Feb-08:
Rev 0.5
Initial Version
Preliminary Datasheet
This datasheet contains preliminary technical data, which is subject to change without notice. Contact Kenet
prior to initiating design activity using this product.
Rev 0.5 Preliminary
Page 31