P-Channel Logic Level Enhancement NIKO-SEM PA102FMG Mode Field Effect Transistor (Preliminary) SOT-23 Lead-Free D PRODUCT SUMMARY V(BR)DSS RDS(ON) ID -20 118mΩ -3A 1 :GATE 2 :DRAIN 3 :SOURCE G S ABSOLUTE MAXIMUM RATINGS (TC = 25 °C Unless Otherwise Noted) PARAMETERS/TEST CONDITIONS SYMBOL LIMITS UNITS Drain-Source Voltage VDS -20 V Gate-Source Voltage VGS ±12 V TC = 25 °C Continuous Drain Current -3 ID TC = 70 °C Pulsed Drain Current -1.4 1 IDM TC = 25 °C Power Dissipation A -10 1.25 PD TC = 70 °C W 0.8 Operating Junction & Storage Temperature Range Tj, Tstg -55 to 150 °C THERMAL RESISTANCE RATINGS THERMAL RESISTANCE SYMBOL Junction-to-Ambient TYPICAL MAXIMUM UNITS 166 °C / W RθJA 1 Pulse width limited by maximum junction temperature. Duty cycle ≤ 1% 2 ELECTRICAL CHARACTERISTICS (TC = 25 °C, Unless Otherwise Noted) PARAMETER SYMBOL TEST CONDITIONS LIMITS UNIT MIN TYP MAX STATIC Drain-Source Breakdown Voltage V(BR)DSS VGS = 0V, ID = -250µA VGS(th) VDS = VGS, ID = -250µA Gate-Body Leakage IGSS VDS = 0V, VGS = ±12V ±100 Zero Gate Voltage Drain Current IDSS VDS = -16V, VGS = 0V -1 VDS = -16V, VGS = 0V, TJ = 125 °C -10 Gate Threshold Voltage On-State Drain Current 1 Drain-Source On-State Resistance1 Forward Transconductance1 ID(ON) RDS(ON) gfs VDS = -5V, VGS = -4.5V -20 V -0.45 -0.8 -1.2 -6 nA µA A VGS = -2.5V, ID =-1A 150 215 VGS = -4.5V, ID = -2A 98 118 VGS = -10V, ID = -2A 72 85 VDS = -5V, ID = -2A 16 mΩ S Mar-25-2005 1 P-Channel Logic Level Enhancement NIKO-SEM PA102FMG Mode Field Effect Transistor (Preliminary) SOT-23 Lead-Free DYNAMIC Input Capacitance Ciss Output Capacitance Coss Reverse Transfer Capacitance Crss 95 Total Gate Charge2 Qg 7.6 2 430 VGS = 0V, VDS = -6V, f = 1MHz Gate-Source Charge Qgs VDS = 0.5V (BR)DSS, VGS = -4.5V, 3.2 Gate-Drain Charge2 Qgd ID = -2A 2 Turn-On Delay Time2 td(on) 2 tr td(off) Rise Time 2 Turn-Off Delay Time Fall Time2 pF 235 10 nC 11 22 VDD = -10V 32 55 ID ≅ -1A, VGS = -4.5V, RG = 6Ω 38 68 32 55 tf nS SOURCE-DRAIN DIODE RATINGS AND CHARACTERISTICS (TC = 25 °C) Continuous Current IS -1.6 Pulsed Current 3 ISM -3 Forward Voltage1 VSD IF = -1A, VGS = 0V -1.2 A V Pulse test : Pulse Width ≤ 300 µsec, Duty Cycle ≤ 2％. Independent of operating temperature. 3 Pulse width limited by maximum junction temperature. 1 2 REMARK: THE PRODUCT MARKED WITH “21YWW”, DATE CODE or LOT # Orders for parts with Lead-Free plating can be placed using the PXXXXXXG parts name. Mar-25-2005 2 NIKO-SEM P-Channel Logic Level Enhancement Mode Field Effect Transistor (Preliminary) PA102FMG SOT-23 Lead-Free Mar-25-2005 3 P-Channel Logic Level Enhancement NIKO-SEM Mode Field Effect Transistor (Preliminary) PA102FMG SOT-23 Lead-Free Body Diode Forward Voltage Variation with Source Current and Temperature -Is - Reverse Drain Current(A) 10 V GS = 0V T A = 125°C 1 0.1 25°C 0.01 -55°C 0.001 0.0001 0 0.2 0.4 0.6 0.8 1.0 -V - Body Diode Forward Voltage(V) 1.2 Mar-25-2005 4 P-Channel Logic Level Enhancement NIKO-SEM PA102FMG Mode Field Effect Transistor (Preliminary) SOT-23 Lead-Free SOT-23 (M3) MECHANICAL DATA mm mm Dimension Dimension Min. Typ. Max. Min. Typ. Max. 0.15 0.25 A 0.85 1.15 H 0.1 B 2.4 3 I 0.37 C 1.4 1.6 1.8 J D 2.7 2.9 3.1 K E 1 1.1 1.3 L F 0 0.1 M G 0.35 0.5 N H 2 C 1 3 B A I D E G F Mar-25-2005 5