ETC CS5821

Century Semiconductor Inc.
CS5821
21:3 LVDS Receiver
GENERAL DESCRIPTION
FEATURES
CS5821 receives three LVDS data channels and
one LVDS clock channel.
Each data channel is
deserialized into 7-bit parallel data bus for output.
The clock channel is used for frame sync and fed into
an internal PLL that generates the 7X serial clock
used in the deserializer. A digital phase alignment
circuit can generate the sampling clock of the
deserializer front-end. The frame sync clock aligned
to the output 7-bit data is also output for timing
reference.
CS5821 supports open-safe design of LVDS when
the input is not connected to LVDS drivers and the
receiver outputs are forced low. Putting CS5821 into
inhibit mode by a shutdown control (SHTDNN) signal
can lower power consumption.
• Three 7-bit serial data LVDS channels and one
clock LVDS channel.
• Compatible with ANSI TIA/EIA-644 LVDS standard.
• Wide serial clocking speed ranges from 31MHz to
68MHz.
• Support open-safe LVDS design.
• Fully integrated on-chip PLL and digital phase
alignment provide accurate deserializer operation.
• Support power-down mode.
• 5V/3.3V tolerant data input.
• Single 3.3V supply operation.
• CMOS low power consumption.
• Functional compatible with DS90CF364 and
SN75LVDS86.
• Available in 48-pin TSSOP package.
BLOCK DIAGRAM
AIP
AIM
SERIAL-IN PARALLEL-OUT
7-Bit SHIFT REGISTER
DIN
D0-D6
CLK
BIP
BIM
DIN
SERIAL-IN PARALLEL-OUT
7-Bit SHIFT REGISTER
D7-D13
CLK
CIP
CIM
DIN
SERIAL-IN PARALLEL-OUT
7-Bit SHIFT REGISTER
D14-D20
CLK
7xCLK
CKIP
PHASE LOCK LOOP
AND
PHASE ALIGNER
CLKOUT
CKIM
SHTDNN
CONTROL LOGIC
CS5821
Century Semiconductor, Inc.
Taiwan:
No. 2, Industry East Rd. 3rd,
Science-Based Industrial Park, Hsin-Chu, Taiwan
Tel: 886-3-5784866 Fax: 886-3-5784349
USA:
1485 Saratoga Ave. #200
San Jose, CA, 95129
Tel: 408-973-8388 Fax: 408-973-9388
Sales@century-semi.com
Sales@century-semi.com.tw
www.century-semi.com
Rev.0.5 May 2001
page 1 of 14
Century Semiconductor Inc.
CS5821
PIN CONNECTION DIAGRAM
D17
1
48
VDD
D18
2
47
D16
VSS
3
46
D15
D19
4
45
D14
D20
5
44
VSS
RESETN
6
43
D13
VSS
7
42
VDD
AIM
8
41
D12
AIP
9
40
D11
BIM
10
39
D10
BIP
11
38
VSS
VDD
12
37
D9
VSS
13
36
VDD
CIM
14
35
D8
CIP
15
34
D7
CKIM
16
33
D6
CKIP
17
32
VSS
VSS
18
31
D5
VSS
19
30
D4
VDD
20
29
D3
VSS
21
28
VDD
SHTDNN
22
27
D2
CLKOUT
23
26
D1
D0
24
25
VSS
CS5821
Figure-1 48-pin TSSOP
page 2 of 14
Century Semiconductor Inc.
CS5821
PIN DESCRIPTION
Name
Pin
Description
AIP,
AIM
I
LVDS data channel A input. These are differential LVDS inputs for A channel
corresponds to D[0-6]. AIP is the positive data input and AIM is the negative input.
BIP,
BIM
I
LVDS data channel B output. These are differential LVDS inputs for B channel
corresponds to D[7-13].
CIP,
CIM
I
LVDS data channel C output. These are differential LVDS outputs for C channel
corresponds to D[14-21].
I
LVDS clock channel input. These are differential LVDS input for the frame sync clock.
The clock is sent to an on-chip PLL to generate 7X serial clock; An phase aligner is used
to align the deserializer clock.
O
Parallel data output for LVDS channel A. D[0] is LSB and D[6] is MSB. MSB is shifted in
first.
D[7-13]
O
Parallel data output for LVDS channel B. D[7] is LSB and D[13] is MSB.
D[14-20]
O
Parallel data output for LVDS channel C. D[14] is LSB and D[20] is MSB.
O
Parallel data clock output. This clock signal recovered clock for data output reference.
The falling edge should be used as the strobe for the next stage.
I
Shutdown control (low active). When SHTDNN is low, the internal PLL is put into inhibit
mode and all data outputs are forced low. This also resets all internal registers. For
normal operation, SHTDNN should be set to high.
VDD
P
Positive supply. A 3.3V supply should be used.
VSS
P
Negative supply. Connect to 0V.
CKIP,
CKIM
D[0-6]
CLKOUT
SHTDNN
page 3 of 14
Century Semiconductor Inc.
CS5821
FUNCTIONAL DESCRIPTION
Serial-In Parallel-Out 7-Bit Shift Register
It receives the serial data from the transmitter. It uses the 7xclk to strobe the serial data and sends 7-bit parallel
data with input clock’s frequency.
Phase Lock Loop and Phase Aligner
The PLL generates the seven times input clock which is used for deserialized. The phase aligner is used for
synchronous the input clock and output.
Control logic
There are two modes in this circuit. One is normal mode, and another is power down mode. Two modes are
controlled by the control signal “SHTDNN”. If SHTDNN is high, the circuit is in the normal mode, else if low, the
circuit is in the power down mode. In the power down mode, every block is off to make sure the least power
consumption.
page 4 of 14
Century Semiconductor Inc.
CS5821
Recommended Operating Conditions
Min
Typ
Max
Unit
Supply voltage
3
3.3
3.6
V
VIH(SHTDN)
High-level input voltage
2
-
-
V
VIL(SHTDN)
Low-level input voltage
-
-
0.8
V
Receiver input range
0
-
2.4
V
Operating free-air temperature
0
-
70
°C
Min
Typ
Max
Unit
Cycle time, input clock*
14.7
tc
32.4
ns
tsu1
Setup time, input
600
-
-
ps
th1
Hold time, input
600
-
-
ps
Symbol
VCC
TA
Parameter
Timing Requirements
Symbol
tc
Parameter
Note: Parameter tc is defined as the mean duration of a minimum of 32000 clock cycles.
Electrical Characteristics over recommended operating conditions (unless otherwise noted)
Symbol
Parameter
VIT+
Min
Typ
Max
Unit
Differential input high threshold voltage
-
-
100
mV
VIT-
Differential input low threshold voltage
-100
-
-
mV
VOH
High-level output voltage
IOH = -4mA
2.4
-
-
V
VOL
Low-level output voltage
IOL = 4mA
-
-
0.4
V
Disabled (power down
mode), All inputs open
-
280
-
µA
Enabled, AnP = 1V,
AnM = 1.4V, tc = 15.38ns
-
58
72
mA
Enabled, CL = 8 pF,
Grayscale pattern,
tc = 15.38ns
-
69
-
mA
Enabled, CL = 8 pF,
Grayscale pattern,
tc = 15.38ns
-
94
-
mA
ICC
Quiescent current (average)
Condition
IIH
High-level input current (SHTDN)
VIH = VCC
-
-
±20
µA
IIL
Low-level input current (SHTDN)
VIL = 0
-
-
±20
µA
II
Input current (LVDS input terminals A
and CLKIN)
0 ≤ V1 ≤ 2.4V
-
-
±10
µA
High-impedance output current
VO = 0 or VCC
-
-
±10
µA
IOZ
page 5 of 14
Century Semiconductor Inc.
CS5821
Switching Characteristics over recommended operating conditions (unless otherwise noted)
Symbol
Parameter
tsu2
Setup time, D0 - D20 valid to CLKOUT↓
th2
Hold time, CLKOUT↓ to D0 - D20 valid
Condition
CL = 8pF (Figure-3)
Min
Typ
Max
Unit
5
-
-
ns
5
-
-
ns
Receive input skew margin
tc = 15.38 ns (±0.2%),
Input clock jitter < 50 ps
(Figure-4)
490
-
-
ps
td
Delay time, CLKIN↑ to CLKOUT ↓
tc = 15.38 ns (±0.2%),
CL = 8 pF
-
3.7
-
ns
∆ tc(o)
Cycle time, change in output clock
period#
-
± 100
-
ps
ten
Enable time, SHTDN↑ to Dn valid
Figure-6
-
1
-
ms
tdis
Disable time, SHTDN↓ to off state
Figure-7
-
400
-
ns
tt
Transition time, output (10% to 90% tr or
tf)
CL = 8pF
-
3
-
ns
tw
Pulse duration, output clock
-
-
0.43tc
-
ns
tRSKM
Switching Characteristics
Symbol
Parameter
Min
Typ
Max
Unit
LHT
low to high transition time
-
2.2
5
ns
HLT
high to low transitions time
-
2.2
5
ns
Pos0
input strobe position for bit 0 (f = 65MHz)
0.7
1.1
1.4
ns
Pos1
input strobe position for bit 1 (f = 65MHz)
2.9
3.3
3.6
ns
Pos2
input strobe position for bit 2 (f = 65MHz)
5.1
5.5
5.8
ns
Pos3
input strobe position for bit 3 (f = 65MHz)
7.3
7.7
8.0
ns
Pos4
input strobe position for bit 4 (f = 65MHz)
9.5
9.9
10.2
ns
Pos5
input strobe position for bit 5 (f = 65MHz)
11.7
12.1
12.4
ns
Pos6
input strobe position for bit 6 (f = 65MHz)
13.9
14.3
14.6
ns
SKM
Rxin skew margin (f = 65MHz)
400
-
-
ps
COP
RxCLK OUT Period
14.7
-
32.2
ns
COH
RxCLK OUT high time (f = 65MHz)
7.5
-
-
ns
COL
RxCKK OUT low time (f = 65MHz)
3.5
-
-
ns
SRC
RxOUT setup to RxCLKOUT (f = 65MHz)
2.5
-
-
ns
HRC
RxOUT hold to RxCLKOUT (f = 65MHz)
2.5
-
-
ns
CCD
RxCLK In to RxCLK OUT delay
5
-
9
ns
PLLs
Phase Lock Loop set
-
-
10
ms
PDD
Power down delay
-
-
1
µs
page 6 of 14
Century Semiconductor Inc.
CS5821
Electrical Characteristics
Symbol
Parameter
Condition
Min
Typ
Max
Unit
IRCCG
Receiver Supply Current
CL = 8pF, f = 65MHz
(Worst Case pattern)
-
-
-
mA
IRCCW
Receiver Supply Current
CL = 8pF, f = 65MHz
(Grayscale pattern)
-
-
-
mA
IRCCS
Receiver Power Down
Supply Current
-
200
300
µA
Power Down = Low
page 7 of 14
Century Semiconductor Inc.
CS5821
TIMING DIAGRAMS
CMOS/TTL
OUTPUT
CS
8pF
Figure-2 CMOS/TTL Output Load
80%
80%
20%
20%
LHT
HLT
Figure-3 CMOS/TTL Output Transition Times
COP
CLKOUT
2.0v
2.0v
0.8v
COH
COL
SRC
D[20:0]
2.0v
Setup
HRC
2.0v
Hold
Figure-4 Setup/Hold and High/Low Times
page 8 of 14
Century Semiconductor Inc.
CS5821
TEST PATTERN
CLKIN
D0, 6, 12
D1, 7, 13
D2, 8, 14
D3, 9, 15
D18, 19, 20
D4, 5, 10,
11, 16, 17
Figure-5 16-Grayscale Testing Pattern Waveforms
tsu2
CLKIN/CLKOUT
Even Dn
Odd Dn
Figure-6 The Worst-case Testing Pattern Waveforms
tsu2
70% VOH
D0 - D20
30% VOH
th2
70% VOH
CLKOUT
30% VOH
Figure-7 Setup and Hold Time Waveforms
page 9 of 14
Century Semiconductor Inc.
CS5821
PARAMETER MEASUREMENT INFORMATION
4/7 tc ± t(RSKM)
(see Note A)
tsu1
tc
th1
3/7 tc ± t(RSKM)
(see Note A)
An
and An
CLKIN
7 x CLK
(Internal)
td
tW
CLKOUT
tr < 1ns
80%
CLKIN
or An
≈ 300mV
0V
20%
≈ -300mV
tW
td
VOH
1.4V
VOL
CLKOUT
NOTE A: CLKIN is advanced or delayed with respect to data until errors are observed at the receiver outputs. The
advance or delay is then reduced until there are no data errors observed. The magnitude of the advance or
delay is t(RSKM).
Figure-8 Receiver Input Skew Margin, Setup/Hold Time, and Delay Time Definitions
page 10 of 14
Century Semiconductor Inc.
CKIP/CKIM
CS5821
Vdiff=0v
CCD
CLKOUT
Figure-9 Clock-in to Clock-out Delay
2V
Power Down
3V
Vcc
PLLs
CKIP/CKIM
RxCLK OUT
2V
Figure-10 Phase Lock Loop Stable Time
Power Down
(Low Active)
1.5V
RxCLK In
PDD
RxOUT
Low
Figure-11 Power Down Delay
page 11 of 14
Century Semiconductor Inc.
CS5821
CKIP/CKIM
AI
BI
CI
Pos0
Min.
Pos0
Max.
Pos1
Min
Pos1
Max.
Pos2
Min.
Pos2
Max.
Pos3
Min.
Pos3
Max.
Pos4
Min.
Pos4
Max.
Pos5
Min.
Pos5
Max.
Pos6
Min.
Pos6
Max.
Figure-12 Strobe positions of LVDS inputs
Ideal Strobe Position
*IP or *IM
~1.4V
C
*IM or *IP
~1.0V
RSKM
min.
max.
Tpposn
RSKM
min.
max.
Rsposn
min.
max.
Tpposn+1
Figure-13 Skew Margin of LVDS data inputs
page 12 of 14
Century Semiconductor Inc.
CS5821
PACKAGE OUTLINE (48-pin TSSOP)
D
c
E1
E
L
θ
A2
A
A1
b
b
e
Symbol
Dimensions in Millimeters
Dimensions in Inches
MIN
NOM
MAX
MIN
NOM
MAX
A
1.05
-
1.20
0.04
-
0.047
A1
0.05
-
0.15
0.002
-
0.006
A2
-
0.90
-
-
0.035
-
b
0.17
0.20
0.27
0.007
0.008
0.010
c
0.09
0.15
0.20
0.004
0.006
0.008
D
12.40
12.50
12.60
0.488
0.492
0.496
E
7.80
8.10
8.40
0.307
0.319
0.330
E1
6.00
6.10
6.20
0.236
0.240
0.244
e
-
0.50
-
-
0.0197
-
L
0.50
-
0.75
0.020
-
0.030
θ
0°
-
7°
0°
-
7°
page 13 of 14
Century Semiconductor Inc.
CS5821
APPLICATION CIRCUIT SCHEMATIC
JC1
LVDS Connector
1
2
3
4
5
9CLK+ 6
7
8
9
10
11
12
13
9A1+
9A2-
1
2
3
4
5
6
7
8
9
10
11
12
13
26
25
24
23
22
21
20
19
18
17
16
15
14
26
25
24
23
22
21
20
19
18
17
16
15
14
9A0+
9A1-
R1
10K
SW1
9A2+
9CLK-
R2
R3
R4
R5
50
50
50
50
C10
0.1u
C12
0.1u
JS1
C3
0.1u
R6
R7
+3.3V R8
R9
50
50
50
50
R10 10k
1
2
3
VIN VOUT
GND
+3.3V
2
+ C2
100u
C4
0.1u
LT1086-3.3/DD
1
2
3
VS1
4
ENA1
5
6
7
9A08
9A0+
9
10
9A19A1+ 11
12
13
9A214
9A2+ 15
9CLK- 16
9CLK+ 17
18
19
20
21
22
DCLK 23
R0
24
+3.3V
U1
Vcc
OUT16
OUT15
OUT14
GND
OUT13
Vcc
OUT12
OUT11
OUT10
GND
OUT9
Vcc
OUT8
OUT7
OUT6
GND
OUT5
OUT4
OUT3
Vcc
OUT2
OUT1
GND
OUT17
OUT18
GND
OUT19
OUT20
N/C
LVDS GND
IN0IN0+
IN1IN1+
LVDS Vcc
LVDS GND
IN2IN2+
CLK INCLK IN+
LVDS GND
PLL GND
PLL Vcc
PLL GND
PWR DWN
CLK OUT
OUT0
+3.3V
PWR_DN
L1
100uH
+ C14
10u
+ C1
220u
3
1
Reset
B5
HS1
C9
0.1u
D1
0.2V
2
C5
0.1u
C7
0.1u
+3.3V
JP1
DC+5V
1
9A0-
U2
+3.3V
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
B4
B3
B2
+3.3V
C6
0.1u
B1
B0
G5
G4
C8
0.1u
G3
G2
G1
G0
C11
0.1u
R5
R4
R3
R2
R1
CS5821
C13
0.1u
B5
B4
B3
VS1
B2
ENA1
B1
B0
G5
G4
G3
G2
G1
G0
R5
R4
R3
R2
R1
R0
JC2
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
HS1
DCLK
HEADER 20X2
To LCD Panel
L2
100uH
C16
0.1u
C17
0.01u
C18
0.01u
C19
0.1u
+ C15
10u
Figure-14 Using 48-pin TSSOP package
page 14 of 14