256Mb SDRAM Ordering Information EM 48 8M 32 4 4 V B A – 8 F EOREX Logo EDO/FPM D-RAMBUS DDRSDRAM DDRSGRAM SGRAM SDRAM : : : : : : F: PB free package Power Blank : Standard L : Low power I : Industrial 40 41 42 43 46 48 Density 16M : 16 Mega Bits 8M : 8 Mega Bits 4M : 4 Mega Bits 2M : 2 Mega Bits 1M : 1 Mega Bit Min Cycle Time ( Max Freq.) -5 : 5ns ( 200MHz ) -6 : 5ns ( 167MHz ) -7 : 7ns ( 143MHz ) -75 : 7.5ns ( 133MHz ) -8 : 8ns ( 125MHz ) -10 : 10ns ( 100MHz ) Organization 8 : x8 9 : x9 16 : x16 18 : x18 32 : x32 Refresh 1 : 1K, 8 : 8K 2 : 2K, 6 :16K 4 : 4K Bank 2 : 2Bank 6 : 16Bank 4 : 4Bank 3 : 32Bank 8 : 8Bank Revision A : 1st B : 2nd C : 3rd D :4th G: for VGA version only Interface V: 3.3V R: 2.5V URL: http://www.eorex.com Email: [email protected] Package C: CSP B: FBGA T: TSOP Q: TQFP P: PQFP ( QFP ) L: LQFP Rev.01 1/33 256Mb SDRAM 256Mb( 4Banks ) Synchronous DRAM EM488M3244VBA (8Mx32) Description The EM488M3244VBA is Synchronous Dynamic Random Access Memory ( SDRAM ) organized as 2Meg words x 4 banks x 32 bits. All inputs and outputs are synchronized with the positive edge of the clock . The 256Mb SDRAM uses synchronized pipelined architecture to achieve high speed data transfer rates and is designed to operate in 3.3V low power memory system. It also provides auto refresh with power saving / down mode. All inputs and outputs voltage levels are compatible with LVTTL. Features • Fully synchronous to positive clock edge • Clock frequency :125MHz(max) • Single 3.3V +/- 0.3V power supply • LVTTL compatible with multiplexed address • Programmable Burst Length ( B/ L ) - 1,2,4,8 or full page • Programmable CAS Latency ( C/ L ) - 2 or 3 • Data Mask ( DQM ) for Read/Write masking • Programmable wrap sequential - Sequential ( B/ L = 1/2/4/8/full page ) - Interleave ( B/ L = 1/2/4/8 ) • Burst read with single-bit write operation • All inputs are sampled at the positive rising edge of the system clock. • Auto refresh and self refresh • 4,096 refresh cycles / 64ms (15.6us/row) • FBGA package is lead free solder (Sn-Ag-Cu) * EOREX reserves the right to change products or specification without notice. Rev.01 2/33 256Mb SDRAM Pin Assignment ( Top View ) 90-ball FBGA 1 A B C D 2 3 G K L M N P R 8 O VDD DQ23 VSS O O O O DQ28 VDDQ VSSQ VDDQ 9 O DQ21 O O VSSQ DQ19 O O O O O O VSSQ DQ27 DQ25 DQ22 DQ20 VDDQ O O O DQ30 O O O O O DQ17 DQ18 O O NC NC DQ16 O O O O O VSS DQM3 A2 DQM2 A3 O O O O VDDQ O VSSQ O VDD O O O A6 A10 A0 A1 O O O A5 O O O NC NC BA1 A11 O O O O CLK BA0 A7 J 7 O A4 H 6 DQ26 DQ24 VDDQ DQ31 F 5 O O O VSSQ DQ29 E 4 A8 CKE A9 O O /CS /RAS O O O O O O DQM1 NC /CAS /WE DQM0 NC O O O O O O VDDQ DQ8 VDD DQ7 VSSQ VSS O O O O O O VSSQ DQ10 DQ9 DQ6 DQ5 VDDQ O O O O O O VSSQ DQ12 DQ14 DQ1 DQ3 VDDQ O O O O O O DQ11 VDDQ VSSQ VDDQ VSSQ DQ4 O O O O DQ13 DQ15 VDD VSS O O DQ0 DQ2 (Top view) Rev.01 3/33 256Mb SDRAM Pin Descriptions ( Simplified ) Pin Name Pin Function CLK /CS System Clock Chip select Master Clock Input(Active on the Positive rising edge) Selects chip when active CKE Clock Enable Activates the CLK when “H” and deactivates when “L”. CKE should be enabled at least one cycle prior to new command. Disable input buffers for power down in standby. Row address (A0 to A11) is determined by A0 to A11 level at the bank active command cycle CLK rising edge. CA(CA0 to CA8) is determined by A0 to A8 level at the read or write command cycle CLK rising edge. And this column address becomes burst access start address. A10 defines the pre-charge mode. When A10 = High at the pre-charge command cycle, all banks are pre-charged. But when A10 = Low at the pre-charge command cycle, only the bank that is selected by BA is pre-charged. A0 ~ A11 Address BA0~BA1 Bank Address /RAS Row address strobe /CAS Column address strobe Latches Column Addresses on the positive rising edge of the CLK with /CAS low. Enables column access. /WE Write Enable Latches Column Addresses on the positive rising edge of the CLK with /CAS low. Enables column access. DQM0 ~ DQM3 Data input/output Mask DQ0 ~ 31 Data input/output VDD/VSS Power supply/Ground VDD and VSS are power supply pins for internal circuits. VDDQ/VSSQ Power supply/Ground VDDQ and VSSQ are power supply pins for the output buffers. NC No connection Selects which bank is to be active. Latches Row Addresses on the positive rising edge of the CLK with /RAS “L”. Enables row access & pre-charge. DQM controls I/O buffers. DQ pins have the same function as I/O pins on a conventional DRAM. This pin is recommended to be left No Connection on the device. Rev.01 4/33 256Mb SDRAM Block Diagram Auto/Self Refresh Counter A0 A1 A2 DQM A6 A7 A8 Address Register A5 Row Add. Buffer A4 Row Decoder A3 Memory Array Write DQM Control Data In A9 S/A & I/O gating A10 DQi Col. Decoder Data Out A11 Col. Add. Buffer BA0 Read DQM Control BA1 Col. Add. Counter Mode Register Set DQM Burst Counter Timing Register CLK /CLK CKE /CS /RAS /CAS Rev.01 /WE DQM 5/33 256Mb SDRAM Commands Mode register set command ( /CS, /RAS, / CAS, /WE = Low ) CLK The EM488M3244VBA have a mode register that defines how the device operates. In this command, A0 through BA are the data input pins. After power on, the mode register set command must be executed to initialize the device. The mode register can be set only when all banks are in idle state. The EM488M3244VBA, cannot accept any other commands,only during 2CLK can following this command. /CS /RAS /CAS /WE BA A10 CKE ( Figure. 1 Mode register set command ) ‘H’ Add Active command ( /CS, /RAS = Low , /CAS, /WE = High ) CLK The EM488M3244VBA have 4 banks, each with 4,096 rows. This command activates the bank selected by BA and a row address selected by A0 through A11.This command corresponds to a conventional DRAM’s /RAS falling. /CS /RAS /CAS /WE BA Row A10 CKE Add ‘H’ Row ( Figure. 2 Row address strobe and bank activate command ) Rev.01 6/33 256Mb SDRAM Precharge command ( /CS, /RAS, /WE = Low , / CAS = High ) CLK This command begins precharge operation of the bank selected by. When A10 is high,all banks are precharged, regardless of. When A10 is low,only the bank selected by BA is precharged. /CS /RAS /CAS /WE BA A10 CKE ‘H’ Add ( Figure. 3 Precharged command ) Write command ( /CS, /CAS, /WE = Low, /RAS = High ) CLK If the mode register is in the burst write mode, this command sets the burst start address given by the column address to begin the burst write operation. The first write data in burst mode can input with this command with subsequent data on following clicks. /CS /RAS /CAS /WE BA A10 CKE Add ‘H’ Column ( Figure. 4 Column address and write command ) Rev.01 7/33 256Mb SDRAM Read command ( /CS, /CAS = Low , / RAS, /WE = High ) CLK Read data is available after /CAS latency requirements have been met. This command sets the burst start address given by the column. /CS /RAS /CAS /WE BA A10 CKE ‘H’ Add ( Figure. 5 Column address and read command ) Column Auto refresh command ( /CS, /RAS, /CAS = Low, /WE, CKE = High ) CLK This command is a request to begin the CBR refresh operation. The refresh address is generated internally. Before Executing CBR refresh, all banks must be precharged. After this cycle, all banks will be in the idle (Precharged ) state and ready for a row activate command. During tRC period ( from refresh command to refresh or activate command ), the EM488M3244VBA cannot accept any other command. /CS /RAS /CAS /WE BA A10 CKE ‘H’ ( Figure. 6 Auto refresh command ) Add Rev.01 8/33 256Mb SDRAM Self refresh entry command ( /CS, / RAS , /CAS, CKE = Low , /WE = High ) CLK After the command execution, self refresh operation continues while CKE remains low. When CKE goes high, the memory exits the self refresh mode. During self refresh mode, refresh interval and refresh operation are performed internally, so there before is no need for external control. Before executing self refresh, both banks must be precharged. /CS /RAS /CAS /WE BA A10 CKE ( Figure. 7 Self refresh entry command ) Add Burst stop command ( /CS, /WE = Low, /RAS, /CAS = High ) CLK This command can stop the current burst operation. /CS /RAS /CAS /WE BA A10 CKE ‘H’ ( Figure. 8 Burst stop command in full page mode ) Add Rev.01 9/33 256Mb SDRAM No operation ( /CS = Low, / RAS , /CAS, /WE = High ) CLK This command is not execution command so there is no operations begin or terminate by this command. /CS /RAS /CAS /WE BA A10 CKE ‘H‘ Add ( Figure. 9 No operation ) Initialization The synchronous DRAM is initialized in the power-on sequence according to the following: 1. CLK,CKE,/CS,DQM,DQ pin keep low till power stabilizes, and the CLK pin is stabilized whin 100us after power stabilizes before the following initialization sequence. 2. To stabilize internal circuits, when power is applied, a 200us or longer pause must precede any signal toggling. 3. After the pause, all banks must be precharged using the precharged command ( The precharge all banks command is convenient ). 4. Once the precharge is completed and the minimum tRP is satisfied, the mode register can be programmed. 5. Two or more Arto refresh must be performed. Remanks: 1. The sequence of Mode register programming and Refresh above may be transposed. 2. CKE and DQM must be held high until the precharge command is issued to ensure data-bus Hi-Z. Rev.01 10/33 256Mb SDRAM Programming the Mode Register The mode register is programmed by the Mode register set command using address bits BA through A0 as data inputs. The register retains data until it is reprogrammed or the device loses power. Options /CAS Latency Wrap type Burst Length BA through A7 A6 through A4 A3 A2 through A0 Following mode register programming, no command can be issued before at least 2 CLK elapsed. /CAS Latency /CAS Latency is the most critical of the parameters begin set. It tells the device how many clocks must elapse before the data will be available. Burst Length Burst length is the number of the words that will be output or input in a write cycle. After a read burst is completed, the output bus will become Hi-Z. The burst length is programmable as 1,2,4,8 or full page. Wrap Type ( Burst Sequence ) The wrap type specifies the order in which the burst data will be addressed. This order is programmable as either Sequence or Interleave. The method chosen will depend on the type of CPU in the system. Some microprocessor cache systems are optimized for sequential addressing and others for interleaved. Rev.01 11/33 256Mb SDRAM Simplified State Diagram Self Refresh LF SE LF SE Mode Register Set MRS it Ex CBR Refresh REF IDLE CK E CK E ACT Power Down w it Wr ite READ Write CKE WRITEA CKE POWER ON Precharge Active Power Down CKE READ Suspend CKE READA PR E CKE Read h Read BS Re T ad CKE w it WRITE E PR WRITEA Suspend CKE ad Re h Write WRITE Suspend CKE Row Active CKE CKE READA Suspend Precharge Manual Input Automatic Sequence Rev.01 12/33 256Mb SDRAM Address Input for Mode Register Set BA0/1 A10/11 A9 A8 A7 A6 Operation Mode A5 A4 A3 CAS Latency BT Sequential 1 2 4 8 Reserved Reserved Reserved Full Page BA0/1 A10/11 0 0 0 0 A9 0 1 A8 0 0 A7 0 0 A6 0 0 0 0 1 1 1 1 A5 0 0 1 1 0 0 1 1 A1 A0 Burst Length Burst Length Interleave A2 1 0 2 0 4 0 8 0 Reserved 1 Reserved 1 Reserved 1 Reserved 1 Burst Type Sequential Interleave CAS Latency Reserved Reserved 2 3 Reserved Reserved Reserved Reserved A2 A1 0 0 1 1 0 0 1 1 A0 0 1 0 1 0 1 0 1 A3 0 1 A4 0 1 0 1 0 1 0 1 Operation Mode Normal Burst read with Single-bit Write Rev.01 13/33 256Mb SDRAM Burst Type ( A3 ) Burst Length 2 4 8 Full Page * A2 A1 A0 XX0 XX1 X0 0 X0 1 X1 0 X1 1 000 001 010 011 100 101 110 111 nnn Sequential Addressing 01 10 0123 1230 2301 3012 01234567 12345670 23456701 34567012 45670123 56701234 67012345 70123456 Cn Cn+1 Cn+2 …... Interleave Addressing 01 10 0123 1032 2301 3210 01234567 10325476 23016745 32107654 45670123 54761032 67452301 76543210 - * Page length is a function of I/O organization and column addressing x32 (CA0 ~ CA8) : Full page = 512 bits Rev.01 14/33 256Mb SDRAM Precharge The precharge command can be issued anytime after tRAS ( min.) is satisfied. Soon After the precharge command is issued, precharge operation performed and the synchronous DRAM enters the idle state after tRP is satisfied. The parameter tRP is the time required to perform the precharge. The earliest timing in a read cycle that a precharege command can be issued without losing any data in the burst is as follows. It is depends on the /CAS latency and clock cycle time. 0 1 2 3 4 5 6 7 8 CLK Command ( CL= 2 ) Read DQ ( CL= 2 ) PRE Q1 Command ( CL= 3 ) Q2 Read Q3 Hi-Z Q4 PRE Q1 DQ ( CL= 3 ) Q2 Q3 Hi-Z Q4 BL=4 In order to write all data to the memory cell correctly, the asynchronous parameter tDPL must be satisfied. The tDPL (min.) specification defines the eariliest time that a precharge command can be issued. Minimum number of clocks is calculated by dividing tDPL(min.) with clock cycle time. In a word, the precharge command can be issued relative to reference clock that indicates the last data word is valid. The minus in the following table means clocks before the reference and the plus means time after the reference. /CAS latency Read Write 2 -1 + tDPL( min.) 3 -2 + tDPL ( min.) Rev.01 15/33 256Mb SDRAM Auto precharge During a read or write command cycle, A10 controls whether auto precharge is selected. A10 high in the Read or Write command ( Read with Auto precharge command or Write with Auto precharge command ), auto precharge is selected and begins automatically. The tRAS must be satisfied with a read with auto precharge or a write with auto precharge operation. In addition, the next activate command to the bank being precharged cannot be executed until the precharge cycle ends. In read cycle, once auto precharge has started , an activate command to the bank can be issued after tRP has been satisfied Read with Auto Precharge During a read cycle, the auto precharge begins same as ( /CAS latency of 2 ) or one clock earlier ( /CAS latency of 3 ) the last data word output. 0 1 2 3 4 5 6 7 8 CLK Command ( CL= 2 ) Read AP DQ ( CL= 2 ) Command ( CL= 3 ) DQ ( CL= 3 ) Auto precharge starts Q1 Read AP Q2 Q3 Hi-Z Q4 Auto precharge starts Q1 Q2 Q3 Q4 Hi-Z BL=4 ( tRAS must be satisfied ) Remanks: Read AP means Read with auto precharge Rev.01 16/33 256Mb SDRAM Write with Auto Precharge During write cycle, the auto precharge starts at the timing that is equal to the value of the tDPL( min.) after the last dataword input to the device. 0 1 2 3 4 5 6 7 8 CLK Command ( CL= 2 ) DQ ( CL= 2 ) Write AP D1 Auto precharge starts D2 D3 Hi-Z D4 tDPL( min. ) Command ( CL= 3 ) Write AP D1 DQ ( CL= 3 ) Auto precharge starts D2 D3 Hi-Z D4 tDPL( min. ) BL=4 ( tRAS must be satisf ied ) Remanks: Write AP means Write with auto precharge In summary, the auto precharge begins relative to a reference clock that indicates the last data word is valid. In the following table minus means clocks before the reference ,plus means after the reference. /CAS latency Read Write 2 -1 + tDPL( min.) 3 -2 + tDPL ( min.) Rev.01 17/33 256Mb SDRAM Read / Write command interval Read to read command interval During a read cycle, when new Read command is issued,it will be effective after / CAS latency, even if the previous read operation does not completed. Read will be interrupted by another Read. The interval between the commands is 1 cycle minimum. Each Read command can be issued in every clock without any restriction. 0 1 2 3 4 5 6 7 QA1 QB1 QB2 QB3 QB4 8 CLK Command Read A Read B DQ Hi-Z 1 Cycle B L = 4, C L = 2 Write to write command interval During a write cycle, when new write command is issued, the previous burst will terminate and the new burst will begin with a new write command. Write will be interrupted by another Write. The interval between the commands is minimum 1 cycle. Each write command can be issued in every clock without any restriction. 0 1 2 3 4 5 DB2 DB3 DB4 6 7 8 CLK Command DQ Write A Write B DA1 DB1 Hi-Z 1 Cycle B L = 4, C L = 2 Rev.01 18/33 256Mb SDRAM Write to read command interval Write and Read command interval is also 1 cycle. Only the write data before read command will be written. The data bus must be Hi-Z at least one cycle prior to the first D OUT. 0 1 2 3 4 5 6 7 QB1 QB2 QB3 QB4 QB1 QB2 QB3 8 CLK Command ( CL = 2 ) DQ ( CL = 2 ) Command ( CL = 3 ) DQ ( CL = 3 ) Write A DA1 Write A DA1 Read B Hi-Z Read B Hi-Z QB4 BL=4 Rev.01 19/33 256Mb SDRAM Read to write command interval During a read cycle, Read can be interrupt by Write. The read and write command interval is 1 cycle minimum. There’s a restriction to avoid data conflict. The data bus must be Hi-Z using DQM before write. 0 1 2 Read Write 3 4 5 6 7 8 9 CLK Command DQM Hi-Z DQ D1 D2 D3 D3 BL=4 Read can be interrupted by Write. DQM must be high at least 3 clicks prior to the write command. 0 1 2 3 4 5 6 7 8 9 CLK Command ( CL = 2 ) Read Write DQM DQ ( CL = 2 ) Q1 Q2 Q3 D1 D2 D3 D2 D3 Hi-Z is necessar y Command ( CL = 3 ) Read Write DQM DQ ( CL = 3 ) Q1 Q2 D1 Hi-Z is necessar y BL=8 Rev.01 20/33 256Mb SDRAM Burst terminate There are two ways to terminate a burst operation other than using a Read or a Write command. One is the burst stop command and the other is the precharge command. Burst stop command During a read cycle,when the burst stop command is issued, the burst read are terminated and the data bus goes to Hi-Z after the /CAS latency from the burst stop command. 0 1 2 3 4 5 6 7 8 9 CLK Command Burst Stop Read DQ ( CL = 2 ) Q1 DQ ( CL = 3 ) Q2 Q3 Q1 Q2 Hi-Z Hi-Z Q3 B L = don’t care During a write cycle,when the burst stop command is issued, the burst write data are terminated and the data bus goes to Hi-Z at the same clock with the burst stop command. 0 1 2 3 4 5 6 7 8 9 CLK Command Write DQ ( CL = 2 /3 ) D1 Burst Stop D2 D3 D4 Hi-Z B L = don’t care Rev.01 21/33 256Mb SDRAM Precharge Termination Precharge Termination in READ Cycle During a read cycle, the burst read operation is terminated by a precharge command. When the precharge command is issued, the burst read operation is terminated and precharge starts. The same banks can be activated again after tRP from the precharge command. To issue a precharge command , tRAS must be satisfied. When /CAS Latency is 2, the read data will remain valid until two clocks after the precharge command. 0 1 2 3 4 5 6 7 8 9 CLK Precharge Read Command Q1 DQ Q2 Q3 Activ e Hi-Z Q4 t RP B L = don’t care , CL= 2 When /CAS Latency is 3, the read data will remain valid until two clocks after the precharge command. 0 1 2 3 4 5 6 7 8 9 CLK Command DQ Precharge Read Q1 Q2 Activ e Q4 Q3 Hi-Z t RP B L = don’t care , CL= 3 Rev.01 22/33 256Mb SDRAM Precharge Termination in Write Cycle During a write cycle, the burst write operation is terminated by a precharge command. When the precharge command is issued, the burst write operation is terminated and precharge starts. The same banks can be activated again after tRP from the precharge command. To issue a precharge command , tRAS must be satisfied. When /CAS Latency is 2, the write data written prior to the precharge command will be correctly stored. However, invalid data may be written at the same clock as the precharge command. In order to avoid this situation, DQM must be high at the same clock as the precharge command. This will mask the invalid data. 0 1 2 3 4 5 6 7 8 9 CLK Precharge Write Command Activ e DQM D1 DQ D4 D3 D2 Hi-Z D5 t RP B L = don’t care, CL= 2 ( tRAS must be satisfied ) When /CAS Latency is 3, the write data written prior to the precharge command will be correctly stored. However, invalid data may be written at the same clock as the precharge command. In order to avoid this situation, DQM must be high at the same clock as the precharge command. This will mask the invalid data. 0 1 2 3 4 5 6 7 8 9 CLK Command Precharge Write Activ e DQM DQ D1 D2 D3 D4 Hi-Z D5 t RP B L =don’t care , CL= 3 ( tRAS must be satisf ied ) Rev.01 23/33 256Mb SDRAM Truth Table 1. Command Truth Table ( EM488M3244VBA ) Command Symbol Ignore Command No operation Burst stop Read Read with auto pre-charge Write Write with auto pre-charge Bank activate Pre-charge select bank Pre-charge all banks Mode register set CKE /CS /RAS /CAS /WE BA A10 A9~A0 n-1 n DESL H X H X X X X X X NOP H X L H H H X X X BSTH H X L H H L X X X READ H X L H L H V L V READA H X L H L H V H V L V WRIT H X L H L L V WRITA H X L L H H V H V ACT H X L L H H V V V PRE H X L L H L V L X PALL H X L L H L X H X MRS H X L L L L L L V Note : H = High level, L = Low level, X = High or Low level (Don't care), V = Valid data input 2. DQM Truth Table Command Symbol CKE n-1 n /CS Data w rite / output enable ENB H X H Data mask / output disable MASK H X L Upper byte w rite enable / output enable BSTH H X L Read READ H X L Read w ith auto pre-charge READA H X L Write WRIT H X L Write w ith auto pre-charge WRITA H X L Bank activate ACT H X L Pre-charge select bank PRE H X L Pre-charge all banks PALL H X L Mode register set MRS H X L Note : H = High level, L = Low level, X = High or Low level (Don't care), V = Valid data input 3. CKE Truth Table Command Activating Any Clock suspend Idle Idle Command Symbol CKE /CS /RAS /CAS /WE Addr. n-1 n Clock suspend mode entry H L X X X X X Clock suspend mode L L X X X X X Clock suspend mode exit L H X X X X X CBR refresh command REF H H L L L H X Self refresh entry SELF H L L L L H X L H L H H H X L H H X X X X Self refresh Self refresh exit Idle Power down Pow er dow n entry H L X X X X X Pow er dow n exit L H X X X X X Re m ark H = High level, L = Low level, X = High or Low level (Don't care) Rev.01 24/33 256Mb SDRAM 4. Operative Command Table Current state Idle Row active Read Write /CS /R /C /W Addr. Command Action Notes H X X X X DESL Nop or pow er dow n 2 L H H X X NOP or BST Nop or pow er dow n 2 L H L H BA/CA/A10 READ/READA ILLEGAL 3 L H L L BA/CA/A10 WRIT/WRITA ILLEGAL 3 L L H H BA/RA ACT L L H L BA, A10 PRE/PALL Nop L L L H X REF/SELF Ref resh or self refresh Row activating 4 L L L L Op-Code MRS Mode register accessing H X X X X DESL Nop L H H X X NOP or BST Nop L H L H BA/CA/A10 READ/READA Begin read : Determine AP 5 L H L L BA/CA/A10 WRIT/WRITA Begin w rite : Determine AP 5 L L H H BA/RA ACT ILLEGAL 3 L L H L BA, A10 PRE/PALL Precharge 6 L L L H X REF/SELF ILLEGAL 4 L L L L Op-Code MRS ILLEGAL H X X X X DESL Continue burst to end Row active L H H H X NOP Continue burst to end Row active L H H L X BST Burst stop Row active L H L H BA/CA/A10 READ/READA Terminate burst, new read : Determine AP 7 L L L L BA/CA/A10 WRIT/WRITA Terminate burst, start w rite : Determine AP 7, 8 L L H H BA/RA ACT ILLEGAL 3 L L H L BA/A10 PRE/PALL Terminate burst, pre-charging 4 L L L H X REF/SELF ILLEGAL L L L L Op-Code MRS ILLEGAL H X X X X DESL Continue burst to end Write recovering L H H H X NOP Continue burst to end Write recovering L H H L X BST Burst stop Row active L H L H BA/CA/A10 READ/READA Terminate burst, start read : Determine AP 7, 8 L L L L BA/CA/A10 WRIT/WRITA Terminate burst, new w rite : Determine AP 7 7 L L H H BA/RA ACT ILLEGAL 3 L L H L BA/A10 PRE/PALL Terminate burst, pre-charging 9 L L L H X REF/SELF ILLEGAL L L L L Op-Code MRS ILLEGAL 7,8 Re m ark H = High level, L = Low level, X = High or Low level (Don't care) Rev.01 25/33 256Mb SDRAM Current state Read w ith AP Write w ith AP Pre charging Row activating /CS /R /C /W Addr. Command Action Notes H X X X X DESL Continue burst to end Precharging L H H H X NOP Continue burst to end Precharging L H H L X BST ILLEGAL L H L H BA/CA/A10 READ/READA ILLEGAL 3 L H L L BA/CA/A10 WRIT/WRITA ILLEGAL 3 L L H H BA/RA ACT ILLEGAL 3 L L H L BA, A10 PRE/PALL ILLEGAL 3 L L L H X REF/SELF ILLEGAL L L L L Op-Code MRS ILLEGAL H X X X X DESL burst to end Write recovering w ith auto precharge L H H H X NOP Continue burst to end Write recovering w ith auto precharge L H H L X BST ILLEGAL L H L H BA/CA/A10 READ/READA ILLEGAL 3 L H L L BA/CA/A10 WRIT/WRITA ILLEGAL 3 L L H H BA/RA ACT ILLEGAL 3 L L H L BA, A10 PRE/PALL ILLEGAL 3 L L L H X REF/SELF ILLEGAL L L L L Op-Code MRS ILLEGAL H X X X X DESL Nop Enter idle af ter tRP L H H H X NOP Nop Enter idle af ter tRP L H H L X BST ILLEGAL L H L H BA/CA/A10 READ/READA ILLEGAL 3 L H L L BA/CA/A10 WRIT/WRITA ILLEGAL 3 L L H H BA/RA ACT ILLEGAL 3 L L H L BA, A10 PRE/PALL Nop Enter idle af ter tRP L L L H X REF/SELF ILLEGAL L L L L Op-Code MRS ILLEGAL H X X X X DESL Nop Enter idle af ter tRCD L H H H X NOP Nop Enter idle af ter tRCD L H H L X BST ILLEGAL L H L H BA/CA/A10 READ/READA ILLEGAL L H L L BA/CA/A10 WRIT/WRITA ILLEGAL 3 L L H H BA/RA ACT ILLEGAL 3,10 L L H L BA, A10 PRE/PALL ILLEGAL 3 L L L H X REF/SELF ILLEGAL L L L L Op-Code MRS ILLEGAL 3 Re m ark H = High level, L = Low level, X = High or Low level (Don't care), AP = Auto Precharge Rev.01 26/33 256Mb SDRAM Current state Write recovering Write recovering w ith AP Refres hing M ode Regis ter Acces s ing /CS /R /C /W Addr. Command Action Notes H X X X X DESL Nop Enter row active af ter tDPL L H H H X NOP Nop Enter row active af ter tDPL L H H L X BST Nop Enter row active af ter tDPL L H L H BA/CA/A10 READ/READA Start read, Determine AP L H L L BA/CA/A10 WRIT/WRITA New w rite, Determine AP 8 L L H H BA/RA ACT ILLEGAL 3 L L H L BA, A10 PRE/PALL ILLEGAL 3 L L L H X REF/SELF ILLEGAL L L L L Op-Code MRS ILLEGAL H X X X X DESL Nop Enter precharge af ter tDPL L H H H X NOP Nop Enter precharge af ter tDPL L H H L X BST Nop Enter precharge af ter tDPL L H L H BA/CA/A10 READ/READA ILLEGAL 3,8 L H L L BA/CA/A10 WRIT/WRITA ILLEGAL 3 L L H H BA/RA ACT ILLEGAL 3 L L H L BA, A10 PRE/PALL ILLEGAL L L L H X REF/SELF ILLEGAL L L L L Op-Code MRS ILLEGAL H X X X X DESL Nop Enter idle after tRC L H H X X NOP/ BST Nop Enter idle after tRC L H L X X READ/WRIT ILLEGAL L L H X X ACT/PRE/PALL ILLEGAL L L L X X REF/SELF/MRS ILLEGAL H X X X X DESL Nop L H H H X NOP Nop L H H L X BST ILLEGAL L H L X X READ/WRIT ILLEGAL L L X X X ACT/PRE/PALL/ REF/SELF/MRS ILLEGAL Re m ark H = High level, L = Low level, X = High or Low level (Don't care), AP = Auto Precharge Notes 1. All entries assume that CKE w as active (High level) during the preceding clock cycle. 2. If all banks are idle, and CKE is inactive (Low level), SDRAM w ill enter Pow er dow n mode. All input buf fers except CKE w ill be disabled. 3. Illegal to bank in specified states; Function may be legal in the bank indicated by Bank Address (BA0/1), depending on the state of that bank. 4. If all banks are idle, and CKE is inactive (Low level), SDRAM w ill enter Self refresh mode. All input buf fers except CKE w ill be disabled. 5. Illegal if tRCD is not satisfied. 6. Illegal if tRAS is not satisfied. 7. Must satisfy burst interrupt condition. 8. Must satisfy bus contention, bus turn around, and/or w rite recovery requirements. 9. Must mask preceding data w hich don't satisfy tDPL. 10. Illegal if tRRD is not satisfied. Rev.01 27/33 256Mb SDRAM 5. Command Truth Table for CKE Current state Self re fres h Self re fres h re covery CKE n-1 n /CS /R /C /W Addr. Action H X X X X X X INVALID, CLK (n – 1) w ould exit self refresh L H H X X X X Self refresh recovery L H L H H X X Self refresh recovery L H L H L X X ILLEGAL L H L L X X X ILLEGAL L L X X X X X Maintain self refresh H H H X X X X Idle after tRC H H L H H X X Idle after tRC H H L H L X X ILLEGAL H H L L X X X ILLEGAL H L H X X X X ILLEGAL H L L H H X X ILLEGAL H L L H L X X ILLEGAL H L L L X X X ILLEGAL H X X X X X X INVALID, CLK(n-1) w ould exit pow er dow n Pow e r dow n L H X X X X X Exit pow er dow n Idle L L X X X X X Maintain pow er dow n mode H H H X X X Refer to operations in Operative Command Table H H L H X X Refer to operations in Operative Command Table H H L L H X H H L L L H X H H L L L L Op-Code H L H X X X Refer to operations in Operative Command Table H L L H X X Refer to operations in Operative Command Table H L L L H X Refer to operations in Operative Command Table H L L L L H X H L L L L L Op-Code Both bank s idle Row active Any s tate other than lis ted above Notes Refer to operations in Operative Command Table Refresh Refer to operations in Operative Command Table Self refresh 1 Refer t o operations in Operative Command Table L X X X X X X Pow er dow n H X X X X X X Refer to operations in Operative Command Table X Pow er dow n L X X X X X H H X X X X H L X X X X X Begin clock suspend next cycle L H X X X X X Exit clock suspend next cycle L L X X X X X Maintain clock suspend 1 1 Refer to operations in Operative Command Table 2 Re m ark : H = High level, L = Low level, X = High or Low level (Don't care) Notes 1. Self refresh can be entered only from the both banks idle state. Pow er dow n can be entered only from both banks idle or row active state. 2. Must be legal command as defined in Operative Command Table. Rev.01 28/33 256Mb SDRAM Absolute Maximum Ratings Symbol Item Rating Units VIN, VOUT Input, Output Voltage -0.5 ~ 4.6 V VDD, VDDQ Power Supply Voltage -0.5 ~ 4.6 V TOP Operating Temperature 0 ~ 70 C TSTG Storage Temperature -55 ~ 125 C PD Power Dissipation 1 W IOS Short Circuit Current 50 mA Note : Caution Exposing the device to stress above those listed in Absolute Maximum Ratings could cause permanent damage. The device is not meant to be operated under conditions outside the limits described in the operational section of this specification. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Recommended DC Operation Conditions ( Ta = 0 ~ 70°C) Symbol Parameter Min. Typical Max. Units VDD Power Supply Voltage 3.0 3.3 3.6 V VDDQ Power Supply Voltage (for I/O Buffer) 3.0 3.3 3.6 V VIH Input logic high voltage 2.0 VDD+0.3 V VIL Input logic low voltage -0.3 0.8 V Note : 1. All voltage referred to V SS. 2. V IH (max) = VDD+1.5V for pulse w idth 5ns 3. V IL (min) = VSS-1.5V f or pulse w idth 5ns Capacitance ( Vcc =3.3V, f = 1M Hz, Ta = 25°C ) Symbol Parameter Min. Max. Units CCLK Clock capacitance 1.5 3.0 pF CI Input capacitance for CLK, CKE, Address, /CS, /RAS, /CAS, /WE, DQM0 ~ 3 1.5 3.0 pF CO Input/Output capacitance 3.0 5.5 pF Rev.01 29/33 256Mb SDRAM Recommended DC Operating Conditions ( VDD = 3.3V +/- 0.3 V, Ta = 0 ~ 70 °C, Ta = -40 to 85°C ) Parameter Symbol Operating current ICC1 Precharge standby ICC2P current in power down ICC2PS mode Precharge standby current in non-power down mode Active standby current in power down mode Test condition Burst length = 1, tRC =tRC (min), IOL = 0 mA, One bank active MAX Units Notes 125 mA CKE V IL (max.), tCk = tck(min) 3 mA CKE V IL (max.), tCk = 2 mA 20 mA ICC2N CKE V IL (min.), tCK = tck(min), /CS V IH (min.)Input signals are changed one time during 2clk ICC2NS CKE,/CS V IL (min.), tCK = Input signals are stable 9 mA ICC3P CKE VIL(max), tCK = tck(min) 4 mA ICC3PS CKE VIL(max), tCK = 3 mA ICC3N CKE VIL(min), tCK = tck(min) , / CS VIH(min) Input signals are changed one time during 2clk 45 mA ICC3NS CKE VIL(min), tCK = Input signals are stable 30 mA Active standby current in non-power down mode 1 operating current (Burst mode) ICC4 tCCD = 2CLKs , IOL = 0 mA 150 mA 2 Refresh current ICC5 tRC =tRC(min.) 270 mA 3 Self Refresh current ICC6 VIL 0.2V ,VIH VDD-0.2V 3 mA 4 Note : 1. ICC1 depends on output loading and cycle rates. Specified values are obtained w ith the output open. Input signals are changed only one time during tCK(min) 2. ICC4 depends on output loading and cycle rates. Specified values are obtained w ith the output open. Input signals are changed only one time during tCK(min) 3. Input signals are changed only one time during tCK(min) 4. Standard pow er version. Rev.01 30/33 256Mb SDRAM Recommended DC Operating Conditions ( Continued ) Parameter Symbol Test condition Min. Max. Unit Input leakage current IIL 0 VI VDDQ, VDDQ=VDD All other pins not under test=0 V -1 +1 uA Output leakage current IOL 0 VO VDDQ, DOUT is disabled -1.5 +1.5 uA High level output voltage VOH Io = -2mA 2.4 Low level output voltage VOL Io = +2mA V 0.4 V AC Operating Test Conditions ( VDD = 3.3V +/- 0.3 V, Ta = 0 ~ 70° C ) Output Reference Level 1.4V / 1.4V Output Load CL=30pF Input Signal Level 2.4V / 0.4V Transition Time of Input Signals 2ns Input Reference Level 1.4V Rev.01 31/33 256Mb SDRAM Operating AC Characteristics ( VDD = 3.3V +/- 0.3 V, Ta = 0 ~ 70°C, Ta = -40 to 85°C ) Parameter Clock cycle time Symbol CL = 3 CL = 2 tCK -8 Min. Max. Units Notes 8 - ns 10 - ns - 5.4 ns Access time from CLK tAC CLK high level width tCH 2.5 - ns CLK low level width tCL 2.5 - ns Data-out hold time tOH 2 - Data-out high impedance time tHZ - 5.4 Data-out low impedance time tLZ 0 - Input hold time tIH 0.8 ns Input setup time tIS 1.5 ns ACTIVE to ACTIVE command period tRC 67.5 ns 3 ACTIVE to PRECHARGE command period tRAS 45 120k ns 3 PRECHARGE to ACTIVE command period tRP 20 ns 3 ACTIVE to READ/WRITE delay time tRCD 20 ns 3 ACTIVE(one) to ACTIVE(another) command tRRD 15 ns 3 READ/WRITE command to READ/WRITE command tCCD 1 CLK Data-in to PRECHARGE command tDPL 2 CLK Data-in to BURST stop command tBDL 1 CLK Data-out to high impedance from CL = 3 PRECHARGE command CL = 2 tROH 3 CLK 2 CLK Refresh time(4,096 cycle) tREF 64 ns ns ns 2 ns ns ns ms Note : 1. All voltages referenced to Vss. 2. tHZ defines the time at which the output achieve the open circuit condition and is not referenced to output voltage levels. 3. These parameters account for the number of clock cycle and depend on the operating frequency of the clock, as follows : The number of clock cycles = Specified value of timing/clock period (Count fractions as a whole number) Rev.01 32/33 256Mb SDRAM Package Dimension * EOREX reserves the right to change products or specification without notice. Rev.01 33/33