ETC IL-P1-XXXX-B

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DALSA
IL-P1-xxxx-B
Image Sensors
TheIL-P1-xxxx-Bsetsnewlinescanstandards.Itsunprecedented design and fabrication sophistication has produced
superiorperformance:highblueresponseandlowimagelag,
two taps for high line rates, low-voltage clocks—and DALSA’s standard 100% fill factor.
12V/(µJ/cm2)
Description
Features
n
n
n
n
n
n
n Highly sensitive, with responsivity reaching
2 taps @ 25MHz data rate per tap
Line rates to 87kHz
Low voltage clocks (<5V)
10µm (H) x 10µm (V) pixels, 100% fill factor
512, 1024, or 2048 pixels
Antiblooming and exposure control
IL-P1-xxxx-B
Physical Characteristics
Pixel dimensions
10µm x 10µm
Active area 10µm x
5.1 / 10.2 / 20.5
Active pixels per line
512 / 1024 / 2048
Isolation pixels per line
14
Table 1. IL-P1-xxxx-B Pin Functional Description
Pin
1,13
2,18
3
4
5
6, 22
7, 23
8
9
10
11, 28
12, 27
14, 15, 17, 19
16
20, 21, 26
24
25, 29
30
31
32
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Symbol
VLOW
VDD
OS1
VSET
CRLAST
CR1S
CR2S
TCK
PR
VPR
CR1B
CR2B
VHIGH
NC
VBB
VSTOR
VSS
OS2
VOD
RST
Name
Low Bias Voltage
Amplifier Supply Voltage
Output Signal 1
Output Node Set Gate Voltage
Readout Clock, Last storage phase
Readout Clock, Phase 1—Storage Phase
Readout Clock, Phase 2Storage Phase
Transfer Clock
Pixel Reset Clock
Pixel Reset Drain Voltage
Readout Clock, Phase 1Barrier Phase
Readout Clock, Phase 2—Barrier Phase
High Bias Voltage
No Connection
Substrate Bias Voltage
Storage Well Voltage
Ground Reference
Output Signal 2
Output Reset Drain Voltage
Output Reset Clock
VLOW
VDD
OS1
VSET
CRLAST
CR1S
CR2S
TCK
PR
VPR
CR1B
CR2B
VLOW
VHIGH
VHIGH
NC
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1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
RST
VOD
OS2
VSS
CR1B
CR2B
VBB
VSS
VSTOR
CR2S
CR1S
VBB
VBB
VHIGH
VDD
VHIGH
1
ISO 9001
IL-P1-xxxx-B
Line Scan Sensors
For product information and updates visit www.dalsa.com
Figure 1. IL-P1-xxxx-B Block Diagram
CR1S, CR2S,
CR1B, CR2B, CRLAST
OS2
5I
CCD Readout Shift Register
4I
Storage Well with Exposure Control and Reset Structure
32 S
4I
N Photoelements (10µm x 10µm)
4I
TCK
32 S
VSTOR
PR
VPR
Storage Well with Exposure Control and Reset Structure
VDD
5I
VBB
RST
VSET
VOD
OS1
1
CCD Readout Shift Register
CR1S, CR2S,
CR1B, CR2B, CRLAST
VSS
Relative position of package Pin 1
Table 3. # of DC Biases Required
Table 2. # of Clock Drivers Required
Clock Drivers
Voltage
Speed
Low
High
1.
2.
High
Low
DC Biases
Regulated?
Min. # Required
PR off
PR on
1
2
3
1
Shielded pixels per line
# Required
PR off
PR on
1
2
3
Yes
10
9
2
No
3
3
Redundant clock drivers may be required to drive
the CCD input capacitance. Refer to Figure 7 for
details.
PR = Pixel Reset (exposure control).
32
DALSA’s IL-P1-xxxx-B series of linear CCD image sensors use proprietary technology to provide two outputs
at 25 MHz each. The series employs buried channel CCD
shift registers to maximize output speed and reduce
noise. The sensor has a dynamic range of >3200:1 and
provides output which is linear for the operating range of
light input. The IL-P1-xxxx-B’s exposure control allows
integration times shorter than the readout time. Proprietary DALSA image sensor architecture provides low image lag pixels and high blue response.
The IL-P1-xxxx-B sensor’s superior performance makes it
ideally suited for applications requiring maximum speed
and high resolution, such as:
n High performance document scanning
n Inspection
n Optical character recognition
Functional Description
The IL-P1-xxxx-B sensor is composed of three main functional groups: photodiodes in which the signal charge
packets are generated, two CCD readout shift registers,
2
ISO 9001
4I
32 S Light-shielded pixels
4 I Isolation pixels
N = 512, 1024,
or 2048
1.
2.
Refer to Figure 7 for details.
PR = Pixel Reset (exposure control).
and two output amplifiers where the charge packets are
converted to voltage pulses.
Detection
The IL-P1-xxxx-B series includes sensors with 512, 1024,
or 2048 pixels with active imaging area lengths of 5, 10,
and 20mm respectively. Photoelements are 10µm square
2
for a photosensitive area of 100µm and a 1:1 aspect ratio. Light incident on these photoelements is converted
into charge packets whose size (i.e., number of electrons)
is linearly dependent on the light intensity and the integration time. The charge is collected into a separate storage well (VSTOR) adjacent to each photoelement. This
helps to minimize both image lag and nonuniformities associated with the use of pixel reset.
With exposure control disabled, integration time is the
period between successive pulses of the transfer (TCK)
clock. Integration time can be further reduced with electronic exposure control using the pixel reset (PR) clock.
The pixel reset clock resets not the photoelements themselves but the storage well adjacent to each photoelement. When PR is clocked, the integration time becomes
the duration between the falling edge of the PR clock and
the rising edge of the TCK clock.
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IL-P1-xxxx-B
Line Scan Sensors
When PR is clocked, the PR pulse must be damped to
produce a smooth PR pulse. If PR switches too rapidly,
the uniformity of the OSn signals will be affected by the
PR clock feedthrough.
should preferably have a slower rise and fall time than
CR1 and CR2.
Antiblooming is always present when biases fall within the
specified operating conditions. By adjusting VSTOR however, the user has the added flexibility of selecting the antiblooming level (the signal level beyond which additional
signal charges are drained away). A higher VSTOR bias
results in a higher antiblooming level.
Output
Transfer
The TCK clock controls the transfer of electrons from
the storage well into two discrete readout registers for
alternating odd/even pixel readout. Transfer is from the
storage wells into the CR1 phases of the readout registers. The readout registers are then used to serially shift
the charge packets to the two high-speed low-noise output amplifiers.
The two readout registers are pseudo-2-phase buriedchannel CCD shift registers. The CR1x and CR2x phases
are complements of each other. Each of these two phases
has a storage (CRxS) and a barrier (CRxB) gate. The
storage and barrier gates of each phase are clocked in
phase (i.e., CR1S is clocked in phase with CR1B, and
CR2S is clocked in phase with CR2B). The only difference
between the storage and barrier phase clocks is the bias
levels applied to these clocks. AC-coupling and then DCshifting the CRxS phases will produce the CRxB phases.
The final storage electrode of each readout register is
connected separately to CRLAST. CRLAST should be
clocked in phase with CR1.
All CR clocks operate with 50% duty cycle.
Unlike CR1 and CR2, the CRLAST pin is connected to
only two CCD gates, one for each of the two CCD shift
registers on each side. Consequently, the CRLAST capacitance is much smaller than the CR1 or CR2 capacitance.
To prevent CRLAST from switching much faster than
CR1 and CR2, we recommend that a 100Ω resistor be
connected in series with CRLAST. The CRLAST clock
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Additional details on driving the sensor are provided on
Figure 7.
The signal charge packets from the readout shift registers
are transferred serially from the last readout gate
(CRLAST), over the set gate (VSET), to a floating sense
node diffusion. The set gate isolates the sense node diffusion from the last readout gate and the rest of the readout shift register. As signal charge accumulates on the
floating node diffusion, the potential of this diffusion decreases. The floating node diffusion is connected to the
input of a 2.5-stage low-noise amplifier, producing an output signal voltage on the amplifier output (OSn). The
floating diffusion is cleared of signal charge by the reset
gate (RST) in preparation for the next signal charge
packet. The voltage level of the floating diffusion after
each reset is determined by the output reset drain voltage (VOD). AC coupling the output is recommended to
eliminate the DC offset.
Each of the output signals (OSn) requires an off-chip load
drawing approximately 8mA of load current. If the sensor
is running at greater than 35MHz data rate, or if the load
capacitance (CLOAD) is greater than 10pF, larger load current (up to the 18mA limit) may be required. As the load
current increases, the amplifier bandwidth increases. The
amplifier can also drive larger capacitive loads when the
load current is larger. We recommend however that just
enough bandwidth be used since larger bandwidth also
results in increased noise.
If an off-chip current load is not available, each of the amplifier outputs (OSn) can be connected to a 1.2kΩ load
resistor. The use of a passive (resistive) load reduces the
amplifier gain, resulting in lower responsivity and saturation output signal.
The variations in charge conversion efficiency among the
various outputs of the sensor, along with component
variations in the drive electronics, result in output gain
mismatch. To match outputs, we recommend that the
camera electronics incorporate a gain correction of up to
15%.
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3
ISO 9001
IL-P1-xxxx-B
Line Scan Sensors
For product information and updates visit www.dalsa.com
Table 4. IL-P1-xxxx-B Absolute Maximum Ratings
Parameter
Unit
Min.
Max.
Storage Temp
°C
-20
80
Operating Temp
°C
-20
60
Voltage on CR1x, CR2x, CRLAST, RST, VSET,
VSTOR, TCK, PR with respect to VBB
V
-10
18
Voltage on OSn, VDD, VOD, VSS, VPR, VHIGH,
VLOW with respect to VBB
V
0
18
Voltage on OSn with respect to VSS
V
VDD-8
VDD+1
Amplifier Load Current (ILOAD)
WARNING:
mA per output
20
Exceeding these values will void product warranty and may damage the device.
CAUTION! These devices are sensitive to damage from electrostatic discharge (ESD).
The leads should be shorted together during storage or handling to prevent damage
to the device.
Table 5. IL-P1-xxxx-B Input/Output Characteristics
Input Characteristics: Capacitance to VBB 1
Unit
Typical
512
1024
2048
pF
90
130
220
pF
100
140
240
from CRLAST
pF
12
12
12
from RST
pF
10
10
10
from PR
pF
40
60
110
from TCK
pF
70
110
200
from CR1S, CR2S
1
from CR1B, CR2B
2
Output Characteristics:
Output Impedance (ROUT)
4
Amplifier Supply Current (IDD)
DC Output Offset (VOS)
5
6
Ω
180Ω with ILOAD = 8mA
mA
36mA with ILOAD = 8mA
V
10V with ILOAD = 8mA
Notes:
1.
2.
3.
Using 1V pk-pk 1MHz signal with +5V DC offset.
The two CR1S pins (pins 6 and 22) are internally connected, as are the two CR2S pins (pins 7 and 23).
The two CR1B pins (pins 11 and 28) are not internally connected, nor are the two CR2B pins (pins 12 and 27).
Capacitance values indicated refer to the total capacitance of the two CRxB pins.
4.
5.
6.
In general, ROUT (Ω) ~ 520 * (ILOAD) , ILOAD in mA.
In general, IDD (mA) = 2 * (10 + ILOAD), ILOAD in mA.
2
In general, VOFFSET (V) = 0.003 * (ILOAD) - 0.22 * (ILOAD) + 11.5, ILOAD in mA.
4
ISO 9001
-0.5
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IL-P1-xxxx-B
Line Scan Sensors
For product information and updates visit www.dalsa.com
Table 6. IL-P1-xxxx-B DC Operating Conditions
Symbol
ILOAD
2
Description
Unit
Load current to each output (OSn)
Min.
Rec.
1
Max.
mA
7.5
8.0
18.0
Amplifier supply voltage
V
14.0
14.0
15.0
VOD
Output reset drain voltage
V
11.0
11.3
VDD - 2
VSET
Output node set gate voltage
V
CRLAST offset
+0.5
0
CRLAST offset
+1.0
VDD
VSTOR
3
Storage well voltage
V
-1
0
0.2
Pixel reset drain voltage
V
13
14
15
Substrate bias
V
-3
-2
-1
Low bias voltage
V
VBB
0
0
VHIGH
High bias voltage
V
13
14
15
VSS
Ground Reference
V
VPR
VBB
VLOW
4
0
Notes:
1.
2.
3.
4.
Selecting a bias that deviates significantly from the recommended value can cause the recommended value of
another bias to fall outside the Min. and Max. bias range. If this occurs, ignore the recommended value and ensure
that each of the biases falls within its own Min. and Max. range.
ILOAD needs to be > 10mA only if ƒRST > 35MHz or CLOAD > 10pF.
VSTOR may be adjusted to affect the antiblooming level. VSAT decreases by ∼418mV for every 1.0V reduction in
VSTOR.
If your implementation uses separate digital and analog grounds, connect VLOW to the digital ground.
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5
ISO 9001
IL-P1-xxxx-B
Line Scan Sensors
For product information and updates visit www.dalsa.com
Table 7. IL-P1-xxxx-B AC Operating Conditions
Symbol
Description
Unit
Min.
Rec.
Max.
CRx
All CR Clocks
swing*
V
4.5
5.0
6.5
CRxS
Readout Register Clocks
(storage phase)
Readout Register Clocks
(barrier phase)
Readout Register Clocks
(last storage phase)
Reset Clock
offset*
V
0
0
0.5
offset
V
-(CRx swing)+1.5
-3.0
-(CRx swing)+2.5
offset
V
CRxB offset+1.5
-0.8
CRxB offset+2.5
offset
V
VOD-RST swing-6.8
-0.5
0
swing
V
4.8
5.5
6.5
offset
V
VBB
0
0
swing
V
VSTOR+5.0
8
10
offset
V
0.5
1.2
1.5
swing
V
VSTOR+4.5
8
10
40
CRxB
CRLAST
RST
TCK
Transfer Clock
PR
Pixel Reset Clock
ƒRST
Data rate per output
MHz
25
ƒDATA
Effective data rate
MHz
50
80
ƒLINE
Line rate
kHz
87.3
137.5
1024
46.1
73.1
2048
23.7
37.8
Notes:
1.
0512
Selecting a bias that deviates significantly from the recommended value
can cause the recommended value of another bias to fall outside the Min.
and Max. bias range. If this occurs, ignore the recommended value and
ensure that each of the biases falls within its own Min. and Max. range.
6
ISO 9001
Swing
* Offset
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IL-P1-xxxx-B
Line Scan Sensors
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Table 8. IL-P1-xxxx-B Performance Specifications
Specification
Unit
Saturation Output Voltage (VSAT)
mV
rms Noise
mV
Wavelength of Peak Responsivity
nm
Peak Responsivity
V/(µJ/cm2)
Dynamic Range
Charge Conversion Efficiency (CCE)
µV/e2
Noise Equivalent Exposure (NEE)
pJ/cm
Saturation Equivalent Exposure (SEE)
nJ/cm2
Full Well Capacity
ke
1,2
PR exposure control disabled
mV
Fixed Pattern Noise (FPN)
PR exposure control enabled
mV
3,4
Photoresponse Non-Uniformity (PRNU)
PR exposure control disabled
8 pixel local neighborhood
PR exposure control enabled
Min.
Typ.
Max.
700
900
0.28
700
12.0
3200:1
5.0
23
75
180
0.5
2.0
1100
0.31
11.0
2250:1
4.7
21
52
132
13.5
3900:1
5.3
28
1.0
5.0
2.2
6.0
Global
3.5
8.5
8 pixel local neighborhood
2.5
6.5
Global
3.8
8.8
0.999999
11.5
0.15
0.5
Charge Transfer Efficiency (CTE) (readout register)
First Field Lag 5
Dark Signal, Integration time = 84µs
0.99999
mV
mV
Notes:
1.
2.
3.
4.
5.
Maximum peak-to-peak variation of all outputs.
Due to its general purpose design, DALSA's camera and sensor evaluation hardware provides an output that cannot
be used to directly measure low FPN.
The peak-to-peak variation is measured at ~50% SEE.
With output gain mismatch correction.
Lag is measured at VSAT with LINE = 10kHz.
Test Conditions:
n
n
n
n
n
n
Operating temperature = 35°C.
ƒRST = data rate per output = 25MHz.
ILOAD = 8mA.
CLOAD = 10pF.
Tungsten halogen light source, black body color temperature 3200K, filtered with 750nm IR cutoff filter.
See Sensor Measurement Definitions (doc# 03-36-00149) for specification definitions.
Life Support Applications
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. DALSA customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify DALSA for any damages resulting from such
improper use or sale.
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7
ISO 9001
IL-P1-xxxx-B
Line Scan Sensors
For product information and updates visit www.dalsa.com
Figure 2. Performance Measurements
400µW/cm2 100µW/cm2
100
12
10
8
6
4
2
0
400 500 600 700 800 900 1000
Wavelength (nm)
Responsivity
Signal Output
(%)
Saturation Output
2
Responsivity [V/(µJ/cm )]
14
80
60
40
20
40µW/cm
2
0
0.2 0.4 0.6 0.8 1.0
Integration Time (ms)
Output vs. Integration Time
(@700nm)
Table 9. IL-P1-xxxx-B Timing Parameters
Symbol Description
tCR
Period of CRx clocks
t1
Integration time (PR disabled)
Unit
Min.
Rec.
Max.
t2
Integration time (PR enabled)
t3
TCK to first valid pixel
pixels
23
t4
Overclock pixels
pixels
0
23
t5
CRxB falling edge to CRxS falling edge
ns
0
0
0.25tCR
t6
CR1B falling edge to CRLAST falling edge
ns
0
0
0.25tCR
t7
TCK high overlap with CR1S high
ns
200
300
23
t8
TCK falling edge to CR1S falling edge
ns
2
t9
CRLAST rising to RST rising edge
ns
0
0.5tCR - t11
0.5tCR - t11
t10
RST falling edge to CRLAST falling edge
ns
0
0
0.5tCR-t11
t11
RST pulse width (FWHM)
ns
5
5
0.25tCR
t12
CR1x and CR2x rise and fall time
ns
2
5
0.25tCR
t13
CRLAST rise and fall time
ns
t12
t12 + 1
0.25tCR
1
Notes:
1.
Full Width Half Maximum
8
ISO 9001
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IL-P1-xxxx-B
Line Scan Sensors
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Figure 3. IL-P1-xxxx-B Overall Timing
CR1x
CR2x
CRLAST
t1
TCK
RST
t2
PR
OSn
Line 1
Line 2
Active Pixels
t3
Line 3
t3
t4
Figure 4. IL-P1-xxxx-B Detailed Readout Register Timing
t8
t5
CR1S
t12
t12
tCR
CR1B
t5
CR2S
CR2B
t10
t6
CRLAST
t7
t9
TCK
t13
t13
t11
RST
OSn
Overclock Overclock
Pixel
Pixel
Isolation
Pixel
Isolation
Pixel
Figure 5. IL-P1-xxxx-B Gate Structure Diagram
VPR
PR
VDD
Pixel
OS
VSTOR
n+
VSS
TCK
n+
CR1B
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CR1S
CR2B
CR2S
CR1B
CR1S
CR2B
CR2S
CR1B
CRLAST VSET
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n+
RST
VOD
9
ISO 9001
IL-P1-xxxx-B
Line Scan Sensors
For product information and updates visit www.dalsa.com
10
ISO 9001
OC
I14
I10
S32
S17
I9
I8
Pixel
N
Pixel
N-2
Pixel
4
Pixel
2
I6
I5
S16
S1
I5
I
Isolation Pixel.
S
Light-Shielded Pixel.
OC Overclock Pixel.
Sample video
I1
OC
OS2
OC
OC
OS1
RST
TCK
CRLAST
CR2x
CR1x
OC
I1
I5
S1
S16
I5
I6
Pixel
1
Pixel
3
Pixel
N-3
Pixel
N-1
I8
I9
S17
S32
I10
I14
OC
Figure 6. IL-P1-xxxx-B Readout Register Timing
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RST
CR22=CR1
CR11
High-speed
Low-voltage
Clock Drivers
PR
(with
exposure
control)
TCK
Low-speed
High-voltage
Clock Drivers
(PIN 8)
TCK
VPR
VDD
VDD6
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(PINS 3,30)
OSx
10kΩ
(PIN 4)
(PIN 24)
VSET
VSTOR
VSET
VSTOR7
ILOAD
BIAS
(PINS 25,29)
(PINS 20,21,26)
VSS
VBB
VSS
VBB
(PINS 2,18)
(PINS 14,15,17,19)
(PIN 31)
VHIGH
VOD
(PINS 1,13)
(PIN 10)
(PIN 9)
(PIN 32)
RST
PR
(PINS 7,23)3,4
CR2S
(PINS 12,27)4
(PINS 11, 28)3,4
CR1B,
CR2B
(PINS 6,22)3,4
(PIN 5)5
CR1S
CRLAST
VHIGH
511Ω
1kΩ
10kΩ
10kΩ
100Ω
10kΩ
IL-P1
VLOW
OSx Buffer
100nF
100nF
100nF
Possible
Interface
Circuitry
VLOW
VPR
Non-Critical
DC Bias
VOD
PR
(without
exposure
control)
CRxBBIAS
CRLAST
BIAS
Regulated
DC Bias
For product information and updates visit www.dalsa.com
IL-P1-xxxx-B
Line Scan Sensors
Figure 7. IL-P1-xxxx-B Sensor Operation Connections
11
ISO 9001
IL-P1-xxxx-B
Line Scan Sensors
For product information and updates visit www.dalsa.com
Notes to Figure 7.
1.
2.
3.
4.
a.
b.
Clock drivers are designed to drive only up to a maximum capacitance (CMAX) at a given clock frequency. If the total
capacitances of CRLAST, CR1S, and CR1B (see Table 5) exceed CMAX, more than one CR1 driver is required.
Clock drivers are designed to drive only up to a maximum capacitance (CMAX) at a given clock frequency. If the total
capacitances of CR2S and CR2B (see Table 5) exceed CMAX, more than one CR2 driver is required.
Both pins should be connected to clock drivers, though not necessarily to the same clock driver. If more than one
clock driver is used, it is acceptable to drive each pin from separate drivers.
Although the sensors are sufficiently robust that the rise and fall times of CRxS and CRxB do not need to be very
closely matched, performance is more optimal if attempts are made to match the CRxS and CRxB rise and fall
times. If more than one CRx clock driver is used, time constants are more closely matched if the sensor is driven
using either one of the following configurations:
Drive the CRxS pins with n CRx drivers. Tie the CRxB pins together. Drive the CRxB pins with a separate set of n
CRx drivers.
Drive the CRxS pins with 2n CRx drivers. Drive each CRxB pin separately with separate sets of n CRx drivers.
c.
Connect a 10Ω resistor in series with CRxS. Drive the CRxS pins with n CRx clock drivers. Connect a 20Ω resistor
in series with each CRxB pin. Drive each CRxB pin with separate sets of n CRx drivers.
Note that the CRxS pins are internally connected together, while the CRxB pins are not.
5. CRLAST should not have a fall time that is much faster than the fall time of CR1B. Unlike CR1B however, the
CRLAST pin is connected to only two CCD gates, one for each of the CCD shift registers. Consequently, the
CRLAST capacitance is much smaller than the CR2B capacitance. This is not an issue if the CRLAST clock is tapped
from CR1. However, if CRLAST is being driven from a separate driver, we recommend that a 150Ω resistor be
connected in series with CRLAST.
6. Need to source IDD = 2 * (10 + ILOAD) mA.
7. May have an optional antiblooming level adjustment.
ISO 9001 DALSA maintains a registered quality system meeting the ISO 9001 standard.
12
ISO 9001
DALSA Corp.: Phone: 519-886-6000 Fax: 519-886-8023
DALSA EUROPE: Phone: +49-8142-46770 Fax: +49-8142-467746
03-36-00134-07
www.dalsa.com
IL-P1-xxxx-B
Line Scan Sensors
For product information and updates visit www.dalsa.com
Figure 8. IL-P1-xxxx-B Package Dimensions
31.8±0.3
0512
15.9±0.3 TO CL
1.1±0.3 DIE TO
WINDOW SURFACE
No. 17
No. 1
No. 16
+0.05
0.3
-0.03
12.7±0.3
12.5±0.1
0.4±0.1
2.8±0.3
PIXEL 1
0.5±0.1
NOTES:
5.0±0.3
6.3±0.3 TO CL
OF OPTICAL AREA
OF OPTICAL AREA
No. 32
1. DIMENSIONS ARE IN MM
2. MAXIMUM DIE ROTATION IS 0.6°
1.8±0.1
26.7±0.1
2.5±0.3
(P=1.8 x 15)
31.8±0.3
1.1±0.3 DIE TO
WINDOW SURFACE
No. 17
No. 1
No. 16
12.7±0.3
12.5±0.1
0.4±0.1
2.8±0.3
PIXEL 1
0.5±0.1
5.0±0.3
6.3±0.3 TO CL
OF OPTICAL AREA
OF OPTICAL AREA
No. 32
+0.05
0.3
-0.03
1024
15.9±0.3 TO CL
NOTES:
1. DIMENSIONS ARE IN MM
2. MAXIMUM DIE ROTATION IS 0.6°
1.8±0.1
2.5±0.3
03-36-00134-07
www.dalsa.com
26.7±0.1
(P=1.8 x 15)
DALSA Corp.: Phone: 519-886-6000 Fax: 519-886-8023
DALSA EUROPE: Phone: +49-8142-46770 Fax: +49-8142-467746
13
ISO 9001
IL-P1-xxxx-B
Line Scan Sensors
For product information and updates visit www.dalsa.com
2048
31.8±0.3
15.9±0.3 TO CL
1.1±0.3 DIE TO
WINDOW SURFACE
No. 17
No. 1
No. 16
2.8±0.3
PIXEL 1
0.5±0.1
+0.05
0.3
-0.03
12.7±0.3
12.5±0.1
0.4±0.1
5.0±0.3
6.3±0.3 TO CL
OF OPTICAL AREA
OF OPTICAL AREA
No. 32
NOTES:
1. DIMENSIONS ARE IN MM
2. MAXIMUM DIE ROTATION IS 0.6°
1.8±0.1
2.5±0.3
14
ISO 9001
26.7±0.1
(P=1.8 x 15)
DALSA Corp.: Phone: 519-886-6000 Fax: 519-886-8023
DALSA EUROPE: Phone: +49-8142-46770 Fax: +49-8142-467746
03-36-00134-07
www.dalsa.com