ETC IP101ALF

IP101A LF
Data Sheet
Single port 10/100 Fast Ethernet Transceiver
Features
General Description
10/100Mbps TX
Full-duplex or half-duplex
Supports Auto MDI/MDIX function
Fully compliant with IEEE 802.3/802.3u
Supports IEEE 802.3u auto-negotiation
Supports MII / RMII / SNI interface
IEEE 802.3 full duplex control specification
Supports Automatic Power Saving mode
Supports
BaseLine
Wander
(BLW)
compensation
Supports Interrupt function
Supports repeater mode
Single 3.3V power supply with built-in 2.5V
regulator
DSP-based PHY Transceiver technology
Using either 25MHz crystal/oscillator or
50MHz oscillator REF_CLK as clock source
Flexible LED display for speed, duplex, link,
activity and collision
Supports flow control to communicate with
other MAC through MDC and MDIO
0.25u, CMOS technology
48-pin LQFP
Support Lead Free package (Please refer to
the Order Information)
IP101A LF is an IEEE 802.3/802.3u compliant
single-port Fast Ethernet Transceiver for both
100Mbps and 10Mbps operations. It supports
Auto MDI/MDIX function to simplify the network
installation and reduce the system maintenance
cost. To improve the system performance, IP101A
LF provides a hardware interrupt pin to indicate
the link, speed and duplex status change. IP101A
LF also provides Media Independent Interface
(MII) / Serial Network Interface (SNI) or Reduced
Media Independent Interface (RMII) to connect
with different types of 10/100Mbps Media Access
Controller (MAC). IP101A LF is designed to use
category 5 unshielded twisted-pair cable
connecting to other LAN devices.
IP101A LF Transceiver is fabricated with
advanced CMOS technology, which the chip only
requires 3.3V as power supply and consumes
very low power in the Auto Power Saving mode.
IP101A LF can be implemented as Network
Interface Adapter with RJ-45 for twisted-pair
connection. It can also be easily implemented into
HUB, Switch, Router, Access Point.
1/36
Copyright © 2004, IC Plus Corp.
Oct 22, 2007
IP101A LF-DS-R12
IP101A LF
Data Sheet
Table Of Contents
Features................................................................................................................................................... 1
General Description ................................................................................................................................. 1
Table Of Contents .................................................................................................................................... 2
Revision History....................................................................................................................................... 3
Transmit and Receive Data Path Block Diagram .................................................................................... 4
Pin Assignments ...................................................................................................................................... 5
1 Pin Descriptions................................................................................................................................ 6
Pin Descriptions (continued).................................................................................................................... 7
Pin Descriptions (continued).................................................................................................................... 8
Pin Descriptions (continued).................................................................................................................... 9
Pin Descriptions (continued).................................................................................................................. 10
Pin Descriptions (continued)...................................................................................................................11
Pin Descriptions (continued).................................................................................................................. 12
2 Register Descriptions ..................................................................................................................... 13
Register Descriptions (continued) ......................................................................................................... 14
Register Descriptions (continued) ......................................................................................................... 15
Register Descriptions (continued) ......................................................................................................... 16
Register Descriptions (continued) ......................................................................................................... 17
Register Descriptions (continued) ......................................................................................................... 18
Register Descriptions (continued) ......................................................................................................... 19
Register Descriptions (continued) ......................................................................................................... 20
3 Functional Description .................................................................................................................... 21
4 Serial management interface ......................................................................................................... 28
5 Crystal Specifications ..................................................................................................................... 29
6 Layout Guideline............................................................................................................................. 30
7 Electrical Characteristics ................................................................................................................ 31
7.1
D.C. Characteristic....................................................................................................... 31
7.1.1
Absolute Maximum Rating...................................................................................... 31
7.1.2
Power Dissipation ................................................................................................... 31
7.1.3
Operating Condition ................................................................................................ 31
7.1.4
Supply Voltage ........................................................................................................ 31
7.2
A.C. Characteristic....................................................................................................... 32
7.2.1
MII Timing ............................................................................................................... 32
7.2.2
RMII Timing............................................................................................................. 33
7.2.3
SMI Timing .............................................................................................................. 34
8 Order Information ........................................................................................................................... 35
9 Package and Mechanical Specification .......................................................................................... 36
2/36
Copyright © 2004, IC Plus Corp.
Oct 22, 2007
IP101A LF-DS-R12
IP101A LF
Data Sheet
Revision History
Revision #
IP101A LF-DS-R01
IP101A LF-DS-R02
IP101A LF-DS-R03
IP101A LF-DS-R04
IP101A LF-DS-R05
IP101A LF-DS-R06
IP101A LF-DS-R07
IP101A LF-DS-R08
IP101A LF-DS-R09
IP101A LF-DS-R10
IP101A LF-DS-R11
IP101A LF-DS-R12
Change Description
Initial release.
Add Crystal Specification and MII AC Timing.
Modify 7.1.2 Power Dissipation in page 41.
Modify register 5.11 in page 16.
Add the order information for lead free package.
Revise the general description & modify the application diagram.
Modify MII reg3 content in page 15.
Remove Circuit diagram.
Modify Pin assignments in page 5.
Delete the “Preliminary” & Modify X1 input Voltage in Page30
Modify “RXER” Pin description in page 7.
Add SMI timing chart in page 28 & page 34.
3/36
Copyright © 2004, IC Plus Corp.
Oct 22, 2007
IP101A LF-DS-R12
IP101A LF
Data Sheet
Transmit and Receive Data Path Block Diagram
TXD
MII/SNI/RMII
Interface
100Mbps
4B/5B
Encoder
RXD
100Mbps
10Mbps
4B/5B
Decoder
10Mbps
Serial to
Parallel
100Mbps
100Mbps
MII Registers
10Mbps
Descrambler
Manchester/
NRZ
Decoder
Scrambler
100Mbps
5B
Serial to
Parallel
100Mbps
AutoNegotiation
Mux
100Mbps
Parallel to
Serial
100Mbps
Parallel to
Serial
MLT3/NRZI
Decoder
100Mbps
10Mbps
NRZI/MLT-3
Encoder
NRZ/Manchester
Encoder
100Mbps
10Mbps
Clock
Recovery
Clock
Recovery
10Mbps
100Mbps
5B
10Mbps
10Mbps
Squelch
100Mbps
DSP Engine
100Mbps
10Mbps
D/A & Line Driver
TXO
RJ-45
Connector
RXI
Figure 1: Flow chart of IP101A LF
4/36
Copyright © 2004, IC Plus Corp.
Oct 22, 2007
IP101A LF-DS-R12
IP101A LF
Data Sheet
25. MDC
26. MDIO
27. TEST_ON
28. ISET
29. AGND
30. MDI_RN
31. MDI_RP
32. REGOUT
33. MDI_TN
34. MDI_TP
35. AGND
36. AVDD33
Pin Assignments
24. RX_ER
37. AN_ENA
38. DPLX
23. CRS
/LEDMOD
39. SPD
22. RX_DV
/CRS_DV
40. RPTR
21. RXD0
41. APS
20. RXD1
42. RESET_N
19. RXD2
IP101A LF
43. ISOL
18. RXD3
Fast Ethernet Single Phy Transceiver Chip
48 pins LQFP package
44. MII_SNIB
17. DGND
12. LED2/
PHYAD2
11. DGND
10. LED1/
PHYAD1
9. LED0/
PHYAD0
8. REGIN
13. LED3/
PHYAD3
7. TX_CLK/
REF_CLK
48. INTR
6. TXD0
14. DVDD33
5. TXD1
47. X2
4. TXD2
15. LED4/
PHYAD4
3. TXD3
46. X1
2. TX_EN
16. RX_CLK/
C50M_O
1. COL
/RMII
45. DGND
Figure 2 : IP101A LF pins assignment
5/36
Copyright © 2004, IC Plus Corp.
Oct 22, 2007
IP101A LF-DS-R12
IP101A LF
Data Sheet
1
Pin Descriptions
Type
LI
Description
Latched Input in power up or reset
Type
PD
Description
Internal Pull-Down
I/O
Bi-directional input and output
PU
Internal Pull-Up
I
O
Input
Output
P
OD
Power
Open Drain
Pin no.
Label
Type
Description
MII and PCS Interface - Management Interface Pins
25
MDC
I
Management Data Interface Clock: This pin provides a clock
reference to MDIO. The clock rate can be up to 10MHz.
26
MDIO
I/O
Management Data interface Input/Output: The function of this
pin is to transfer management information between PHY and
MAC.
MII and PCS Interface – Media Independent Interface (MII) Pins
2
TX_EN
I
Transmit Enable: This pin is an active high input. At high status,
(PD) it indicates the nibble data in TXD[3:0] is valid.
7
TX_CLK
O
Transmit Clock: This pin provides a continuous 25MHz clock at
100BT and 2.5Mbps at 10BT as timing reference for TXD[3:0]
and TX_EN when the chip operates under MII.
3, 4, 5, 6
TXD[3:0]
I
Transmit Data: When TX_EN is set high, MAC will transmit data
through these 4 lines to PHY which the transmission is
synchronizing with TX_CLK.
22
RX_DV
O
Receive Data Valid: At high status stands for data flow is
present within RXD[0:3] lines and low means no data exchange
occurred.
16
RX_CLK
O
Receive Clock: This pin provides 25MHz for 100BT or 2.5Mhz
for 10BT and RX_DV pin uses this pin as its reference under MII.
18, 19,
20, 21
RXD[3:0]
O
Receive Data: These 4 data lines are transmission path for PHY
to send data to MAC and they are synchronizing with RX_CLK.
6/36
Copyright © 2004, IC Plus Corp.
Oct 22, 2007
IP101A LF-DS-R12
IP101A LF
Data Sheet
Pin Descriptions (continued)
Pin no.
Label
Type
Description
MII and PCS Interface – Media Independent Interface (MII) Pins
24
RX_ER
O
Receive error: This pin outputs a high status when errors
(PD) occurred in the decoded data in the reception.
(Notice: This pin is pulled down internally. An external 5.1KΩ
pull down resistor is needed to avoid the noise interference.)
1
COL/RMII
O/LI
(PD)
Collision Detected: When this pin outputs a high status signal it
means collision is detected.
RMII Mode: During power on reset, this pin status is latched and
arranged with MII/SNIB (pin44) to determine MAC interface
RMII MII/SNIB
1
X
RMII Interface
0
1
MII Interface
0
0
SNI Interface
(Notice: This pin is pulled down internally)
23
CRS/LEDMOD
O
(PD)
Carrier Sense: When signal output from this pin is high
indicates the transmission or reception is in process and at low
status means the line is in idle state.
LEDMOD: During power on reset, this pin status is latched to
determine at which LED mode to operate, please refer to the
LED pins description.
(Notice: This pin is pulled down internally)
7/36
Copyright © 2004, IC Plus Corp.
Oct 22, 2007
IP101A LF-DS-R12
IP101A LF
Data Sheet
Pin Descriptions (continued)
Pin no.
Label
RMII (Reduced MII)
7
REF_CLK
16
C50M_O
2
TX_EN
Type
Description
I
Reference Clock: This pin is an input pin operates as 50MHz
reference clock (REF_CLK) in RMII mode.
Reference Clock out: This pin could be configured as 50MHz
clock output in RMII mode. With 25MHz crystal/oscillator, IP101A
LF could generate 50MHz output for RMII mode.
Transmit Enable: For MAC to indicate transmit operation
O
I
(PD)
5,6
TXD[1:0]
24
RX_ER
I/O
Receive Error
CRS_DV
RXD[1:0]
O
O
Carrier Sense and Receive Data Valid
Received two-bit Data
22
20, 21
I
Transmit two-bit Data
SNI (Serial Network Interface): 10Mbps only
2
TX_EN
I
Transmit Enable: Indicate transmit operation to MAC
(PD)
7
TX_CLK
O
Transmit Clock: 10MHz, clock generated by PHY
6
TXD0
I
16
RX_CLK
O
Transmit Serial Data
Receive Clock: 10MHz, clock recovery from received data
21
RXD0
O
Received Serial Data
1
23
COL
CRS
O
O
Collision Detect
Carrier Sense
Cable Transmission Interface
34
MDI_TP
I/O
33
MDI_TN
I/O
31
30
MDI_RP
MDI_RN
I/O
I/O
Transmit Output Pair: Differential pair shared by 100Base-TX
and 10Base-T modes. When configured as 100Base-TX, output
is an MLT-3 encoded waveform. When configured as 10Base-T,
the output is Manchester code.
Receive Input Pair: Differential pair shared by 100Base-TX and
10Base-T modes.
8/36
Copyright © 2004, IC Plus Corp.
Oct 22, 2007
IP101A LF-DS-R12
IP101A LF
Data Sheet
Pin Descriptions (continued)
Pin no.
Label
IC Configuration Options
43
ISOL
Type
Description
I
(PD)
Set high to this pin will isolate IP101A LF from other MAC. This
action will also isolate the MDC/MDIO management interface.
The power usage is at minimum when this pin is activated. This
pin can be directly connected to GND or VCC. (An internal weak
pulled-down is used to be inactive as a default)
Enable this pin to high will put the IP101A LF into repeater
mode. This pin can be directly connected to GND or VCC. (An
internal weak pulled-down is used to be inactive as a default)
This pin is latched to input during a power on or reset condition.
Set high to put the IP101A LF into 100Mbps operation. This pin
can be directly connected to GND or VCC. (An internal weak
pulled-up is used to set 100Mbps as a default)
40
RPTR
I
(PD)
39
SPD
LI/O
(PU)
38
DPLX
LI/O
(PU)
This pin is latched to input during a power on or reset condition.
Set high to enable full duplex. This pin can be directly connected
to GND or VCC. (An internal weak pulled-up is used to set full
duplex as a default)
37
AN_ENA
LI/O
(PU)
This pin is latched to input during a power on or reset condition.
Set high to enable auto-negotiation mode, set low to force mode.
This pin can be directly connected to GND or VCC. (An internal
weak pulled-up is used to enable Auto-Negotiation as a default)
41
APS
I
(PU)
44
MII_SNIB
LI/O
(PU)
Set high to put the IP101A LF into APS mode. This pin can be
directly connected to GND or VCC. Please refer to power down
modes description for more information. (An internal weak
pulled-up is used to enable APS mode as a default)
This pin is latched to input during a power on or reset condition.
Pull high to set the IP101A LF into MII mode operation. Set low
for SNI mode. This pin can be directly connected to GND or
VCC. (An internal weak pulled-up is used to set MII mode as a
default)
9/36
Copyright © 2004, IC Plus Corp.
Oct 22, 2007
IP101A LF-DS-R12
IP101A LF
Data Sheet
Pin Descriptions (continued)
Pin no.
Label
Type
Description
LED and PHY Address Configuration
These five pins are latched into the IP101A LF during reset to configure PHY address [4:0] used for MII
management register interface. And then, in normal operation after initial reset, they are used as driving
pins for status indication LED. The driving polarity, active low or active high, is determined by each
latched status of the PHY address [4:0] during reset. If latched status is high then it will be active low,
and if latched status is Low then it will be active high. Moreover, IP101A LF provides 2 LED operation
modes. If 2nd LED mode is selected by pulling up pin CRS, only 4 LEDs are needed for status
indication. Default is first LED mode.
LED0
LED1
LED2
LED3
LED4
LED mode 1
LINK
FULL DUPLEX
10BT /ACT(blinking)
100BT /ACT(blinking)
COL
LED mode 2
LINK /ACT(blinking)
FULL DUPLEX /COL(blinking)
10BT
100BT
Reserved
9
PHYAD0/
LED0
LI/O
PHY Address [0]
Status:
Mode1: Active when linked.
Mode2: Active when linked and blinking when transmitting or
receiving data.
10
PHYAD1/
LED1
LI/O
PHY Address [1]
Status:
Mode1: Active when in Full Duplex operation.
Mode2: Active when in Full Duplex operation and blinking when
collisions occur.
12
PHYAD2/
LED2
LI/O
PHY Address [2]
Status:
Mode1: Active when linked in 10Base-T mode, and blinking
when transmitting or receiving data.
Mode2: Active when linked in 10Base-T mode.
13
PHYAD3/
LED3
LI/O
PHY Address [3]
Status:
Mode1: Active when linked in 100Base-TX and blinking when
transmitting or receiving data.
Mode2: Active when linked in 100Base-TX mode.
15
PHYAD4/
LED4
LI/O
PHY Address [4]
Status:
Mode1: Active when collisions occur.
Mode2: Reserved.
10/36
Copyright © 2004, IC Plus Corp.
Oct 22, 2007
IP101A LF-DS-R12
IP101A LF
Data Sheet
Pin Descriptions (continued)
Pin no.
Label
Type
Description
Clock and Miscellaneous - Crystal Input/Output Pins
47
X2
O
25MHz Crystal Output: Connects to crystal to provide the
25MHz output. It must be left open when X1 is driven with an
external 25MHz oscillator.
46
X1
I
25MHz Crystal Input: Connects to crystal to provide the 25MHz
crystal input. If a 25MHz oscillator is used, connect X1 to the
oscillator’s output. If a 50MHz clock is applied to pin7, X1 should
be connected to VSS or 2.5v VDD. Please refer to the clock
source description.
Clock and Miscellaneous - Miscellaneous Pins
42
RESET_N
I
RESET_N: Enable a low status signal will reset the chip. For a
complete reset function. 25MHz clock (x1) must be active for a
minimum of 10 clock cycles before the rising edge of RESET_N.
Chip will be able to operate after 2.5ms delay of the rising edge
of RESET_N. The 2.5ms extention is to ensure the stability of
system power.
INTR
48
O
Interrupt Pin: When the MII register 17:<15> is set to high, this
(OD) pin is used as an interrupt pin (Notice: this is an open drain
output, so an external pulled-up resistor is needed)
27
TEST_ON
(PD) Test Enable: Set this pin to high to enable test mode, while for
normal operation, this pin does not need to be connected. (An
internal weak pulled-down is used to disable test mode as a
default)
28
ISET
I
Transmit Bias Resistor Connection: This pin should be
connected to GND via a 6.2KΩ (1%) resistor to define driving
current for transmit DAC.
11/36
Copyright © 2004, IC Plus Corp.
Oct 22, 2007
IP101A LF-DS-R12
IP101A LF
Data Sheet
Pin Descriptions (continued)
Pin no.
Label
Power and Ground
32
REGOUT
36
Type
P
Description
Regulator Power Output: This is a regulator power output for
IP101A LF digital circuitry.
3.3V Analog power input: This is a 3.3V power supply for
analog circuitry, and it should be decoupled carefully.
AVDD33
P
29,35
AGND
P
Analog Ground: These 2 pins should connect to motherboard’s
GND.
8
REGIN
P
Regulator Power Input: This is a regulator power input from
Pin32. No external regulator needed.
14
DVDD33
P
3.3V Digital Power input: This is a 3.3V power supply for digital
circuitry.
DGND
P
Digital Ground: These 3 pins should connect to motherboard’s
GND.
11,17,45
12/36
Copyright © 2004, IC Plus Corp.
Oct 22, 2007
IP101A LF-DS-R12
IP101A LF
Data Sheet
2
Register Descriptions
Bit
Name
Default value
(h): 3100
Description/Usage
Register 0 : MII Control Register
15
Reset
14
Loop-back
13
Speed Selection
12
AutoNegotiation
Enable
11
Power Down
10
Isolate
9
Restart AutoNegotiation
8
Duplex Mode
7
Collision Test
6:0
When set, this action will bring both status and control
registers of the PHY to default state. This bit is self-clearing.
1 = Software reset
0 = Normal operation
This bit enables loop-back of transmit data to the receive
data path, i.e., TXD to RXD. IP101A LF requires at least
512us to link after programming this bit. TX/RX packets
should be activated after 512us.
1 = enable loop-back
0 = normal operation
This bit sets the speed of transmission.
1 = 100Mbps
0 = 10Mbps
This bit determines the auto-negotiation function.
1 = enable auto-negotiation; bits 13 and 8 will be ignored.
0 = disable auto-negotiation; bits 13 and 0:<8> will determine
the link speed and the data transfer mode, under this condition.
Auto-MDIX function should be disabled (set Reg16.11=1) if
this bit has been set to “0”. Please refer to section 7
Auto-MDIX function description for details.
This bit will turn down the power of the PHY chip and the
internal crystal oscillator circuit if this bit is enabled. The MDC
and MDIO are still activated for accessing to the MAC.
1 = power down
0 = normal operation
1=electrically Isolate PHY from MII but not isolate MDC and
MDIO
0=normal operation
This bit allows the auto-negotiation function to be reset.
1 = restart auto-negotiation
0 = normal operation
This bit sets the duplex mode if auto-negotiation is disabled (bit
12=0)
1 = full duplex
0 = half duplex
After completing auto-negotiation, this bit will reflect the
duplex status.(1: Full duplex, 0: Half duplex)
1=enable COL signal test
0=disable COL signal test
Reserved
0, RW
1, RW
1, RW (TP)
0, RW
0,RW
0, RW
1, RW
0,RW
0, RO
13/36
Copyright © 2004, IC Plus Corp.
0, RW
Oct 22, 2007
IP101A LF-DS-R12
IP101A LF
Data Sheet
Register Descriptions (continued)
Bit
Name
Default value
(h): 7849
Description/Usage
Register 1 : MII Status Register
15
100Base-T4
1 = enable 100Base-T4 support
0 = suppress 100Base-T4 support
14
13
12
11
10:7
0, RO
100Base-TX
Full Duplex
100BASE-TX
Half Duplex
1 = enable 100Base-TX full duplex support
0 = suppress 100Base-TX full duplex support
1 = enable 100Base-TX half duplex support
0 = suppress 100Base-TX half duplex support
1, RO
10Base-T Full
Duplex
10_Base-T Half
Duplex
1 = enable 10Base-T full duplex support
0 = suppress 10Base-T full duplex support
1 = enable 10Base-T half duplex support
0 = suppress 10Base-T half duplex support
1, RO
1, RO
1, RO
Reserved
0, RO
6
MF Preamble
Suppression
The IP101A LF will accept management frames with
preamble suppressed. The IP101A LF accepts management
frames without preamble. A Minimum of 32 preamble bits are
required for the first SMI read/write transaction after reset.
One idle bit is required between any two management
transactions as per IEEE802.3u specifications
1, RO
5
AutoNegotiation
Complete
1 = auto-negotiation process completed
0 = auto-negotiation process not completed
0, RO
4
Remote Fault
1 = remote fault condition detected (cleared on read)
0 = no remote fault condition detected
3
AutoNegotiation
1 = Link had not been experienced fail state
0 = Link had been experienced fail state
2
Link Status
1 = valid link established
0 = no valid link established
0, RO/LL
1
Jabber Detect
1 = jabber condition detected
0 = no jabber condition detected
0, RO/LH
0
Extended
Capability
1 = extended register capability
0 = basic register capability only
1, RO
14/36
Copyright © 2004, IC Plus Corp.
0, RO/LH
1, RO
Oct 22, 2007
IP101A LF-DS-R12
IP101A LF
Data Sheet
Register Descriptions (continued)
Bit
Name
Description/Usage
Register 2 : PHY Identifier Register 1
15:0 PHYID1
PHY identifier ID for software recognize IP101A LF
Bit
Name
Description/Usage
Register 3 : PHY Identifier Register 2
15:0 PHYID2
PHY identifier ID for software recognize
Default value
(h): 0243
0X0243, RO
Default value
(h): 0C54
0X0C54, RO
Note : Register 2 and register 3 identifier registers altogether consist of Vender model, model revision
number and Organizationally Unique identifier (OUI) information. Total of 32 bits allocate in these 2
registers and they can return all zeroes in all bits if desired. Register 2 contains OUI’s most significant bits
and OUI’s least significant bits, Vender model, Model revision number are allocated in register 3.
15/36
Copyright © 2004, IC Plus Corp.
Oct 22, 2007
IP101A LF-DS-R12
IP101A LF
Data Sheet
Register Descriptions (continued)
Register 4 lists the advertised abilities during auto-negotiation for what will be transmitted to IP101A LF’s
Link Partner.
Bit
Name
Default value
(h): 0001
Description/Usage
Register 4 : Auto-Negotiation Advertisement Register
15
NP
Next Page bit.
0 = transmitting the primary capability data page
1 = transmitting the protocol specific data page
14
Reserved
13
RF
12
Reserved
11
0, RO
0, RO
1 = advertise remote fault detection capability
0 = do not advertise remote fault detection capability
0, RW
1 = asymmetric flow control is supported by local node
0 = asymmetric flow control is NOT supported by local node
1 = flow control is supported by local node
0 = flow control is NOT supported by local node
0, RW
10
Asymmetric.
Pause
Pause
9
T4
8
TX Full Duplex
1 = 100Base-T4 is supported by local node
0 = 100Base-T4 not supported by local node
1 = 100Base-TX full duplex is supported by local node
0 = 100Base-TX full duplex not supported by local node
7
TX
6
10 Full Duplex
5
4:0
0, RO
0, RW
0, RO
1, RW
1 = 100Base-TX is supported by local node
0 = 100Base-TX not supported by local node
1 = 10Base-T full duplex supported by local node
0 = 10Base-T full duplex not supported by local node
1, RW
10
1 = 10Base-T is supported by local node
0 = 10Base-T not supported by local node
1, RW
Selector
Binary encoded selector supported by this node. Currently
only CSMA/CD <00001> is specified. No other protocols are
supported.
16/36
Copyright © 2004, IC Plus Corp.
1, RW
<00001>,
RO
Oct 22, 2007
IP101A LF-DS-R12
IP101A LF
Data Sheet
Register Descriptions (continued)
This register contains the advertised abilities of the Link Partner as received during Auto-negotiation. The
content changes after the successful Auto-negotiation if Next-pages are supported.
Bit
Name
Default value
(h): 0000
Description/Usage
Register 5 Auto-Negotiation Link Partner Ability Register (ANLPAR)
15
Next Page
Next Page bit.
0 = transmitting the primary capability data page
1 = transmitting the protocol specific data page
0, RO
14
Acknowledge
1 = link partner acknowledges reception of local node’s
capability data word
0 = no acknowledgement
0, RO
13
Remote Fault
1 = link partner is indicating a remote fault
0 = link partner does not indicate a remote fault
0, RO
12
Reserved
11
Asymmetric.
Pause
1 = asymmetric flow control is supported link partner
0 = asymmetric flow control is NOT supported by link partner
0, RO
10
Pause
1 = flow control is supported by Link partner
0 = flow control is NOT supported by Link partner
0, RO
9
T4
1 = 100Base-T4 is supported by link partner
0 = 100Base-T4 not supported by link partner
0, RO
8
TXFD
1 = 100Base-TX full duplex is supported by link partner
0 = 100Base-TX full duplex not supported by link partner
0, RO
7
100BASE-TX
1 = 100Base-TX is supported by link partner
0 = 100Base-TX not supported by link partner
This bit will also be set after the link in 100Base-TX is
established by parallel detection.
0, RO
6
10FD
0, RO
5
10Base-T
1 = 10Base-T full duplex is supported by link partner
0 = 10Base-T full duplex not supported by link partner
1 = 10Base-T is supported by link partner
0 = 10Base-T not supported by link partner
This bit will also be set after the link in 10Base-T is
established by parallel detection.
Link Partner’s binary encoded node selector Currently only
CSMA/CD <00001> is specified
<00000>,
RO
4:0
Selector
0, RO
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Copyright © 2004, IC Plus Corp.
0, RO
Oct 22, 2007
IP101A LF-DS-R12
IP101A LF
Data Sheet
Register Descriptions (continued)
Register 6 defines more auto-negotiation registers to meet the requirement.
Bit
Name
Default value
(h):
0000
Description/Usage
Register 6 : Auto-Negotiation Expansion Register
15:5 Reserved
This bit is always set to 0.
0, RO
4
MLF
This status indicates if a multiple link fault has occurred.
1 = fault occurred
0 = no fault occurred
0, RO
3
LP_NP_ABLE
0, RO
2
NP_ABLE
This status indicates if the link partner supports Next Page
negotiation.
1 = supported
0 = not supported
This bit indicates if the device is able to send additional Next
Pages.
1
PAGE_RX
This bit will be set if a new link code word page has been
received. It is cleared automatically after the
auto-negotiation link partner’s ability register (register 5) is
read by the management.
0, RO
0
LP_NW_ABLE
1 = link partner supports auto-negotiation.
0, RO
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Copyright © 2004, IC Plus Corp.
0, RO
Oct 22, 2007
IP101A LF-DS-R12
IP101A LF
Data Sheet
Register Descriptions (continued)
Bit
Name
Default value
(h): 0000
Description/Usage
Register 16 : PHY Spec. Control Register
15
Debug Mode
0 = IP101A LF operates at normal mode
1 = IP101A LF operates at debug mode
(Note: the functionalities of bit 16:<14:12>, and 16:<4:0>
depend on the setting of this bit 16:<15>)
14:12
Reserved
0, R/W
0, RO
11
Auto MDIX Off
Set high to disable the automatic switch of MDI and MDI-X
modes. If AN is disabled by setting pin37=0 during power
up, this bit will be set to 1 (Auto-MDIX off) automatically.
Setting Reg0.12=1 will re-activate AN, in this case, if user
needs Auto-MDIX function, this bit should be set to 0. For
details, please refer to section 7 Auto-MDIX function
description.
0, R/W
10
Heart Beat
Enable
Heart beat function enable at 10Base-T
0, R/W
9
Jabber Enable
Jabber function enable at 10Base-T
0, R/W
8
Far-End Fault
Enable/Disable
To enable or disable the functionality of Far-End Fault
Mode
Enable Disable
100Base-TX
1
0
0, R/W
7
Analog Power
Saving Disable
Set high to disable the power saving during auto-negotiation
0, R/W
6
5
Reserved
Bypass DSP
reset
4:3
Set high to bypass the reset DSP mechanism in PCS
sub-layer
Reserved
0, RO
0, R/W
0, RO
2
Repeater Mode
Set high to put IP101A LF into repeater mode
0, R/W
1
0
APS Mode
Analog Off
Set high to enable Auto Power Saving mode
Set high to power down analog transceiver
0, R/W
0, R/W
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Copyright © 2004, IC Plus Corp.
Oct 22, 2007
IP101A LF-DS-R12
IP101A LF
Data Sheet
Register Descriptions (continued)
Bit
Name
Default value
(h): 0E00
Description/Usage
Register 17 : PHY Interrupt Ctrl/Status Register
15
INTR pin used
Set high to enable pin48 as an interrupt pin. Pin48 will be
high impedance if this bit is set low.
0, R/W
14:12
Reserved
0, RO
11
All Mask
When this bit is set high, changes in all events will not cause
an interrupt
1, R/W
10
Speed Mask
When this bit is set high, changes in speed mode will not
cause an interrupt
1, R/W
9
Duplex Mask
When this bit is set high, changes in duplex mode will not
cause an interrupt
1, R/W
8
Link Mask
When this bit is set high, changes in link status will not cause
an interrupt
1, R/W
7
Arbiter State
Enable
When this bit is set low, changes in Auto-Negotiation arbiter
state machine will not cause an interrupt
0, R/W
6
Arbiter State
Change
Flag to indicate Auto-Negotiation arbiter change interrupt
0, RC
Reserved
Link Status
Change
Flag to indicate link status change interrupt
0, RO
0, RC
1
Speed Change
Flag to indicate speed change interrupt
0, RC
0
Duplex Change
Flag to indicate duplex change interrupt
0, RC
5:3
2
20/36
Copyright © 2004, IC Plus Corp.
Oct 22, 2007
IP101A LF-DS-R12
IP101A LF
Data Sheet
3
Functional Description
IP101A LF 10/100Mbps Ethernet PHY Transceiver integrates 100 Base-TX and 10 Base-T modules into a
single chip. IP101A LF acts as an interface between physical signaling and Media Access Controller
(MAC).
IP101A LF has several major functions:
1. PCS layer (Physical Coding Sub-Layer): This function contains transmit, receive and carrier sense
functional circuitries.
2. Management interface: Media Independent Interface (MII) or Reduced Management Interface (RMII)
registers contains information for communication with other MAC.
3. Auto-Negotiation: Communication conditions between 2 PHY transceivers. IP101A LF advertise its
own ability and also detects corresponding operational mode from the other party, eventually both
sides will come to an agreement for their optimized transmission mode.
IP101A LF’s major features included:
1. Flow Control ability
2. LED configuration access
3. Operation modes for both full and half duplex
4. APS (Auto Power Saving) mode
5. Base Line Wander (BLW) compensation
6. Auto MDI/MDIX function
7. Interrupt function
8. Repeater Mode
9. Flexible clock source
Major Functional Block Description
The functional blocks diagram is referred to Figure 1:
1. 4B/5B encoder: 100 Base-X transmissions require converting 4-bit nibble data into 5-bit wide data
code-word format. Transmitting data is packaged by J/K codes at the start of packet and by T/R codes
at the end of packet in the 4B/5B block. When transmit error has occurred during a transmitting
process, the H error code will be sent. The idle code is sent between two packets.
2. 4B/5B Decoder: The decoder performs the 5B/4B decoding from the received code-groups. The 5
bits (5B) data is decoded into four bits nibble data. The decoded 4 bit (4B) data is then forwarded
through MII to the repeater, switch or MAC device. The SSD is then converted into 4B 5 nibbles and
the ESD and IDLE Codes are replaced by 4B 0 nibbles data. The decoded data is driven onto the
corresponding MII port or shared MII port. Receiving an invalid code group will cause PHY to assert
the MII RXER signal.
3. Scrambler/Descrambler: Repetitive patterns exist in 4B/5B encoded data which result in large RF
spectrum peaks and keep the system from being approved by regulatory agencies. The peak in the
radiated signal is reduced significantly by scrambling the transmitted signal. Scrambler adds a
random generator to the data signal output. The resulting signal is with fewer repetitive data patterns.
The scrambled data stream is descrambled at the receiver by adding another random generator to the
output. The receiver’s random generator has the same function as the transmitter’s random generator.
Scrambler operation is dictated by the 100Base-TX and TP_FDDI standards.
4. NRZI/MLT-3(Manchester) Encoder and Decoder: 100Base-TX Transmission requires to encode the
data into NRZ format and again converted into MLT-3 signal, while 10 Base-T will convert into
Manchester form after NRZ coding. This helps to remove the high frequency noise generated by the
twisted pair cables. At receiving end, the coding is reversed from MLT-3 (Manchester) signal back to
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Copyright © 2004, IC Plus Corp.
Oct 22, 2007
IP101A LF-DS-R12
IP101A LF
Data Sheet
NRZ format.
5. Clock Recovery: The receiver circuit recovers data from the input stream by regenerating clocking
information embedded in the serial stream. The clock recovery block extracts the RXCLK from the
transition of received
6. DSP Engine: This block includes Adaptive equalizer and Base Line Wander correction function.
Transmission Description
10Mbps Transmit flow path:
TXD J Parallel to Serial J NRZI/Manchester Encoder J D/A & line driver J TXO
After MAC passes data to PHY via 4 bits nibbles, the data are serialized in the parallel to serial converter.
The converter outputs NRZI coded data which the data are then mapped to Manchester code within the
Manchester Encoder. Before transmitting to the physical medium, the Manchester coded data are shaped
by D/A converter to fit the physical medium.
10Mbps Receive:
RXI J Squelch J Clock Recovery J Manchester/NRZ Decoder J Serial to Parallel J RXD
The squelch block determines valid data from both AC timing and DC amplitude measurement. When a
valid data is present in the medium, squelch block will generate a signal to indicate the data has received.
The data receive are coded in Manchester form, and are decoded in the Manchester to NRZ Decoder.
Then the data are mapped to 4 bits nibbles and transmitted onto MAC interface.
100Mbps TX Transmit:
TXD J 4B/5B Encoder J Scrambler J Mux J Parallel to Serial J NRZI/MLT-3 Encoder J D/A & line
driver J TXO
The major differences between 10Mbps transmission and 100Mbps transmission are that 100Mbps
transmission requires to be coded from 4-bit wide nibbles to 5 bits wide data coding, and after that the
data are scrambled through scrambler to reduce the radiated energy generated by the 4B/5B conversion.
Then the data is converted into NRZI form and again from NRZI coded form into MLT-3 form. The MLT-3
data form is fed into D/A converter and shaped to fit the physical medium transmission.
100Mbps RX Receive:
RXI J DSP J MLT-3/NRZI Decoder J Clock Recovery J Serial to Parallel J Descrambler J 4B/5B
Decoder J RXD
The received data first go through DSP engines which includes adaptive equalizer and base-line wander
correction mechanism. The adaptive equalizer will compensate the loss of signals during the transmission,
while base-line wander monitors and corrects the equalization process. If a valid data is detected then the
data are parallelized in Serial to Parallel block, which it converts NRZI coded data form back to scrambled
data. The scrambled data are descrambled and converted back to 4 bits–wide format data and then feed
into MAC.
MII and Management Control Interface
Media Independent Interface (MII) is described in clause 22 in the IEEE 802.3u standard. The main
function of this interface is to provide a communication path between PHY and MAC/Repeater. It can
operate either in 10Mbps or 100Mbps environment, and operate at 2.5MHz frequency for 10Mbps clock
data rate or 25MHz frequency for 100Mbps data rate transmission. MII consists of 4 bit wide data path for
both transmit and receive. The transmission pins consists of TXD[3:0], TX_EN and TXC, and at receiving
MII pins have RXD[3:0], RXER, RX_DV and RXC. The Management control pins include MDC and MDIO.
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Copyright © 2004, IC Plus Corp.
Oct 22, 2007
IP101A LF-DS-R12
IP101A LF
Data Sheet
MDC, Management Data Clock, provides management data clock at maximum of 10MHz as a reference
for MDIO, Management Data Input/Output. CRS, Carrier Sense, is used for signaling data transmission is
in process while COL, Collision, is used for signaling the occurrence of collision during transmission.
Transmitting a packet, MAC will first assert TX_EN and convert the information into 4 bit wide data and
then pass the data to IP101A LF. IP101A LF will sample the data according to TX_CLK until TX_EN is low.
While receiving a packet, IP101A LF asserts RX_DV high when data present in the medium through
RXD[3:0] bus lines. IP101A LF samples received data according to RX_CLK until the medium is back to
idle state.
RMII Interface
Reduced Media Independent Interface (RMII) is defined to provide a fewer pins data transmission
condition. The management interface, MDC and MDIO, are identical to the MII defined in IEEE 802.3.
RMII supports 10/100Mb data rates and the clock source is provided by a single 50MHz clock from either
external or within IP101A LF. This clock is used as reference for transmit, receive and control. RMII
provides independent 2 bit wide transmit and receive data path, i.e., TXD[1:0] and RXD[1:0]. CRS_DV is
asserted when the receive medium is not idle and de-asserted when the medium is idle.
Before any transmission occurs, CRS_DV should be de-asserted and value “00” should be present in
both TXD[1:0] and RXD[1:0]. When transmission begins, IP101A LF will send “01” (TXD[1:0] = 01) for
preamble to indicate SFD, and also assert TX_EN synchronous with first nibble of the preamble. TX_EN
should be de-asserted until the end of the data transmission. At receiving mechanism, by receiving “01”
means a valid data is available. If False carrier is detected, RXD[1:0] shall be “10” until the end of the
transmission.
At 10Mbps mode, every 10th cycle of REF_CLK will be sampled in RXD[1:0] and TXD[1:], because the
REF_CLK frequency is 10 times faster than the data rate of the 10Mbps.
SNI Interface
The IP101A LF also provides serial-network interface for legacy MACs, when the chip operates at
10BASE-T either by Auto-Negotiation resolved result or by forced mode. To setup for this mode of
operation, pull both the MII/SNIB and the COL/RMII pins to low.
The transaction protocol of SNI interface is almost identical to that of MII interface, except of data bit width
and clock rate. This interface consists of 10Mbps transmit and receive clock generated by PHY’s digital
phase-locked loop (DPLL), 10Mbps transmit and receive serial data, transmit enable, collision detect, and
carry sense signals.
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Copyright © 2004, IC Plus Corp.
Oct 22, 2007
IP101A LF-DS-R12
IP101A LF
Data Sheet
Auto-Negotiation and Related Information
IP101A LF supports clause 28 in the IEEE 802.3u standard. IP101A LF can be operated either in
10Mbps/100Mbps or half/full duplex transmission mode. IP101A LF also supports flow control mechanism
to prevent any collision in the network. If the other end does not support Auto-Negotiation function,
IP101A LF will link at half duplex mode and enter parallel detection.
At beginning of auto-negotiation, IP101A LF will advertise its own ability by sending FLP waveform out to
the other end and also listening signals from the other end. IP101A LF will place itself into correct
connection speed depends on the received signals. If NLP signal is replied from the other end, IP101A LF
will enter 10Mbps, while active idle pulses (unique 100Mbps pattern) IP101A LF will go to 100Mbps mode
instead.
Once the negotiation has completed with the other party, IP101A LF will configure itself to the desired
connection mode, i.e., 10/100Mbps or Half/Full duplex modes. If there is no detection of link pulses within
1200~1500ms, IP101A LF will enter Link Fail State and restart auto-negotiation procedure.
The auto-negotiation information is stored in the IP101A LF’s MII registers. These registers can be
modified and monitor the IP101A LF’s Auto-Negotiation status. The reset auto-negotiation in register 0 of
MII registers can be set at any time to restart auto-negotiation.
The flow control ability is also included in the IP101A LF chip. If MAC supports flow control condition, then
flow control will be enabled by setting bit 10 (Pause) of the Register 4.
Pin 37 (AN_ENA), 38 (DLPX), 39 (SPD) can be configured manually to set IP101A LF’s transmission
ability.
1. Enabling Pin 37 (set high) will put IP101A LF to Auto-Negotiation mode, if set low to pin 37, it will put
IP101A LF into forced mode.
2. Pin 38 will configure Duplex ability of IP101A LF, at high, IP101A LF is set to Full-Duplex and low will
let IP101A LF enter half duplex mode.
3. Pin 39 determines the speed of connection. If the pin is pulled high, IP101A LF is set at 100Mbps,
while at low will make IP101A LF to connect at 10Mbps speed.
AN_ENA
(Pin 37)
DLPX
(Pin38)
SPD
(Pin39)
H
L
L
Auto-Negotiation enable, the ability field does not support 100Mbps
and full duplex mode operation
H
H
L
H
L
H
Auto-Negotiation enable, the ability field does not support 100Mbps
operation
Auto-Negotiation enable, the ability field does not support full duplex
mode operation
H
H
H
L
L
L
L
H
L
Auto-Negotiation disable, force the IP101A LF into 10BT and full
duplex mode.
L
L
H
Auto-Negotiation disable, force the IP101A LF into 100BT and half
duplex mode.
L
H
H
Auto-Negotiation disable, force the IP101A LF into 100BT and full
duplex mode.
Operation
Default setup, auto-negotiation enable, the IP101A LF will support
10BT/100BT, half/full duplex mode operation
Auto-Negotiation disable, force the IP101A LF into 10BT and half
duplex mode.
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Copyright © 2004, IC Plus Corp.
Oct 22, 2007
IP101A LF-DS-R12
IP101A LF
Data Sheet
Auto MDIX function
IP101A LF will keep sensing incoming signal in MDI RX pair, if no incoming signal is detected, IP101A LF
will switch TX and RX pairs automatically trying to establish connection. IP101A LF supports this function
both in Auto-Negotiation mode and force mode.
LED Configuration
IP101A LF provides 2 LED operation modes,
Mode 1 (default):
LED
Function
LED0
LED1
Link status: Active indicates the link has established
Duplex operation: Active indicates full duplex
LED2
10BT/ACT: Active indicates 10Mbps connection has established, and blinking while
TX/RX events occur.
LED3
100BT/ACT: Active indicates 100Mbps connection has established, and blinking
while TX/RX events occur.
LED4
Collision detect: Active indicates Collision has occurred
Mode 2 (could be set by pulling up CRS with a 4.7K resistor):
LED
Function
LED0
Link/ACT: Active indicates the link has established, and blinking while TX/RX events
occur.
LED1
Duplex/COL: Active indicates full duplex, and blinking while collision events occur.
LED2
10BT: Active indicates 10Mbps connection has established
LED3
LED4
100BT: Active indicates 100Mbps connection has established
Reserved.
LED pins also include the information of PHY address, the default PHY address is set at 00001b (01h).
The PHY address can be modified by changing the LED circuitry. The modification can be arranged as
follow:
VDD33
R27
R27
5.1k ohm
5.1k ohm
R26
LED
510 ohm
D6
LEDx {X=0:4}
D6
R26
LEDx {X=0:4}
LED
510 ohm
Figure 3: PHY address Configuration
The left diagram will enable the specific PHY address to 1, if it is connected to VDD33. The diagram on
the right shows the configuration for setting PHY address to 0, when the circuit is connected to ground.
By setting either one of the bits according to the diagram will allow one to modify PHY addresses from
PHYAD0 to PHYAD4.
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Copyright © 2004, IC Plus Corp.
Oct 22, 2007
IP101A LF-DS-R12
IP101A LF
Data Sheet
Flexible Clock Source
Pin1
COL/RMII
1
Pin44
MII/SNIB
1
Function
1
0
RMII, 25MHz crystal or osc from X1,X2; 50MHz clk out to pin16. (Please refer
to the following figure for our recommened application circuit.)
0
1
MII, 25MHz crystal or osc from X1,X2
0
0
SNI, 25MHz crystal or osc from X1,X2
RMII, ext 50MHz osc clk in to pin7
While pin1=1 and pin44=0 has been selected, 50MHz clock will be provided by IP101A LF in RMII mode.
We suggest the application circuit as the following :
CPU/Switch/MAC
50MHz colck
Other PHY
Buffer
Pin16
Pin7
IP101A
25M
Pin46
Pin47
For this configuration, RMII reference clock for IP101A LF is from pin7. Clock skew could be eliminated by
adding an external buffer and placing equal trace lengths between buffer outputs and each chip.
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Copyright © 2004, IC Plus Corp.
Oct 22, 2007
IP101A LF-DS-R12
IP101A LF
Data Sheet
Power-Down Modes
IP101A LF can be power-down by 4 methods. These 4 methods are as follow:
Power Down in bit 11 of Register 0: Enable this bit will disconnect the power to IP101A LF and also
internal clock, but MDC and MDIO are still activated.
APS mode in bit 1 of Register 16: Set high to this bit will set PHY into power saving mode(APS sleeping
mode) while link is down, MDC and MDIO are kept activated. IP101A LF will send NLP every 64ms during
APS sleeping mode.
Analog off in bit 0 of Register 16: Enable this bit will put IP101A LF in analog off state. This will power
down all analog functions but internal 25MHz operating clock is active, and MDC and MDIO are also
activated.
ISOL pin (pin 43): Set high will isolate IP101A LF from MAC and disable management interface (MDC and
MDIO). The power usage is at minimum when this pin is activated.
Repeater Modes
To enter Repeater mode, one can either set pin 40 (RPTR) to high or set 1 to bit 2 of Register 16 will allow
IP101A LF to enter Repeater mode. If IP101A LF is used in repeater, CRS will be high if IC is in process of
receiving packets, while IP101A LF is used in a network interface card, CRS will be generated in both
transmitting and receiving packets.
Miscellaneous
ISET (pin 28) should be connected to GND via a 6.2k ohm resistor with 1% accuracy to ensure a correct
driving current for transmit DAC.
Set low to pin 42, REST_N, for at least 10ms will reset all functions available in IP101A LF. The bit 15 of
Register 0 will put PHY into its default status.
Interrupt
IP101A LF provides 4 kinds of interrupt function: speed change, duplex change, link change and arbiter
state change. Interrupt masks could be selected by Reg 17, and an active low interrupt will be sent from
pin48 when event occurs.
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Copyright © 2004, IC Plus Corp.
Oct 22, 2007
IP101A LF-DS-R12
IP101A LF
Data Sheet
4
Serial management interface
User can access IP101A LF’s MII registers through serial management interface MDC and MDIO. A
specific pattern on MDIO is used to access a MII register. Its format is shown in the following table. When
the SMI is idle, MDIO is in high impedance. To initialize the MDIO interface, the management entity sends
a sequence of 32 contiguous “1” and “start” on MDIO.
Frame
format
<Idle><start><op code><IP101A LF’s address><Registers address><turnaround>
<data><idle>
Read
Operation
<Idle><01><10><A4A3A2A1A0><R4R3R2R1R0><Z0>
<b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1b0><Idle>
Write
Operation
<Idle><01><01><A4A3A2A1A0><R4R3R2R1R0><10>
<b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1b0><Idle>
MDC
z
z
MDIO
1..1 0 1 0 1 0 0 0 0 1 0 0 0 0 0 1 0 0 0 1
op
A A A A A R R R R R TA b b b
idle start
code
4 3 2 1 0 4 3 2 1 0
1 1 1
write
PHY address =
Reg address =
5 4 3
01h
00h
1
b
1
2
0
b
1
1
0 1 1 0 0 0 0 0 0 0 0 1..1
b b b b b b b b b b b idle
1 9 8 7 6 5 4 3 2 1 0
0
Register data
MDC
MDIO
z
z
z
1..1 0 1 1 0 0 0 0 0 1 0 0 0 0 0 Z 0 0 0 1 1 0 0 0 1 0 0 0 0 0 0 0 0 1..1
idle
start
op
code
read
A A A A A R R R R R TA b b b b b b b b b b b b b b b b
4 3 2 1 0 4 3 2 1 0
1 1 1 1 1 1 9 8 7 6 5 4 3 2 1 0
PHY address =
Reg address =
5 4 3 2 1 0
Register data
01h
00h
28/36
Copyright © 2004, IC Plus Corp.
idle
Oct 22, 2007
IP101A LF-DS-R12
IP101A LF
Data Sheet
5
Crystal Specifications
Item
1
Parameter
Range
Nominal Frequency
25.000 MHz
2
Oscillation Mode
Fundamental Mode
3
Frequency Tolerance at 25℃
+/- 50 ppm
4
5
Temperature Characteristics
Operating Temperature Range
+/- 50 ppm
-10℃ ~ +70℃
6
Equivalent Series Resistance
40 ohm Max.
7
Drive Level
100μW
8
Load Capacitance
20 pF
9
Shunt Capacitance
7 pF Max
10
Insulation Resistance
Mega ohm Min./DC 100V
11
Aging Rate A Year
+/- 5 ppm/year
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Copyright © 2004, IC Plus Corp.
Oct 22, 2007
IP101A LF-DS-R12
IP101A LF
Data Sheet
6
Layout Guideline
General Layout Guideline
Best performance depends on good layout. The following recommendation steps will help customer to
gain maximum performance.
Create good power source to minimize noise from switching power source.
All components are qualified, especially high noise component, such as clock component.
Use bulk capacitors between power plane and ground plane for 4 layers board, signals trace on
component and bottom side, power plane on third layer, and ground layer on second layer.
Use decoupling capacitors to decouple high frequency noise between chip’s power and ground,
must be as close as possible to IP101A LF.
The clock trace length to IP101A LF must be equal the clock trace length to MAC.
Use guard traces to protect clock traces if possible
Avoid signals path parallel to clock signals path, because clock signals will interference with other
parallel signals, degrading signal quality, such as MDC and X1signals.
The clock must be low jitter with less than 0.5ns for 25/50/125Mhz 100ppm.
Avoid highly speed signal across ground gap to prevent large EMI effect.
Keep ground region as one continuous and unbroken plane.
Place a gap between the system and chassis grounds.
No any ground loop exists on the chassis ground.
Twisted Pair recommendation
When routing the TD+/- signal traces from IP101A LF to transformer, the traces should be as short as
possible, the termination resistors should be as close as possible to the output of the TD+/- pair of IP101A
LF. Center tap of primary winding of these transformers must be connected to analog 2.5V respectively. It
is recommended that RD+/- trace pair be route such that the space between it and others is three times
space, which can separate individual traces from one another.
It is recommended that offers chassis ground in the area between transformer and media connector
(RJ-45 port), this isolates the analog signals from external noise sources and reduces EMI effect. Note the
usage of the vias, it is best not use via to place anywhere other than in close proximity to device, in order
to minimize impedance variations in a given signal trace.
30/36
Copyright © 2004, IC Plus Corp.
Oct 22, 2007
IP101A LF-DS-R12
IP101A LF
Data Sheet
7
Electrical Characteristics
7.1
D.C. Characteristic
7.1.1
Absolute Maximum Rating
Symbol
Conditions
Minimum
Supply Voltage
Storage Temp
7.1.2
3.0 V
Maximum
3.6V
125°C
Power Dissipation
IP101A LF
Auto Power Saving Mode
Analog off Mode
41mA
17mA
Power Down Mode
11mA
Isolate Mode
11mA
100 Full
138mA
100 Half
10 Full
137mA
148mA
10 Half
147mA
10 Transmit
145mA
10 Receive
147mA
10 IDLE
95mA
Operating Condition
Symbol
Vcc
Conditions
3.3V Supply voltage
Minimum
3.0 V
TA
Operating Temperature
0°C
7.1.4
3.3V
-55°C
Symbol
7.1.3
Typical
Typical
3.3V
Maximum
3.6V
70°C
Supply Voltage
Symbol
Specific Name
Condition
Min
VIH
VIL
Input High Voltage
Input Low Voltage
0.5*Vcc
-0.5V
VIH
X1 Input High Voltage
1.25V
VIL
X1 Input Low Voltage
VOH
Output High Voltage
VOL
IOZ
Output Low Voltage
Tri-state Leakage
Vout=Vcc or GND
IIN
Input Current
Vin=Vcc or GND
Icc
Average Operating Supply Current
Iout=0mA
Vcc+0.5V
0.3*Vcc
0.42V
0.9*Vcc
Vcc
0.1*Vcc
31/36
Copyright © 2004, IC Plus Corp.
Max
200mA
Oct 22, 2007
IP101A LF-DS-R12
IP101A LF
Data Sheet
7.2
7.2.1
A.C. Characteristic
MII Timing
a. Pin Reset and Clock output timing relationship
Symbol
Tdelay
Description
Delay time after reset to clock output
Min.
Typ.
Max.
Unit
-
40
-
us
Min.
Typ.
Max.
Unit
2
0.5
40
400
-
-
ns
ns
ns
ns
Min.
Typ.
Max.
Unit
1
40
400
-
4
ns
ns
ns
Tdelay
RESET_N
MII_TXCLK
MII_RXCLK
b. Transmit Timing Requirements
Symbol
TTxClk
TTxClk
TsTxClk
ThTxClk
Description
Transmit clock period 100M MII
Transmit clock period 10M MII
TXEN, TXD to MII_TXCLK setup time
TXEN, TXD to MII_TXCLK hold time
T T xC lk
M II_T X C L K
T hT xC lk
T XE N , T X D [3:0]
T sT xC lk
c. Receive Timing
Symbol
TRxClk
TRxClk
TdRxClk
Description
Receive clock period 100M MII
Receive clock period 10M MII
MII_RXCLK falling edge to RXDV, RXD
T RxClk
MII_RXCLK
T dRxClk
RXDV, RXD[3:0]
32/36
Copyright © 2004, IC Plus Corp.
Oct 22, 2007
IP101A LF-DS-R12
IP101A LF
Data Sheet
7.2.2
RMII Timing
a.
Pin Reset and Clock output timing relationship (If pin 16 has been configured as 50MHz output )
Symbol
Tdelay
Description
Min.
Typ.
Max.
Unit
-
40
-
us
Min
Typ
Delay time after reset to clock output
Tdelay
RESET_N
C50M_O
b. Clock Timing RMII
Symbol
TR_CLKRMII
Description
REFCLK Rise time
Notes
VIL (max) to VIH (min)
-
TF_CLKRMII
REFCLK Fall time
VIH (min) to VIL (max)
-
TP_CLKRMII
REFCLK Period
TH_CLKRMII
REFCLK High
8.0
10.0
12.0
ns
TL_CLKRMII
REFCLK Low
8.0
10.0
12.0
ns
Units
ns
-
3.0
ns
ns
20.0 ± 50
ppm
T
T
REFCLK
-
Max
3.0
V
IH
V
IL
T
P_CLKRMII
T
H_CLKRMII
R_CLKRMII
T
L_CLKRMII
F_CLKRMII
Figure 4: Clock Timing RMII
c. RMII Receive Timing
Symbol
Description
TDLY_RXD
REFCLK rising edge
to RXD[1:0], RX_ER
and CRS_DV delay
TR_RXD
RXD[1:0], RX_ER,
CRS_DV Rise time
TF_RXD
RXD[1:0], RX_ER,
CRS_DV Fall time
Notes
Typ
Max
Units
Initial rising edge of
CRS_DV is
asynchronous to
REFCLK
VIL (max) to VIH (min)
12.0
15.0
ns
1.0
2.5
ns
VIH (min) to VIL (max)
1.0
2.5
ns
33/36
Copyright © 2004, IC Plus Corp.
Min
Oct 22, 2007
IP101A LF-DS-R12
IP101A LF
Data Sheet
REFCLK
RXD[1:0]
RX_ER
CRS_DV
T
DLY_RXD
Figure 5: Receive Delay
RXD[1:0]
RX_ER
CRS_DV
T
V
IH_DIG(MAX)
V
IL_DIG(MAX)
T
R_RXD
F_RXD
Figure 6: RMII Rise and Fall Times
d. RMII Transmit Timing
Symbol
TSU_TXD_RMII
THD_TXD_RMII
Parameter
TXD[1:0], TX_EN, Data Setup to REFCLK rising
edge
Min
4.0
TXD[1:0], TX_EN, Data Hold from REFCLK
rising edge
2.0
Typ
Max
Units
ns
ns
REFCLK
T
T
SU_TXD_RMII
TX[1:0]
TX_EN
HD_TXD_RMII
Valid Data
Figure 7: RMII Transmit Timing
7.2.3
SMI Timing
a. MDC/MDIO Timing
Symbol
Tch
Tcl
Tcm
Tmd
Description
MDC High Time
MDC Low Time
MDC period
MDIO output delay
34/36
Copyright © 2004, IC Plus Corp.
Min.
Typ.
Max.
Unit
40
40
80
-
-
5
ns
ns
ns
ns
Oct 22, 2007
IP101A LF-DS-R12
IP101A LF
Data Sheet
Tmh
Tms
MDIO setup time
MDIO hold time
10
10
-
-
ns
ns
MDC
Tms
Tmh
M D IO
W r ite C yc le
MDC
T cl
T ch
Tmd
T cm
M D IO
R e a d C yc le
8
Order Information
Part No.
IP101A
Package
48-PIN LQFP
Notice
-
IP101A LF
48-PIN LQFP
Lead free
35/36
Copyright © 2004, IC Plus Corp.
Oct 22, 2007
IP101A LF-DS-R12
IP101A LF
Data Sheet
9
Package and Mechanical Specification
48
37
1
36
D
PH
12
25
13
HE
24
"E"
b 12"
e
A
A2
GAUGE PLANE
θ
A1
F y
c
F
SEATING
PLANE
D
0.254
12"
L
E
L1
DETAIL "E"
13
24
unit
Symbol
12
A
A1
A2
b
c
D
25
2
E
e
Hd
He
L
L1
y
2
1
36
48
37
mm
inch
1.600MAX.
0.050~0.150
1.400 + 0.05
0.200TYP
0.127TYP
7.000 + 0.100
7.000 + 0.100
-
0.0630MAX.
0.0020~0.0059
0.0551 + 0.0020
0.0078TYP
0.0050TYP
0.2756 + 0.0039
0.2756 + 0.0039
0.500TYP
9.000 + 0.250
9.000 + 0.250
0.600 + 0.150
1.000REF
0.100MAX.
0"~7"
-
0.0196TYP
0.3543 + 0.0098
0.3543 + 0.0098
0.0236 + 0.006
0.0393REF
0.0039MAX.
0"~7"
-
-
-
-
Notes:
1. DIMENSION D & E DO NOT INCLUDE MOLD FLASH OR PROTRUSION.
2. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION / INTRUSION.
3. MAX. END FLASH IS 0.15MM.
4. MAX. DAMBAR PROTRUSION IS 0.13MM.
GENERAL APPEARANCE SPEC SHOULD BE BASED ON FINAL VISUAL INSPECTION SPEC.
IC Plus Corp.
Headquarters
10F, No.47, Lane 2, Kwang-Fu Road, Sec. 2,
Hsin-Chu City, Taiwan 300, R.O.C.
TEL : 886-3-575-0275
FAX : 886-3-575-0475
Website : www.icplus.com.tw
Sales Office
4F, No. 106, Hsin-Tai-Wu Road, Sec.1,
Hsi-Chih, Taipei Hsien, Taiwan 221, R.O.C.
TEL : 886-2-2696-1669
FAX : 886-2-2696-2220
36/36
Copyright © 2004, IC Plus Corp.
Oct 22, 2007
IP101A LF-DS-R12