P3503EVG NIKO-SEM P-Channel Logic Level Enhancement SOP-8 Lead-Free Mode Field Effect Transistor D PRODUCT SUMMARY V(BR)DSS RDS(ON) ID -30 35mΩ -8A 4 :GATE 5,6,7,8 :DRAIN 1,2,3 :SOURCE G S ABSOLUTE MAXIMUM RATINGS (TC = 25 °C Unless Otherwise Noted) PARAMETERS/TEST CONDITIONS SYMBOL LIMITS UNITS Drain-Source Voltage VDS -30 V Gate-Source Voltage VGS ±20 V TC = 25 °C Continuous Drain Current -8 ID TC = 70 °C Pulsed Drain Current -7 1 IDM TC = 25 °C Power Dissipation A -30 2.5 PD TC = 70 °C W 1.3 Operating Junction & Storage Temperature Range Tj, Tstg -55 to 150 °C THERMAL RESISTANCE RATINGS THERMAL RESISTANCE SYMBOL TYPICAL MAXIMUM UNITS Junction-to-Case RθJc 25 °C / W Junction-to-Ambient RθJA 50 °C / W 1 Pulse width limited by maximum junction temperature. Duty cycle ≤ 1% ELECTRICAL CHARACTERISTICS (TC = 25 °C, Unless Otherwise Noted) 2 PARAMETER SYMBOL TEST CONDITIONS LIMITS UNIT MIN TYP MAX STATIC Drain-Source Breakdown Voltage V(BR)DSS VGS = 0V, ID = -250µA -30 VGS(th) VDS = VGS, ID = -250µA -0.8 Gate-Body Leakage IGSS VDS = 0V, VGS = ±20V ±100 Zero Gate Voltage Drain Current IDSS VDS = -24V, VGS = 0V -1 VDS = -20V, VGS = 0V, TJ = 125 °C -10 Gate Threshold Voltage On-State Drain Current 1 Drain-Source On-State Resistance1 Forward Transconductance1 ID(ON) RDS(ON) gfs VDS = -5V, VGS = -10V V -1.5 -2.5 -30 nA µA A VGS = -4.5V, ID = -6A 44 60 VGS = -10V, ID = -8A 28 35 VDS = -10V, ID = -6A 7 mΩ S Jan-06-2005 1 P3503EVG NIKO-SEM P-Channel Logic Level Enhancement SOP-8 Lead-Free Mode Field Effect Transistor DYNAMIC Input Capacitance Ciss Output Capacitance Coss Reverse Transfer Capacitance Crss 180 Total Gate Charge Qg 28 Gate-Source Charge2 Qgs VDS = 0.5V (BR)DSS, VGS = -10V, 6 Gate-Drain Charge2 Qgd ID = -8A 12 2 2 Turn-On Delay Time Rise Time2 Turn-Off Delay Time2 Fall Time2 970 VGS = 0V, VDS = -10V, f = 1MHz td(on) pF 370 nC 20 tr VDS = -15V, RL = 1Ω 17 td(off) ID ≅ -1A, VGS = -10V, RGS = 6Ω 180 tf nS 75 SOURCE-DRAIN DIODE RATINGS AND CHARACTERISTICS (TC = 25 °C) Continuous Current IS -3 Pulsed Current 3 ISM -6 Forward Voltage1 VSD Reverse Recovery Charge Qrr IF = -1A, VGS = 0V -1 7.9 A V nC Pulse test : Pulse Width ≤ 300 µsec, Duty Cycle ≤ 2％. Independent of operating temperature. 3 Pulse width limited by maximum junction temperature. 1 2 REMARK: THE PRODUCT MARKED WITH “P3503EVG”, DATE CODE or LOT # Orders for parts with Lead-Free plating can be placed using the PXXXXXXG parts name. Jan-06-2005 2 NIKO-SEM P3503EVG P-Channel Logic Level Enhancement Mode Field Effect Transistor SOP-8 Lead-Free Jan-06-2005 3 NIKO-SEM P3503EVG P-Channel Logic Level Enhancement Mode Field Effect Transistor SOP-8 Lead-Free Jan-06-2005 4 NIKO-SEM P3503EVG P-Channel Logic Level Enhancement SOP-8 Lead-Free Mode Field Effect Transistor SOIC-8(D) MECHANICAL DATA mm mm Dimension Dimension Min. Typ. Max. Min. Typ. Max. A 4.8 4.9 5.0 H 0.5 0.715 0.83 B 3.8 3.9 4.0 I 0.18 0.254 0.25 C 5.8 6.0 6.2 J D 0.38 0.445 0.51 K 1.27 E 0.22 0° 4° 8° L F 1.35 1.55 1.75 M G 0.1 0.175 0.25 N Jan-06-2005 5